2 * arch/arm/mach-ixp4xx/common.c
4 * Generic code shared across all IXP4XX platforms
6 * Maintainer: Deepak Saxena <dsaxena@plexity.net>
8 * Copyright 2002 (c) Intel Corporation
9 * Copyright 2003-2004 (c) MontaVista, Software, Inc.
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
16 #include <linux/kernel.h>
18 #include <linux/init.h>
19 #include <linux/serial.h>
20 #include <linux/tty.h>
21 #include <linux/platform_device.h>
22 #include <linux/serial_core.h>
23 #include <linux/interrupt.h>
24 #include <linux/bitops.h>
25 #include <linux/time.h>
26 #include <linux/clocksource.h>
27 #include <linux/clockchips.h>
29 #include <linux/export.h>
30 #include <linux/gpio.h>
31 #include <linux/cpu.h>
32 #include <linux/sched_clock.h>
35 #include <mach/hardware.h>
37 #include <asm/uaccess.h>
38 #include <asm/pgtable.h>
41 #include <asm/system_misc.h>
43 #include <asm/mach/map.h>
44 #include <asm/mach/irq.h>
45 #include <asm/mach/time.h>
47 #define IXP4XX_TIMER_FREQ 66666000
50 * The timer register doesn't allow to specify the two least significant bits of
51 * the timeout value and assumes them being zero. So make sure IXP4XX_LATCH is
52 * the best value with the two least significant bits unset.
54 #define IXP4XX_LATCH DIV_ROUND_CLOSEST(IXP4XX_TIMER_FREQ, \
55 (IXP4XX_OST_RELOAD_MASK + 1) * HZ) * \
56 (IXP4XX_OST_RELOAD_MASK + 1)
58 static void __init ixp4xx_clocksource_init(void);
59 static void __init ixp4xx_clockevent_init(void);
60 static struct clock_event_device clockevent_ixp4xx;
62 /*************************************************************************
63 * IXP4xx chipset I/O mapping
64 *************************************************************************/
65 static struct map_desc ixp4xx_io_desc[] __initdata = {
66 { /* UART, Interrupt ctrl, GPIO, timers, NPEs, MACs, USB .... */
67 .virtual = (unsigned long)IXP4XX_PERIPHERAL_BASE_VIRT,
68 .pfn = __phys_to_pfn(IXP4XX_PERIPHERAL_BASE_PHYS),
69 .length = IXP4XX_PERIPHERAL_REGION_SIZE,
71 }, { /* Expansion Bus Config Registers */
72 .virtual = (unsigned long)IXP4XX_EXP_CFG_BASE_VIRT,
73 .pfn = __phys_to_pfn(IXP4XX_EXP_CFG_BASE_PHYS),
74 .length = IXP4XX_EXP_CFG_REGION_SIZE,
76 }, { /* PCI Registers */
77 .virtual = (unsigned long)IXP4XX_PCI_CFG_BASE_VIRT,
78 .pfn = __phys_to_pfn(IXP4XX_PCI_CFG_BASE_PHYS),
79 .length = IXP4XX_PCI_CFG_REGION_SIZE,
81 }, { /* Queue Manager */
82 .virtual = (unsigned long)IXP4XX_QMGR_BASE_VIRT,
83 .pfn = __phys_to_pfn(IXP4XX_QMGR_BASE_PHYS),
84 .length = IXP4XX_QMGR_REGION_SIZE,
89 void __init ixp4xx_map_io(void)
91 iotable_init(ixp4xx_io_desc, ARRAY_SIZE(ixp4xx_io_desc));
98 * The following converted to the real HW bits the gpio_line_config
101 #define IXP4XX_GPIO_OUT 0x1
102 #define IXP4XX_GPIO_IN 0x2
104 /* GPIO signal types */
105 #define IXP4XX_GPIO_LOW 0
106 #define IXP4XX_GPIO_HIGH 1
109 #define IXP4XX_GPIO_CLK_0 14
110 #define IXP4XX_GPIO_CLK_1 15
112 static void gpio_line_config(u8 line, u32 direction)
114 if (direction == IXP4XX_GPIO_IN)
115 *IXP4XX_GPIO_GPOER |= (1 << line);
117 *IXP4XX_GPIO_GPOER &= ~(1 << line);
120 static void gpio_line_get(u8 line, int *value)
122 *value = (*IXP4XX_GPIO_GPINR >> line) & 0x1;
125 static void gpio_line_set(u8 line, int value)
127 if (value == IXP4XX_GPIO_HIGH)
128 *IXP4XX_GPIO_GPOUTR |= (1 << line);
129 else if (value == IXP4XX_GPIO_LOW)
130 *IXP4XX_GPIO_GPOUTR &= ~(1 << line);
133 /*************************************************************************
134 * IXP4xx chipset IRQ handling
136 * TODO: GPIO IRQs should be marked invalid until the user of the IRQ
137 * (be it PCI or something else) configures that GPIO line
139 **************************************************************************/
140 enum ixp4xx_irq_type {
141 IXP4XX_IRQ_LEVEL, IXP4XX_IRQ_EDGE
144 /* Each bit represents an IRQ: 1: edge-triggered, 0: level triggered */
145 static unsigned long long ixp4xx_irq_edge = 0;
148 * IRQ -> GPIO mapping table
150 static signed char irq2gpio[32] = {
151 -1, -1, -1, -1, -1, -1, 0, 1,
152 -1, -1, -1, -1, -1, -1, -1, -1,
153 -1, -1, -1, 2, 3, 4, 5, 6,
154 7, 8, 9, 10, 11, 12, -1, -1,
157 static int ixp4xx_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
161 for (irq = 0; irq < 32; irq++) {
162 if (irq2gpio[irq] == gpio)
168 static int ixp4xx_set_irq_type(struct irq_data *d, unsigned int type)
170 int line = irq2gpio[d->irq];
172 enum ixp4xx_irq_type irq_type;
173 volatile u32 *int_reg;
182 case IRQ_TYPE_EDGE_BOTH:
183 int_style = IXP4XX_GPIO_STYLE_TRANSITIONAL;
184 irq_type = IXP4XX_IRQ_EDGE;
186 case IRQ_TYPE_EDGE_RISING:
187 int_style = IXP4XX_GPIO_STYLE_RISING_EDGE;
188 irq_type = IXP4XX_IRQ_EDGE;
190 case IRQ_TYPE_EDGE_FALLING:
191 int_style = IXP4XX_GPIO_STYLE_FALLING_EDGE;
192 irq_type = IXP4XX_IRQ_EDGE;
194 case IRQ_TYPE_LEVEL_HIGH:
195 int_style = IXP4XX_GPIO_STYLE_ACTIVE_HIGH;
196 irq_type = IXP4XX_IRQ_LEVEL;
198 case IRQ_TYPE_LEVEL_LOW:
199 int_style = IXP4XX_GPIO_STYLE_ACTIVE_LOW;
200 irq_type = IXP4XX_IRQ_LEVEL;
206 if (irq_type == IXP4XX_IRQ_EDGE)
207 ixp4xx_irq_edge |= (1 << d->irq);
209 ixp4xx_irq_edge &= ~(1 << d->irq);
211 if (line >= 8) { /* pins 8-15 */
213 int_reg = IXP4XX_GPIO_GPIT2R;
214 } else { /* pins 0-7 */
215 int_reg = IXP4XX_GPIO_GPIT1R;
218 /* Clear the style for the appropriate pin */
219 *int_reg &= ~(IXP4XX_GPIO_STYLE_CLEAR <<
220 (line * IXP4XX_GPIO_STYLE_SIZE));
222 *IXP4XX_GPIO_GPISR = (1 << line);
224 /* Set the new style */
225 *int_reg |= (int_style << (line * IXP4XX_GPIO_STYLE_SIZE));
227 /* Configure the line as an input */
228 gpio_line_config(irq2gpio[d->irq], IXP4XX_GPIO_IN);
233 static void ixp4xx_irq_mask(struct irq_data *d)
235 if ((cpu_is_ixp46x() || cpu_is_ixp43x()) && d->irq >= 32)
236 *IXP4XX_ICMR2 &= ~(1 << (d->irq - 32));
238 *IXP4XX_ICMR &= ~(1 << d->irq);
241 static void ixp4xx_irq_ack(struct irq_data *d)
243 int line = (d->irq < 32) ? irq2gpio[d->irq] : -1;
246 *IXP4XX_GPIO_GPISR = (1 << line);
250 * Level triggered interrupts on GPIO lines can only be cleared when the
251 * interrupt condition disappears.
253 static void ixp4xx_irq_unmask(struct irq_data *d)
255 if (!(ixp4xx_irq_edge & (1 << d->irq)))
258 if ((cpu_is_ixp46x() || cpu_is_ixp43x()) && d->irq >= 32)
259 *IXP4XX_ICMR2 |= (1 << (d->irq - 32));
261 *IXP4XX_ICMR |= (1 << d->irq);
264 static struct irq_chip ixp4xx_irq_chip = {
266 .irq_ack = ixp4xx_irq_ack,
267 .irq_mask = ixp4xx_irq_mask,
268 .irq_unmask = ixp4xx_irq_unmask,
269 .irq_set_type = ixp4xx_set_irq_type,
272 void __init ixp4xx_init_irq(void)
277 * ixp4xx does not implement the XScale PWRMODE register
278 * so it must not call cpu_do_idle().
280 cpu_idle_poll_ctrl(true);
282 /* Route all sources to IRQ instead of FIQ */
285 /* Disable all interrupt */
288 if (cpu_is_ixp46x() || cpu_is_ixp43x()) {
289 /* Route upper 32 sources to IRQ instead of FIQ */
290 *IXP4XX_ICLR2 = 0x00;
292 /* Disable upper 32 interrupts */
293 *IXP4XX_ICMR2 = 0x00;
296 /* Default to all level triggered */
297 for(i = 0; i < NR_IRQS; i++) {
298 irq_set_chip_and_handler(i, &ixp4xx_irq_chip,
300 set_irq_flags(i, IRQF_VALID);
305 /*************************************************************************
307 * We use OS timer1 on the CPU for the timer tick and the timestamp
308 * counter as a source of real clock ticks to account for missed jiffies.
309 *************************************************************************/
311 static irqreturn_t ixp4xx_timer_interrupt(int irq, void *dev_id)
313 struct clock_event_device *evt = dev_id;
315 /* Clear Pending Interrupt by writing '1' to it */
316 *IXP4XX_OSST = IXP4XX_OSST_TIMER_1_PEND;
318 evt->event_handler(evt);
323 static struct irqaction ixp4xx_timer_irq = {
325 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
326 .handler = ixp4xx_timer_interrupt,
327 .dev_id = &clockevent_ixp4xx,
330 void __init ixp4xx_timer_init(void)
332 /* Reset/disable counter */
335 /* Clear Pending Interrupt by writing '1' to it */
336 *IXP4XX_OSST = IXP4XX_OSST_TIMER_1_PEND;
338 /* Reset time-stamp counter */
341 /* Connect the interrupt handler and enable the interrupt */
342 setup_irq(IRQ_IXP4XX_TIMER1, &ixp4xx_timer_irq);
344 ixp4xx_clocksource_init();
345 ixp4xx_clockevent_init();
348 static struct pxa2xx_udc_mach_info ixp4xx_udc_info;
350 void __init ixp4xx_set_udc_info(struct pxa2xx_udc_mach_info *info)
352 memcpy(&ixp4xx_udc_info, info, sizeof *info);
355 static struct resource ixp4xx_udc_resources[] = {
359 .flags = IORESOURCE_MEM,
362 .start = IRQ_IXP4XX_USB,
363 .end = IRQ_IXP4XX_USB,
364 .flags = IORESOURCE_IRQ,
369 * USB device controller. The IXP4xx uses the same controller as PXA25X,
370 * so we just use the same device.
372 static struct platform_device ixp4xx_udc_device = {
373 .name = "pxa25x-udc",
376 .resource = ixp4xx_udc_resources,
378 .platform_data = &ixp4xx_udc_info,
382 static struct platform_device *ixp4xx_devices[] __initdata = {
386 static struct resource ixp46x_i2c_resources[] = {
390 .flags = IORESOURCE_MEM,
393 .start = IRQ_IXP4XX_I2C,
394 .end = IRQ_IXP4XX_I2C,
395 .flags = IORESOURCE_IRQ
400 * I2C controller. The IXP46x uses the same block as the IOP3xx, so
401 * we just use the same device name.
403 static struct platform_device ixp46x_i2c_controller = {
404 .name = "IOP3xx-I2C",
407 .resource = ixp46x_i2c_resources
410 static struct platform_device *ixp46x_devices[] __initdata = {
411 &ixp46x_i2c_controller
414 unsigned long ixp4xx_exp_bus_size;
415 EXPORT_SYMBOL(ixp4xx_exp_bus_size);
417 static int ixp4xx_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
419 gpio_line_config(gpio, IXP4XX_GPIO_IN);
424 static int ixp4xx_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,
427 gpio_line_set(gpio, level);
428 gpio_line_config(gpio, IXP4XX_GPIO_OUT);
433 static int ixp4xx_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
437 gpio_line_get(gpio, &value);
442 static void ixp4xx_gpio_set_value(struct gpio_chip *chip, unsigned gpio,
445 gpio_line_set(gpio, value);
448 static struct gpio_chip ixp4xx_gpio_chip = {
449 .label = "IXP4XX_GPIO_CHIP",
450 .direction_input = ixp4xx_gpio_direction_input,
451 .direction_output = ixp4xx_gpio_direction_output,
452 .get = ixp4xx_gpio_get_value,
453 .set = ixp4xx_gpio_set_value,
454 .to_irq = ixp4xx_gpio_to_irq,
459 void __init ixp4xx_sys_init(void)
461 ixp4xx_exp_bus_size = SZ_16M;
463 platform_add_devices(ixp4xx_devices, ARRAY_SIZE(ixp4xx_devices));
465 gpiochip_add(&ixp4xx_gpio_chip);
467 if (cpu_is_ixp46x()) {
470 platform_add_devices(ixp46x_devices,
471 ARRAY_SIZE(ixp46x_devices));
473 for (region = 0; region < 7; region++) {
474 if((*(IXP4XX_EXP_REG(0x4 * region)) & 0x200)) {
475 ixp4xx_exp_bus_size = SZ_32M;
481 printk("IXP4xx: Using %luMiB expansion bus window size\n",
482 ixp4xx_exp_bus_size >> 20);
488 static u64 notrace ixp4xx_read_sched_clock(void)
497 static cycle_t ixp4xx_clocksource_read(struct clocksource *c)
502 unsigned long ixp4xx_timer_freq = IXP4XX_TIMER_FREQ;
503 EXPORT_SYMBOL(ixp4xx_timer_freq);
504 static void __init ixp4xx_clocksource_init(void)
506 sched_clock_register(ixp4xx_read_sched_clock, 32, ixp4xx_timer_freq);
508 clocksource_mmio_init(NULL, "OSTS", ixp4xx_timer_freq, 200, 32,
509 ixp4xx_clocksource_read);
515 static int ixp4xx_set_next_event(unsigned long evt,
516 struct clock_event_device *unused)
518 unsigned long opts = *IXP4XX_OSRT1 & IXP4XX_OST_RELOAD_MASK;
520 *IXP4XX_OSRT1 = (evt & ~IXP4XX_OST_RELOAD_MASK) | opts;
525 static void ixp4xx_set_mode(enum clock_event_mode mode,
526 struct clock_event_device *evt)
528 unsigned long opts = *IXP4XX_OSRT1 & IXP4XX_OST_RELOAD_MASK;
529 unsigned long osrt = *IXP4XX_OSRT1 & ~IXP4XX_OST_RELOAD_MASK;
532 case CLOCK_EVT_MODE_PERIODIC:
533 osrt = IXP4XX_LATCH & ~IXP4XX_OST_RELOAD_MASK;
534 opts = IXP4XX_OST_ENABLE;
536 case CLOCK_EVT_MODE_ONESHOT:
537 /* period set by 'set next_event' */
539 opts = IXP4XX_OST_ENABLE | IXP4XX_OST_ONE_SHOT;
541 case CLOCK_EVT_MODE_SHUTDOWN:
542 opts &= ~IXP4XX_OST_ENABLE;
544 case CLOCK_EVT_MODE_RESUME:
545 opts |= IXP4XX_OST_ENABLE;
547 case CLOCK_EVT_MODE_UNUSED:
553 *IXP4XX_OSRT1 = osrt | opts;
556 static struct clock_event_device clockevent_ixp4xx = {
557 .name = "ixp4xx timer1",
558 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
560 .set_mode = ixp4xx_set_mode,
561 .set_next_event = ixp4xx_set_next_event,
564 static void __init ixp4xx_clockevent_init(void)
566 clockevent_ixp4xx.cpumask = cpumask_of(0);
567 clockevents_config_and_register(&clockevent_ixp4xx, IXP4XX_TIMER_FREQ,
571 void ixp4xx_restart(enum reboot_mode mode, const char *cmd)
573 if (mode == REBOOT_SOFT) {
574 /* Jump into ROM at address 0 */
577 /* Use on-chip reset capability */
579 /* set the "key" register to enable access to
580 * "timer" and "enable" registers
582 *IXP4XX_OSWK = IXP4XX_WDT_KEY;
584 /* write 0 to the timer register for an immediate reset */
587 *IXP4XX_OSWE = IXP4XX_WDT_RESET_ENABLE | IXP4XX_WDT_COUNT_ENABLE;
591 #ifdef CONFIG_IXP4XX_INDIRECT_PCI
593 * In the case of using indirect PCI, we simply return the actual PCI
594 * address and our read/write implementation use that to drive the
595 * access registers. If something outside of PCI is ioremap'd, we
596 * fallback to the default.
599 static void __iomem *ixp4xx_ioremap_caller(phys_addr_t addr, size_t size,
600 unsigned int mtype, void *caller)
602 if (!is_pci_memory(addr))
603 return __arm_ioremap_caller(addr, size, mtype, caller);
605 return (void __iomem *)addr;
608 static void ixp4xx_iounmap(void __iomem *addr)
610 if (!is_pci_memory((__force u32)addr))
614 void __init ixp4xx_init_early(void)
616 arch_ioremap_caller = ixp4xx_ioremap_caller;
617 arch_iounmap = ixp4xx_iounmap;
620 void __init ixp4xx_init_early(void) {}