2 * arch/arm/mach-kirkwood/common.c
4 * Core functions for Marvell Kirkwood SoCs
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/platform_device.h>
14 #include <linux/serial_8250.h>
15 #include <linux/mbus.h>
16 #include <linux/mv643xx_eth.h>
17 #include <linux/mv643xx_i2c.h>
18 #include <linux/ata_platform.h>
19 #include <linux/mtd/nand.h>
20 #include <linux/spi/orion_spi.h>
23 #include <asm/timex.h>
24 #include <asm/mach/map.h>
25 #include <asm/mach/time.h>
26 #include <mach/kirkwood.h>
27 #include <mach/bridge-regs.h>
28 #include <plat/cache-feroceon-l2.h>
29 #include <plat/ehci-orion.h>
30 #include <plat/mvsdio.h>
31 #include <plat/mv_xor.h>
32 #include <plat/orion_nand.h>
33 #include <plat/orion_wdt.h>
34 #include <plat/time.h>
37 /*****************************************************************************
39 ****************************************************************************/
40 static struct map_desc kirkwood_io_desc[] __initdata = {
42 .virtual = KIRKWOOD_PCIE_IO_VIRT_BASE,
43 .pfn = __phys_to_pfn(KIRKWOOD_PCIE_IO_PHYS_BASE),
44 .length = KIRKWOOD_PCIE_IO_SIZE,
47 .virtual = KIRKWOOD_PCIE1_IO_VIRT_BASE,
48 .pfn = __phys_to_pfn(KIRKWOOD_PCIE1_IO_PHYS_BASE),
49 .length = KIRKWOOD_PCIE1_IO_SIZE,
52 .virtual = KIRKWOOD_REGS_VIRT_BASE,
53 .pfn = __phys_to_pfn(KIRKWOOD_REGS_PHYS_BASE),
54 .length = KIRKWOOD_REGS_SIZE,
59 void __init kirkwood_map_io(void)
61 iotable_init(kirkwood_io_desc, ARRAY_SIZE(kirkwood_io_desc));
65 * Default clock control bits. Any bit _not_ set in this variable
66 * will be cleared from the hardware after platform devices have been
67 * registered. Some reserved bits must be set to 1.
69 unsigned int kirkwood_clk_ctrl = CGC_DUNIT | CGC_RESERVED;
72 /*****************************************************************************
74 ****************************************************************************/
75 static struct orion_ehci_data kirkwood_ehci_data = {
76 .dram = &kirkwood_mbus_dram_info,
77 .phy_version = EHCI_PHY_NA,
80 static u64 ehci_dmamask = 0xffffffffUL;
83 /*****************************************************************************
85 ****************************************************************************/
86 static struct resource kirkwood_ehci_resources[] = {
88 .start = USB_PHYS_BASE,
89 .end = USB_PHYS_BASE + 0x0fff,
90 .flags = IORESOURCE_MEM,
92 .start = IRQ_KIRKWOOD_USB,
93 .end = IRQ_KIRKWOOD_USB,
94 .flags = IORESOURCE_IRQ,
98 static struct platform_device kirkwood_ehci = {
102 .dma_mask = &ehci_dmamask,
103 .coherent_dma_mask = 0xffffffff,
104 .platform_data = &kirkwood_ehci_data,
106 .resource = kirkwood_ehci_resources,
107 .num_resources = ARRAY_SIZE(kirkwood_ehci_resources),
110 void __init kirkwood_ehci_init(void)
112 kirkwood_clk_ctrl |= CGC_USB0;
113 platform_device_register(&kirkwood_ehci);
117 /*****************************************************************************
119 ****************************************************************************/
120 struct mv643xx_eth_shared_platform_data kirkwood_ge00_shared_data = {
121 .dram = &kirkwood_mbus_dram_info,
124 static struct resource kirkwood_ge00_shared_resources[] = {
127 .start = GE00_PHYS_BASE + 0x2000,
128 .end = GE00_PHYS_BASE + 0x3fff,
129 .flags = IORESOURCE_MEM,
131 .name = "ge00 err irq",
132 .start = IRQ_KIRKWOOD_GE00_ERR,
133 .end = IRQ_KIRKWOOD_GE00_ERR,
134 .flags = IORESOURCE_IRQ,
138 static struct platform_device kirkwood_ge00_shared = {
139 .name = MV643XX_ETH_SHARED_NAME,
142 .platform_data = &kirkwood_ge00_shared_data,
144 .num_resources = ARRAY_SIZE(kirkwood_ge00_shared_resources),
145 .resource = kirkwood_ge00_shared_resources,
148 static struct resource kirkwood_ge00_resources[] = {
151 .start = IRQ_KIRKWOOD_GE00_SUM,
152 .end = IRQ_KIRKWOOD_GE00_SUM,
153 .flags = IORESOURCE_IRQ,
157 static struct platform_device kirkwood_ge00 = {
158 .name = MV643XX_ETH_NAME,
161 .resource = kirkwood_ge00_resources,
163 .coherent_dma_mask = 0xffffffff,
167 void __init kirkwood_ge00_init(struct mv643xx_eth_platform_data *eth_data)
169 kirkwood_clk_ctrl |= CGC_GE0;
170 eth_data->shared = &kirkwood_ge00_shared;
171 kirkwood_ge00.dev.platform_data = eth_data;
173 platform_device_register(&kirkwood_ge00_shared);
174 platform_device_register(&kirkwood_ge00);
178 /*****************************************************************************
180 ****************************************************************************/
181 struct mv643xx_eth_shared_platform_data kirkwood_ge01_shared_data = {
182 .dram = &kirkwood_mbus_dram_info,
183 .shared_smi = &kirkwood_ge00_shared,
186 static struct resource kirkwood_ge01_shared_resources[] = {
189 .start = GE01_PHYS_BASE + 0x2000,
190 .end = GE01_PHYS_BASE + 0x3fff,
191 .flags = IORESOURCE_MEM,
193 .name = "ge01 err irq",
194 .start = IRQ_KIRKWOOD_GE01_ERR,
195 .end = IRQ_KIRKWOOD_GE01_ERR,
196 .flags = IORESOURCE_IRQ,
200 static struct platform_device kirkwood_ge01_shared = {
201 .name = MV643XX_ETH_SHARED_NAME,
204 .platform_data = &kirkwood_ge01_shared_data,
206 .num_resources = ARRAY_SIZE(kirkwood_ge01_shared_resources),
207 .resource = kirkwood_ge01_shared_resources,
210 static struct resource kirkwood_ge01_resources[] = {
213 .start = IRQ_KIRKWOOD_GE01_SUM,
214 .end = IRQ_KIRKWOOD_GE01_SUM,
215 .flags = IORESOURCE_IRQ,
219 static struct platform_device kirkwood_ge01 = {
220 .name = MV643XX_ETH_NAME,
223 .resource = kirkwood_ge01_resources,
225 .coherent_dma_mask = 0xffffffff,
229 void __init kirkwood_ge01_init(struct mv643xx_eth_platform_data *eth_data)
231 kirkwood_clk_ctrl |= CGC_GE1;
232 eth_data->shared = &kirkwood_ge01_shared;
233 kirkwood_ge01.dev.platform_data = eth_data;
235 platform_device_register(&kirkwood_ge01_shared);
236 platform_device_register(&kirkwood_ge01);
240 /*****************************************************************************
242 ****************************************************************************/
243 static struct resource kirkwood_switch_resources[] = {
247 .flags = IORESOURCE_IRQ,
251 static struct platform_device kirkwood_switch_device = {
255 .resource = kirkwood_switch_resources,
258 void __init kirkwood_ge00_switch_init(struct dsa_platform_data *d, int irq)
263 kirkwood_switch_resources[0].start = irq;
264 kirkwood_switch_resources[0].end = irq;
265 kirkwood_switch_device.num_resources = 1;
268 d->netdev = &kirkwood_ge00.dev;
269 for (i = 0; i < d->nr_chips; i++)
270 d->chip[i].mii_bus = &kirkwood_ge00_shared.dev;
271 kirkwood_switch_device.dev.platform_data = d;
273 platform_device_register(&kirkwood_switch_device);
277 /*****************************************************************************
279 ****************************************************************************/
280 static struct resource kirkwood_nand_resource = {
281 .flags = IORESOURCE_MEM,
282 .start = KIRKWOOD_NAND_MEM_PHYS_BASE,
283 .end = KIRKWOOD_NAND_MEM_PHYS_BASE +
284 KIRKWOOD_NAND_MEM_SIZE - 1,
287 static struct orion_nand_data kirkwood_nand_data = {
293 static struct platform_device kirkwood_nand_flash = {
294 .name = "orion_nand",
297 .platform_data = &kirkwood_nand_data,
299 .resource = &kirkwood_nand_resource,
303 void __init kirkwood_nand_init(struct mtd_partition *parts, int nr_parts,
306 kirkwood_clk_ctrl |= CGC_RUNIT;
307 kirkwood_nand_data.parts = parts;
308 kirkwood_nand_data.nr_parts = nr_parts;
309 kirkwood_nand_data.chip_delay = chip_delay;
310 platform_device_register(&kirkwood_nand_flash);
313 void __init kirkwood_nand_init_rnb(struct mtd_partition *parts, int nr_parts,
314 int (*dev_ready)(struct mtd_info *))
316 kirkwood_clk_ctrl |= CGC_RUNIT;
317 kirkwood_nand_data.parts = parts;
318 kirkwood_nand_data.nr_parts = nr_parts;
319 kirkwood_nand_data.dev_ready = dev_ready;
320 platform_device_register(&kirkwood_nand_flash);
323 /*****************************************************************************
325 ****************************************************************************/
326 static struct resource kirkwood_rtc_resource = {
327 .start = RTC_PHYS_BASE,
328 .end = RTC_PHYS_BASE + SZ_16 - 1,
329 .flags = IORESOURCE_MEM,
332 static void __init kirkwood_rtc_init(void)
334 platform_device_register_simple("rtc-mv", -1, &kirkwood_rtc_resource, 1);
338 /*****************************************************************************
340 ****************************************************************************/
341 static struct resource kirkwood_sata_resources[] = {
344 .start = SATA_PHYS_BASE,
345 .end = SATA_PHYS_BASE + 0x5000 - 1,
346 .flags = IORESOURCE_MEM,
349 .start = IRQ_KIRKWOOD_SATA,
350 .end = IRQ_KIRKWOOD_SATA,
351 .flags = IORESOURCE_IRQ,
355 static struct platform_device kirkwood_sata = {
359 .coherent_dma_mask = 0xffffffff,
361 .num_resources = ARRAY_SIZE(kirkwood_sata_resources),
362 .resource = kirkwood_sata_resources,
365 void __init kirkwood_sata_init(struct mv_sata_platform_data *sata_data)
367 kirkwood_clk_ctrl |= CGC_SATA0;
368 if (sata_data->n_ports > 1)
369 kirkwood_clk_ctrl |= CGC_SATA1;
370 sata_data->dram = &kirkwood_mbus_dram_info;
371 kirkwood_sata.dev.platform_data = sata_data;
372 platform_device_register(&kirkwood_sata);
376 /*****************************************************************************
378 ****************************************************************************/
379 static struct resource mvsdio_resources[] = {
381 .start = SDIO_PHYS_BASE,
382 .end = SDIO_PHYS_BASE + SZ_1K - 1,
383 .flags = IORESOURCE_MEM,
386 .start = IRQ_KIRKWOOD_SDIO,
387 .end = IRQ_KIRKWOOD_SDIO,
388 .flags = IORESOURCE_IRQ,
392 static u64 mvsdio_dmamask = 0xffffffffUL;
394 static struct platform_device kirkwood_sdio = {
398 .dma_mask = &mvsdio_dmamask,
399 .coherent_dma_mask = 0xffffffff,
401 .num_resources = ARRAY_SIZE(mvsdio_resources),
402 .resource = mvsdio_resources,
405 void __init kirkwood_sdio_init(struct mvsdio_platform_data *mvsdio_data)
409 kirkwood_pcie_id(&dev, &rev);
410 if (rev == 0 && dev != MV88F6282_DEV_ID) /* catch all Kirkwood Z0's */
411 mvsdio_data->clock = 100000000;
413 mvsdio_data->clock = 200000000;
414 mvsdio_data->dram = &kirkwood_mbus_dram_info;
415 kirkwood_clk_ctrl |= CGC_SDIO;
416 kirkwood_sdio.dev.platform_data = mvsdio_data;
417 platform_device_register(&kirkwood_sdio);
421 /*****************************************************************************
423 ****************************************************************************/
424 static struct orion_spi_info kirkwood_spi_plat_data = {
427 static struct resource kirkwood_spi_resources[] = {
429 .start = SPI_PHYS_BASE,
430 .end = SPI_PHYS_BASE + SZ_512 - 1,
431 .flags = IORESOURCE_MEM,
435 static struct platform_device kirkwood_spi = {
438 .resource = kirkwood_spi_resources,
440 .platform_data = &kirkwood_spi_plat_data,
442 .num_resources = ARRAY_SIZE(kirkwood_spi_resources),
445 void __init kirkwood_spi_init()
447 kirkwood_clk_ctrl |= CGC_RUNIT;
448 platform_device_register(&kirkwood_spi);
452 /*****************************************************************************
454 ****************************************************************************/
455 static struct mv64xxx_i2c_pdata kirkwood_i2c_pdata = {
456 .freq_m = 8, /* assumes 166 MHz TCLK */
458 .timeout = 1000, /* Default timeout of 1 second */
461 static struct resource kirkwood_i2c_resources[] = {
463 .start = I2C_PHYS_BASE,
464 .end = I2C_PHYS_BASE + 0x1f,
465 .flags = IORESOURCE_MEM,
467 .start = IRQ_KIRKWOOD_TWSI,
468 .end = IRQ_KIRKWOOD_TWSI,
469 .flags = IORESOURCE_IRQ,
473 static struct platform_device kirkwood_i2c = {
474 .name = MV64XXX_I2C_CTLR_NAME,
476 .num_resources = ARRAY_SIZE(kirkwood_i2c_resources),
477 .resource = kirkwood_i2c_resources,
479 .platform_data = &kirkwood_i2c_pdata,
483 void __init kirkwood_i2c_init(void)
485 platform_device_register(&kirkwood_i2c);
489 /*****************************************************************************
491 ****************************************************************************/
492 static struct plat_serial8250_port kirkwood_uart0_data[] = {
494 .mapbase = UART0_PHYS_BASE,
495 .membase = (char *)UART0_VIRT_BASE,
496 .irq = IRQ_KIRKWOOD_UART_0,
497 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
505 static struct resource kirkwood_uart0_resources[] = {
507 .start = UART0_PHYS_BASE,
508 .end = UART0_PHYS_BASE + 0xff,
509 .flags = IORESOURCE_MEM,
511 .start = IRQ_KIRKWOOD_UART_0,
512 .end = IRQ_KIRKWOOD_UART_0,
513 .flags = IORESOURCE_IRQ,
517 static struct platform_device kirkwood_uart0 = {
518 .name = "serial8250",
521 .platform_data = kirkwood_uart0_data,
523 .resource = kirkwood_uart0_resources,
524 .num_resources = ARRAY_SIZE(kirkwood_uart0_resources),
527 void __init kirkwood_uart0_init(void)
529 platform_device_register(&kirkwood_uart0);
533 /*****************************************************************************
535 ****************************************************************************/
536 static struct plat_serial8250_port kirkwood_uart1_data[] = {
538 .mapbase = UART1_PHYS_BASE,
539 .membase = (char *)UART1_VIRT_BASE,
540 .irq = IRQ_KIRKWOOD_UART_1,
541 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
549 static struct resource kirkwood_uart1_resources[] = {
551 .start = UART1_PHYS_BASE,
552 .end = UART1_PHYS_BASE + 0xff,
553 .flags = IORESOURCE_MEM,
555 .start = IRQ_KIRKWOOD_UART_1,
556 .end = IRQ_KIRKWOOD_UART_1,
557 .flags = IORESOURCE_IRQ,
561 static struct platform_device kirkwood_uart1 = {
562 .name = "serial8250",
565 .platform_data = kirkwood_uart1_data,
567 .resource = kirkwood_uart1_resources,
568 .num_resources = ARRAY_SIZE(kirkwood_uart1_resources),
571 void __init kirkwood_uart1_init(void)
573 platform_device_register(&kirkwood_uart1);
577 /*****************************************************************************
578 * Cryptographic Engines and Security Accelerator (CESA)
579 ****************************************************************************/
581 static struct resource kirkwood_crypto_res[] = {
584 .start = CRYPTO_PHYS_BASE,
585 .end = CRYPTO_PHYS_BASE + 0xffff,
586 .flags = IORESOURCE_MEM,
589 .start = KIRKWOOD_SRAM_PHYS_BASE,
590 .end = KIRKWOOD_SRAM_PHYS_BASE + KIRKWOOD_SRAM_SIZE - 1,
591 .flags = IORESOURCE_MEM,
593 .name = "crypto interrupt",
594 .start = IRQ_KIRKWOOD_CRYPTO,
595 .end = IRQ_KIRKWOOD_CRYPTO,
596 .flags = IORESOURCE_IRQ,
600 static struct platform_device kirkwood_crypto_device = {
603 .num_resources = ARRAY_SIZE(kirkwood_crypto_res),
604 .resource = kirkwood_crypto_res,
607 void __init kirkwood_crypto_init(void)
609 kirkwood_clk_ctrl |= CGC_CRYPTO;
610 platform_device_register(&kirkwood_crypto_device);
614 /*****************************************************************************
616 ****************************************************************************/
617 static struct mv_xor_platform_shared_data kirkwood_xor_shared_data = {
618 .dram = &kirkwood_mbus_dram_info,
621 static u64 kirkwood_xor_dmamask = DMA_BIT_MASK(32);
624 /*****************************************************************************
626 ****************************************************************************/
627 static struct resource kirkwood_xor0_shared_resources[] = {
630 .start = XOR0_PHYS_BASE,
631 .end = XOR0_PHYS_BASE + 0xff,
632 .flags = IORESOURCE_MEM,
634 .name = "xor 0 high",
635 .start = XOR0_HIGH_PHYS_BASE,
636 .end = XOR0_HIGH_PHYS_BASE + 0xff,
637 .flags = IORESOURCE_MEM,
641 static struct platform_device kirkwood_xor0_shared = {
642 .name = MV_XOR_SHARED_NAME,
645 .platform_data = &kirkwood_xor_shared_data,
647 .num_resources = ARRAY_SIZE(kirkwood_xor0_shared_resources),
648 .resource = kirkwood_xor0_shared_resources,
651 static struct resource kirkwood_xor00_resources[] = {
653 .start = IRQ_KIRKWOOD_XOR_00,
654 .end = IRQ_KIRKWOOD_XOR_00,
655 .flags = IORESOURCE_IRQ,
659 static struct mv_xor_platform_data kirkwood_xor00_data = {
660 .shared = &kirkwood_xor0_shared,
662 .pool_size = PAGE_SIZE,
665 static struct platform_device kirkwood_xor00_channel = {
668 .num_resources = ARRAY_SIZE(kirkwood_xor00_resources),
669 .resource = kirkwood_xor00_resources,
671 .dma_mask = &kirkwood_xor_dmamask,
672 .coherent_dma_mask = DMA_BIT_MASK(64),
673 .platform_data = &kirkwood_xor00_data,
677 static struct resource kirkwood_xor01_resources[] = {
679 .start = IRQ_KIRKWOOD_XOR_01,
680 .end = IRQ_KIRKWOOD_XOR_01,
681 .flags = IORESOURCE_IRQ,
685 static struct mv_xor_platform_data kirkwood_xor01_data = {
686 .shared = &kirkwood_xor0_shared,
688 .pool_size = PAGE_SIZE,
691 static struct platform_device kirkwood_xor01_channel = {
694 .num_resources = ARRAY_SIZE(kirkwood_xor01_resources),
695 .resource = kirkwood_xor01_resources,
697 .dma_mask = &kirkwood_xor_dmamask,
698 .coherent_dma_mask = DMA_BIT_MASK(64),
699 .platform_data = &kirkwood_xor01_data,
703 static void __init kirkwood_xor0_init(void)
705 kirkwood_clk_ctrl |= CGC_XOR0;
706 platform_device_register(&kirkwood_xor0_shared);
709 * two engines can't do memset simultaneously, this limitation
710 * satisfied by removing memset support from one of the engines.
712 dma_cap_set(DMA_MEMCPY, kirkwood_xor00_data.cap_mask);
713 dma_cap_set(DMA_XOR, kirkwood_xor00_data.cap_mask);
714 platform_device_register(&kirkwood_xor00_channel);
716 dma_cap_set(DMA_MEMCPY, kirkwood_xor01_data.cap_mask);
717 dma_cap_set(DMA_MEMSET, kirkwood_xor01_data.cap_mask);
718 dma_cap_set(DMA_XOR, kirkwood_xor01_data.cap_mask);
719 platform_device_register(&kirkwood_xor01_channel);
723 /*****************************************************************************
725 ****************************************************************************/
726 static struct resource kirkwood_xor1_shared_resources[] = {
729 .start = XOR1_PHYS_BASE,
730 .end = XOR1_PHYS_BASE + 0xff,
731 .flags = IORESOURCE_MEM,
733 .name = "xor 1 high",
734 .start = XOR1_HIGH_PHYS_BASE,
735 .end = XOR1_HIGH_PHYS_BASE + 0xff,
736 .flags = IORESOURCE_MEM,
740 static struct platform_device kirkwood_xor1_shared = {
741 .name = MV_XOR_SHARED_NAME,
744 .platform_data = &kirkwood_xor_shared_data,
746 .num_resources = ARRAY_SIZE(kirkwood_xor1_shared_resources),
747 .resource = kirkwood_xor1_shared_resources,
750 static struct resource kirkwood_xor10_resources[] = {
752 .start = IRQ_KIRKWOOD_XOR_10,
753 .end = IRQ_KIRKWOOD_XOR_10,
754 .flags = IORESOURCE_IRQ,
758 static struct mv_xor_platform_data kirkwood_xor10_data = {
759 .shared = &kirkwood_xor1_shared,
761 .pool_size = PAGE_SIZE,
764 static struct platform_device kirkwood_xor10_channel = {
767 .num_resources = ARRAY_SIZE(kirkwood_xor10_resources),
768 .resource = kirkwood_xor10_resources,
770 .dma_mask = &kirkwood_xor_dmamask,
771 .coherent_dma_mask = DMA_BIT_MASK(64),
772 .platform_data = &kirkwood_xor10_data,
776 static struct resource kirkwood_xor11_resources[] = {
778 .start = IRQ_KIRKWOOD_XOR_11,
779 .end = IRQ_KIRKWOOD_XOR_11,
780 .flags = IORESOURCE_IRQ,
784 static struct mv_xor_platform_data kirkwood_xor11_data = {
785 .shared = &kirkwood_xor1_shared,
787 .pool_size = PAGE_SIZE,
790 static struct platform_device kirkwood_xor11_channel = {
793 .num_resources = ARRAY_SIZE(kirkwood_xor11_resources),
794 .resource = kirkwood_xor11_resources,
796 .dma_mask = &kirkwood_xor_dmamask,
797 .coherent_dma_mask = DMA_BIT_MASK(64),
798 .platform_data = &kirkwood_xor11_data,
802 static void __init kirkwood_xor1_init(void)
804 kirkwood_clk_ctrl |= CGC_XOR1;
805 platform_device_register(&kirkwood_xor1_shared);
808 * two engines can't do memset simultaneously, this limitation
809 * satisfied by removing memset support from one of the engines.
811 dma_cap_set(DMA_MEMCPY, kirkwood_xor10_data.cap_mask);
812 dma_cap_set(DMA_XOR, kirkwood_xor10_data.cap_mask);
813 platform_device_register(&kirkwood_xor10_channel);
815 dma_cap_set(DMA_MEMCPY, kirkwood_xor11_data.cap_mask);
816 dma_cap_set(DMA_MEMSET, kirkwood_xor11_data.cap_mask);
817 dma_cap_set(DMA_XOR, kirkwood_xor11_data.cap_mask);
818 platform_device_register(&kirkwood_xor11_channel);
822 /*****************************************************************************
824 ****************************************************************************/
825 static struct orion_wdt_platform_data kirkwood_wdt_data = {
829 static struct platform_device kirkwood_wdt_device = {
833 .platform_data = &kirkwood_wdt_data,
838 static void __init kirkwood_wdt_init(void)
840 kirkwood_wdt_data.tclk = kirkwood_tclk;
841 platform_device_register(&kirkwood_wdt_device);
845 /*****************************************************************************
847 ****************************************************************************/
850 int __init kirkwood_find_tclk(void)
854 kirkwood_pcie_id(&dev, &rev);
856 if ((dev == MV88F6281_DEV_ID && (rev == MV88F6281_REV_A0 ||
857 rev == MV88F6281_REV_A1)) ||
858 (dev == MV88F6282_DEV_ID))
864 static void __init kirkwood_timer_init(void)
866 kirkwood_tclk = kirkwood_find_tclk();
867 orion_time_init(IRQ_KIRKWOOD_BRIDGE, kirkwood_tclk);
870 struct sys_timer kirkwood_timer = {
871 .init = kirkwood_timer_init,
875 /*****************************************************************************
877 ****************************************************************************/
879 * Identify device ID and revision.
881 static char * __init kirkwood_id(void)
885 kirkwood_pcie_id(&dev, &rev);
887 if (dev == MV88F6281_DEV_ID) {
888 if (rev == MV88F6281_REV_Z0)
889 return "MV88F6281-Z0";
890 else if (rev == MV88F6281_REV_A0)
891 return "MV88F6281-A0";
892 else if (rev == MV88F6281_REV_A1)
893 return "MV88F6281-A1";
895 return "MV88F6281-Rev-Unsupported";
896 } else if (dev == MV88F6192_DEV_ID) {
897 if (rev == MV88F6192_REV_Z0)
898 return "MV88F6192-Z0";
899 else if (rev == MV88F6192_REV_A0)
900 return "MV88F6192-A0";
901 else if (rev == MV88F6192_REV_A1)
902 return "MV88F6192-A1";
904 return "MV88F6192-Rev-Unsupported";
905 } else if (dev == MV88F6180_DEV_ID) {
906 if (rev == MV88F6180_REV_A0)
907 return "MV88F6180-Rev-A0";
908 else if (rev == MV88F6180_REV_A1)
909 return "MV88F6180-Rev-A1";
911 return "MV88F6180-Rev-Unsupported";
912 } else if (dev == MV88F6282_DEV_ID) {
913 if (rev == MV88F6282_REV_A0)
914 return "MV88F6282-Rev-A0";
916 return "MV88F6282-Rev-Unsupported";
918 return "Device-Unknown";
922 static void __init kirkwood_l2_init(void)
924 #ifdef CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH
925 writel(readl(L2_CONFIG_REG) | L2_WRITETHROUGH, L2_CONFIG_REG);
928 writel(readl(L2_CONFIG_REG) & ~L2_WRITETHROUGH, L2_CONFIG_REG);
933 void __init kirkwood_init(void)
935 printk(KERN_INFO "Kirkwood: %s, TCLK=%d.\n",
936 kirkwood_id(), kirkwood_tclk);
937 kirkwood_ge00_shared_data.t_clk = kirkwood_tclk;
938 kirkwood_ge01_shared_data.t_clk = kirkwood_tclk;
939 kirkwood_spi_plat_data.tclk = kirkwood_tclk;
940 kirkwood_uart0_data[0].uartclk = kirkwood_tclk;
941 kirkwood_uart1_data[0].uartclk = kirkwood_tclk;
944 * Disable propagation of mbus errors to the CPU local bus,
945 * as this causes mbus errors (which can occur for example
946 * for PCI aborts) to throw CPU aborts, which we're not set
949 writel(readl(CPU_CONFIG) & ~CPU_CONFIG_ERROR_PROP, CPU_CONFIG);
951 kirkwood_setup_cpu_mbus();
953 #ifdef CONFIG_CACHE_FEROCEON_L2
957 /* internal devices that every board has */
960 kirkwood_xor0_init();
961 kirkwood_xor1_init();
962 kirkwood_crypto_init();
965 static int __init kirkwood_clock_gate(void)
967 unsigned int curr = readl(CLOCK_GATING_CTRL);
970 kirkwood_pcie_id(&dev, &rev);
971 printk(KERN_DEBUG "Gating clock of unused units\n");
972 printk(KERN_DEBUG "before: 0x%08x\n", curr);
974 /* Make sure those units are accessible */
975 writel(curr | CGC_SATA0 | CGC_SATA1 | CGC_PEX0 | CGC_PEX1, CLOCK_GATING_CTRL);
977 /* For SATA: first shutdown the phy */
978 if (!(kirkwood_clk_ctrl & CGC_SATA0)) {
979 /* Disable PLL and IVREF */
980 writel(readl(SATA0_PHY_MODE_2) & ~0xf, SATA0_PHY_MODE_2);
982 writel(readl(SATA0_IF_CTRL) | 0x200, SATA0_IF_CTRL);
984 if (!(kirkwood_clk_ctrl & CGC_SATA1)) {
985 /* Disable PLL and IVREF */
986 writel(readl(SATA1_PHY_MODE_2) & ~0xf, SATA1_PHY_MODE_2);
988 writel(readl(SATA1_IF_CTRL) | 0x200, SATA1_IF_CTRL);
991 /* For PCIe: first shutdown the phy */
992 if (!(kirkwood_clk_ctrl & CGC_PEX0)) {
993 writel(readl(PCIE_LINK_CTRL) | 0x10, PCIE_LINK_CTRL);
995 if (readl(PCIE_STATUS) & 0x1)
997 writel(readl(PCIE_LINK_CTRL) & ~0x10, PCIE_LINK_CTRL);
1000 /* For PCIe 1: first shutdown the phy */
1001 if (dev == MV88F6282_DEV_ID) {
1002 if (!(kirkwood_clk_ctrl & CGC_PEX1)) {
1003 writel(readl(PCIE1_LINK_CTRL) | 0x10, PCIE1_LINK_CTRL);
1005 if (readl(PCIE1_STATUS) & 0x1)
1007 writel(readl(PCIE1_LINK_CTRL) & ~0x10, PCIE1_LINK_CTRL);
1009 } else /* keep this bit set for devices that don't have PCIe1 */
1010 kirkwood_clk_ctrl |= CGC_PEX1;
1012 /* Now gate clock the required units */
1013 writel(kirkwood_clk_ctrl, CLOCK_GATING_CTRL);
1014 printk(KERN_DEBUG " after: 0x%08x\n", readl(CLOCK_GATING_CTRL));
1018 late_initcall(kirkwood_clock_gate);