2 * arch/arm/mach-kirkwood/include/mach/kirkwood.h
4 * Generic definitions for Marvell Kirkwood SoC flavors:
5 * 88F6180, 88F6192 and 88F6281.
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
12 #ifndef __ASM_ARCH_KIRKWOOD_H
13 #define __ASM_ARCH_KIRKWOOD_H
16 * Marvell Kirkwood address maps.
19 * e0000000 PCIe Memory space
20 * f1000000 on-chip peripheral registers
21 * f2000000 PCIe I/O space
22 * f3000000 NAND controller address window
25 * fee00000 f1000000 1M on-chip peripheral registers
26 * fef00000 f2000000 1M PCIe I/O space
29 #define KIRKWOOD_NAND_MEM_PHYS_BASE 0xf3000000
30 #define KIRKWOOD_NAND_MEM_SIZE SZ_1K
32 #define KIRKWOOD_PCIE_IO_PHYS_BASE 0xf2000000
33 #define KIRKWOOD_PCIE_IO_VIRT_BASE 0xfef00000
34 #define KIRKWOOD_PCIE_IO_BUS_BASE 0x00000000
35 #define KIRKWOOD_PCIE_IO_SIZE SZ_1M
37 #define KIRKWOOD_REGS_PHYS_BASE 0xf1000000
38 #define KIRKWOOD_REGS_VIRT_BASE 0xfee00000
39 #define KIRKWOOD_REGS_SIZE SZ_1M
41 #define KIRKWOOD_PCIE_MEM_PHYS_BASE 0xe0000000
42 #define KIRKWOOD_PCIE_MEM_SIZE SZ_128M
47 #define DDR_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x00000)
48 #define DDR_WINDOW_CPU_BASE (DDR_VIRT_BASE | 0x1500)
49 #define DDR_OPERATION_BASE (DDR_VIRT_BASE | 0x1418)
51 #define DEV_BUS_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x10000)
52 #define DEV_BUS_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x10000)
53 #define SAMPLE_AT_RESET (DEV_BUS_VIRT_BASE | 0x0030)
54 #define DEVICE_ID (DEV_BUS_VIRT_BASE | 0x0034)
55 #define RTC_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x0300)
56 #define SPI_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x0600)
57 #define I2C_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x1000)
58 #define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2000)
59 #define UART0_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2000)
60 #define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2100)
61 #define UART1_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2100)
63 #define BRIDGE_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x20000)
65 #define PCIE_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x40000)
66 #define PCIE_LINK_CTRL (PCIE_VIRT_BASE | 0x70)
67 #define PCIE_STATUS (PCIE_VIRT_BASE | 0x1a04)
69 #define USB_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x50000)
71 #define XOR0_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x60800)
72 #define XOR0_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x60800)
73 #define XOR1_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x60900)
74 #define XOR1_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x60900)
75 #define XOR0_HIGH_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x60A00)
76 #define XOR0_HIGH_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x60A00)
77 #define XOR1_HIGH_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x60B00)
78 #define XOR1_HIGH_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x60B00)
80 #define GE00_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x70000)
81 #define GE01_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x74000)
83 #define SATA_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x80000)
84 #define SATA_VIRT_BASE (KIRKWOOD_REGS_VIRT_BASE | 0x80000)
85 #define SATA0_IF_CTRL (SATA_VIRT_BASE | 0x2050)
86 #define SATA0_PHY_MODE_2 (SATA_VIRT_BASE | 0x2330)
87 #define SATA1_IF_CTRL (SATA_VIRT_BASE | 0x4050)
88 #define SATA1_PHY_MODE_2 (SATA_VIRT_BASE | 0x4330)
90 #define SDIO_PHYS_BASE (KIRKWOOD_REGS_PHYS_BASE | 0x90000)
93 * Supported devices and revisions.
95 #define MV88F6281_DEV_ID 0x6281
96 #define MV88F6281_REV_Z0 0
97 #define MV88F6281_REV_A0 2
99 #define MV88F6192_DEV_ID 0x6192
100 #define MV88F6192_REV_Z0 0
101 #define MV88F6192_REV_A0 2
103 #define MV88F6180_DEV_ID 0x6180
104 #define MV88F6180_REV_A0 2