2 * arch/arm/mach-kirkwood/pcie.c
4 * PCIe functions for Marvell Kirkwood SoCs
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
11 #include <linux/kernel.h>
12 #include <linux/pci.h>
13 #include <linux/slab.h>
14 #include <linux/mbus.h>
15 #include <video/vga.h>
17 #include <asm/mach/pci.h>
18 #include <plat/pcie.h>
19 #include <mach/bridge-regs.h>
22 void kirkwood_enable_pcie(void)
24 u32 curr = readl(CLOCK_GATING_CTRL);
25 if (!(curr & CGC_PEX0))
26 writel(curr | CGC_PEX0, CLOCK_GATING_CTRL);
29 void __init kirkwood_pcie_id(u32 *dev, u32 *rev)
31 kirkwood_enable_pcie();
32 *dev = orion_pcie_dev_id((void __iomem *)PCIE_VIRT_BASE);
33 *rev = orion_pcie_rev((void __iomem *)PCIE_VIRT_BASE);
41 struct resource res[2];
44 static int pcie_port_map[2];
45 static int num_pcie_ports;
47 static inline struct pcie_port *bus_to_port(struct pci_bus *bus)
49 struct pci_sys_data *sys = bus->sysdata;
50 return sys->private_data;
53 static int pcie_valid_config(struct pcie_port *pp, int bus, int dev)
56 * Don't go out when trying to access --
57 * 1. nonexisting device on local bus
58 * 2. where there's no device connected (no link)
60 if (bus == pp->root_bus_nr && dev == 0)
63 if (!orion_pcie_link_up(pp->base))
66 if (bus == pp->root_bus_nr && dev != 1)
74 * PCIe config cycles are done by programming the PCIE_CONF_ADDR register
75 * and then reading the PCIE_CONF_DATA register. Need to make sure these
76 * transactions are atomic.
79 static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
82 struct pcie_port *pp = bus_to_port(bus);
86 if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0) {
88 return PCIBIOS_DEVICE_NOT_FOUND;
91 spin_lock_irqsave(&pp->conf_lock, flags);
92 ret = orion_pcie_rd_conf(pp->base, bus, devfn, where, size, val);
93 spin_unlock_irqrestore(&pp->conf_lock, flags);
98 static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
99 int where, int size, u32 val)
101 struct pcie_port *pp = bus_to_port(bus);
105 if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0)
106 return PCIBIOS_DEVICE_NOT_FOUND;
108 spin_lock_irqsave(&pp->conf_lock, flags);
109 ret = orion_pcie_wr_conf(pp->base, bus, devfn, where, size, val);
110 spin_unlock_irqrestore(&pp->conf_lock, flags);
115 static struct pci_ops pcie_ops = {
116 .read = pcie_rd_conf,
117 .write = pcie_wr_conf,
120 static void __init pcie0_ioresources_init(struct pcie_port *pp)
122 pp->base = (void __iomem *)PCIE_VIRT_BASE;
123 pp->irq = IRQ_KIRKWOOD_PCIE;
128 pp->res[0].name = "PCIe 0 I/O Space";
129 pp->res[0].start = KIRKWOOD_PCIE_IO_BUS_BASE;
130 pp->res[0].end = pp->res[0].start + KIRKWOOD_PCIE_IO_SIZE - 1;
131 pp->res[0].flags = IORESOURCE_IO;
136 pp->res[1].name = "PCIe 0 MEM";
137 pp->res[1].start = KIRKWOOD_PCIE_MEM_PHYS_BASE;
138 pp->res[1].end = pp->res[1].start + KIRKWOOD_PCIE_MEM_SIZE - 1;
139 pp->res[1].flags = IORESOURCE_MEM;
142 static void __init pcie1_ioresources_init(struct pcie_port *pp)
144 pp->base = (void __iomem *)PCIE1_VIRT_BASE;
145 pp->irq = IRQ_KIRKWOOD_PCIE1;
150 pp->res[0].name = "PCIe 1 I/O Space";
151 pp->res[0].start = KIRKWOOD_PCIE1_IO_BUS_BASE;
152 pp->res[0].end = pp->res[0].start + KIRKWOOD_PCIE1_IO_SIZE - 1;
153 pp->res[0].flags = IORESOURCE_IO;
158 pp->res[1].name = "PCIe 1 MEM";
159 pp->res[1].start = KIRKWOOD_PCIE1_MEM_PHYS_BASE;
160 pp->res[1].end = pp->res[1].start + KIRKWOOD_PCIE1_MEM_SIZE - 1;
161 pp->res[1].flags = IORESOURCE_MEM;
164 static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys)
166 extern unsigned int kirkwood_clk_ctrl;
167 struct pcie_port *pp;
170 if (nr >= num_pcie_ports)
173 index = pcie_port_map[nr];
174 printk(KERN_INFO "PCI: bus%d uses PCIe port %d\n", sys->busnr, index);
176 pp = kzalloc(sizeof(*pp), GFP_KERNEL);
178 panic("PCIe: failed to allocate pcie_port data");
179 sys->private_data = pp;
180 pp->root_bus_nr = sys->busnr;
181 spin_lock_init(&pp->conf_lock);
185 kirkwood_clk_ctrl |= CGC_PEX0;
186 pcie0_ioresources_init(pp);
189 kirkwood_clk_ctrl |= CGC_PEX1;
190 pcie1_ioresources_init(pp);
193 panic("PCIe setup: invalid controller %d", index);
196 if (request_resource(&ioport_resource, &pp->res[0]))
197 panic("Request PCIe%d IO resource failed\n", index);
198 if (request_resource(&iomem_resource, &pp->res[1]))
199 panic("Request PCIe%d Memory resource failed\n", index);
201 sys->resource[0] = &pp->res[0];
202 sys->resource[1] = &pp->res[1];
203 sys->resource[2] = NULL;
207 * Generic PCIe unit setup.
209 orion_pcie_set_local_bus_nr(pp->base, sys->busnr);
211 orion_pcie_setup(pp->base, &kirkwood_mbus_dram_info);
216 static void __devinit rc_pci_fixup(struct pci_dev *dev)
219 * Prevent enumeration of root complex.
221 if (dev->bus->parent == NULL && dev->devfn == 0) {
224 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
225 dev->resource[i].start = 0;
226 dev->resource[i].end = 0;
227 dev->resource[i].flags = 0;
231 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup);
233 static struct pci_bus __init *
234 kirkwood_pcie_scan_bus(int nr, struct pci_sys_data *sys)
238 if (nr < num_pcie_ports) {
239 bus = pci_scan_bus(sys->busnr, &pcie_ops, sys);
248 static int __init kirkwood_pcie_map_irq(const struct pci_dev *dev, u8 slot,
251 struct pcie_port *pp = bus_to_port(dev->bus);
256 static struct hw_pci kirkwood_pci __initdata = {
257 .swizzle = pci_std_swizzle,
258 .setup = kirkwood_pcie_setup,
259 .scan = kirkwood_pcie_scan_bus,
260 .map_irq = kirkwood_pcie_map_irq,
263 static void __init add_pcie_port(int index, unsigned long base)
265 printk(KERN_INFO "Kirkwood PCIe port %d: ", index);
267 if (orion_pcie_link_up((void __iomem *)base)) {
268 printk(KERN_INFO "link up\n");
269 pcie_port_map[num_pcie_ports++] = index;
271 printk(KERN_INFO "link down, ignoring\n");
274 void __init kirkwood_pcie_init(unsigned int portmask)
276 vga_base = KIRKWOOD_PCIE_MEM_PHYS_BASE;
278 if (portmask & KW_PCIE0)
279 add_pcie_port(0, PCIE_VIRT_BASE);
281 if (portmask & KW_PCIE1)
282 add_pcie_port(1, PCIE1_VIRT_BASE);
284 kirkwood_pci.nr_controllers = num_pcie_ports;
285 pci_common_init(&kirkwood_pci);