2 * arch/arm/mach-kirkwood/pcie.c
4 * PCIe functions for Marvell Kirkwood SoCs
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
11 #include <linux/kernel.h>
12 #include <linux/pci.h>
13 #include <linux/slab.h>
14 #include <linux/clk.h>
15 #include <video/vga.h>
17 #include <asm/mach/pci.h>
18 #include <plat/pcie.h>
19 #include <mach/bridge-regs.h>
20 #include <plat/addr-map.h>
23 static void kirkwood_enable_pcie_clk(const char *port)
27 clk = clk_get_sys("pcie", port);
29 printk(KERN_ERR "PCIE clock %s missing\n", port);
32 clk_prepare_enable(clk);
36 /* This function is called very early in the boot when probing the
37 hardware to determine what we actually are, and what rate tclk is
38 ticking at. Hence calling kirkwood_enable_pcie_clk() is not
39 possible since the clk tree has not been created yet. */
40 void kirkwood_enable_pcie(void)
42 u32 curr = readl(CLOCK_GATING_CTRL);
43 if (!(curr & CGC_PEX0))
44 writel(curr | CGC_PEX0, CLOCK_GATING_CTRL);
47 void kirkwood_pcie_id(u32 *dev, u32 *rev)
49 kirkwood_enable_pcie();
50 *dev = orion_pcie_dev_id((void __iomem *)PCIE_VIRT_BASE);
51 *rev = orion_pcie_rev((void __iomem *)PCIE_VIRT_BASE);
59 struct resource res[2];
62 static int pcie_port_map[2];
63 static int num_pcie_ports;
65 static int pcie_valid_config(struct pcie_port *pp, int bus, int dev)
68 * Don't go out when trying to access --
69 * 1. nonexisting device on local bus
70 * 2. where there's no device connected (no link)
72 if (bus == pp->root_bus_nr && dev == 0)
75 if (!orion_pcie_link_up(pp->base))
78 if (bus == pp->root_bus_nr && dev != 1)
86 * PCIe config cycles are done by programming the PCIE_CONF_ADDR register
87 * and then reading the PCIE_CONF_DATA register. Need to make sure these
88 * transactions are atomic.
91 static int pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
94 struct pci_sys_data *sys = bus->sysdata;
95 struct pcie_port *pp = sys->private_data;
99 if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0) {
101 return PCIBIOS_DEVICE_NOT_FOUND;
104 spin_lock_irqsave(&pp->conf_lock, flags);
105 ret = orion_pcie_rd_conf(pp->base, bus, devfn, where, size, val);
106 spin_unlock_irqrestore(&pp->conf_lock, flags);
111 static int pcie_wr_conf(struct pci_bus *bus, u32 devfn,
112 int where, int size, u32 val)
114 struct pci_sys_data *sys = bus->sysdata;
115 struct pcie_port *pp = sys->private_data;
119 if (pcie_valid_config(pp, bus->number, PCI_SLOT(devfn)) == 0)
120 return PCIBIOS_DEVICE_NOT_FOUND;
122 spin_lock_irqsave(&pp->conf_lock, flags);
123 ret = orion_pcie_wr_conf(pp->base, bus, devfn, where, size, val);
124 spin_unlock_irqrestore(&pp->conf_lock, flags);
129 static struct pci_ops pcie_ops = {
130 .read = pcie_rd_conf,
131 .write = pcie_wr_conf,
134 static void __init pcie0_ioresources_init(struct pcie_port *pp)
136 pp->base = (void __iomem *)PCIE_VIRT_BASE;
137 pp->irq = IRQ_KIRKWOOD_PCIE;
142 pp->res[0].name = "PCIe 0 I/O Space";
143 pp->res[0].start = KIRKWOOD_PCIE_IO_BUS_BASE;
144 pp->res[0].end = pp->res[0].start + KIRKWOOD_PCIE_IO_SIZE - 1;
145 pp->res[0].flags = IORESOURCE_IO;
150 pp->res[1].name = "PCIe 0 MEM";
151 pp->res[1].start = KIRKWOOD_PCIE_MEM_PHYS_BASE;
152 pp->res[1].end = pp->res[1].start + KIRKWOOD_PCIE_MEM_SIZE - 1;
153 pp->res[1].flags = IORESOURCE_MEM;
156 static void __init pcie1_ioresources_init(struct pcie_port *pp)
158 pp->base = (void __iomem *)PCIE1_VIRT_BASE;
159 pp->irq = IRQ_KIRKWOOD_PCIE1;
164 pp->res[0].name = "PCIe 1 I/O Space";
165 pp->res[0].start = KIRKWOOD_PCIE1_IO_BUS_BASE;
166 pp->res[0].end = pp->res[0].start + KIRKWOOD_PCIE1_IO_SIZE - 1;
167 pp->res[0].flags = IORESOURCE_IO;
172 pp->res[1].name = "PCIe 1 MEM";
173 pp->res[1].start = KIRKWOOD_PCIE1_MEM_PHYS_BASE;
174 pp->res[1].end = pp->res[1].start + KIRKWOOD_PCIE1_MEM_SIZE - 1;
175 pp->res[1].flags = IORESOURCE_MEM;
178 static int __init kirkwood_pcie_setup(int nr, struct pci_sys_data *sys)
180 struct pcie_port *pp;
183 if (nr >= num_pcie_ports)
186 index = pcie_port_map[nr];
187 printk(KERN_INFO "PCI: bus%d uses PCIe port %d\n", sys->busnr, index);
189 pp = kzalloc(sizeof(*pp), GFP_KERNEL);
191 panic("PCIe: failed to allocate pcie_port data");
192 sys->private_data = pp;
193 pp->root_bus_nr = sys->busnr;
194 spin_lock_init(&pp->conf_lock);
198 kirkwood_enable_pcie_clk("0");
199 pcie0_ioresources_init(pp);
202 kirkwood_enable_pcie_clk("1");
203 pcie1_ioresources_init(pp);
206 panic("PCIe setup: invalid controller %d", index);
209 if (request_resource(&ioport_resource, &pp->res[0]))
210 panic("Request PCIe%d IO resource failed\n", index);
211 if (request_resource(&iomem_resource, &pp->res[1]))
212 panic("Request PCIe%d Memory resource failed\n", index);
215 pci_add_resource_offset(&sys->resources, &pp->res[0], sys->io_offset);
216 pci_add_resource_offset(&sys->resources, &pp->res[1], sys->mem_offset);
219 * Generic PCIe unit setup.
221 orion_pcie_set_local_bus_nr(pp->base, sys->busnr);
223 orion_pcie_setup(pp->base);
228 static void __devinit rc_pci_fixup(struct pci_dev *dev)
231 * Prevent enumeration of root complex.
233 if (dev->bus->parent == NULL && dev->devfn == 0) {
236 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
237 dev->resource[i].start = 0;
238 dev->resource[i].end = 0;
239 dev->resource[i].flags = 0;
243 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_ANY_ID, rc_pci_fixup);
245 static struct pci_bus __init *
246 kirkwood_pcie_scan_bus(int nr, struct pci_sys_data *sys)
250 if (nr < num_pcie_ports) {
251 bus = pci_scan_root_bus(NULL, sys->busnr, &pcie_ops, sys,
261 static int __init kirkwood_pcie_map_irq(const struct pci_dev *dev, u8 slot,
264 struct pci_sys_data *sys = dev->sysdata;
265 struct pcie_port *pp = sys->private_data;
270 static struct hw_pci kirkwood_pci __initdata = {
271 .setup = kirkwood_pcie_setup,
272 .scan = kirkwood_pcie_scan_bus,
273 .map_irq = kirkwood_pcie_map_irq,
276 static void __init add_pcie_port(int index, unsigned long base)
278 printk(KERN_INFO "Kirkwood PCIe port %d: ", index);
280 if (orion_pcie_link_up((void __iomem *)base)) {
281 printk(KERN_INFO "link up\n");
282 pcie_port_map[num_pcie_ports++] = index;
284 printk(KERN_INFO "link down, ignoring\n");
287 void __init kirkwood_pcie_init(unsigned int portmask)
289 vga_base = KIRKWOOD_PCIE_MEM_PHYS_BASE;
291 if (portmask & KW_PCIE0)
292 add_pcie_port(0, PCIE_VIRT_BASE);
294 if (portmask & KW_PCIE1)
295 add_pcie_port(1, PCIE1_VIRT_BASE);
297 kirkwood_pci.nr_controllers = num_pcie_ports;
298 pci_common_init(&kirkwood_pci);