arch/arm/mach-lpc32xx/phy3250.c

   1 /*
   2  * arch/arm/mach-lpc32xx/phy3250.c
   3  *
   4  * Author: Kevin Wells <kevin.wells@nxp.com>
   5  *
   6  * Copyright (C) 2010 NXP Semiconductors
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #include <linux/init.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/device.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/irq.h>
  24 #include <linux/dma-mapping.h>
  25 #include <linux/device.h>
  26 #include <linux/spi/spi.h>
  27 #include <linux/spi/eeprom.h>
  28 #include <linux/leds.h>
  29 #include <linux/gpio.h>
  30 #include <linux/amba/bus.h>
  31 #include <linux/amba/clcd.h>
  32 #include <linux/amba/pl022.h>
  33
  34 #include <asm/setup.h>
  35 #include <asm/mach-types.h>
  36 #include <asm/mach/arch.h>
  37
  38 #include <mach/hardware.h>
  39 #include <mach/platform.h>
  40 #include <mach/gpio-lpc32xx.h>
  41 #include "common.h"
  42
  43 /*
  44  * Mapped GPIOLIB GPIOs
  45  */
  46 #define SPI0_CS_GPIO    LPC32XX_GPIO(LPC32XX_GPIO_P3_GRP, 5)
  47 #define LCD_POWER_GPIO  LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 0)
  48 #define BKL_POWER_GPIO  LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 4)
  49 #define LED_GPIO        LPC32XX_GPIO(LPC32XX_GPO_P3_GRP, 1)
  50
  51 /*
  52  * AMBA LCD controller
  53  */
  54 static struct clcd_panel conn_lcd_panel = {
  55         .mode           = {
  56                 .name           = "QVGA portrait",
  57                 .refresh        = 60,
  58                 .xres           = 240,
  59                 .yres           = 320,
  60                 .pixclock       = 191828,
  61                 .left_margin    = 22,
  62                 .right_margin   = 11,
  63                 .upper_margin   = 2,
  64                 .lower_margin   = 1,
  65                 .hsync_len      = 5,
  66                 .vsync_len      = 2,
  67                 .sync           = 0,
  68                 .vmode          = FB_VMODE_NONINTERLACED,
  69         },
  70         .width          = -1,
  71         .height         = -1,
  72         .tim2           = (TIM2_IVS | TIM2_IHS),
  73         .cntl           = (CNTL_BGR | CNTL_LCDTFT | CNTL_LCDVCOMP(1) |
  74                                 CNTL_LCDBPP16_565),
  75         .bpp            = 16,
  76 };
  77 #define PANEL_SIZE (3 * SZ_64K)
  78
  79 static int lpc32xx_clcd_setup(struct clcd_fb *fb)
  80 {
  81         dma_addr_t dma;
  82
  83         fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev,
  84                 PANEL_SIZE, &dma, GFP_KERNEL);
  85         if (!fb->fb.screen_base) {
  86                 printk(KERN_ERR "CLCD: unable to map framebuffer\n");
  87                 return -ENOMEM;
  88         }
  89
  90         fb->fb.fix.smem_start = dma;
  91         fb->fb.fix.smem_len = PANEL_SIZE;
  92         fb->panel = &conn_lcd_panel;
  93
  94         if (gpio_request(LCD_POWER_GPIO, "LCD power"))
  95                 printk(KERN_ERR "Error requesting gpio %u",
  96                         LCD_POWER_GPIO);
  97         else if (gpio_direction_output(LCD_POWER_GPIO, 1))
  98                 printk(KERN_ERR "Error setting gpio %u to output",
  99                         LCD_POWER_GPIO);
 100
 101         if (gpio_request(BKL_POWER_GPIO, "LCD backlight power"))
 102                 printk(KERN_ERR "Error requesting gpio %u",
 103                         BKL_POWER_GPIO);
 104         else if (gpio_direction_output(BKL_POWER_GPIO, 1))
 105                 printk(KERN_ERR "Error setting gpio %u to output",
 106                         BKL_POWER_GPIO);
 107
 108         return 0;
 109 }
 110
 111 static int lpc32xx_clcd_mmap(struct clcd_fb *fb, struct vm_area_struct *vma)
 112 {
 113         return dma_mmap_writecombine(&fb->dev->dev, vma,
 114                 fb->fb.screen_base, fb->fb.fix.smem_start,
 115                 fb->fb.fix.smem_len);
 116 }
 117
 118 static void lpc32xx_clcd_remove(struct clcd_fb *fb)
 119 {
 120         dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len,
 121                 fb->fb.screen_base, fb->fb.fix.smem_start);
 122 }
 123
 124 /*
 125  * On some early LCD modules (1307.0), the backlight logic is inverted.
 126  * For those board variants, swap the disable and enable states for
 127  * BKL_POWER_GPIO.
 128 */
 129 static void clcd_disable(struct clcd_fb *fb)
 130 {
 131         gpio_set_value(BKL_POWER_GPIO, 0);
 132         gpio_set_value(LCD_POWER_GPIO, 0);
 133 }
 134
 135 static void clcd_enable(struct clcd_fb *fb)
 136 {
 137         gpio_set_value(BKL_POWER_GPIO, 1);
 138         gpio_set_value(LCD_POWER_GPIO, 1);
 139 }
 140
 141 static struct clcd_board lpc32xx_clcd_data = {
 142         .name           = "Phytec LCD",
 143         .check          = clcdfb_check,
 144         .decode         = clcdfb_decode,
 145         .disable        = clcd_disable,
 146         .enable         = clcd_enable,
 147         .setup          = lpc32xx_clcd_setup,
 148         .mmap           = lpc32xx_clcd_mmap,
 149         .remove         = lpc32xx_clcd_remove,
 150 };
 151
 152 static AMBA_AHB_DEVICE(lpc32xx_clcd, "dev:clcd", 0,
 153         LPC32XX_LCD_BASE, { IRQ_LPC32XX_LCD }, &lpc32xx_clcd_data);
 154
 155 /*
 156  * AMBA SSP (SPI)
 157  */
 158 static void phy3250_spi_cs_set(u32 control)
 159 {
 160         gpio_set_value(SPI0_CS_GPIO, (int) control);
 161 }
 162
 163 static struct pl022_config_chip spi0_chip_info = {
 164         .com_mode               = INTERRUPT_TRANSFER,
 165         .iface                  = SSP_INTERFACE_MOTOROLA_SPI,
 166         .hierarchy              = SSP_MASTER,
 167         .slave_tx_disable       = 0,
 168         .rx_lev_trig            = SSP_RX_4_OR_MORE_ELEM,
 169         .tx_lev_trig            = SSP_TX_4_OR_MORE_EMPTY_LOC,
 170         .ctrl_len               = SSP_BITS_8,
 171         .wait_state             = SSP_MWIRE_WAIT_ZERO,
 172         .duplex                 = SSP_MICROWIRE_CHANNEL_FULL_DUPLEX,
 173         .cs_control             = phy3250_spi_cs_set,
 174 };
 175
 176 static struct pl022_ssp_controller lpc32xx_ssp0_data = {
 177         .bus_id                 = 0,
 178         .num_chipselect         = 1,
 179         .enable_dma             = 0,
 180 };
 181
 182 static AMBA_APB_DEVICE(lpc32xx_ssp0, "dev:ssp0", 0,
 183         LPC32XX_SSP0_BASE, { IRQ_LPC32XX_SSP0 }, &lpc32xx_ssp0_data);
 184
 185 /* AT25 driver registration */
 186 static int __init phy3250_spi_board_register(void)
 187 {
 188 #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
 189         static struct spi_board_info info[] = {
 190                 {
 191                         .modalias = "spidev",
 192                         .max_speed_hz = 5000000,
 193                         .bus_num = 0,
 194                         .chip_select = 0,
 195                         .controller_data = &spi0_chip_info,
 196                 },
 197         };
 198
 199 #else
 200         static struct spi_eeprom eeprom = {
 201                 .name = "at25256a",
 202                 .byte_len = 0x8000,
 203                 .page_size = 64,
 204                 .flags = EE_ADDR2,
 205         };
 206
 207         static struct spi_board_info info[] = {
 208                 {
 209                         .modalias = "at25",
 210                         .max_speed_hz = 5000000,
 211                         .bus_num = 0,
 212                         .chip_select = 0,
 213                         .mode = SPI_MODE_0,
 214                         .platform_data = &eeprom,
 215                         .controller_data = &spi0_chip_info,
 216                 },
 217         };
 218 #endif
 219         return spi_register_board_info(info, ARRAY_SIZE(info));
 220 }
 221 arch_initcall(phy3250_spi_board_register);
 222
 223 static struct i2c_board_info __initdata phy3250_i2c_board_info[] = {
 224         {
 225                 I2C_BOARD_INFO("pcf8563", 0x51),
 226         },
 227 };
 228
 229 static struct gpio_led phy_leds[] = {
 230         {
 231                 .name                   = "led0",
 232                 .gpio                   = LED_GPIO,
 233                 .active_low             = 1,
 234                 .default_trigger        = "heartbeat",
 235         },
 236 };
 237
 238 static struct gpio_led_platform_data led_data = {
 239         .leds = phy_leds,
 240         .num_leds = ARRAY_SIZE(phy_leds),
 241 };
 242
 243 static struct platform_device lpc32xx_gpio_led_device = {
 244         .name                   = "leds-gpio",
 245         .id                     = -1,
 246         .dev.platform_data      = &led_data,
 247 };
 248
 249 static struct platform_device *phy3250_devs[] __initdata = {
 250         &lpc32xx_rtc_device,
 251         &lpc32xx_tsc_device,
 252         &lpc32xx_i2c0_device,
 253         &lpc32xx_i2c1_device,
 254         &lpc32xx_i2c2_device,
 255         &lpc32xx_watchdog_device,
 256         &lpc32xx_gpio_led_device,
 257         &lpc32xx_adc_device,
 258 };
 259
 260 static struct amba_device *amba_devs[] __initdata = {
 261         &lpc32xx_clcd_device,
 262         &lpc32xx_ssp0_device,
 263 };
 264
 265 /*
 266  * Board specific functions
 267  */
 268 static void __init phy3250_board_init(void)
 269 {
 270         u32 tmp;
 271         int i;
 272
 273         lpc32xx_gpio_init();
 274
 275         /* Register GPIOs used on this board */
 276         if (gpio_request(SPI0_CS_GPIO, "spi0 cs"))
 277                 printk(KERN_ERR "Error requesting gpio %u",
 278                         SPI0_CS_GPIO);
 279         else if (gpio_direction_output(SPI0_CS_GPIO, 1))
 280                 printk(KERN_ERR "Error setting gpio %u to output",
 281                         SPI0_CS_GPIO);
 282
 283         /* Setup network interface for RMII mode */
 284         tmp = __raw_readl(LPC32XX_CLKPWR_MACCLK_CTRL);
 285         tmp &= ~LPC32XX_CLKPWR_MACCTRL_PINS_MSK;
 286         tmp |= LPC32XX_CLKPWR_MACCTRL_USE_RMII_PINS;
 287         __raw_writel(tmp, LPC32XX_CLKPWR_MACCLK_CTRL);
 288
 289         /* Setup SLC NAND controller muxing */
 290         __raw_writel(LPC32XX_CLKPWR_NANDCLK_SEL_SLC,
 291                 LPC32XX_CLKPWR_NAND_CLK_CTRL);
 292
 293         /* Setup LCD muxing to RGB565 */
 294         tmp = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL) &
 295                 ~(LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_MSK |
 296                 LPC32XX_CLKPWR_LCDCTRL_PSCALE_MSK);
 297         tmp |= LPC32XX_CLKPWR_LCDCTRL_LCDTYPE_TFT16;
 298         __raw_writel(tmp, LPC32XX_CLKPWR_LCDCLK_CTRL);
 299
 300         /* Set up I2C pull levels */
 301         tmp = __raw_readl(LPC32XX_CLKPWR_I2C_CLK_CTRL);
 302         tmp |= LPC32XX_CLKPWR_I2CCLK_USBI2CHI_DRIVE |
 303                 LPC32XX_CLKPWR_I2CCLK_I2C2HI_DRIVE;
 304         __raw_writel(tmp, LPC32XX_CLKPWR_I2C_CLK_CTRL);
 305
 306         /* Disable IrDA pulsing support on UART6 */
 307         tmp = __raw_readl(LPC32XX_UARTCTL_CTRL);
 308         tmp |= LPC32XX_UART_UART6_IRDAMOD_BYPASS;
 309         __raw_writel(tmp, LPC32XX_UARTCTL_CTRL);
 310
 311         /* Enable DMA for I2S1 channel */
 312         tmp = __raw_readl(LPC32XX_CLKPWR_I2S_CLK_CTRL);
 313         tmp = LPC32XX_CLKPWR_I2SCTRL_I2S1_USE_DMA;
 314         __raw_writel(tmp, LPC32XX_CLKPWR_I2S_CLK_CTRL);
 315
 316         lpc32xx_serial_init();
 317
 318         /*
 319          * AMBA peripheral clocks need to be enabled prior to AMBA device
 320          * detection or a data fault will occur, so enable the clocks
 321          * here. However, we don't want to enable them if the peripheral
 322          * isn't included in the image
 323          */
 324 #ifdef CONFIG_FB_ARMCLCD
 325         tmp = __raw_readl(LPC32XX_CLKPWR_LCDCLK_CTRL);
 326         __raw_writel((tmp | LPC32XX_CLKPWR_LCDCTRL_CLK_EN),
 327                 LPC32XX_CLKPWR_LCDCLK_CTRL);
 328 #endif
 329 #ifdef CONFIG_SPI_PL022
 330         tmp = __raw_readl(LPC32XX_CLKPWR_SSP_CLK_CTRL);
 331         __raw_writel((tmp | LPC32XX_CLKPWR_SSPCTRL_SSPCLK0_EN),
 332                 LPC32XX_CLKPWR_SSP_CLK_CTRL);
 333 #endif
 334
 335         platform_add_devices(phy3250_devs, ARRAY_SIZE(phy3250_devs));
 336         for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
 337                 struct amba_device *d = amba_devs[i];
 338                 amba_device_register(d, &iomem_resource);
 339         }
 340
 341         /* Test clock needed for UDA1380 initial init */
 342         __raw_writel(LPC32XX_CLKPWR_TESTCLK2_SEL_MOSC |
 343                 LPC32XX_CLKPWR_TESTCLK_TESTCLK2_EN,
 344                 LPC32XX_CLKPWR_TEST_CLK_SEL);
 345
 346         i2c_register_board_info(0, phy3250_i2c_board_info,
 347                 ARRAY_SIZE(phy3250_i2c_board_info));
 348 }
 349
 350 static int __init lpc32xx_display_uid(void)
 351 {
 352         u32 uid[4];
 353
 354         lpc32xx_get_uid(uid);
 355
 356         printk(KERN_INFO "LPC32XX unique ID: %08x%08x%08x%08x\n",
 357                 uid[3], uid[2], uid[1], uid[0]);
 358
 359         return 1;
 360 }
 361 arch_initcall(lpc32xx_display_uid);
 362
 363 MACHINE_START(PHY3250, "Phytec 3250 board with the LPC3250 Microcontroller")
 364         /* Maintainer: Kevin Wells, NXP Semiconductors */
 365         .atag_offset    = 0x100,
 366         .map_io         = lpc32xx_map_io,
 367         .init_irq       = lpc32xx_init_irq,
 368         .timer          = &lpc32xx_timer,
 369         .init_machine   = phy3250_board_init,
 370         .restart        = lpc23xx_restart,
 371 MACHINE_END