arch/arm/mach-mmp/aspenite.c

   1 /*
   2  *  linux/arch/arm/mach-mmp/aspenite.c
   3  *
   4  *  Support for the Marvell PXA168-based Aspenite and Zylonite2
   5  *  Development Platform.
   6  *
   7  *  This program is free software; you can redistribute it and/or modify
   8  *  it under the terms of the GNU General Public License version 2 as
   9  *  publishhed by the Free Software Foundation.
  10  */
  11
  12 #include <linux/init.h>
  13 #include <linux/kernel.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/smc91x.h>
  16 #include <linux/mtd/mtd.h>
  17 #include <linux/mtd/partitions.h>
  18 #include <linux/mtd/nand.h>
  19
  20 #include <asm/mach-types.h>
  21 #include <asm/mach/arch.h>
  22 #include <mach/addr-map.h>
  23 #include <mach/mfp-pxa168.h>
  24 #include <mach/pxa168.h>
  25 #include <mach/gpio.h>
  26 #include <video/pxa168fb.h>
  27
  28 #include "common.h"
  29
  30 static unsigned long common_pin_config[] __initdata = {
  31         /* Data Flash Interface */
  32         GPIO0_DFI_D15,
  33         GPIO1_DFI_D14,
  34         GPIO2_DFI_D13,
  35         GPIO3_DFI_D12,
  36         GPIO4_DFI_D11,
  37         GPIO5_DFI_D10,
  38         GPIO6_DFI_D9,
  39         GPIO7_DFI_D8,
  40         GPIO8_DFI_D7,
  41         GPIO9_DFI_D6,
  42         GPIO10_DFI_D5,
  43         GPIO11_DFI_D4,
  44         GPIO12_DFI_D3,
  45         GPIO13_DFI_D2,
  46         GPIO14_DFI_D1,
  47         GPIO15_DFI_D0,
  48
  49         /* Static Memory Controller */
  50         GPIO18_SMC_nCS0,
  51         GPIO34_SMC_nCS1,
  52         GPIO23_SMC_nLUA,
  53         GPIO25_SMC_nLLA,
  54         GPIO28_SMC_RDY,
  55         GPIO29_SMC_SCLK,
  56         GPIO35_SMC_BE1,
  57         GPIO36_SMC_BE2,
  58         GPIO27_GPIO,    /* Ethernet IRQ */
  59
  60         /* UART1 */
  61         GPIO107_UART1_RXD,
  62         GPIO108_UART1_TXD,
  63
  64         /* SSP1 */
  65         GPIO113_I2S_MCLK,
  66         GPIO114_I2S_FRM,
  67         GPIO115_I2S_BCLK,
  68         GPIO116_I2S_RXD,
  69         GPIO117_I2S_TXD,
  70
  71         /* LCD */
  72         GPIO56_LCD_FCLK_RD,
  73         GPIO57_LCD_LCLK_A0,
  74         GPIO58_LCD_PCLK_WR,
  75         GPIO59_LCD_DENA_BIAS,
  76         GPIO60_LCD_DD0,
  77         GPIO61_LCD_DD1,
  78         GPIO62_LCD_DD2,
  79         GPIO63_LCD_DD3,
  80         GPIO64_LCD_DD4,
  81         GPIO65_LCD_DD5,
  82         GPIO66_LCD_DD6,
  83         GPIO67_LCD_DD7,
  84         GPIO68_LCD_DD8,
  85         GPIO69_LCD_DD9,
  86         GPIO70_LCD_DD10,
  87         GPIO71_LCD_DD11,
  88         GPIO72_LCD_DD12,
  89         GPIO73_LCD_DD13,
  90         GPIO74_LCD_DD14,
  91         GPIO75_LCD_DD15,
  92         GPIO76_LCD_DD16,
  93         GPIO77_LCD_DD17,
  94         GPIO78_LCD_DD18,
  95         GPIO79_LCD_DD19,
  96         GPIO80_LCD_DD20,
  97         GPIO81_LCD_DD21,
  98         GPIO82_LCD_DD22,
  99         GPIO83_LCD_DD23,
 100 };
 101
 102 static struct smc91x_platdata smc91x_info = {
 103         .flags  = SMC91X_USE_16BIT | SMC91X_NOWAIT,
 104 };
 105
 106 static struct resource smc91x_resources[] = {
 107         [0] = {
 108                 .start  = SMC_CS1_PHYS_BASE + 0x300,
 109                 .end    = SMC_CS1_PHYS_BASE + 0xfffff,
 110                 .flags  = IORESOURCE_MEM,
 111         },
 112         [1] = {
 113                 .start  = gpio_to_irq(27),
 114                 .end    = gpio_to_irq(27),
 115                 .flags  = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
 116         }
 117 };
 118
 119 static struct platform_device smc91x_device = {
 120         .name           = "smc91x",
 121         .id             = 0,
 122         .dev            = {
 123                 .platform_data = &smc91x_info,
 124         },
 125         .num_resources  = ARRAY_SIZE(smc91x_resources),
 126         .resource       = smc91x_resources,
 127 };
 128
 129 static struct mtd_partition aspenite_nand_partitions[] = {
 130         {
 131                 .name           = "bootloader",
 132                 .offset         = 0,
 133                 .size           = SZ_1M,
 134                 .mask_flags     = MTD_WRITEABLE,
 135         }, {
 136                 .name           = "reserved",
 137                 .offset         = MTDPART_OFS_APPEND,
 138                 .size           = SZ_128K,
 139                 .mask_flags     = MTD_WRITEABLE,
 140         }, {
 141                 .name           = "reserved",
 142                 .offset         = MTDPART_OFS_APPEND,
 143                 .size           = SZ_8M,
 144                 .mask_flags     = MTD_WRITEABLE,
 145         }, {
 146                 .name           = "kernel",
 147                 .offset         = MTDPART_OFS_APPEND,
 148                 .size           = (SZ_2M + SZ_1M),
 149                 .mask_flags     = 0,
 150         }, {
 151                 .name           = "filesystem",
 152                 .offset         = MTDPART_OFS_APPEND,
 153                 .size           = SZ_48M,
 154                 .mask_flags     = 0,
 155         }
 156 };
 157
 158 static struct pxa3xx_nand_platform_data aspenite_nand_info = {
 159         .enable_arbiter = 1,
 160         .parts          = aspenite_nand_partitions,
 161         .nr_parts       = ARRAY_SIZE(aspenite_nand_partitions),
 162 };
 163
 164 static struct i2c_board_info aspenite_i2c_info[] __initdata = {
 165         { I2C_BOARD_INFO("wm8753", 0x1b), },
 166 };
 167
 168 static struct fb_videomode video_modes[] = {
 169         [0] = {
 170                 .pixclock       = 30120,
 171                 .refresh        = 60,
 172                 .xres           = 800,
 173                 .yres           = 480,
 174                 .hsync_len      = 1,
 175                 .left_margin    = 215,
 176                 .right_margin   = 40,
 177                 .vsync_len      = 1,
 178                 .upper_margin   = 34,
 179                 .lower_margin   = 10,
 180                 .sync           = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_HOR_HIGH_ACT,
 181         },
 182 };
 183
 184 struct pxa168fb_mach_info aspenite_lcd_info = {
 185         .id                     = "Graphic Frame",
 186         .modes                  = video_modes,
 187         .num_modes              = ARRAY_SIZE(video_modes),
 188         .pix_fmt                = PIX_FMT_RGB565,
 189         .io_pin_allocation_mode = PIN_MODE_DUMB_24,
 190         .dumb_mode              = DUMB_MODE_RGB888,
 191         .active                 = 1,
 192         .panel_rbswap           = 0,
 193         .invert_pixclock        = 0,
 194 };
 195
 196 static void __init common_init(void)
 197 {
 198         mfp_config(ARRAY_AND_SIZE(common_pin_config));
 199
 200         /* on-chip devices */
 201         pxa168_add_uart(1);
 202         pxa168_add_twsi(1, NULL, ARRAY_AND_SIZE(aspenite_i2c_info));
 203         pxa168_add_ssp(1);
 204         pxa168_add_nand(&aspenite_nand_info);
 205         pxa168_add_fb(&aspenite_lcd_info);
 206
 207         /* off-chip devices */
 208         platform_device_register(&smc91x_device);
 209 }
 210
 211 MACHINE_START(ASPENITE, "PXA168-based Aspenite Development Platform")
 212         .phys_io        = APB_PHYS_BASE,
 213         .io_pg_offst    = (APB_VIRT_BASE >> 18) & 0xfffc,
 214         .map_io         = mmp_map_io,
 215         .init_irq       = pxa168_init_irq,
 216         .timer          = &pxa168_timer,
 217         .init_machine   = common_init,
 218 MACHINE_END
 219
 220 MACHINE_START(ZYLONITE2, "PXA168-based Zylonite2 Development Platform")
 221         .phys_io        = APB_PHYS_BASE,
 222         .io_pg_offst    = (APB_VIRT_BASE >> 18) & 0xfffc,
 223         .map_io         = mmp_map_io,
 224         .init_irq       = pxa168_init_irq,
 225         .timer          = &pxa168_timer,
 226         .init_machine   = common_init,
 227 MACHINE_END