2 * linux/arch/arm/mach-mmp/time.c
4 * Support for clocksource and clockevents
6 * Copyright (C) 2008 Marvell International Ltd.
9 * 2008-04-11: Jason Chagas <Jason.chagas@marvell.com>
10 * 2008-10-08: Bin Yang <bin.yang@marvell.com>
12 * The timers module actually includes three timers, each timer with up to
13 * three match comparators. Timer #0 is used here in free-running mode as
14 * the clock source, and match comparator #1 used as clock event device.
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
21 #include <linux/init.h>
22 #include <linux/kernel.h>
23 #include <linux/interrupt.h>
24 #include <linux/clockchips.h>
27 #include <linux/irq.h>
29 #include <linux/of_address.h>
30 #include <linux/of_irq.h>
31 #include <linux/sched_clock.h>
33 #include <mach/addr-map.h>
34 #include <mach/regs-timers.h>
35 #include <mach/regs-apbc.h>
36 #include <mach/irqs.h>
37 #include <mach/cputype.h>
38 #include <asm/mach/time.h>
42 #ifdef CONFIG_CPU_MMP2
43 #define MMP_CLOCK_FREQ 6500000
45 #define MMP_CLOCK_FREQ 3250000
48 #define TIMERS_VIRT_BASE TIMERS1_VIRT_BASE
50 #define MAX_DELTA (0xfffffffe)
51 #define MIN_DELTA (16)
53 static void __iomem *mmp_timer_base = TIMERS_VIRT_BASE;
56 * FIXME: the timer needs some delay to stablize the counter capture
58 static inline uint32_t timer_read(void)
62 __raw_writel(1, mmp_timer_base + TMR_CVWR(1));
67 return __raw_readl(mmp_timer_base + TMR_CVWR(1));
70 static u64 notrace mmp_read_sched_clock(void)
75 static irqreturn_t timer_interrupt(int irq, void *dev_id)
77 struct clock_event_device *c = dev_id;
80 * Clear pending interrupt status.
82 __raw_writel(0x01, mmp_timer_base + TMR_ICR(0));
87 __raw_writel(0x02, mmp_timer_base + TMR_CER);
94 static int timer_set_next_event(unsigned long delta,
95 struct clock_event_device *dev)
99 local_irq_save(flags);
104 __raw_writel(0x02, mmp_timer_base + TMR_CER);
107 * Clear and enable timer match 0 interrupt.
109 __raw_writel(0x01, mmp_timer_base + TMR_ICR(0));
110 __raw_writel(0x01, mmp_timer_base + TMR_IER(0));
113 * Setup new clockevent timer value.
115 __raw_writel(delta - 1, mmp_timer_base + TMR_TN_MM(0, 0));
120 __raw_writel(0x03, mmp_timer_base + TMR_CER);
122 local_irq_restore(flags);
127 static int timer_set_shutdown(struct clock_event_device *evt)
131 local_irq_save(flags);
132 /* disable the matching interrupt */
133 __raw_writel(0x00, mmp_timer_base + TMR_IER(0));
134 local_irq_restore(flags);
139 static struct clock_event_device ckevt = {
140 .name = "clockevent",
141 .features = CLOCK_EVT_FEAT_ONESHOT,
143 .set_next_event = timer_set_next_event,
144 .set_state_shutdown = timer_set_shutdown,
145 .set_state_oneshot = timer_set_shutdown,
148 static cycle_t clksrc_read(struct clocksource *cs)
153 static struct clocksource cksrc = {
154 .name = "clocksource",
157 .mask = CLOCKSOURCE_MASK(32),
158 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
161 static void __init timer_config(void)
163 uint32_t ccr = __raw_readl(mmp_timer_base + TMR_CCR);
165 __raw_writel(0x0, mmp_timer_base + TMR_CER); /* disable */
167 ccr &= (cpu_is_mmp2()) ? (TMR_CCR_CS_0(0) | TMR_CCR_CS_1(0)) :
168 (TMR_CCR_CS_0(3) | TMR_CCR_CS_1(3));
169 __raw_writel(ccr, mmp_timer_base + TMR_CCR);
171 /* set timer 0 to periodic mode, and timer 1 to free-running mode */
172 __raw_writel(0x2, mmp_timer_base + TMR_CMR);
174 __raw_writel(0x1, mmp_timer_base + TMR_PLCR(0)); /* periodic */
175 __raw_writel(0x7, mmp_timer_base + TMR_ICR(0)); /* clear status */
176 __raw_writel(0x0, mmp_timer_base + TMR_IER(0));
178 __raw_writel(0x0, mmp_timer_base + TMR_PLCR(1)); /* free-running */
179 __raw_writel(0x7, mmp_timer_base + TMR_ICR(1)); /* clear status */
180 __raw_writel(0x0, mmp_timer_base + TMR_IER(1));
182 /* enable timer 1 counter */
183 __raw_writel(0x2, mmp_timer_base + TMR_CER);
186 static struct irqaction timer_irq = {
188 .flags = IRQF_TIMER | IRQF_IRQPOLL,
189 .handler = timer_interrupt,
193 void __init timer_init(int irq)
197 sched_clock_register(mmp_read_sched_clock, 32, MMP_CLOCK_FREQ);
199 ckevt.cpumask = cpumask_of(0);
201 setup_irq(irq, &timer_irq);
203 clocksource_register_hz(&cksrc, MMP_CLOCK_FREQ);
204 clockevents_config_and_register(&ckevt, MMP_CLOCK_FREQ,
205 MIN_DELTA, MAX_DELTA);
209 static const struct of_device_id mmp_timer_dt_ids[] = {
210 { .compatible = "mrvl,mmp-timer", },
214 void __init mmp_dt_init_timer(void)
216 struct device_node *np;
219 np = of_find_matching_node(NULL, mmp_timer_dt_ids);
225 irq = irq_of_parse_and_map(np, 0);
230 mmp_timer_base = of_iomap(np, 0);
231 if (!mmp_timer_base) {
238 pr_err("Failed to get timer from device tree with error:%d\n", ret);