1 /* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
18 #include <linux/kernel.h>
19 #include <linux/platform_device.h>
20 #include <linux/bootmem.h>
22 #include <mach/msm_iomap-8x60.h>
23 #include <mach/irqs-8x60.h>
24 #include <mach/iommu.h>
26 static struct resource msm_iommu_jpegd_resources[] = {
28 .start = MSM_IOMMU_JPEGD_PHYS,
29 .end = MSM_IOMMU_JPEGD_PHYS + MSM_IOMMU_JPEGD_SIZE - 1,
31 .flags = IORESOURCE_MEM,
34 .name = "nonsecure_irq",
35 .start = SMMU_JPEGD_CB_SC_NON_SECURE_IRQ,
36 .end = SMMU_JPEGD_CB_SC_NON_SECURE_IRQ,
37 .flags = IORESOURCE_IRQ,
41 .start = SMMU_JPEGD_CB_SC_SECURE_IRQ,
42 .end = SMMU_JPEGD_CB_SC_SECURE_IRQ,
43 .flags = IORESOURCE_IRQ,
47 static struct resource msm_iommu_vpe_resources[] = {
49 .start = MSM_IOMMU_VPE_PHYS,
50 .end = MSM_IOMMU_VPE_PHYS + MSM_IOMMU_VPE_SIZE - 1,
52 .flags = IORESOURCE_MEM,
55 .name = "nonsecure_irq",
56 .start = SMMU_VPE_CB_SC_NON_SECURE_IRQ,
57 .end = SMMU_VPE_CB_SC_NON_SECURE_IRQ,
58 .flags = IORESOURCE_IRQ,
62 .start = SMMU_VPE_CB_SC_SECURE_IRQ,
63 .end = SMMU_VPE_CB_SC_SECURE_IRQ,
64 .flags = IORESOURCE_IRQ,
68 static struct resource msm_iommu_mdp0_resources[] = {
70 .start = MSM_IOMMU_MDP0_PHYS,
71 .end = MSM_IOMMU_MDP0_PHYS + MSM_IOMMU_MDP0_SIZE - 1,
73 .flags = IORESOURCE_MEM,
76 .name = "nonsecure_irq",
77 .start = SMMU_MDP0_CB_SC_NON_SECURE_IRQ,
78 .end = SMMU_MDP0_CB_SC_NON_SECURE_IRQ,
79 .flags = IORESOURCE_IRQ,
83 .start = SMMU_MDP0_CB_SC_SECURE_IRQ,
84 .end = SMMU_MDP0_CB_SC_SECURE_IRQ,
85 .flags = IORESOURCE_IRQ,
89 static struct resource msm_iommu_mdp1_resources[] = {
91 .start = MSM_IOMMU_MDP1_PHYS,
92 .end = MSM_IOMMU_MDP1_PHYS + MSM_IOMMU_MDP1_SIZE - 1,
94 .flags = IORESOURCE_MEM,
97 .name = "nonsecure_irq",
98 .start = SMMU_MDP1_CB_SC_NON_SECURE_IRQ,
99 .end = SMMU_MDP1_CB_SC_NON_SECURE_IRQ,
100 .flags = IORESOURCE_IRQ,
103 .name = "secure_irq",
104 .start = SMMU_MDP1_CB_SC_SECURE_IRQ,
105 .end = SMMU_MDP1_CB_SC_SECURE_IRQ,
106 .flags = IORESOURCE_IRQ,
110 static struct resource msm_iommu_rot_resources[] = {
112 .start = MSM_IOMMU_ROT_PHYS,
113 .end = MSM_IOMMU_ROT_PHYS + MSM_IOMMU_ROT_SIZE - 1,
115 .flags = IORESOURCE_MEM,
118 .name = "nonsecure_irq",
119 .start = SMMU_ROT_CB_SC_NON_SECURE_IRQ,
120 .end = SMMU_ROT_CB_SC_NON_SECURE_IRQ,
121 .flags = IORESOURCE_IRQ,
124 .name = "secure_irq",
125 .start = SMMU_ROT_CB_SC_SECURE_IRQ,
126 .end = SMMU_ROT_CB_SC_SECURE_IRQ,
127 .flags = IORESOURCE_IRQ,
131 static struct resource msm_iommu_ijpeg_resources[] = {
133 .start = MSM_IOMMU_IJPEG_PHYS,
134 .end = MSM_IOMMU_IJPEG_PHYS + MSM_IOMMU_IJPEG_SIZE - 1,
136 .flags = IORESOURCE_MEM,
139 .name = "nonsecure_irq",
140 .start = SMMU_IJPEG_CB_SC_NON_SECURE_IRQ,
141 .end = SMMU_IJPEG_CB_SC_NON_SECURE_IRQ,
142 .flags = IORESOURCE_IRQ,
145 .name = "secure_irq",
146 .start = SMMU_IJPEG_CB_SC_SECURE_IRQ,
147 .end = SMMU_IJPEG_CB_SC_SECURE_IRQ,
148 .flags = IORESOURCE_IRQ,
152 static struct resource msm_iommu_vfe_resources[] = {
154 .start = MSM_IOMMU_VFE_PHYS,
155 .end = MSM_IOMMU_VFE_PHYS + MSM_IOMMU_VFE_SIZE - 1,
157 .flags = IORESOURCE_MEM,
160 .name = "nonsecure_irq",
161 .start = SMMU_VFE_CB_SC_NON_SECURE_IRQ,
162 .end = SMMU_VFE_CB_SC_NON_SECURE_IRQ,
163 .flags = IORESOURCE_IRQ,
166 .name = "secure_irq",
167 .start = SMMU_VFE_CB_SC_SECURE_IRQ,
168 .end = SMMU_VFE_CB_SC_SECURE_IRQ,
169 .flags = IORESOURCE_IRQ,
173 static struct resource msm_iommu_vcodec_a_resources[] = {
175 .start = MSM_IOMMU_VCODEC_A_PHYS,
176 .end = MSM_IOMMU_VCODEC_A_PHYS + MSM_IOMMU_VCODEC_A_SIZE - 1,
178 .flags = IORESOURCE_MEM,
181 .name = "nonsecure_irq",
182 .start = SMMU_VCODEC_A_CB_SC_NON_SECURE_IRQ,
183 .end = SMMU_VCODEC_A_CB_SC_NON_SECURE_IRQ,
184 .flags = IORESOURCE_IRQ,
187 .name = "secure_irq",
188 .start = SMMU_VCODEC_A_CB_SC_SECURE_IRQ,
189 .end = SMMU_VCODEC_A_CB_SC_SECURE_IRQ,
190 .flags = IORESOURCE_IRQ,
194 static struct resource msm_iommu_vcodec_b_resources[] = {
196 .start = MSM_IOMMU_VCODEC_B_PHYS,
197 .end = MSM_IOMMU_VCODEC_B_PHYS + MSM_IOMMU_VCODEC_B_SIZE - 1,
199 .flags = IORESOURCE_MEM,
202 .name = "nonsecure_irq",
203 .start = SMMU_VCODEC_B_CB_SC_NON_SECURE_IRQ,
204 .end = SMMU_VCODEC_B_CB_SC_NON_SECURE_IRQ,
205 .flags = IORESOURCE_IRQ,
208 .name = "secure_irq",
209 .start = SMMU_VCODEC_B_CB_SC_SECURE_IRQ,
210 .end = SMMU_VCODEC_B_CB_SC_SECURE_IRQ,
211 .flags = IORESOURCE_IRQ,
215 static struct resource msm_iommu_gfx3d_resources[] = {
217 .start = MSM_IOMMU_GFX3D_PHYS,
218 .end = MSM_IOMMU_GFX3D_PHYS + MSM_IOMMU_GFX3D_SIZE - 1,
220 .flags = IORESOURCE_MEM,
223 .name = "nonsecure_irq",
224 .start = SMMU_GFX3D_CB_SC_NON_SECURE_IRQ,
225 .end = SMMU_GFX3D_CB_SC_NON_SECURE_IRQ,
226 .flags = IORESOURCE_IRQ,
229 .name = "secure_irq",
230 .start = SMMU_GFX3D_CB_SC_SECURE_IRQ,
231 .end = SMMU_GFX3D_CB_SC_SECURE_IRQ,
232 .flags = IORESOURCE_IRQ,
236 static struct resource msm_iommu_gfx2d0_resources[] = {
238 .start = MSM_IOMMU_GFX2D0_PHYS,
239 .end = MSM_IOMMU_GFX2D0_PHYS + MSM_IOMMU_GFX2D0_SIZE - 1,
241 .flags = IORESOURCE_MEM,
244 .name = "nonsecure_irq",
245 .start = SMMU_GFX2D0_CB_SC_NON_SECURE_IRQ,
246 .end = SMMU_GFX2D0_CB_SC_NON_SECURE_IRQ,
247 .flags = IORESOURCE_IRQ,
250 .name = "secure_irq",
251 .start = SMMU_GFX2D0_CB_SC_SECURE_IRQ,
252 .end = SMMU_GFX2D0_CB_SC_SECURE_IRQ,
253 .flags = IORESOURCE_IRQ,
257 static struct platform_device msm_root_iommu_dev = {
262 static struct msm_iommu_dev jpegd_smmu = {
267 static struct msm_iommu_dev vpe_smmu = {
271 static struct msm_iommu_dev mdp0_smmu = {
275 static struct msm_iommu_dev mdp1_smmu = {
279 static struct msm_iommu_dev rot_smmu = {
283 static struct msm_iommu_dev ijpeg_smmu = {
287 static struct msm_iommu_dev vfe_smmu = {
292 static struct msm_iommu_dev vcodec_a_smmu = {
296 static struct msm_iommu_dev vcodec_b_smmu = {
300 static struct msm_iommu_dev gfx3d_smmu = {
305 static struct msm_iommu_dev gfx2d0_smmu = {
310 static struct platform_device msm_device_smmu_jpegd = {
314 .parent = &msm_root_iommu_dev.dev,
316 .num_resources = ARRAY_SIZE(msm_iommu_jpegd_resources),
317 .resource = msm_iommu_jpegd_resources,
320 static struct platform_device msm_device_smmu_vpe = {
324 .parent = &msm_root_iommu_dev.dev,
326 .num_resources = ARRAY_SIZE(msm_iommu_vpe_resources),
327 .resource = msm_iommu_vpe_resources,
330 static struct platform_device msm_device_smmu_mdp0 = {
334 .parent = &msm_root_iommu_dev.dev,
336 .num_resources = ARRAY_SIZE(msm_iommu_mdp0_resources),
337 .resource = msm_iommu_mdp0_resources,
340 static struct platform_device msm_device_smmu_mdp1 = {
344 .parent = &msm_root_iommu_dev.dev,
346 .num_resources = ARRAY_SIZE(msm_iommu_mdp1_resources),
347 .resource = msm_iommu_mdp1_resources,
350 static struct platform_device msm_device_smmu_rot = {
354 .parent = &msm_root_iommu_dev.dev,
356 .num_resources = ARRAY_SIZE(msm_iommu_rot_resources),
357 .resource = msm_iommu_rot_resources,
360 static struct platform_device msm_device_smmu_ijpeg = {
364 .parent = &msm_root_iommu_dev.dev,
366 .num_resources = ARRAY_SIZE(msm_iommu_ijpeg_resources),
367 .resource = msm_iommu_ijpeg_resources,
370 static struct platform_device msm_device_smmu_vfe = {
374 .parent = &msm_root_iommu_dev.dev,
376 .num_resources = ARRAY_SIZE(msm_iommu_vfe_resources),
377 .resource = msm_iommu_vfe_resources,
380 static struct platform_device msm_device_smmu_vcodec_a = {
384 .parent = &msm_root_iommu_dev.dev,
386 .num_resources = ARRAY_SIZE(msm_iommu_vcodec_a_resources),
387 .resource = msm_iommu_vcodec_a_resources,
390 static struct platform_device msm_device_smmu_vcodec_b = {
394 .parent = &msm_root_iommu_dev.dev,
396 .num_resources = ARRAY_SIZE(msm_iommu_vcodec_b_resources),
397 .resource = msm_iommu_vcodec_b_resources,
400 static struct platform_device msm_device_smmu_gfx3d = {
404 .parent = &msm_root_iommu_dev.dev,
406 .num_resources = ARRAY_SIZE(msm_iommu_gfx3d_resources),
407 .resource = msm_iommu_gfx3d_resources,
410 static struct platform_device msm_device_smmu_gfx2d0 = {
414 .parent = &msm_root_iommu_dev.dev,
416 .num_resources = ARRAY_SIZE(msm_iommu_gfx2d0_resources),
417 .resource = msm_iommu_gfx2d0_resources,
420 static struct msm_iommu_ctx_dev jpegd_src_ctx = {
426 static struct msm_iommu_ctx_dev jpegd_dst_ctx = {
432 static struct msm_iommu_ctx_dev vpe_src_ctx = {
438 static struct msm_iommu_ctx_dev vpe_dst_ctx = {
444 static struct msm_iommu_ctx_dev mdp_vg1_ctx = {
450 static struct msm_iommu_ctx_dev mdp_rgb1_ctx = {
453 .mids = {1, 3, 4, 5, 6, 7, 8, 9, 10, -1}
456 static struct msm_iommu_ctx_dev mdp_vg2_ctx = {
462 static struct msm_iommu_ctx_dev mdp_rgb2_ctx = {
465 .mids = {1, 3, 4, 5, 6, 7, 8, 9, 10, -1}
468 static struct msm_iommu_ctx_dev rot_src_ctx = {
474 static struct msm_iommu_ctx_dev rot_dst_ctx = {
480 static struct msm_iommu_ctx_dev ijpeg_src_ctx = {
486 static struct msm_iommu_ctx_dev ijpeg_dst_ctx = {
492 static struct msm_iommu_ctx_dev vfe_imgwr_ctx = {
495 .mids = {2, 3, 4, 5, 6, 7, 8, -1}
498 static struct msm_iommu_ctx_dev vfe_misc_ctx = {
501 .mids = {0, 1, 9, -1}
504 static struct msm_iommu_ctx_dev vcodec_a_stream_ctx = {
505 .name = "vcodec_a_stream",
510 static struct msm_iommu_ctx_dev vcodec_a_mm1_ctx = {
511 .name = "vcodec_a_mm1",
513 .mids = {0, 1, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, -1}
516 static struct msm_iommu_ctx_dev vcodec_b_mm2_ctx = {
517 .name = "vcodec_b_mm2",
519 .mids = {0, 1, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, -1}
522 static struct msm_iommu_ctx_dev gfx3d_rbpa_ctx = {
523 .name = "gfx3d_rbpa",
528 static struct msm_iommu_ctx_dev gfx3d_cpvgttc_ctx = {
529 .name = "gfx3d_cpvgttc",
531 .mids = {0, 1, 2, 3, 4, 5, 6, 7, -1}
534 static struct msm_iommu_ctx_dev gfx3d_smmu_ctx = {
535 .name = "gfx3d_smmu",
537 .mids = {8, 9, 10, 11, 12, -1}
540 static struct msm_iommu_ctx_dev gfx2d0_pixv1_ctx = {
541 .name = "gfx2d0_pixv1_smmu",
543 .mids = {0, 3, 4, -1}
546 static struct msm_iommu_ctx_dev gfx2d0_texv3_ctx = {
547 .name = "gfx2d0_texv3_smmu",
549 .mids = {1, 6, 7, -1}
552 static struct platform_device msm_device_jpegd_src_ctx = {
553 .name = "msm_iommu_ctx",
556 .parent = &msm_device_smmu_jpegd.dev,
560 static struct platform_device msm_device_jpegd_dst_ctx = {
561 .name = "msm_iommu_ctx",
564 .parent = &msm_device_smmu_jpegd.dev,
568 static struct platform_device msm_device_vpe_src_ctx = {
569 .name = "msm_iommu_ctx",
572 .parent = &msm_device_smmu_vpe.dev,
576 static struct platform_device msm_device_vpe_dst_ctx = {
577 .name = "msm_iommu_ctx",
580 .parent = &msm_device_smmu_vpe.dev,
584 static struct platform_device msm_device_mdp_vg1_ctx = {
585 .name = "msm_iommu_ctx",
588 .parent = &msm_device_smmu_mdp0.dev,
592 static struct platform_device msm_device_mdp_rgb1_ctx = {
593 .name = "msm_iommu_ctx",
596 .parent = &msm_device_smmu_mdp0.dev,
600 static struct platform_device msm_device_mdp_vg2_ctx = {
601 .name = "msm_iommu_ctx",
604 .parent = &msm_device_smmu_mdp1.dev,
608 static struct platform_device msm_device_mdp_rgb2_ctx = {
609 .name = "msm_iommu_ctx",
612 .parent = &msm_device_smmu_mdp1.dev,
616 static struct platform_device msm_device_rot_src_ctx = {
617 .name = "msm_iommu_ctx",
620 .parent = &msm_device_smmu_rot.dev,
624 static struct platform_device msm_device_rot_dst_ctx = {
625 .name = "msm_iommu_ctx",
628 .parent = &msm_device_smmu_rot.dev,
632 static struct platform_device msm_device_ijpeg_src_ctx = {
633 .name = "msm_iommu_ctx",
636 .parent = &msm_device_smmu_ijpeg.dev,
640 static struct platform_device msm_device_ijpeg_dst_ctx = {
641 .name = "msm_iommu_ctx",
644 .parent = &msm_device_smmu_ijpeg.dev,
648 static struct platform_device msm_device_vfe_imgwr_ctx = {
649 .name = "msm_iommu_ctx",
652 .parent = &msm_device_smmu_vfe.dev,
656 static struct platform_device msm_device_vfe_misc_ctx = {
657 .name = "msm_iommu_ctx",
660 .parent = &msm_device_smmu_vfe.dev,
664 static struct platform_device msm_device_vcodec_a_stream_ctx = {
665 .name = "msm_iommu_ctx",
668 .parent = &msm_device_smmu_vcodec_a.dev,
672 static struct platform_device msm_device_vcodec_a_mm1_ctx = {
673 .name = "msm_iommu_ctx",
676 .parent = &msm_device_smmu_vcodec_a.dev,
680 static struct platform_device msm_device_vcodec_b_mm2_ctx = {
681 .name = "msm_iommu_ctx",
684 .parent = &msm_device_smmu_vcodec_b.dev,
688 static struct platform_device msm_device_gfx3d_rbpa_ctx = {
689 .name = "msm_iommu_ctx",
692 .parent = &msm_device_smmu_gfx3d.dev,
696 static struct platform_device msm_device_gfx3d_cpvgttc_ctx = {
697 .name = "msm_iommu_ctx",
700 .parent = &msm_device_smmu_gfx3d.dev,
704 static struct platform_device msm_device_gfx3d_smmu_ctx = {
705 .name = "msm_iommu_ctx",
708 .parent = &msm_device_smmu_gfx3d.dev,
712 static struct platform_device msm_device_gfx2d0_pixv1_ctx = {
713 .name = "msm_iommu_ctx",
716 .parent = &msm_device_smmu_gfx2d0.dev,
720 static struct platform_device msm_device_gfx2d0_texv3_ctx = {
721 .name = "msm_iommu_ctx",
724 .parent = &msm_device_smmu_gfx2d0.dev,
728 static struct platform_device *msm_iommu_devs[] = {
729 &msm_device_smmu_jpegd,
730 &msm_device_smmu_vpe,
731 &msm_device_smmu_mdp0,
732 &msm_device_smmu_mdp1,
733 &msm_device_smmu_rot,
734 &msm_device_smmu_ijpeg,
735 &msm_device_smmu_vfe,
736 &msm_device_smmu_vcodec_a,
737 &msm_device_smmu_vcodec_b,
738 &msm_device_smmu_gfx3d,
739 &msm_device_smmu_gfx2d0,
742 static struct msm_iommu_dev *msm_iommu_data[] = {
756 static struct platform_device *msm_iommu_ctx_devs[] = {
757 &msm_device_jpegd_src_ctx,
758 &msm_device_jpegd_dst_ctx,
759 &msm_device_vpe_src_ctx,
760 &msm_device_vpe_dst_ctx,
761 &msm_device_mdp_vg1_ctx,
762 &msm_device_mdp_rgb1_ctx,
763 &msm_device_mdp_vg2_ctx,
764 &msm_device_mdp_rgb2_ctx,
765 &msm_device_rot_src_ctx,
766 &msm_device_rot_dst_ctx,
767 &msm_device_ijpeg_src_ctx,
768 &msm_device_ijpeg_dst_ctx,
769 &msm_device_vfe_imgwr_ctx,
770 &msm_device_vfe_misc_ctx,
771 &msm_device_vcodec_a_stream_ctx,
772 &msm_device_vcodec_a_mm1_ctx,
773 &msm_device_vcodec_b_mm2_ctx,
774 &msm_device_gfx3d_rbpa_ctx,
775 &msm_device_gfx3d_cpvgttc_ctx,
776 &msm_device_gfx3d_smmu_ctx,
777 &msm_device_gfx2d0_pixv1_ctx,
778 &msm_device_gfx2d0_texv3_ctx,
781 static struct msm_iommu_ctx_dev *msm_iommu_ctx_data[] = {
796 &vcodec_a_stream_ctx,
806 static int msm8x60_iommu_init(void)
810 ret = platform_device_register(&msm_root_iommu_dev);
812 pr_err("Failed to register root IOMMU device!\n");
816 for (i = 0; i < ARRAY_SIZE(msm_iommu_devs); i++) {
817 ret = platform_device_add_data(msm_iommu_devs[i],
819 sizeof(struct msm_iommu_dev));
821 pr_err("platform_device_add_data failed, "
826 ret = platform_device_register(msm_iommu_devs[i]);
829 pr_err("platform_device_register smmu failed, "
835 for (i = 0; i < ARRAY_SIZE(msm_iommu_ctx_devs); i++) {
836 ret = platform_device_add_data(msm_iommu_ctx_devs[i],
837 msm_iommu_ctx_data[i],
838 sizeof(*msm_iommu_ctx_devs[i]));
840 pr_err("platform_device_add_data smmu failed, "
842 goto failure_unwind2;
845 ret = platform_device_register(msm_iommu_ctx_devs[i]);
847 pr_err("platform_device_register ctx failed, "
849 goto failure_unwind2;
856 platform_device_unregister(msm_iommu_ctx_devs[i]);
859 platform_device_unregister(msm_iommu_devs[i]);
861 platform_device_unregister(&msm_root_iommu_dev);
866 static void msm8x60_iommu_exit(void)
870 for (i = 0; i < ARRAY_SIZE(msm_iommu_ctx_devs); i++)
871 platform_device_unregister(msm_iommu_ctx_devs[i]);
873 for (i = 0; i < ARRAY_SIZE(msm_iommu_devs); ++i)
874 platform_device_unregister(msm_iommu_devs[i]);
876 platform_device_unregister(&msm_root_iommu_dev);
879 subsys_initcall(msm8x60_iommu_init);
880 module_exit(msm8x60_iommu_exit);
882 MODULE_LICENSE("GPL v2");
883 MODULE_AUTHOR("Stepan Moskovchenko <stepanm@codeaurora.org>");