1 /* Copyright (c) 2008-2009, Code Aurora Forum. All rights reserved.
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
20 #include <linux/irq.h>
21 #include <linux/interrupt.h>
24 static unsigned int int_enable;
25 static unsigned int wake_enable;
27 static struct sirc_regs_t sirc_regs = {
28 .int_enable = SPSS_SIRC_INT_ENABLE,
29 .int_enable_clear = SPSS_SIRC_INT_ENABLE_CLEAR,
30 .int_enable_set = SPSS_SIRC_INT_ENABLE_SET,
31 .int_type = SPSS_SIRC_INT_TYPE,
32 .int_polarity = SPSS_SIRC_INT_POLARITY,
33 .int_clear = SPSS_SIRC_INT_CLEAR,
36 static struct sirc_cascade_regs sirc_reg_table[] = {
38 .int_status = SPSS_SIRC_IRQ_STATUS,
39 .cascade_irq = INT_SIRC_0,
43 /* Mask off the given interrupt. Keep the int_enable mask in sync with
44 the enable reg, so it can be restored after power collapse. */
45 static void sirc_irq_mask(unsigned int irq)
50 mask = 1 << (irq - FIRST_SIRC_IRQ);
51 writel(mask, sirc_regs.int_enable_clear);
56 /* Unmask the given interrupt. Keep the int_enable mask in sync with
57 the enable reg, so it can be restored after power collapse. */
58 static void sirc_irq_unmask(unsigned int irq)
62 mask = 1 << (irq - FIRST_SIRC_IRQ);
63 writel(mask, sirc_regs.int_enable_set);
68 static void sirc_irq_ack(unsigned int irq)
72 mask = 1 << (irq - FIRST_SIRC_IRQ);
73 writel(mask, sirc_regs.int_clear);
77 static int sirc_irq_set_wake(unsigned int irq, unsigned int on)
81 /* Used to set the interrupt enable mask during power collapse. */
82 mask = 1 << (irq - FIRST_SIRC_IRQ);
91 static int sirc_irq_set_type(unsigned int irq, unsigned int flow_type)
96 mask = 1 << (irq - FIRST_SIRC_IRQ);
97 val = readl(sirc_regs.int_polarity);
99 if (flow_type & (IRQF_TRIGGER_LOW | IRQF_TRIGGER_FALLING))
104 writel(val, sirc_regs.int_polarity);
106 val = readl(sirc_regs.int_type);
107 if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) {
109 irq_desc[irq].handle_irq = handle_edge_irq;
112 irq_desc[irq].handle_irq = handle_level_irq;
115 writel(val, sirc_regs.int_type);
120 /* Finds the pending interrupt on the passed cascade irq and redrives it */
121 static void sirc_irq_handler(unsigned int irq, struct irq_desc *desc)
123 unsigned int reg = 0;
127 while ((reg < ARRAY_SIZE(sirc_reg_table)) &&
128 (sirc_reg_table[reg].cascade_irq != irq))
131 status = readl(sirc_reg_table[reg].int_status);
137 (sirq < NR_SIRC_IRQS) && ((status & (1U << sirq)) == 0);
140 generic_handle_irq(sirq+FIRST_SIRC_IRQ);
142 desc->chip->ack(irq);
145 static struct irq_chip sirc_irq_chip = {
148 .mask = sirc_irq_mask,
149 .unmask = sirc_irq_unmask,
150 .set_wake = sirc_irq_set_wake,
151 .set_type = sirc_irq_set_type,
154 void __init msm_init_sirc(void)
161 for (i = FIRST_SIRC_IRQ; i < LAST_SIRC_IRQ; i++) {
162 set_irq_chip(i, &sirc_irq_chip);
163 set_irq_handler(i, handle_edge_irq);
164 set_irq_flags(i, IRQF_VALID);
167 for (i = 0; i < ARRAY_SIZE(sirc_reg_table); i++) {
168 set_irq_chained_handler(sirc_reg_table[i].cascade_irq,
170 set_irq_wake(sirc_reg_table[i].cascade_irq, 1);