2 * arch/arm/mach-mv78xx0/common.c
4 * Core functions for Marvell MV78xx0 SoCs
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/platform_device.h>
14 #include <linux/serial_8250.h>
15 #include <linux/mbus.h>
16 #include <linux/mv643xx_eth.h>
17 #include <linux/mv643xx_i2c.h>
18 #include <linux/ata_platform.h>
19 #include <linux/ethtool.h>
20 #include <asm/mach/map.h>
21 #include <asm/mach/time.h>
22 #include <mach/mv78xx0.h>
23 #include <mach/bridge-regs.h>
24 #include <linux/spi/orion_spi.h>
25 #include <plat/cache-feroceon-l2.h>
26 #include <plat/ehci-orion.h>
27 #include <plat/mv_xor.h>
28 #include <plat/orion_nand.h>
29 #include <plat/orion_wdt.h>
30 #include <plat/time.h>
34 /*****************************************************************************
36 ****************************************************************************/
37 int mv78xx0_core_index(void)
42 * Read Extra Features register.
44 __asm__("mrc p15, 1, %0, c15, c1, 0" : "=r" (extra));
46 return !!(extra & 0x00004000);
49 static int get_hclk(void)
54 * HCLK tick rate is configured by DEV_D[7:5] pins.
56 switch ((readl(SAMPLE_AT_RESET_LOW) >> 5) & 7) {
73 panic("unknown HCLK PLL setting: %.8x\n",
74 readl(SAMPLE_AT_RESET_LOW));
80 static void get_pclk_l2clk(int hclk, int core_index, int *pclk, int *l2clk)
85 * Core #0 PCLK/L2CLK is configured by bits [13:8], core #1
86 * PCLK/L2CLK by bits [19:14].
88 if (core_index == 0) {
89 cfg = (readl(SAMPLE_AT_RESET_LOW) >> 8) & 0x3f;
91 cfg = (readl(SAMPLE_AT_RESET_LOW) >> 14) & 0x3f;
95 * Bits [11:8] ([17:14] for core #1) configure the PCLK:HCLK
96 * ratio (1, 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6).
98 *pclk = ((u64)hclk * (2 + (cfg & 0xf))) >> 1;
101 * Bits [13:12] ([19:18] for core #1) configure the PCLK:L2CLK
104 *l2clk = *pclk / (((cfg >> 4) & 3) + 1);
107 static int get_tclk(void)
112 * TCLK tick rate is configured by DEV_A[2:0] strap pins.
114 switch ((readl(SAMPLE_AT_RESET_HIGH) >> 6) & 7) {
122 panic("unknown TCLK PLL setting: %.8x\n",
123 readl(SAMPLE_AT_RESET_HIGH));
130 /*****************************************************************************
131 * I/O Address Mapping
132 ****************************************************************************/
133 static struct map_desc mv78xx0_io_desc[] __initdata = {
135 .virtual = MV78XX0_CORE_REGS_VIRT_BASE,
137 .length = MV78XX0_CORE_REGS_SIZE,
140 .virtual = MV78XX0_PCIE_IO_VIRT_BASE(0),
141 .pfn = __phys_to_pfn(MV78XX0_PCIE_IO_PHYS_BASE(0)),
142 .length = MV78XX0_PCIE_IO_SIZE * 8,
145 .virtual = MV78XX0_REGS_VIRT_BASE,
146 .pfn = __phys_to_pfn(MV78XX0_REGS_PHYS_BASE),
147 .length = MV78XX0_REGS_SIZE,
152 void __init mv78xx0_map_io(void)
157 * Map the right set of per-core registers depending on
158 * which core we are running on.
160 if (mv78xx0_core_index() == 0) {
161 phys = MV78XX0_CORE0_REGS_PHYS_BASE;
163 phys = MV78XX0_CORE1_REGS_PHYS_BASE;
165 mv78xx0_io_desc[0].pfn = __phys_to_pfn(phys);
167 iotable_init(mv78xx0_io_desc, ARRAY_SIZE(mv78xx0_io_desc));
171 /*****************************************************************************
173 ****************************************************************************/
174 static struct orion_ehci_data mv78xx0_ehci_data = {
175 .dram = &mv78xx0_mbus_dram_info,
176 .phy_version = EHCI_PHY_NA,
179 static u64 ehci_dmamask = 0xffffffffUL;
182 /*****************************************************************************
184 ****************************************************************************/
185 static struct resource mv78xx0_ehci0_resources[] = {
187 .start = USB0_PHYS_BASE,
188 .end = USB0_PHYS_BASE + 0x0fff,
189 .flags = IORESOURCE_MEM,
191 .start = IRQ_MV78XX0_USB_0,
192 .end = IRQ_MV78XX0_USB_0,
193 .flags = IORESOURCE_IRQ,
197 static struct platform_device mv78xx0_ehci0 = {
198 .name = "orion-ehci",
201 .dma_mask = &ehci_dmamask,
202 .coherent_dma_mask = 0xffffffff,
203 .platform_data = &mv78xx0_ehci_data,
205 .resource = mv78xx0_ehci0_resources,
206 .num_resources = ARRAY_SIZE(mv78xx0_ehci0_resources),
209 void __init mv78xx0_ehci0_init(void)
211 platform_device_register(&mv78xx0_ehci0);
215 /*****************************************************************************
217 ****************************************************************************/
218 static struct resource mv78xx0_ehci1_resources[] = {
220 .start = USB1_PHYS_BASE,
221 .end = USB1_PHYS_BASE + 0x0fff,
222 .flags = IORESOURCE_MEM,
224 .start = IRQ_MV78XX0_USB_1,
225 .end = IRQ_MV78XX0_USB_1,
226 .flags = IORESOURCE_IRQ,
230 static struct platform_device mv78xx0_ehci1 = {
231 .name = "orion-ehci",
234 .dma_mask = &ehci_dmamask,
235 .coherent_dma_mask = 0xffffffff,
236 .platform_data = &mv78xx0_ehci_data,
238 .resource = mv78xx0_ehci1_resources,
239 .num_resources = ARRAY_SIZE(mv78xx0_ehci1_resources),
242 void __init mv78xx0_ehci1_init(void)
244 platform_device_register(&mv78xx0_ehci1);
248 /*****************************************************************************
250 ****************************************************************************/
251 static struct resource mv78xx0_ehci2_resources[] = {
253 .start = USB2_PHYS_BASE,
254 .end = USB2_PHYS_BASE + 0x0fff,
255 .flags = IORESOURCE_MEM,
257 .start = IRQ_MV78XX0_USB_2,
258 .end = IRQ_MV78XX0_USB_2,
259 .flags = IORESOURCE_IRQ,
263 static struct platform_device mv78xx0_ehci2 = {
264 .name = "orion-ehci",
267 .dma_mask = &ehci_dmamask,
268 .coherent_dma_mask = 0xffffffff,
269 .platform_data = &mv78xx0_ehci_data,
271 .resource = mv78xx0_ehci2_resources,
272 .num_resources = ARRAY_SIZE(mv78xx0_ehci2_resources),
275 void __init mv78xx0_ehci2_init(void)
277 platform_device_register(&mv78xx0_ehci2);
281 /*****************************************************************************
283 ****************************************************************************/
284 struct mv643xx_eth_shared_platform_data mv78xx0_ge00_shared_data = {
286 .dram = &mv78xx0_mbus_dram_info,
289 static struct resource mv78xx0_ge00_shared_resources[] = {
292 .start = GE00_PHYS_BASE + 0x2000,
293 .end = GE00_PHYS_BASE + 0x3fff,
294 .flags = IORESOURCE_MEM,
296 .name = "ge err irq",
297 .start = IRQ_MV78XX0_GE_ERR,
298 .end = IRQ_MV78XX0_GE_ERR,
299 .flags = IORESOURCE_IRQ,
303 static struct platform_device mv78xx0_ge00_shared = {
304 .name = MV643XX_ETH_SHARED_NAME,
307 .platform_data = &mv78xx0_ge00_shared_data,
309 .num_resources = ARRAY_SIZE(mv78xx0_ge00_shared_resources),
310 .resource = mv78xx0_ge00_shared_resources,
313 static struct resource mv78xx0_ge00_resources[] = {
316 .start = IRQ_MV78XX0_GE00_SUM,
317 .end = IRQ_MV78XX0_GE00_SUM,
318 .flags = IORESOURCE_IRQ,
322 static struct platform_device mv78xx0_ge00 = {
323 .name = MV643XX_ETH_NAME,
326 .resource = mv78xx0_ge00_resources,
328 .coherent_dma_mask = 0xffffffff,
332 void __init mv78xx0_ge00_init(struct mv643xx_eth_platform_data *eth_data)
334 eth_data->shared = &mv78xx0_ge00_shared;
335 mv78xx0_ge00.dev.platform_data = eth_data;
337 platform_device_register(&mv78xx0_ge00_shared);
338 platform_device_register(&mv78xx0_ge00);
342 /*****************************************************************************
344 ****************************************************************************/
345 struct mv643xx_eth_shared_platform_data mv78xx0_ge01_shared_data = {
347 .dram = &mv78xx0_mbus_dram_info,
348 .shared_smi = &mv78xx0_ge00_shared,
351 static struct resource mv78xx0_ge01_shared_resources[] = {
354 .start = GE01_PHYS_BASE + 0x2000,
355 .end = GE01_PHYS_BASE + 0x3fff,
356 .flags = IORESOURCE_MEM,
360 static struct platform_device mv78xx0_ge01_shared = {
361 .name = MV643XX_ETH_SHARED_NAME,
364 .platform_data = &mv78xx0_ge01_shared_data,
367 .resource = mv78xx0_ge01_shared_resources,
370 static struct resource mv78xx0_ge01_resources[] = {
373 .start = IRQ_MV78XX0_GE01_SUM,
374 .end = IRQ_MV78XX0_GE01_SUM,
375 .flags = IORESOURCE_IRQ,
379 static struct platform_device mv78xx0_ge01 = {
380 .name = MV643XX_ETH_NAME,
383 .resource = mv78xx0_ge01_resources,
385 .coherent_dma_mask = 0xffffffff,
389 void __init mv78xx0_ge01_init(struct mv643xx_eth_platform_data *eth_data)
391 eth_data->shared = &mv78xx0_ge01_shared;
392 mv78xx0_ge01.dev.platform_data = eth_data;
394 platform_device_register(&mv78xx0_ge01_shared);
395 platform_device_register(&mv78xx0_ge01);
399 /*****************************************************************************
401 ****************************************************************************/
402 struct mv643xx_eth_shared_platform_data mv78xx0_ge10_shared_data = {
404 .dram = &mv78xx0_mbus_dram_info,
405 .shared_smi = &mv78xx0_ge00_shared,
408 static struct resource mv78xx0_ge10_shared_resources[] = {
411 .start = GE10_PHYS_BASE + 0x2000,
412 .end = GE10_PHYS_BASE + 0x3fff,
413 .flags = IORESOURCE_MEM,
417 static struct platform_device mv78xx0_ge10_shared = {
418 .name = MV643XX_ETH_SHARED_NAME,
421 .platform_data = &mv78xx0_ge10_shared_data,
424 .resource = mv78xx0_ge10_shared_resources,
427 static struct resource mv78xx0_ge10_resources[] = {
430 .start = IRQ_MV78XX0_GE10_SUM,
431 .end = IRQ_MV78XX0_GE10_SUM,
432 .flags = IORESOURCE_IRQ,
436 static struct platform_device mv78xx0_ge10 = {
437 .name = MV643XX_ETH_NAME,
440 .resource = mv78xx0_ge10_resources,
442 .coherent_dma_mask = 0xffffffff,
446 void __init mv78xx0_ge10_init(struct mv643xx_eth_platform_data *eth_data)
450 eth_data->shared = &mv78xx0_ge10_shared;
451 mv78xx0_ge10.dev.platform_data = eth_data;
454 * On the Z0, ge10 and ge11 are internally connected back
455 * to back, and not brought out.
457 mv78xx0_pcie_id(&dev, &rev);
458 if (dev == MV78X00_Z0_DEV_ID) {
459 eth_data->phy_addr = MV643XX_ETH_PHY_NONE;
460 eth_data->speed = SPEED_1000;
461 eth_data->duplex = DUPLEX_FULL;
464 platform_device_register(&mv78xx0_ge10_shared);
465 platform_device_register(&mv78xx0_ge10);
469 /*****************************************************************************
471 ****************************************************************************/
472 struct mv643xx_eth_shared_platform_data mv78xx0_ge11_shared_data = {
474 .dram = &mv78xx0_mbus_dram_info,
475 .shared_smi = &mv78xx0_ge00_shared,
478 static struct resource mv78xx0_ge11_shared_resources[] = {
481 .start = GE11_PHYS_BASE + 0x2000,
482 .end = GE11_PHYS_BASE + 0x3fff,
483 .flags = IORESOURCE_MEM,
487 static struct platform_device mv78xx0_ge11_shared = {
488 .name = MV643XX_ETH_SHARED_NAME,
491 .platform_data = &mv78xx0_ge11_shared_data,
494 .resource = mv78xx0_ge11_shared_resources,
497 static struct resource mv78xx0_ge11_resources[] = {
500 .start = IRQ_MV78XX0_GE11_SUM,
501 .end = IRQ_MV78XX0_GE11_SUM,
502 .flags = IORESOURCE_IRQ,
506 static struct platform_device mv78xx0_ge11 = {
507 .name = MV643XX_ETH_NAME,
510 .resource = mv78xx0_ge11_resources,
512 .coherent_dma_mask = 0xffffffff,
516 void __init mv78xx0_ge11_init(struct mv643xx_eth_platform_data *eth_data)
520 eth_data->shared = &mv78xx0_ge11_shared;
521 mv78xx0_ge11.dev.platform_data = eth_data;
524 * On the Z0, ge10 and ge11 are internally connected back
525 * to back, and not brought out.
527 mv78xx0_pcie_id(&dev, &rev);
528 if (dev == MV78X00_Z0_DEV_ID) {
529 eth_data->phy_addr = MV643XX_ETH_PHY_NONE;
530 eth_data->speed = SPEED_1000;
531 eth_data->duplex = DUPLEX_FULL;
534 platform_device_register(&mv78xx0_ge11_shared);
535 platform_device_register(&mv78xx0_ge11);
538 /*****************************************************************************
540 ****************************************************************************/
541 static struct orion_spi_info mv78x00_spi_plat_data = {
544 static struct resource mv78x00_spi_resources[] = {
546 .start = SPI_PHYS_BASE,
547 .end = SPI_PHYS_BASE + SZ_512 - 1,
548 .flags = IORESOURCE_MEM,
552 static struct platform_device mv78x00_spi = {
555 .resource = mv78x00_spi_resources,
557 .platform_data = &mv78x00_spi_plat_data,
559 .num_resources = ARRAY_SIZE(mv78x00_spi_resources),
562 void __init mv78x00_spi_init()
564 platform_device_register(&mv78x00_spi);
567 /*****************************************************************************
569 ****************************************************************************/
571 static struct mv64xxx_i2c_pdata mv78xx0_i2c_0_pdata = {
572 .freq_m = 8, /* assumes 166 MHz TCLK */
574 .timeout = 1000, /* Default timeout of 1 second */
577 static struct resource mv78xx0_i2c_0_resources[] = {
579 .start = I2C_0_PHYS_BASE,
580 .end = I2C_0_PHYS_BASE + 0x1f,
581 .flags = IORESOURCE_MEM,
583 .start = IRQ_MV78XX0_I2C_0,
584 .end = IRQ_MV78XX0_I2C_0,
585 .flags = IORESOURCE_IRQ,
590 static struct platform_device mv78xx0_i2c_0 = {
591 .name = MV64XXX_I2C_CTLR_NAME,
593 .num_resources = ARRAY_SIZE(mv78xx0_i2c_0_resources),
594 .resource = mv78xx0_i2c_0_resources,
596 .platform_data = &mv78xx0_i2c_0_pdata,
600 /*****************************************************************************
602 ****************************************************************************/
604 static struct mv64xxx_i2c_pdata mv78xx0_i2c_1_pdata = {
605 .freq_m = 8, /* assumes 166 MHz TCLK */
607 .timeout = 1000, /* Default timeout of 1 second */
610 static struct resource mv78xx0_i2c_1_resources[] = {
612 .start = I2C_1_PHYS_BASE,
613 .end = I2C_1_PHYS_BASE + 0x1f,
614 .flags = IORESOURCE_MEM,
616 .start = IRQ_MV78XX0_I2C_1,
617 .end = IRQ_MV78XX0_I2C_1,
618 .flags = IORESOURCE_IRQ,
623 static struct platform_device mv78xx0_i2c_1 = {
624 .name = MV64XXX_I2C_CTLR_NAME,
626 .num_resources = ARRAY_SIZE(mv78xx0_i2c_1_resources),
627 .resource = mv78xx0_i2c_1_resources,
629 .platform_data = &mv78xx0_i2c_1_pdata,
633 void __init mv78xx0_i2c_init(void)
635 platform_device_register(&mv78xx0_i2c_0);
636 platform_device_register(&mv78xx0_i2c_1);
639 /*****************************************************************************
641 ****************************************************************************/
642 static struct resource mv78xx0_sata_resources[] = {
645 .start = SATA_PHYS_BASE,
646 .end = SATA_PHYS_BASE + 0x5000 - 1,
647 .flags = IORESOURCE_MEM,
650 .start = IRQ_MV78XX0_SATA,
651 .end = IRQ_MV78XX0_SATA,
652 .flags = IORESOURCE_IRQ,
656 static struct platform_device mv78xx0_sata = {
660 .coherent_dma_mask = 0xffffffff,
662 .num_resources = ARRAY_SIZE(mv78xx0_sata_resources),
663 .resource = mv78xx0_sata_resources,
666 void __init mv78xx0_sata_init(struct mv_sata_platform_data *sata_data)
668 sata_data->dram = &mv78xx0_mbus_dram_info;
669 mv78xx0_sata.dev.platform_data = sata_data;
670 platform_device_register(&mv78xx0_sata);
674 /*****************************************************************************
676 ****************************************************************************/
677 static struct plat_serial8250_port mv78xx0_uart0_data[] = {
679 .mapbase = UART0_PHYS_BASE,
680 .membase = (char *)UART0_VIRT_BASE,
681 .irq = IRQ_MV78XX0_UART_0,
682 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
690 static struct resource mv78xx0_uart0_resources[] = {
692 .start = UART0_PHYS_BASE,
693 .end = UART0_PHYS_BASE + 0xff,
694 .flags = IORESOURCE_MEM,
696 .start = IRQ_MV78XX0_UART_0,
697 .end = IRQ_MV78XX0_UART_0,
698 .flags = IORESOURCE_IRQ,
702 static struct platform_device mv78xx0_uart0 = {
703 .name = "serial8250",
706 .platform_data = mv78xx0_uart0_data,
708 .resource = mv78xx0_uart0_resources,
709 .num_resources = ARRAY_SIZE(mv78xx0_uart0_resources),
712 void __init mv78xx0_uart0_init(void)
714 platform_device_register(&mv78xx0_uart0);
718 /*****************************************************************************
720 ****************************************************************************/
721 static struct plat_serial8250_port mv78xx0_uart1_data[] = {
723 .mapbase = UART1_PHYS_BASE,
724 .membase = (char *)UART1_VIRT_BASE,
725 .irq = IRQ_MV78XX0_UART_1,
726 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
734 static struct resource mv78xx0_uart1_resources[] = {
736 .start = UART1_PHYS_BASE,
737 .end = UART1_PHYS_BASE + 0xff,
738 .flags = IORESOURCE_MEM,
740 .start = IRQ_MV78XX0_UART_1,
741 .end = IRQ_MV78XX0_UART_1,
742 .flags = IORESOURCE_IRQ,
746 static struct platform_device mv78xx0_uart1 = {
747 .name = "serial8250",
750 .platform_data = mv78xx0_uart1_data,
752 .resource = mv78xx0_uart1_resources,
753 .num_resources = ARRAY_SIZE(mv78xx0_uart1_resources),
756 void __init mv78xx0_uart1_init(void)
758 platform_device_register(&mv78xx0_uart1);
762 /*****************************************************************************
764 ****************************************************************************/
765 static struct plat_serial8250_port mv78xx0_uart2_data[] = {
767 .mapbase = UART2_PHYS_BASE,
768 .membase = (char *)UART2_VIRT_BASE,
769 .irq = IRQ_MV78XX0_UART_2,
770 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
778 static struct resource mv78xx0_uart2_resources[] = {
780 .start = UART2_PHYS_BASE,
781 .end = UART2_PHYS_BASE + 0xff,
782 .flags = IORESOURCE_MEM,
784 .start = IRQ_MV78XX0_UART_2,
785 .end = IRQ_MV78XX0_UART_2,
786 .flags = IORESOURCE_IRQ,
790 static struct platform_device mv78xx0_uart2 = {
791 .name = "serial8250",
794 .platform_data = mv78xx0_uart2_data,
796 .resource = mv78xx0_uart2_resources,
797 .num_resources = ARRAY_SIZE(mv78xx0_uart2_resources),
800 void __init mv78xx0_uart2_init(void)
802 platform_device_register(&mv78xx0_uart2);
806 /*****************************************************************************
808 ****************************************************************************/
809 static struct plat_serial8250_port mv78xx0_uart3_data[] = {
811 .mapbase = UART3_PHYS_BASE,
812 .membase = (char *)UART3_VIRT_BASE,
813 .irq = IRQ_MV78XX0_UART_3,
814 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
822 static struct resource mv78xx0_uart3_resources[] = {
824 .start = UART3_PHYS_BASE,
825 .end = UART3_PHYS_BASE + 0xff,
826 .flags = IORESOURCE_MEM,
828 .start = IRQ_MV78XX0_UART_3,
829 .end = IRQ_MV78XX0_UART_3,
830 .flags = IORESOURCE_IRQ,
834 static struct platform_device mv78xx0_uart3 = {
835 .name = "serial8250",
838 .platform_data = mv78xx0_uart3_data,
840 .resource = mv78xx0_uart3_resources,
841 .num_resources = ARRAY_SIZE(mv78xx0_uart3_resources),
844 void __init mv78xx0_uart3_init(void)
846 platform_device_register(&mv78xx0_uart3);
849 /*****************************************************************************
850 * Cryptographic Engines and Security Accelerator (CESA)
851 ****************************************************************************/
853 static struct resource mv78xx0_crypto_res[] = {
856 .start = CRYPTO_PHYS_BASE,
857 .end = CRYPTO_PHYS_BASE + 0xffff,
858 .flags = IORESOURCE_MEM,
861 .start = MV78XX0_SRAM_PHYS_BASE,
862 .end = MV78XX0_SRAM_PHYS_BASE + MV78XX0_SRAM_SIZE - 1,
863 .flags = IORESOURCE_MEM,
865 .name = "crypto interrupt",
866 .start = IRQ_MV78XX0_CRYPTO,
867 .end = IRQ_MV78XX0_CRYPTO,
868 .flags = IORESOURCE_IRQ,
872 static struct platform_device mv78xx0_crypto_device = {
875 .num_resources = ARRAY_SIZE(mv78xx0_crypto_res),
876 .resource = mv78xx0_crypto_res,
879 void __init mv78xx0_crypto_init(void)
881 platform_device_register(&mv78xx0_crypto_device);
884 /*****************************************************************************
886 ****************************************************************************/
887 static struct mv_xor_platform_shared_data mv78xx0_xor_shared_data = {
888 .dram = &mv78xx0_mbus_dram_info,
891 static u64 mv78xx0_xor_dmamask = DMA_BIT_MASK(32);
894 /*****************************************************************************
896 ****************************************************************************/
897 static struct resource mv78xx0_xor0_shared_resources[] = {
900 .start = XOR0_PHYS_BASE,
901 .end = XOR0_PHYS_BASE + 0xff,
902 .flags = IORESOURCE_MEM,
904 .name = "xor 0 high",
905 .start = XOR0_HIGH_PHYS_BASE,
906 .end = XOR0_HIGH_PHYS_BASE + 0xff,
907 .flags = IORESOURCE_MEM,
911 static struct platform_device mv78xx0_xor0_shared = {
912 .name = MV_XOR_SHARED_NAME,
915 .platform_data = &mv78xx0_xor_shared_data,
917 .num_resources = ARRAY_SIZE(mv78xx0_xor0_shared_resources),
918 .resource = mv78xx0_xor0_shared_resources,
921 static struct resource mv78xx0_xor00_resources[] = {
923 .start = IRQ_MV78XX0_XOR_0,
924 .end = IRQ_MV78XX0_XOR_0,
925 .flags = IORESOURCE_IRQ,
929 static struct mv_xor_platform_data mv78xx0_xor00_data = {
930 .shared = &mv78xx0_xor0_shared,
932 .pool_size = PAGE_SIZE,
935 static struct platform_device mv78xx0_xor00_channel = {
938 .num_resources = ARRAY_SIZE(mv78xx0_xor00_resources),
939 .resource = mv78xx0_xor00_resources,
941 .dma_mask = &mv78xx0_xor_dmamask,
942 .coherent_dma_mask = DMA_BIT_MASK(64),
943 .platform_data = &mv78xx0_xor00_data,
947 static struct resource mv78xx0_xor01_resources[] = {
949 .start = IRQ_MV78XX0_XOR_1,
950 .end = IRQ_MV78XX0_XOR_1,
951 .flags = IORESOURCE_IRQ,
955 static struct mv_xor_platform_data mv78xx0_xor01_data = {
956 .shared = &mv78xx0_xor0_shared,
958 .pool_size = PAGE_SIZE,
961 static struct platform_device mv78xx0_xor01_channel = {
964 .num_resources = ARRAY_SIZE(mv78xx0_xor01_resources),
965 .resource = mv78xx0_xor01_resources,
967 .dma_mask = &mv78xx0_xor_dmamask,
968 .coherent_dma_mask = DMA_BIT_MASK(64),
969 .platform_data = &mv78xx0_xor01_data,
973 void __init mv78xx0_xor0_init(void)
975 platform_device_register(&mv78xx0_xor0_shared);
978 * two engines can't do memset simultaneously, this limitation
979 * satisfied by removing memset support from one of the engines.
981 dma_cap_set(DMA_MEMCPY, mv78xx0_xor00_data.cap_mask);
982 dma_cap_set(DMA_XOR, mv78xx0_xor00_data.cap_mask);
983 platform_device_register(&mv78xx0_xor00_channel);
985 dma_cap_set(DMA_MEMCPY, mv78xx0_xor01_data.cap_mask);
986 dma_cap_set(DMA_MEMSET, mv78xx0_xor01_data.cap_mask);
987 dma_cap_set(DMA_XOR, mv78xx0_xor01_data.cap_mask);
988 platform_device_register(&mv78xx0_xor01_channel);
992 /*****************************************************************************
994 ****************************************************************************/
995 static struct orion_wdt_platform_data mv78xx0_wdt_data = {
999 static struct platform_device mv78xx0_wdt_device = {
1000 .name = "orion_wdt",
1003 .platform_data = &mv78xx0_wdt_data,
1008 void __init mv78xx0_wdt_init(void)
1010 mv78xx0_wdt_data.tclk = get_tclk();
1011 platform_device_register(&mv78xx0_wdt_device);
1015 /*****************************************************************************
1017 ****************************************************************************/
1018 static void mv78xx0_timer_init(void)
1020 orion_time_init(IRQ_MV78XX0_TIMER_1, get_tclk());
1023 struct sys_timer mv78xx0_timer = {
1024 .init = mv78xx0_timer_init,
1028 /*****************************************************************************
1030 ****************************************************************************/
1031 static char * __init mv78xx0_id(void)
1035 mv78xx0_pcie_id(&dev, &rev);
1037 if (dev == MV78X00_Z0_DEV_ID) {
1038 if (rev == MV78X00_REV_Z0)
1039 return "MV78X00-Z0";
1041 return "MV78X00-Rev-Unsupported";
1042 } else if (dev == MV78100_DEV_ID) {
1043 if (rev == MV78100_REV_A0)
1044 return "MV78100-A0";
1045 else if (rev == MV78100_REV_A1)
1046 return "MV78100-A1";
1048 return "MV78100-Rev-Unsupported";
1049 } else if (dev == MV78200_DEV_ID) {
1050 if (rev == MV78100_REV_A0)
1051 return "MV78200-A0";
1053 return "MV78200-Rev-Unsupported";
1055 return "Device-Unknown";
1059 static int __init is_l2_writethrough(void)
1061 return !!(readl(CPU_CONTROL) & L2_WRITETHROUGH);
1064 void __init mv78xx0_init(void)
1072 core_index = mv78xx0_core_index();
1074 get_pclk_l2clk(hclk, core_index, &pclk, &l2clk);
1077 printk(KERN_INFO "%s ", mv78xx0_id());
1078 printk("core #%d, ", core_index);
1079 printk("PCLK = %dMHz, ", (pclk + 499999) / 1000000);
1080 printk("L2 = %dMHz, ", (l2clk + 499999) / 1000000);
1081 printk("HCLK = %dMHz, ", (hclk + 499999) / 1000000);
1082 printk("TCLK = %dMHz\n", (tclk + 499999) / 1000000);
1084 mv78xx0_setup_cpu_mbus();
1086 #ifdef CONFIG_CACHE_FEROCEON_L2
1087 feroceon_l2_init(is_l2_writethrough());
1090 mv78xx0_ge00_shared_data.t_clk = tclk;
1091 mv78xx0_ge01_shared_data.t_clk = tclk;
1092 mv78xx0_ge10_shared_data.t_clk = tclk;
1093 mv78xx0_ge11_shared_data.t_clk = tclk;
1094 mv78xx0_uart0_data[0].uartclk = tclk;
1095 mv78xx0_uart1_data[0].uartclk = tclk;
1096 mv78xx0_uart2_data[0].uartclk = tclk;
1097 mv78xx0_uart3_data[0].uartclk = tclk;
1098 mv78x00_spi_plat_data.tclk = tclk;