2 * Cogent CSB1725 CPU module board setup with customizations
6 * arch/arm/mach-mv78xx0/db78x00-bp-setup.c
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
13 #include <linux/kernel.h>
14 #include <linux/init.h>
15 #include <linux/platform_device.h>
16 #include <linux/ata_platform.h>
17 #include <linux/mv643xx_eth.h>
18 #include <linux/ethtool.h>
19 #include <linux/spi/spi.h>
20 #include <linux/spi/flash.h>
21 #include <linux/i2c.h>
22 #include <linux/i2c/pca953x.h>
23 #include <linux/mtd/nand.h>
24 #include <linux/mtd/physmap.h>
25 #include <linux/mtd/partitions.h>
26 #include <linux/gpio.h>
28 #include <linux/irq.h>
29 #include <mach/mv78xx0.h>
30 #include <asm/mach-types.h>
31 #include <asm/mach/arch.h>
32 #include <plat/orion_nand.h>
37 static unsigned int rdstor_mpp_config[] __initdata = {
42 MPP12_GPIO, /* parallel LCD */
43 MPP13_GPIO, /* parallel LCD */
44 MPP14_GPIO, /* parallel LCD */
45 MPP15_GPIO, /* parallel LCD */
46 MPP16_UNUSED, /* GPIO16 - n.a. */
47 MPP17_UNUSED, /* GPIO17 */
48 MPP18_GPIO, /* parallel LCD A0 */
49 MPP19_GPIO, /* parallel LCD R/W */
50 MPP20_GPIO, /* parallel LCD LCD_EN */
51 MPP21_GPIO, /* parallel LCD CSn */
52 MPP22_GPIO, /* GPIO22 WAKE0 PCI Express 0 Wake Input (on pin MPP22) */
53 MPP23_GPIO, /* GPIO23 WAKE0 PCI Express 0 Wake Input (on pin MPP23) */
56 MPP26_GPIO, /* LCD module RESETn */
57 MPP27_GPIO, /* LCD module switch */
58 MPP28_GPIO, /* parallel LCD */
59 MPP29_GPIO, /* parallel LCD */
60 MPP30_GPIO, /* parallel LCD */
61 MPP31_GPIO, /* parallel LCD */
62 MPP32_GPIO, /* GPIO0 I2C0_INT I2C IRQ */
63 MPP33_GPIO, /* GPIO1 T_CRIT LM86 thermal IRQ */
64 MPP34_GPIO, /* GPIO2 MII_INT PHY Interrupt for off module MII Bus */
65 MPP35_GPIO, /* GPIO3 PHY_INT 88E1121R Dual PHY Interrupt */
66 MPP36_GPIO, /* PS1 PF input, GPIO4 INTA MXM Interrupt A */
67 MPP37_GPIO, /* PWR SWITCH CSB, GPIO5 INTB MXM Interrupt B */
68 MPP38_GPIO, /* GPIO6 INTC MXM Interrupt C */
69 MPP39_GPIO, /* GPIO7 INTD MXM Interrupt D */
70 MPP47_GPIO, /* GPIO16 N_RDY NAND ready/busy */
80 static struct mv643xx_eth_platform_data db78x00_ge00_data = {
81 .phy_addr = MV643XX_ETH_PHY_ADDR(0 /*8*/),
84 static struct mv643xx_eth_platform_data db78x00_ge01_data = {
85 .phy_addr = MV643XX_ETH_PHY_ADDR(1 /*9*/),
92 static struct mv_sata_platform_data db78x00_sata_data = {
100 static struct pca953x_platform_data rdstor_gpio_ext_pdata = {
108 static struct i2c_board_info __initdata rdstor_i2c_bus0[] = {
110 I2C_BOARD_INFO("pca9555", 0x27),
111 .platform_data = &rdstor_gpio_ext_pdata,
115 static struct i2c_board_info __initdata rdstor_i2c_bus1[] = {
117 I2C_BOARD_INFO("lm86", 0x4c)
119 I2C_BOARD_INFO("24aa00", 0x50)
121 I2C_BOARD_INFO("ds1338", 0x68)
129 static struct mtd_partition rdstor_nand_parts[] = {
131 .name = "nand-kernel",
134 // .mask_flags = MTD_WRITEABLE
137 .name = "nand-kernel-fallback",
138 .offset = MTDPART_OFS_APPEND,
140 // .mask_flags = MTD_WRITEABLE
143 .name = "nand-rootfs",
144 .offset = MTDPART_OFS_APPEND,
145 .size = MTDPART_SIZ_FULL,
146 // .mask_flags = MTD_WRITEABLE
150 static struct resource mv78xx0_nand_resource = {
151 .flags = IORESOURCE_MEM,
152 .start = MV78XX0_NAND_MEM_PHYS_BASE,
153 .end = MV78XX0_NAND_MEM_PHYS_BASE +
154 MV78XX0_NAND_MEM_SIZE - 1,
157 static struct orion_nand_data mv78xx0_nand_data = {
163 static struct platform_device mv78xx0_nand_flash = {
164 .name = "orion_nand",
167 .platform_data = &mv78xx0_nand_data,
169 .resource = &mv78xx0_nand_resource,
174 static int rdstor_nand_dev_ready(struct mtd_info *mtd)
176 return gpio_get_value(16);
179 void __init mv78xx0_nand_init_rb(struct mtd_partition *parts, int nr_parts)
181 mv78xx0_nand_data.parts = parts;
182 mv78xx0_nand_data.nr_parts = nr_parts;
183 mv78xx0_nand_data.dev_ready = rdstor_nand_dev_ready;
185 platform_device_register(&mv78xx0_nand_flash);
189 void __init mv78xx0_nand_init(struct mtd_partition *parts, int nr_parts,
192 mv78xx0_nand_data.parts = parts;
193 mv78xx0_nand_data.nr_parts = nr_parts;
194 mv78xx0_nand_data.chip_delay = chip_delay;
196 platform_device_register(&mv78xx0_nand_flash);
202 static struct resource rdstor_mtd_resource = {
204 .start = MV78XX0_BOOTCS_MEM_PHY_BASE /*0xfc000000*/,
205 .end = MV78XX0_BOOTCS_MEM_PHY_BASE + MV78XX0_BOOTCS_MEM_SIZE /*0xfc000000 + SZ_64M*/ - 1,
206 .flags = IORESOURCE_MEM,
209 static struct mtd_partition rdstor_nor_parts[] = {
214 //.mask_flags = MTD_WRITEABLE
217 .name = "nor-uboot-env",
218 .offset = MTDPART_OFS_APPEND,
220 // .mask_flags = MTD_WRITEABLE
224 .offset = MTDPART_OFS_APPEND,
225 .size = MTDPART_SIZ_FULL,
226 .mask_flags = MTD_WRITEABLE
230 static struct physmap_flash_data rdstor_flash_data[] = {
233 .parts = rdstor_nor_parts,
238 static struct platform_device rdstor_mtd_device = {
239 .name = "physmap-flash",
242 .platform_data = &rdstor_flash_data,
244 .resource = &rdstor_mtd_resource,
249 static struct mtd_partition rdstor_dataflash_partitions[] = {
253 .size = MTDPART_SIZ_FULL,
254 // .mask_flags = MTD_WRITEABLE
258 static struct flash_platform_data rdstor_spi_slave_data = {
260 .nr_parts = ARRAY_SIZE(rdstor_dataflash_partitions),
261 .parts = rdstor_dataflash_partitions,
264 static struct spi_board_info rdstor_spi_devices[] = {
265 { /* DataFlash card */
266 .modalias = "m25p64",
269 .max_speed_hz = 20000000,
271 .platform_data = &rdstor_spi_slave_data,
275 static void __init db78x00_init(void)
278 * Basic MV78xx0 setup. Needs to be called early.
283 mv78xx0_mpp_conf(rdstor_mpp_config);
286 * Partition on-chip peripherals between the two CPU cores.
287 * On the RDstor we also have the single core option so for now
288 * all peripherals are assigned to core #0.
290 if (mv78xx0_core_index() == 0) {
291 mv78xx0_uart0_init();
292 mv78xx0_uart1_init();
293 mv78xx0_uart2_init();
294 //mv78xx0_uart3_init();
298 mv78xx0_ge00_init(&db78x00_ge00_data);
299 mv78xx0_ge01_init(&db78x00_ge01_data);
301 mv78xx0_sata_init(&db78x00_sata_data);
303 /*mv78xx0_ehci0_init();*/ /* somewhere? */
304 mv78xx0_ehci1_init(); /* ext USB */
305 /* USB2 is device mode */
307 i2c_register_board_info(0, ARRAY_AND_SIZE(rdstor_i2c_bus0));
308 i2c_register_board_info(1, ARRAY_AND_SIZE(rdstor_i2c_bus1));
311 platform_device_register(&rdstor_mtd_device);
315 printk(KERN_ERR "NAND read params: 0x%08x\n", readl(MV78XX0_REGS_VIRT_BASE | 0x10418));
316 printk(KERN_ERR "NAND write params: 0x%08x\n", readl(MV78XX0_REGS_VIRT_BASE | 0x1041C));
317 printk(KERN_ERR "NAND control: 0x%08x\n", readl(MV78XX0_REGS_VIRT_BASE | 0x10470));
320 if (gpio_request(16, "NAND READY") != 0 ||
321 gpio_direction_input(16) != 0) {
322 printk(KERN_ERR "nand_init: failed to request GPIO16 for NAND_READY, falling back to udelay\n");
323 mv78xx0_nand_init(ARRAY_AND_SIZE(rdstor_nand_parts), 30);
325 mv78xx0_nand_init_rb(ARRAY_AND_SIZE(rdstor_nand_parts));
327 spi_register_board_info(rdstor_spi_devices, ARRAY_SIZE(rdstor_spi_devices));
330 mv78xx0_crypto_init();
339 static int __init db78x00_pci_init(void)
341 if (1 /*machine_is_db78x00_bp()*/ /*machine_is_rdstor()*/) {
343 * Assign the x16 PCIe slot on the board to CPU core
344 * #0, and let CPU core #1 have the four x1 slots.
346 if (mv78xx0_core_index() == 0) {
347 printk(KERN_ERR "pcie_init core#0\n");
348 mv78xx0_pcie_init(1, 1);
350 mv78xx0_pcie_init(1, 0);
351 printk(KERN_ERR "pcie_init other core\n");
354 printk(KERN_ERR "pcie_init machine mismatch\n");
358 subsys_initcall(db78x00_pci_init);
360 MACHINE_START(RDSTOR, "BDT RDStor, with CSB1725 module")
361 /* Maintainer: Nils Faerber <nils.faerber@kernelconcepts.de> */
362 .boot_params = 0x00000100,
363 .init_machine = db78x00_init,
364 .map_io = mv78xx0_map_io,
365 .init_irq = mv78xx0_init_irq,
366 .timer = &mv78xx0_timer,