2 * arch/arm/mach-mv78xx0/db78x00-bp-setup.c
4 * Marvell DB-78x00-BP Development Board Setup
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/platform_device.h>
14 #include <linux/ata_platform.h>
15 #include <linux/mv643xx_eth.h>
16 #include <linux/ethtool.h>
17 #include <linux/spi/spi.h>
18 #include <linux/spi/flash.h>
19 #include <linux/i2c.h>
20 #include <linux/i2c/pca953x.h>
21 #include <linux/mtd/nand.h>
22 #include <linux/mtd/physmap.h>
23 #include <linux/mtd/partitions.h>
24 #include <linux/gpio.h>
26 #include <linux/irq.h>
27 #include <mach/mv78xx0.h>
28 #include <asm/mach-types.h>
29 #include <asm/mach/arch.h>
30 #include <plat/orion_nand.h>
35 static unsigned int rdstor_mpp_config[] __initdata = {
40 MPP12_GPIO, /* parallel LCD */
41 MPP13_GPIO, /* parallel LCD */
42 MPP14_GPIO, /* parallel LCD */
43 MPP15_GPIO, /* parallel LCD */
44 MPP16_UNUSED, /* GPIO16 - n.a. */
45 MPP17_UNUSED, /* GPIO17 */
46 MPP18_GPIO, /* parallel LCD A0 */
47 MPP19_GPIO, /* parallel LCD R/W */
48 MPP20_GPIO, /* parallel LCD LCD_EN */
49 MPP21_GPIO, /* parallel LCD CSn */
50 MPP22_GPIO, /* GPIO22 WAKE0 PCI Express 0 Wake Input (on pin MPP22) */
51 MPP23_GPIO, /* GPIO23 WAKE0 PCI Express 0 Wake Input (on pin MPP23) */
54 MPP26_GPIO, /* LCD module RESETn */
55 MPP27_GPIO, /* LCD module switch */
56 MPP28_GPIO, /* parallel LCD */
57 MPP29_GPIO, /* parallel LCD */
58 MPP30_GPIO, /* parallel LCD */
59 MPP31_GPIO, /* parallel LCD */
60 MPP32_GPIO, /* GPIO0 I2C0_INT I2C IRQ */
61 MPP33_GPIO, /* GPIO1 T_CRIT LM86 thermal IRQ */
62 MPP34_GPIO, /* GPIO2 MII_INT PHY Interrupt for off module MII Bus */
63 MPP35_GPIO, /* GPIO3 PHY_INT 88E1121R Dual PHY Interrupt */
64 MPP36_GPIO, /* PS1 PF input, GPIO4 INTA MXM Interrupt A */
65 MPP37_GPIO, /* PWR SWITCH CSB, GPIO5 INTB MXM Interrupt B */
66 MPP38_GPIO, /* GPIO6 INTC MXM Interrupt C */
67 MPP39_GPIO, /* GPIO7 INTD MXM Interrupt D */
68 MPP47_GPIO, /* GPIO16 N_RDY NAND ready/busy */
78 static struct mv643xx_eth_platform_data db78x00_ge00_data = {
79 .phy_addr = MV643XX_ETH_PHY_ADDR(0 /*8*/),
82 static struct mv643xx_eth_platform_data db78x00_ge01_data = {
83 .phy_addr = MV643XX_ETH_PHY_ADDR(1 /*9*/),
90 static struct mv_sata_platform_data db78x00_sata_data = {
98 static struct pca953x_platform_data rdstor_gpio_ext_pdata = {
106 static struct i2c_board_info __initdata rdstor_i2c_bus0[] = {
108 I2C_BOARD_INFO("pca9555", 0x27),
109 .platform_data = &rdstor_gpio_ext_pdata,
113 static struct i2c_board_info __initdata rdstor_i2c_bus1[] = {
115 I2C_BOARD_INFO("lm86", 0x4c)
117 I2C_BOARD_INFO("24aa00", 0x50)
119 I2C_BOARD_INFO("ds1338", 0x68)
127 static struct mtd_partition rdstor_nand_parts[] = {
129 .name = "nand-kernel",
132 // .mask_flags = MTD_WRITEABLE
135 .name = "nand-kernel-fallback",
136 .offset = MTDPART_OFS_APPEND,
138 // .mask_flags = MTD_WRITEABLE
141 .name = "nand-rootfs",
142 .offset = MTDPART_OFS_APPEND,
143 .size = MTDPART_SIZ_FULL,
144 // .mask_flags = MTD_WRITEABLE
148 static struct resource mv78xx0_nand_resource = {
149 .flags = IORESOURCE_MEM,
150 .start = MV78XX0_NAND_MEM_PHYS_BASE,
151 .end = MV78XX0_NAND_MEM_PHYS_BASE +
152 MV78XX0_NAND_MEM_SIZE - 1,
155 static struct orion_nand_data mv78xx0_nand_data = {
161 static struct platform_device mv78xx0_nand_flash = {
162 .name = "orion_nand",
165 .platform_data = &mv78xx0_nand_data,
167 .resource = &mv78xx0_nand_resource,
172 static int rdstor_nand_dev_ready(struct mtd_info *mtd)
174 return gpio_get_value(16);
177 void __init mv78xx0_nand_init_rb(struct mtd_partition *parts, int nr_parts)
179 mv78xx0_nand_data.parts = parts;
180 mv78xx0_nand_data.nr_parts = nr_parts;
181 mv78xx0_nand_data.dev_ready = rdstor_nand_dev_ready;
183 platform_device_register(&mv78xx0_nand_flash);
187 void __init mv78xx0_nand_init(struct mtd_partition *parts, int nr_parts,
190 mv78xx0_nand_data.parts = parts;
191 mv78xx0_nand_data.nr_parts = nr_parts;
192 mv78xx0_nand_data.chip_delay = chip_delay;
194 platform_device_register(&mv78xx0_nand_flash);
200 static struct resource rdstor_mtd_resource = {
202 .start = MV78XX0_BOOTCS_MEM_PHY_BASE /*0xfc000000*/,
203 .end = MV78XX0_BOOTCS_MEM_PHY_BASE + MV78XX0_BOOTCS_MEM_SIZE /*0xfc000000 + SZ_64M*/ - 1,
204 .flags = IORESOURCE_MEM,
207 static struct mtd_partition rdstor_nor_parts[] = {
212 //.mask_flags = MTD_WRITEABLE
215 .name = "nor-uboot-env",
216 .offset = MTDPART_OFS_APPEND,
218 // .mask_flags = MTD_WRITEABLE
222 .offset = MTDPART_OFS_APPEND,
223 .size = MTDPART_SIZ_FULL,
224 .mask_flags = MTD_WRITEABLE
228 static struct physmap_flash_data rdstor_flash_data[] = {
231 .parts = rdstor_nor_parts,
236 static struct platform_device rdstor_mtd_device = {
237 .name = "physmap-flash",
240 .platform_data = &rdstor_flash_data,
242 .resource = &rdstor_mtd_resource,
247 static struct mtd_partition rdstor_dataflash_partitions[] = {
251 .size = MTDPART_SIZ_FULL,
252 // .mask_flags = MTD_WRITEABLE
256 static struct flash_platform_data rdstor_spi_slave_data = {
258 .nr_parts = ARRAY_SIZE(rdstor_dataflash_partitions),
259 .parts = rdstor_dataflash_partitions,
262 static struct spi_board_info rdstor_spi_devices[] = {
263 { /* DataFlash card */
264 .modalias = "m25p64",
267 .max_speed_hz = 20000000,
269 .platform_data = &rdstor_spi_slave_data,
273 static void __init db78x00_init(void)
276 * Basic MV78xx0 setup. Needs to be called early.
281 mv78xx0_mpp_conf(rdstor_mpp_config);
284 * Partition on-chip peripherals between the two CPU cores.
285 * On the RDstor we also have the single core option so for now
286 * all peripherals are assigned to core #0.
288 if (mv78xx0_core_index() == 0) {
289 mv78xx0_uart0_init();
290 mv78xx0_uart1_init();
291 mv78xx0_uart2_init();
292 //mv78xx0_uart3_init();
296 mv78xx0_ge00_init(&db78x00_ge00_data);
297 mv78xx0_ge01_init(&db78x00_ge01_data);
299 mv78xx0_sata_init(&db78x00_sata_data);
301 /*mv78xx0_ehci0_init();*/ /* somewhere? */
302 mv78xx0_ehci1_init(); /* ext USB */
303 /* USB2 is device mode */
305 i2c_register_board_info(0, ARRAY_AND_SIZE(rdstor_i2c_bus0));
306 i2c_register_board_info(1, ARRAY_AND_SIZE(rdstor_i2c_bus1));
309 platform_device_register(&rdstor_mtd_device);
313 printk(KERN_ERR "NAND read params: 0x%08x\n", readl(MV78XX0_REGS_VIRT_BASE | 0x10418));
314 printk(KERN_ERR "NAND write params: 0x%08x\n", readl(MV78XX0_REGS_VIRT_BASE | 0x1041C));
315 printk(KERN_ERR "NAND control: 0x%08x\n", readl(MV78XX0_REGS_VIRT_BASE | 0x10470));
317 writel(0xfff40 /*0x07d940*/, MV78XX0_REGS_VIRT_BASE | 0x10470);
318 printk(KERN_ERR "NAND control: 0x%08x\n", readl(MV78XX0_REGS_VIRT_BASE | 0x10470));
320 if (/*1 ||*/ gpio_request(16, "NAND READY") != 0 ||
321 gpio_direction_input(16) != 0) {
322 printk(KERN_ERR "nand_init: failed to request GPIO16 for NAND_READY, falling back to udelay\n");
323 mv78xx0_nand_init(ARRAY_AND_SIZE(rdstor_nand_parts), 30);
325 mv78xx0_nand_init_rb(ARRAY_AND_SIZE(rdstor_nand_parts));
327 spi_register_board_info(rdstor_spi_devices, ARRAY_SIZE(rdstor_spi_devices));
330 mv78xx0_crypto_init();
339 static int __init db78x00_pci_init(void)
341 if (1 /*machine_is_db78x00_bp()*/ /*machine_is_rdstor()*/) {
343 * Assign the x16 PCIe slot on the board to CPU core
344 * #0, and let CPU core #1 have the four x1 slots.
346 if (mv78xx0_core_index() == 0) {
347 printk(KERN_ERR "pcie_init core#0\n");
348 mv78xx0_pcie_init(1, 1);
350 mv78xx0_pcie_init(1, 0);
351 printk(KERN_ERR "pcie_init other core\n");
354 printk(KERN_ERR "pcie_init machine mismatch\n");
358 subsys_initcall(db78x00_pci_init);
360 MACHINE_START(DB78X00_BP /*RDSTOR*/, "BDT RDStor, with CSB1725 module")
361 /* Maintainer: Nils Faerber <nils.faerber@kernelconcepts.de> */
362 .phys_io = MV78XX0_REGS_PHYS_BASE,
363 .io_pg_offst = ((MV78XX0_REGS_VIRT_BASE) >> 18) & 0xfffc,
364 .boot_params = 0x00000100,
365 .init_machine = db78x00_init,
366 .map_io = mv78xx0_map_io,
367 .init_irq = mv78xx0_init_irq,
368 .timer = &mv78xx0_timer,