2 * Copyright (C) 2014-2015 Stefan Roese <sr@denx.de>
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/pl310.h>
11 #include <asm/arch/cpu.h>
12 #include <asm/arch/soc.h>
14 #define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3))
15 #define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3))
17 static struct mbus_win windows[] = {
18 /* PCIE MEM address space */
19 { DEFADR_PCI_MEM, 256 << 20, CPU_TARGET_PCIE13, CPU_ATTR_PCIE_MEM },
21 /* PCIE IO address space */
22 { DEFADR_PCI_IO, 64 << 10, CPU_TARGET_PCIE13, CPU_ATTR_PCIE_IO },
25 { DEFADR_SPIF, 8 << 20, CPU_TARGET_DEVICEBUS_BOOTROM_SPI,
29 { DEFADR_BOOTROM, 8 << 20, CPU_TARGET_DEVICEBUS_BOOTROM_SPI,
33 void reset_cpu(unsigned long ignored)
35 struct mvebu_system_registers *reg =
36 (struct mvebu_system_registers *)MVEBU_SYSTEM_REG_BASE;
38 writel(readl(®->rstoutn_mask) | 1, ®->rstoutn_mask);
39 writel(readl(®->sys_soft_rst) | 1, ®->sys_soft_rst);
44 int mvebu_soc_family(void)
46 u16 devid = (readl(MVEBU_REG_PCIE_DEVID) >> 16) & 0xffff;
48 if (devid == SOC_MV78460_ID)
51 if (devid == SOC_88F6810_ID || devid == SOC_88F6820_ID ||
52 devid == SOC_88F6828_ID)
53 return MVEBU_SOC_A38X;
55 return MVEBU_SOC_UNKNOWN;
58 #if defined(CONFIG_DISPLAY_CPUINFO)
59 int print_cpuinfo(void)
61 u16 devid = (readl(MVEBU_REG_PCIE_DEVID) >> 16) & 0xffff;
62 u8 revid = readl(MVEBU_REG_PCIE_REVID) & 0xff;
84 if (mvebu_soc_family() == MVEBU_SOC_AXP) {
93 printf("?? (%x)\n", revid);
98 if (mvebu_soc_family() == MVEBU_SOC_A38X) {
100 case MV_88F68XX_Z1_ID:
103 case MV_88F68XX_A0_ID:
107 printf("?? (%x)\n", revid);
114 #endif /* CONFIG_DISPLAY_CPUINFO */
117 * This function initialize Controller DRAM Fastpath windows.
118 * It takes the CS size information from the 0x1500 scratch registers
119 * and sets the correct windows sizes and base addresses accordingly.
121 * These values are set in the scratch registers by the Marvell
122 * DDR3 training code, which is executed by the BootROM before the
123 * main payload (U-Boot) is executed. This training code is currently
124 * only available in the Marvell U-Boot version. It needs to be
125 * ported to mainline U-Boot SPL at some point.
127 static void update_sdram_window_sizes(void)
133 for (i = 0; i < SDRAM_MAX_CS; i++) {
134 size = readl((MVEBU_SDRAM_SCRATCH + (i * 8))) & SDRAM_ADDR_MASK;
136 size |= ~(SDRAM_ADDR_MASK);
138 /* Set Base Address */
139 temp = (base & 0xFF000000ll) | ((base >> 32) & 0xF);
140 writel(temp, MVEBU_SDRAM_BASE + DDR_BASE_CS_OFF(i));
143 * Check if out of max window size and resize
146 temp = (readl(MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i)) &
147 ~(SDRAM_ADDR_MASK)) | 1;
148 temp |= (size & SDRAM_ADDR_MASK);
149 writel(temp, MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i));
151 base += ((u64)size + 1);
154 * Disable window if not used, otherwise this
155 * leads to overlapping enabled windows with
156 * pretty strange results
158 clrbits_le32(MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i), 1);
163 #ifdef CONFIG_ARCH_CPU_INIT
164 int arch_cpu_init(void)
166 /* Linux expects the internal registers to be at 0xf1000000 */
167 writel(SOC_REGS_PHY_BASE, INTREG_BASE_ADDR_REG);
170 * We need to call mvebu_mbus_probe() before calling
171 * update_sdram_window_sizes() as it disables all previously
172 * configured mbus windows and then configures them as
173 * required for U-Boot. Calling update_sdram_window_sizes()
174 * without this configuration will not work, as the internal
175 * registers can't be accessed reliably because of potenial
177 * After updating the SDRAM access windows we need to call
178 * mvebu_mbus_probe() again, as this now correctly configures
179 * the SDRAM areas that are later used by the MVEBU drivers
184 * First disable all windows
186 mvebu_mbus_probe(NULL, 0);
188 if (mvebu_soc_family() == MVEBU_SOC_AXP) {
190 * Now the SDRAM access windows can be reconfigured using
191 * the information in the SDRAM scratch pad registers
193 update_sdram_window_sizes();
197 * Finally the mbus windows can be configured with the
198 * updated SDRAM sizes
200 mvebu_mbus_probe(windows, ARRAY_SIZE(windows));
204 #endif /* CONFIG_ARCH_CPU_INIT */
207 * SOC specific misc init
209 #if defined(CONFIG_ARCH_MISC_INIT)
210 int arch_misc_init(void)
212 /* Nothing yet, perhaps we need something here later */
215 #endif /* CONFIG_ARCH_MISC_INIT */
218 int cpu_eth_init(bd_t *bis)
220 u32 enet_base[] = { MVEBU_EGIGA0_BASE, MVEBU_EGIGA1_BASE,
221 MVEBU_EGIGA2_BASE, MVEBU_EGIGA3_BASE };
222 u8 phy_addr[] = CONFIG_PHY_ADDR;
226 * Only Armada XP supports all 4 ethernet interfaces. A38x has
227 * slightly different base addresses for its 2-3 interfaces.
229 if (mvebu_soc_family() != MVEBU_SOC_AXP) {
230 enet_base[1] = MVEBU_EGIGA2_BASE;
231 enet_base[2] = MVEBU_EGIGA3_BASE;
234 for (i = 0; i < ARRAY_SIZE(phy_addr); i++)
235 mvneta_initialize(bis, enet_base[i], i, phy_addr[i]);
241 #ifndef CONFIG_SYS_DCACHE_OFF
242 void enable_caches(void)
244 struct pl310_regs *const pl310 =
245 (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
247 /* First disable L2 cache - may still be enable from BootROM */
248 if (mvebu_soc_family() == MVEBU_SOC_A38X)
249 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
251 /* Avoid problem with e.g. neta ethernet driver */
252 invalidate_dcache_all();
254 /* Enable D-cache. I-cache is already enabled in start.S */