2 * Copyright (C) 2014-2015 Stefan Roese <sr@denx.de>
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/pl310.h>
11 #include <asm/arch/cpu.h>
12 #include <asm/arch/soc.h>
15 #define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3))
16 #define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3))
18 static struct mbus_win windows[] = {
19 /* PCIE MEM address space */
20 { DEFADR_PCI_MEM, 256 << 20, CPU_TARGET_PCIE13, CPU_ATTR_PCIE_MEM },
22 /* PCIE IO address space */
23 { DEFADR_PCI_IO, 64 << 10, CPU_TARGET_PCIE13, CPU_ATTR_PCIE_IO },
26 { DEFADR_SPIF, 8 << 20, CPU_TARGET_DEVICEBUS_BOOTROM_SPI,
30 { DEFADR_BOOTROM, 8 << 20, CPU_TARGET_DEVICEBUS_BOOTROM_SPI,
34 void reset_cpu(unsigned long ignored)
36 struct mvebu_system_registers *reg =
37 (struct mvebu_system_registers *)MVEBU_SYSTEM_REG_BASE;
39 writel(readl(®->rstoutn_mask) | 1, ®->rstoutn_mask);
40 writel(readl(®->sys_soft_rst) | 1, ®->sys_soft_rst);
45 int mvebu_soc_family(void)
47 u16 devid = (readl(MVEBU_REG_PCIE_DEVID) >> 16) & 0xffff;
49 if (devid == SOC_MV78460_ID)
52 if (devid == SOC_88F6810_ID || devid == SOC_88F6820_ID ||
53 devid == SOC_88F6828_ID)
54 return MVEBU_SOC_A38X;
56 return MVEBU_SOC_UNKNOWN;
59 #if defined(CONFIG_DISPLAY_CPUINFO)
60 int print_cpuinfo(void)
62 u16 devid = (readl(MVEBU_REG_PCIE_DEVID) >> 16) & 0xffff;
63 u8 revid = readl(MVEBU_REG_PCIE_REVID) & 0xff;
85 if (mvebu_soc_family() == MVEBU_SOC_AXP) {
94 printf("?? (%x)\n", revid);
99 if (mvebu_soc_family() == MVEBU_SOC_A38X) {
101 case MV_88F68XX_Z1_ID:
104 case MV_88F68XX_A0_ID:
108 printf("?? (%x)\n", revid);
115 #endif /* CONFIG_DISPLAY_CPUINFO */
118 * This function initialize Controller DRAM Fastpath windows.
119 * It takes the CS size information from the 0x1500 scratch registers
120 * and sets the correct windows sizes and base addresses accordingly.
122 * These values are set in the scratch registers by the Marvell
123 * DDR3 training code, which is executed by the BootROM before the
124 * main payload (U-Boot) is executed. This training code is currently
125 * only available in the Marvell U-Boot version. It needs to be
126 * ported to mainline U-Boot SPL at some point.
128 static void update_sdram_window_sizes(void)
134 for (i = 0; i < SDRAM_MAX_CS; i++) {
135 size = readl((MVEBU_SDRAM_SCRATCH + (i * 8))) & SDRAM_ADDR_MASK;
137 size |= ~(SDRAM_ADDR_MASK);
139 /* Set Base Address */
140 temp = (base & 0xFF000000ll) | ((base >> 32) & 0xF);
141 writel(temp, MVEBU_SDRAM_BASE + DDR_BASE_CS_OFF(i));
144 * Check if out of max window size and resize
147 temp = (readl(MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i)) &
148 ~(SDRAM_ADDR_MASK)) | 1;
149 temp |= (size & SDRAM_ADDR_MASK);
150 writel(temp, MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i));
152 base += ((u64)size + 1);
155 * Disable window if not used, otherwise this
156 * leads to overlapping enabled windows with
157 * pretty strange results
159 clrbits_le32(MVEBU_SDRAM_BASE + DDR_SIZE_CS_OFF(i), 1);
164 #ifdef CONFIG_ARCH_CPU_INIT
165 static void set_cbar(u32 addr)
167 asm("mcr p15, 4, %0, c15, c0" : : "r" (addr));
171 int arch_cpu_init(void)
173 /* Linux expects the internal registers to be at 0xf1000000 */
174 writel(SOC_REGS_PHY_BASE, INTREG_BASE_ADDR_REG);
175 set_cbar(SOC_REGS_PHY_BASE + 0xC000);
178 * We need to call mvebu_mbus_probe() before calling
179 * update_sdram_window_sizes() as it disables all previously
180 * configured mbus windows and then configures them as
181 * required for U-Boot. Calling update_sdram_window_sizes()
182 * without this configuration will not work, as the internal
183 * registers can't be accessed reliably because of potenial
185 * After updating the SDRAM access windows we need to call
186 * mvebu_mbus_probe() again, as this now correctly configures
187 * the SDRAM areas that are later used by the MVEBU drivers
192 * First disable all windows
194 mvebu_mbus_probe(NULL, 0);
196 if (mvebu_soc_family() == MVEBU_SOC_AXP) {
198 * Now the SDRAM access windows can be reconfigured using
199 * the information in the SDRAM scratch pad registers
201 update_sdram_window_sizes();
205 * Finally the mbus windows can be configured with the
206 * updated SDRAM sizes
208 mvebu_mbus_probe(windows, ARRAY_SIZE(windows));
212 #endif /* CONFIG_ARCH_CPU_INIT */
215 * SOC specific misc init
217 #if defined(CONFIG_ARCH_MISC_INIT)
218 int arch_misc_init(void)
220 /* Nothing yet, perhaps we need something here later */
223 #endif /* CONFIG_ARCH_MISC_INIT */
226 int cpu_eth_init(bd_t *bis)
228 u32 enet_base[] = { MVEBU_EGIGA0_BASE, MVEBU_EGIGA1_BASE,
229 MVEBU_EGIGA2_BASE, MVEBU_EGIGA3_BASE };
230 u8 phy_addr[] = CONFIG_PHY_ADDR;
234 * Only Armada XP supports all 4 ethernet interfaces. A38x has
235 * slightly different base addresses for its 2-3 interfaces.
237 if (mvebu_soc_family() != MVEBU_SOC_AXP) {
238 enet_base[1] = MVEBU_EGIGA2_BASE;
239 enet_base[2] = MVEBU_EGIGA3_BASE;
242 for (i = 0; i < ARRAY_SIZE(phy_addr); i++)
243 mvneta_initialize(bis, enet_base[i], i, phy_addr[i]);
249 #ifdef CONFIG_MV_SDHCI
250 int board_mmc_init(bd_t *bis)
252 mv_sdh_init(MVEBU_SDIO_BASE, 0, 0,
253 SDHCI_QUIRK_32BIT_DMA_ADDR | SDHCI_QUIRK_WAIT_SEND_CMD);
259 #ifndef CONFIG_SYS_DCACHE_OFF
260 void enable_caches(void)
262 struct pl310_regs *const pl310 =
263 (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
265 /* First disable L2 cache - may still be enable from BootROM */
266 if (mvebu_soc_family() == MVEBU_SOC_A38X)
267 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
269 /* Avoid problem with e.g. neta ethernet driver */
270 invalidate_dcache_all();
272 /* Enable D-cache. I-cache is already enabled in start.S */