3 * Marvell Semiconductor <www.marvell.com>
4 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
6 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/system.h>
16 #define MVEBU_REG_PCIE_DEVID (MVEBU_REG_PCIE_BASE + 0x00)
17 #define MVEBU_REG_PCIE_REVID (MVEBU_REG_PCIE_BASE + 0x08)
32 CPU_TARGET_DRAM = 0x0,
33 CPU_TARGET_DEVICEBUS_BOOTROM_SPI = 0x1,
34 CPU_TARGET_ETH23 = 0x3,
35 CPU_TARGET_PCIE02 = 0x4,
36 CPU_TARGET_ETH01 = 0x7,
37 CPU_TARGET_PCIE13 = 0x8,
38 CPU_TARGET_SASRAM = 0x9,
39 CPU_TARGET_NAND = 0xd,
43 CPU_ATTR_SASRAM = 0x01,
44 CPU_ATTR_DRAM_CS0 = 0x0e,
45 CPU_ATTR_DRAM_CS1 = 0x0d,
46 CPU_ATTR_DRAM_CS2 = 0x0b,
47 CPU_ATTR_DRAM_CS3 = 0x07,
48 CPU_ATTR_NANDFLASH = 0x2f,
49 CPU_ATTR_SPIFLASH = 0x1e,
50 CPU_ATTR_SPI0_CS0 = 0x1e,
51 CPU_ATTR_SPI0_CS1 = 0x5e,
52 CPU_ATTR_SPI1_CS2 = 0x9a,
53 CPU_ATTR_BOOTROM = 0x1d,
54 CPU_ATTR_PCIE_IO = 0xe0,
55 CPU_ATTR_PCIE_MEM = 0xe8,
56 CPU_ATTR_DEV_CS0 = 0x3e,
57 CPU_ATTR_DEV_CS1 = 0x3d,
58 CPU_ATTR_DEV_CS2 = 0x3b,
59 CPU_ATTR_DEV_CS3 = 0x37,
69 * Default Device Address MAP BAR values
71 #define MBUS_PCI_MEM_BASE 0xE8000000
72 #define MBUS_PCI_MEM_SIZE (128 << 20)
73 #define MBUS_PCI_IO_BASE 0xF1100000
74 #define MBUS_PCI_IO_SIZE (64 << 10)
75 #define MBUS_SPI_BASE 0xF4000000
76 #define MBUS_SPI_SIZE (8 << 20)
77 #define MBUS_BOOTROM_BASE 0xF8000000
78 #define MBUS_BOOTROM_SIZE (8 << 20)
89 * Ref: Datasheet sec:A.28
91 struct mvebu_system_registers {
93 u32 rstoutn_mask; /* 0x60 */
94 u32 sys_soft_rst; /* 0x64 */
99 * Ref: Datasheet sec:A.19
101 struct kwgpio_registers {
112 struct sar_freq_modes {
114 u8 ffc; /* Fabric Frequency Configuration */
120 /* Needed for dynamic (board-specific) mbus configuration */
121 extern struct mvebu_mbus_state mbus_state;
126 unsigned int mvebu_sdram_bar(enum memory_bank bank);
127 unsigned int mvebu_sdram_bs(enum memory_bank bank);
128 void mvebu_sdram_size_adjust(enum memory_bank bank);
129 int mvebu_mbus_probe(struct mbus_win windows[], int count);
130 int mvebu_soc_family(void);
131 u32 mvebu_get_nand_clock(void);
133 void return_to_bootrom(void);
135 int mv_sdh_init(unsigned long regbase, u32 max_clk, u32 min_clk, u32 quirks);
137 void get_sar_freq(struct sar_freq_modes *sar_freq);
140 * Highspeed SERDES PHY config init, ported from bin_hdr
143 int serdes_phy_config(void);
146 * DDR3 init / training code ported from Marvell bin_hdr. Now
147 * available in mainline U-Boot in:
148 * drivers/ddr/marvell
152 struct mvebu_lcd_info {
156 int x_fp; /* frontporch */
158 int x_bp; /* backporch */
162 int mvebu_lcd_register_init(struct mvebu_lcd_info *lcd_info);
164 #endif /* __ASSEMBLY__ */
165 #endif /* _MVEBU_CPU_H */