2 * Address map functions for Marvell EBU SoCs (Kirkwood, Armada
3 * 370/XP, Dove, Orion5x and MV78xx0)
5 * Ported from the Barebox version to U-Boot by:
6 * Stefan Roese <sr@denx.de>
8 * The Barebox version is:
9 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
11 * based on mbus driver from Linux
12 * (C) Copyright 2008 Marvell Semiconductor
14 * SPDX-License-Identifier: GPL-2.0
16 * The Marvell EBU SoCs have a configurable physical address space:
17 * the physical address at which certain devices (PCIe, NOR, NAND,
18 * etc.) sit can be configured. The configuration takes place through
19 * two sets of registers:
21 * - One to configure the access of the CPU to the devices. Depending
22 * on the families, there are between 8 and 20 configurable windows,
23 * each can be use to create a physical memory window that maps to a
24 * specific device. Devices are identified by a tuple (target,
27 * - One to configure the access to the CPU to the SDRAM. There are
28 * either 2 (for Dove) or 4 (for other families) windows to map the
29 * SDRAM into the physical address space.
33 * - Reads out the SDRAM address decoding windows at initialization
34 * time, and fills the mbus_dram_info structure with these
35 * informations. The exported function mv_mbus_dram_info() allow
36 * device drivers to get those informations related to the SDRAM
37 * address decoding windows. This is because devices also have their
38 * own windows (configured through registers that are part of each
39 * device register space), and therefore the drivers for Marvell
40 * devices have to configure those device -> SDRAM windows to ensure
41 * that DMA works properly.
43 * - Provides an API for platform code or device drivers to
44 * dynamically add or remove address decoding windows for the CPU ->
45 * device accesses. This API is mvebu_mbus_add_window_by_id(),
46 * mvebu_mbus_add_window_remap_by_id() and
47 * mvebu_mbus_del_window().
51 #include <asm/errno.h>
53 #include <asm/arch/cpu.h>
54 #include <asm/arch/soc.h>
55 #include <linux/compat.h>
56 #include <linux/mbus.h>
58 #define BIT(nr) (1UL << (nr))
60 /* DDR target is the same on all platforms */
63 /* CPU Address Decode Windows registers */
64 #define WIN_CTRL_OFF 0x0000
65 #define WIN_CTRL_ENABLE BIT(0)
66 #define WIN_CTRL_TGT_MASK 0xf0
67 #define WIN_CTRL_TGT_SHIFT 4
68 #define WIN_CTRL_ATTR_MASK 0xff00
69 #define WIN_CTRL_ATTR_SHIFT 8
70 #define WIN_CTRL_SIZE_MASK 0xffff0000
71 #define WIN_CTRL_SIZE_SHIFT 16
72 #define WIN_BASE_OFF 0x0004
73 #define WIN_BASE_LOW 0xffff0000
74 #define WIN_BASE_HIGH 0xf
75 #define WIN_REMAP_LO_OFF 0x0008
76 #define WIN_REMAP_LOW 0xffff0000
77 #define WIN_REMAP_HI_OFF 0x000c
79 #define ATTR_HW_COHERENCY (0x1 << 4)
81 #define DDR_BASE_CS_OFF(n) (0x0000 + ((n) << 3))
82 #define DDR_BASE_CS_HIGH_MASK 0xf
83 #define DDR_BASE_CS_LOW_MASK 0xff000000
84 #define DDR_SIZE_CS_OFF(n) (0x0004 + ((n) << 3))
85 #define DDR_SIZE_ENABLED BIT(0)
86 #define DDR_SIZE_CS_MASK 0x1c
87 #define DDR_SIZE_CS_SHIFT 2
88 #define DDR_SIZE_MASK 0xff000000
90 #define DOVE_DDR_BASE_CS_OFF(n) ((n) << 4)
92 struct mvebu_mbus_state;
94 struct mvebu_mbus_soc_data {
95 unsigned int num_wins;
96 unsigned int num_remappable_wins;
97 unsigned int (*win_cfg_offset)(const int win);
98 void (*setup_cpu_target)(struct mvebu_mbus_state *s);
101 struct mvebu_mbus_state mbus_state
102 __attribute__ ((section(".data")));
103 static struct mbus_dram_target_info mbus_dram_info
104 __attribute__ ((section(".data")));
107 * Functions to manipulate the address decoding windows
110 static void mvebu_mbus_read_window(struct mvebu_mbus_state *mbus,
111 int win, int *enabled, u64 *base,
112 u32 *size, u8 *target, u8 *attr,
115 void __iomem *addr = mbus->mbuswins_base +
116 mbus->soc->win_cfg_offset(win);
117 u32 basereg = readl(addr + WIN_BASE_OFF);
118 u32 ctrlreg = readl(addr + WIN_CTRL_OFF);
120 if (!(ctrlreg & WIN_CTRL_ENABLE)) {
126 *base = ((u64)basereg & WIN_BASE_HIGH) << 32;
127 *base |= (basereg & WIN_BASE_LOW);
128 *size = (ctrlreg | ~WIN_CTRL_SIZE_MASK) + 1;
131 *target = (ctrlreg & WIN_CTRL_TGT_MASK) >> WIN_CTRL_TGT_SHIFT;
134 *attr = (ctrlreg & WIN_CTRL_ATTR_MASK) >> WIN_CTRL_ATTR_SHIFT;
137 if (win < mbus->soc->num_remappable_wins) {
138 u32 remap_low = readl(addr + WIN_REMAP_LO_OFF);
139 u32 remap_hi = readl(addr + WIN_REMAP_HI_OFF);
140 *remap = ((u64)remap_hi << 32) | remap_low;
147 static void mvebu_mbus_disable_window(struct mvebu_mbus_state *mbus,
152 addr = mbus->mbuswins_base + mbus->soc->win_cfg_offset(win);
154 writel(0, addr + WIN_BASE_OFF);
155 writel(0, addr + WIN_CTRL_OFF);
156 if (win < mbus->soc->num_remappable_wins) {
157 writel(0, addr + WIN_REMAP_LO_OFF);
158 writel(0, addr + WIN_REMAP_HI_OFF);
162 /* Checks whether the given window number is available */
163 static int mvebu_mbus_window_is_free(struct mvebu_mbus_state *mbus,
166 void __iomem *addr = mbus->mbuswins_base +
167 mbus->soc->win_cfg_offset(win);
168 u32 ctrl = readl(addr + WIN_CTRL_OFF);
169 return !(ctrl & WIN_CTRL_ENABLE);
173 * Checks whether the given (base, base+size) area doesn't overlap an
176 static int mvebu_mbus_window_conflicts(struct mvebu_mbus_state *mbus,
177 phys_addr_t base, size_t size,
180 u64 end = (u64)base + size;
183 for (win = 0; win < mbus->soc->num_wins; win++) {
189 mvebu_mbus_read_window(mbus, win,
190 &enabled, &wbase, &wsize,
191 &wtarget, &wattr, NULL);
196 wend = wbase + wsize;
199 * Check if the current window overlaps with the
200 * proposed physical range
202 if ((u64)base < wend && end > wbase)
206 * Check if target/attribute conflicts
208 if (target == wtarget && attr == wattr)
215 static int mvebu_mbus_find_window(struct mvebu_mbus_state *mbus,
216 phys_addr_t base, size_t size)
220 for (win = 0; win < mbus->soc->num_wins; win++) {
225 mvebu_mbus_read_window(mbus, win,
226 &enabled, &wbase, &wsize,
232 if (base == wbase && size == wsize)
239 static int mvebu_mbus_setup_window(struct mvebu_mbus_state *mbus,
240 int win, phys_addr_t base, size_t size,
241 phys_addr_t remap, u8 target,
244 void __iomem *addr = mbus->mbuswins_base +
245 mbus->soc->win_cfg_offset(win);
246 u32 ctrl, remap_addr;
248 ctrl = ((size - 1) & WIN_CTRL_SIZE_MASK) |
249 (attr << WIN_CTRL_ATTR_SHIFT) |
250 (target << WIN_CTRL_TGT_SHIFT) |
253 writel(base & WIN_BASE_LOW, addr + WIN_BASE_OFF);
254 writel(ctrl, addr + WIN_CTRL_OFF);
255 if (win < mbus->soc->num_remappable_wins) {
256 if (remap == MVEBU_MBUS_NO_REMAP)
260 writel(remap_addr & WIN_REMAP_LOW, addr + WIN_REMAP_LO_OFF);
261 writel(0, addr + WIN_REMAP_HI_OFF);
267 static int mvebu_mbus_alloc_window(struct mvebu_mbus_state *mbus,
268 phys_addr_t base, size_t size,
269 phys_addr_t remap, u8 target,
274 if (remap == MVEBU_MBUS_NO_REMAP) {
275 for (win = mbus->soc->num_remappable_wins;
276 win < mbus->soc->num_wins; win++)
277 if (mvebu_mbus_window_is_free(mbus, win))
278 return mvebu_mbus_setup_window(mbus, win, base,
284 for (win = 0; win < mbus->soc->num_wins; win++)
285 if (mvebu_mbus_window_is_free(mbus, win))
286 return mvebu_mbus_setup_window(mbus, win, base, size,
287 remap, target, attr);
293 * SoC-specific functions and definitions
296 static unsigned int armada_370_xp_mbus_win_offset(int win)
298 /* The register layout is a bit annoying and the below code
299 * tries to cope with it.
300 * - At offset 0x0, there are the registers for the first 8
301 * windows, with 4 registers of 32 bits per window (ctrl,
302 * base, remap low, remap high)
303 * - Then at offset 0x80, there is a hole of 0x10 bytes for
304 * the internal registers base address and internal units
305 * sync barrier register.
306 * - Then at offset 0x90, there the registers for 12
307 * windows, with only 2 registers of 32 bits per window
313 return 0x90 + ((win - 8) << 3);
316 static unsigned int orion5x_mbus_win_offset(int win)
321 static void mvebu_mbus_default_setup_cpu_target(struct mvebu_mbus_state *mbus)
326 mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
328 for (i = 0, cs = 0; i < 4; i++) {
329 u32 base = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i));
330 u32 size = readl(mbus->sdramwins_base + DDR_SIZE_CS_OFF(i));
333 * We only take care of entries for which the chip
334 * select is enabled, and that don't have high base
335 * address bits set (devices can only access the first
336 * 32 bits of the memory).
338 if ((size & DDR_SIZE_ENABLED) &&
339 !(base & DDR_BASE_CS_HIGH_MASK)) {
340 struct mbus_dram_window *w;
342 w = &mbus_dram_info.cs[cs++];
344 w->mbus_attr = 0xf & ~(1 << i);
345 w->base = base & DDR_BASE_CS_LOW_MASK;
346 w->size = (size | ~DDR_SIZE_MASK) + 1;
349 mbus_dram_info.num_cs = cs;
352 static const struct mvebu_mbus_soc_data
353 armada_370_xp_mbus_data __maybe_unused = {
355 .num_remappable_wins = 8,
356 .win_cfg_offset = armada_370_xp_mbus_win_offset,
357 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
360 static const struct mvebu_mbus_soc_data
361 kirkwood_mbus_data __maybe_unused = {
363 .num_remappable_wins = 4,
364 .win_cfg_offset = orion5x_mbus_win_offset,
365 .setup_cpu_target = mvebu_mbus_default_setup_cpu_target,
369 * Public API of the driver
371 const struct mbus_dram_target_info *mvebu_mbus_dram_info(void)
373 return &mbus_dram_info;
376 int mvebu_mbus_add_window_remap_by_id(unsigned int target,
377 unsigned int attribute,
378 phys_addr_t base, size_t size,
381 struct mvebu_mbus_state *s = &mbus_state;
383 if (!mvebu_mbus_window_conflicts(s, base, size, target, attribute)) {
384 printf("Cannot add window '%x:%x', conflicts with another window\n",
389 return mvebu_mbus_alloc_window(s, base, size, remap, target, attribute);
392 int mvebu_mbus_add_window_by_id(unsigned int target, unsigned int attribute,
393 phys_addr_t base, size_t size)
395 return mvebu_mbus_add_window_remap_by_id(target, attribute, base,
396 size, MVEBU_MBUS_NO_REMAP);
399 int mvebu_mbus_del_window(phys_addr_t base, size_t size)
403 win = mvebu_mbus_find_window(&mbus_state, base, size);
407 mvebu_mbus_disable_window(&mbus_state, win);
411 static void mvebu_mbus_get_lowest_base(struct mvebu_mbus_state *mbus,
417 for (win = 0; win < mbus->soc->num_wins; win++) {
423 mvebu_mbus_read_window(mbus, win,
424 &enabled, &wbase, &wsize,
425 &wtarget, &wattr, NULL);
435 static void mvebu_config_mbus_bridge(struct mvebu_mbus_state *mbus)
441 /* Set MBUS bridge base/ctrl */
442 mvebu_mbus_get_lowest_base(&mbus_state, &base);
444 size = 0xffffffff - base + 1;
445 if (!is_power_of_2(size)) {
446 /* Round up to next power of 2 */
447 size = 1 << (ffs(base) + 1);
448 base = 0xffffffff - size + 1;
451 /* Now write base and size */
452 writel(base, MBUS_BRIDGE_WIN_BASE_REG);
453 /* Align window size to 64KiB */
454 val = (size / (64 << 10)) - 1;
455 writel((val << 16) | 0x1, MBUS_BRIDGE_WIN_CTRL_REG);
458 int mbus_dt_setup_win(struct mvebu_mbus_state *mbus,
459 u32 base, u32 size, u8 target, u8 attr)
461 if (!mvebu_mbus_window_conflicts(mbus, base, size, target, attr)) {
462 printf("Cannot add window '%04x:%04x', conflicts with another window\n",
468 * In U-Boot we first try to add the mbus window to the remap windows.
469 * If this fails, lets try to add the windows to the non-remap windows.
471 if (mvebu_mbus_alloc_window(mbus, base, size, base, target, attr)) {
472 if (mvebu_mbus_alloc_window(mbus, base, size,
473 MVEBU_MBUS_NO_REMAP, target, attr))
478 * Re-configure the mbus bridge registers each time this function
479 * is called. Since it may get called from the board code in
480 * later boot stages as well.
482 mvebu_config_mbus_bridge(mbus);
487 int mvebu_mbus_probe(struct mbus_win windows[], int count)
493 #if defined(CONFIG_KIRKWOOD)
494 mbus_state.soc = &kirkwood_mbus_data;
496 #if defined(CONFIG_ARMADA_XP)
497 mbus_state.soc = &armada_370_xp_mbus_data;
500 mbus_state.mbuswins_base = (void __iomem *)MVEBU_CPU_WIN_BASE;
501 mbus_state.sdramwins_base = (void __iomem *)MVEBU_SDRAM_BASE;
503 for (win = 0; win < mbus_state.soc->num_wins; win++)
504 mvebu_mbus_disable_window(&mbus_state, win);
506 mbus_state.soc->setup_cpu_target(&mbus_state);
508 /* Setup statically declared windows in the DT */
509 for (i = 0; i < count; i++) {
513 target = windows[i].target;
514 attr = windows[i].attr;
515 base = windows[i].base;
516 size = windows[i].size;
517 ret = mbus_dt_setup_win(&mbus_state, base, size, target, attr);