2 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 #include <linux/delay.h>
20 #include <linux/types.h>
21 #include <linux/init.h>
22 #include <linux/clk.h>
23 #include <linux/irq.h>
24 #include <linux/gpio.h>
25 #include <linux/smsc911x.h>
26 #include <linux/platform_device.h>
27 #include <linux/mfd/mc13783.h>
28 #include <linux/spi/spi.h>
29 #include <linux/regulator/machine.h>
30 #include <linux/fsl_devices.h>
31 #include <linux/input/matrix_keypad.h>
33 #include <mach/hardware.h>
34 #include <asm/mach-types.h>
35 #include <asm/mach/arch.h>
36 #include <asm/mach/time.h>
37 #include <asm/memory.h>
38 #include <asm/mach/map.h>
39 #include <mach/common.h>
40 #include <mach/board-mx31_3ds.h>
41 #include <mach/imx-uart.h>
42 #include <mach/iomux-mx3.h>
43 #include <mach/mxc_nand.h>
50 * @brief This file contains the board-specific initialization routines.
55 static int mx31_3ds_pins[] = {
61 IOMUX_MODE(MX31_PIN_GPIO1_1, IOMUX_CONFIG_GPIO),
63 MX31_PIN_CSPI2_SCLK__SCLK,
64 MX31_PIN_CSPI2_MOSI__MOSI,
65 MX31_PIN_CSPI2_MISO__MISO,
66 MX31_PIN_CSPI2_SPI_RDY__SPI_RDY,
67 MX31_PIN_CSPI2_SS0__SS0,
68 MX31_PIN_CSPI2_SS2__SS2, /*CS for MC13783 */
70 IOMUX_MODE(MX31_PIN_GPIO1_3, IOMUX_CONFIG_GPIO),
72 IOMUX_MODE(MX31_PIN_USB_PWR, IOMUX_CONFIG_GPIO),
74 MX31_PIN_USBOTG_DATA0__USBOTG_DATA0,
75 MX31_PIN_USBOTG_DATA1__USBOTG_DATA1,
76 MX31_PIN_USBOTG_DATA2__USBOTG_DATA2,
77 MX31_PIN_USBOTG_DATA3__USBOTG_DATA3,
78 MX31_PIN_USBOTG_DATA4__USBOTG_DATA4,
79 MX31_PIN_USBOTG_DATA5__USBOTG_DATA5,
80 MX31_PIN_USBOTG_DATA6__USBOTG_DATA6,
81 MX31_PIN_USBOTG_DATA7__USBOTG_DATA7,
82 MX31_PIN_USBOTG_CLK__USBOTG_CLK,
83 MX31_PIN_USBOTG_DIR__USBOTG_DIR,
84 MX31_PIN_USBOTG_NXT__USBOTG_NXT,
85 MX31_PIN_USBOTG_STP__USBOTG_STP,
87 MX31_PIN_KEY_ROW0_KEY_ROW0,
88 MX31_PIN_KEY_ROW1_KEY_ROW1,
89 MX31_PIN_KEY_ROW2_KEY_ROW2,
90 MX31_PIN_KEY_COL0_KEY_COL0,
91 MX31_PIN_KEY_COL1_KEY_COL1,
92 MX31_PIN_KEY_COL2_KEY_COL2,
93 MX31_PIN_KEY_COL3_KEY_COL3,
100 static const uint32_t mx31_3ds_keymap[] = {
103 KEY(1, 0, KEY_RIGHT),
105 KEY(1, 2, KEY_ENTER),
112 static struct matrix_keymap_data mx31_3ds_keymap_data = {
113 .keymap = mx31_3ds_keymap,
114 .keymap_size = ARRAY_SIZE(mx31_3ds_keymap),
118 static struct regulator_init_data pwgtx_init = {
125 static struct mc13783_regulator_init_data mx31_3ds_regulators[] = {
127 .id = MC13783_REGU_PWGT1SPI, /* Power Gate for ARM core. */
128 .init_data = &pwgtx_init,
130 .id = MC13783_REGU_PWGT2SPI, /* Power Gate for L2 Cache. */
131 .init_data = &pwgtx_init,
136 static struct mc13783_platform_data mc13783_pdata __initdata = {
137 .regulators = mx31_3ds_regulators,
138 .num_regulators = ARRAY_SIZE(mx31_3ds_regulators),
139 .flags = MC13783_USE_REGULATOR,
143 static int spi1_internal_chipselect[] = {
148 static struct spi_imx_master spi1_pdata = {
149 .chipselect = spi1_internal_chipselect,
150 .num_chipselect = ARRAY_SIZE(spi1_internal_chipselect),
153 static struct spi_board_info mx31_3ds_spi_devs[] __initdata = {
155 .modalias = "mc13783",
156 .max_speed_hz = 1000000,
158 .chip_select = 1, /* SS2 */
159 .platform_data = &mc13783_pdata,
160 .irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
168 static struct mxc_nand_platform_data imx31_3ds_nand_flash_pdata = {
171 #ifdef MACH_MX31_3DS_MXC_NAND_USE_BBT
180 #define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
181 PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
183 #define USBOTG_RST_B IOMUX_TO_GPIO(MX31_PIN_USB_PWR)
185 static void mx31_3ds_usbotg_init(void)
187 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, USB_PAD_CFG);
188 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, USB_PAD_CFG);
189 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, USB_PAD_CFG);
190 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, USB_PAD_CFG);
191 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, USB_PAD_CFG);
192 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, USB_PAD_CFG);
193 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, USB_PAD_CFG);
194 mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, USB_PAD_CFG);
195 mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK, USB_PAD_CFG);
196 mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR, USB_PAD_CFG);
197 mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, USB_PAD_CFG);
198 mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, USB_PAD_CFG);
200 gpio_request(USBOTG_RST_B, "otgusb-reset");
201 gpio_direction_output(USBOTG_RST_B, 0);
203 gpio_set_value(USBOTG_RST_B, 1);
206 static struct fsl_usb2_platform_data usbotg_pdata = {
207 .operating_mode = FSL_USB2_DR_DEVICE,
208 .phy_mode = FSL_USB2_PHY_ULPI,
211 static struct imxuart_platform_data uart_pdata = {
212 .flags = IMXUART_HAVE_RTSCTS,
216 * Support for the SMSC9217 on the Debug board.
219 static struct smsc911x_platform_config smsc911x_config = {
220 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
221 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
222 .flags = SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY,
223 .phy_interface = PHY_INTERFACE_MODE_MII,
226 static struct resource smsc911x_resources[] = {
228 .start = LAN9217_BASE_ADDR,
229 .end = LAN9217_BASE_ADDR + 0xff,
230 .flags = IORESOURCE_MEM,
232 .start = EXPIO_INT_ENET,
233 .end = EXPIO_INT_ENET,
234 .flags = IORESOURCE_IRQ,
238 static struct platform_device smsc911x_device = {
241 .num_resources = ARRAY_SIZE(smsc911x_resources),
242 .resource = smsc911x_resources,
244 .platform_data = &smsc911x_config,
249 * Routines for the CPLD on the debug board. It contains a CPLD handling
250 * LEDs, switches, interrupts for Ethernet.
253 static void mx31_3ds_expio_irq_handler(uint32_t irq, struct irq_desc *desc)
259 imr_val = __raw_readw(CPLD_INT_MASK_REG);
260 int_valid = __raw_readw(CPLD_INT_STATUS_REG) & ~imr_val;
262 expio_irq = MXC_EXP_IO_BASE;
263 for (; int_valid != 0; int_valid >>= 1, expio_irq++) {
264 if ((int_valid & 1) == 0)
266 generic_handle_irq(expio_irq);
271 * Disable an expio pin's interrupt by setting the bit in the imr.
272 * @param irq an expio virtual irq number
274 static void expio_mask_irq(uint32_t irq)
277 uint32_t expio = MXC_IRQ_TO_EXPIO(irq);
279 /* mask the interrupt */
280 reg = __raw_readw(CPLD_INT_MASK_REG);
282 __raw_writew(reg, CPLD_INT_MASK_REG);
286 * Acknowledge an expanded io pin's interrupt by clearing the bit in the isr.
287 * @param irq an expanded io virtual irq number
289 static void expio_ack_irq(uint32_t irq)
291 uint32_t expio = MXC_IRQ_TO_EXPIO(irq);
293 /* clear the interrupt status */
294 __raw_writew(1 << expio, CPLD_INT_RESET_REG);
295 __raw_writew(0, CPLD_INT_RESET_REG);
296 /* mask the interrupt */
301 * Enable a expio pin's interrupt by clearing the bit in the imr.
302 * @param irq a expio virtual irq number
304 static void expio_unmask_irq(uint32_t irq)
307 uint32_t expio = MXC_IRQ_TO_EXPIO(irq);
309 /* unmask the interrupt */
310 reg = __raw_readw(CPLD_INT_MASK_REG);
311 reg &= ~(1 << expio);
312 __raw_writew(reg, CPLD_INT_MASK_REG);
315 static struct irq_chip expio_irq_chip = {
316 .ack = expio_ack_irq,
317 .mask = expio_mask_irq,
318 .unmask = expio_unmask_irq,
321 static int __init mx31_3ds_init_expio(void)
326 /* Check if there's a debug board connected */
327 if ((__raw_readw(CPLD_MAGIC_NUMBER1_REG) != 0xAAAA) ||
328 (__raw_readw(CPLD_MAGIC_NUMBER2_REG) != 0x5555) ||
329 (__raw_readw(CPLD_MAGIC_NUMBER3_REG) != 0xCAFE)) {
330 /* No Debug board found */
334 pr_info("i.MX31 3DS Debug board detected, rev = 0x%04X\n",
335 __raw_readw(CPLD_CODE_VER_REG));
338 * Configure INT line as GPIO input
340 ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1), "sms9217-irq");
342 pr_warning("could not get LAN irq gpio\n");
344 gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1));
346 /* Disable the interrupts and clear the status */
347 __raw_writew(0, CPLD_INT_MASK_REG);
348 __raw_writew(0xFFFF, CPLD_INT_RESET_REG);
349 __raw_writew(0, CPLD_INT_RESET_REG);
350 __raw_writew(0x1F, CPLD_INT_MASK_REG);
351 for (i = MXC_EXP_IO_BASE;
352 i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES);
354 set_irq_chip(i, &expio_irq_chip);
355 set_irq_handler(i, handle_level_irq);
356 set_irq_flags(i, IRQF_VALID);
358 set_irq_type(EXPIO_PARENT_INT, IRQ_TYPE_LEVEL_LOW);
359 set_irq_chained_handler(EXPIO_PARENT_INT, mx31_3ds_expio_irq_handler);
365 * This structure defines the MX31 memory map.
367 static struct map_desc mx31_3ds_io_desc[] __initdata = {
369 .virtual = MX31_CS5_BASE_ADDR_VIRT,
370 .pfn = __phys_to_pfn(MX31_CS5_BASE_ADDR),
371 .length = MX31_CS5_SIZE,
377 * Set up static virtual mappings.
379 static void __init mx31_3ds_map_io(void)
382 iotable_init(mx31_3ds_io_desc, ARRAY_SIZE(mx31_3ds_io_desc));
386 * Board specific initialization.
388 static void __init mxc_board_init(void)
390 mxc_iomux_setup_multiple_pins(mx31_3ds_pins, ARRAY_SIZE(mx31_3ds_pins),
393 mxc_register_device(&mxc_uart_device0, &uart_pdata);
394 mxc_register_device(&mxc_nand_device, &imx31_3ds_nand_flash_pdata);
396 mxc_register_device(&mxc_spi_device1, &spi1_pdata);
397 spi_register_board_info(mx31_3ds_spi_devs,
398 ARRAY_SIZE(mx31_3ds_spi_devs));
400 mxc_register_device(&imx_kpp_device, &mx31_3ds_keymap_data);
402 mx31_3ds_usbotg_init();
403 mxc_register_device(&mxc_otg_udc_device, &usbotg_pdata);
405 if (!mx31_3ds_init_expio())
406 platform_device_register(&smsc911x_device);
409 static void __init mx31_3ds_timer_init(void)
411 mx31_clocks_init(26000000);
414 static struct sys_timer mx31_3ds_timer = {
415 .init = mx31_3ds_timer_init,
419 * The following uses standard kernel macros defined in arch.h in order to
420 * initialize __mach_desc_MX31_3DS data structure.
422 MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)")
423 /* Maintainer: Freescale Semiconductor, Inc. */
424 .phys_io = MX31_AIPS1_BASE_ADDR,
425 .io_pg_offst = (MX31_AIPS1_BASE_ADDR_VIRT >> 18) & 0xfffc,
426 .boot_params = MX3x_PHYS_OFFSET + 0x100,
427 .map_io = mx31_3ds_map_io,
428 .init_irq = mx31_init_irq,
429 .init_machine = mxc_board_init,
430 .timer = &mx31_3ds_timer,