2 * Copyright (C) 2000 Deep Blue Solutions Ltd
3 * Copyright (C) 2002 Shane Nay (shane@minirl.com)
4 * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include <linux/types.h>
18 #include <linux/init.h>
19 #include <linux/clk.h>
20 #include <linux/serial_8250.h>
21 #include <linux/gpio.h>
22 #include <linux/i2c.h>
23 #include <linux/irq.h>
25 #include <asm/mach-types.h>
26 #include <asm/mach/arch.h>
27 #include <asm/mach/time.h>
28 #include <asm/memory.h>
29 #include <asm/mach/map.h>
30 #include <mach/common.h>
31 #include <mach/board-mx31ads.h>
32 #include <mach/iomux-mx3.h>
34 #ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
35 #include <linux/mfd/wm8350/audio.h>
36 #include <linux/mfd/wm8350/core.h>
37 #include <linux/mfd/wm8350/pmic.h>
40 #include "devices-imx31.h"
43 /* PBC Board interrupt status register */
44 #define PBC_INTSTATUS 0x000016
46 /* PBC Board interrupt current status register */
47 #define PBC_INTCURR_STATUS 0x000018
49 /* PBC Interrupt mask register set address */
50 #define PBC_INTMASK_SET 0x00001A
52 /* PBC Interrupt mask register clear address */
53 #define PBC_INTMASK_CLEAR 0x00001C
56 #define PBC_SC16C652_UARTA 0x010000
59 #define PBC_SC16C652_UARTB 0x010010
61 #define PBC_INTSTATUS_REG (PBC_INTSTATUS + PBC_BASE_ADDRESS)
62 #define PBC_INTMASK_SET_REG (PBC_INTMASK_SET + PBC_BASE_ADDRESS)
63 #define PBC_INTMASK_CLEAR_REG (PBC_INTMASK_CLEAR + PBC_BASE_ADDRESS)
64 #define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX31_PIN_GPIO1_4)
66 #define MXC_IRQ_TO_EXPIO(irq) ((irq) - MXC_EXP_IO_BASE)
68 #define EXPIO_INT_XUART_INTA (MXC_EXP_IO_BASE + 10)
69 #define EXPIO_INT_XUART_INTB (MXC_EXP_IO_BASE + 11)
71 #define MXC_MAX_EXP_IO_LINES 16
74 * The serial port definition structure.
76 static struct plat_serial8250_port serial_platform_data[] = {
78 .membase = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTA),
79 .mapbase = (unsigned long)(MX31_CS4_BASE_ADDR + PBC_SC16C652_UARTA),
80 .irq = EXPIO_INT_XUART_INTA,
84 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ,
86 .membase = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTB),
87 .mapbase = (unsigned long)(MX31_CS4_BASE_ADDR + PBC_SC16C652_UARTB),
88 .irq = EXPIO_INT_XUART_INTB,
92 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ,
97 static struct platform_device serial_device = {
101 .platform_data = serial_platform_data,
105 static int __init mxc_init_extuart(void)
107 return platform_device_register(&serial_device);
110 static const struct imxuart_platform_data uart_pdata __initconst = {
111 .flags = IMXUART_HAVE_RTSCTS,
114 static unsigned int uart_pins[] = {
121 static inline void mxc_init_imx_uart(void)
123 mxc_iomux_setup_multiple_pins(uart_pins, ARRAY_SIZE(uart_pins), "uart-0");
124 imx31_add_imx_uart0(&uart_pdata);
127 static void mx31ads_expio_irq_handler(u32 irq, struct irq_desc *desc)
133 imr_val = __raw_readw(PBC_INTMASK_SET_REG);
134 int_valid = __raw_readw(PBC_INTSTATUS_REG) & imr_val;
136 expio_irq = MXC_EXP_IO_BASE;
137 for (; int_valid != 0; int_valid >>= 1, expio_irq++) {
138 if ((int_valid & 1) == 0)
141 generic_handle_irq(expio_irq);
146 * Disable an expio pin's interrupt by setting the bit in the imr.
147 * @param d an expio virtual irq description
149 static void expio_mask_irq(struct irq_data *d)
151 u32 expio = MXC_IRQ_TO_EXPIO(d->irq);
152 /* mask the interrupt */
153 __raw_writew(1 << expio, PBC_INTMASK_CLEAR_REG);
154 __raw_readw(PBC_INTMASK_CLEAR_REG);
158 * Acknowledge an expanded io pin's interrupt by clearing the bit in the isr.
159 * @param d an expio virtual irq description
161 static void expio_ack_irq(struct irq_data *d)
163 u32 expio = MXC_IRQ_TO_EXPIO(d->irq);
164 /* clear the interrupt status */
165 __raw_writew(1 << expio, PBC_INTSTATUS_REG);
169 * Enable a expio pin's interrupt by clearing the bit in the imr.
170 * @param d an expio virtual irq description
172 static void expio_unmask_irq(struct irq_data *d)
174 u32 expio = MXC_IRQ_TO_EXPIO(d->irq);
175 /* unmask the interrupt */
176 __raw_writew(1 << expio, PBC_INTMASK_SET_REG);
179 static struct irq_chip expio_irq_chip = {
180 .name = "EXPIO(CPLD)",
181 .irq_ack = expio_ack_irq,
182 .irq_mask = expio_mask_irq,
183 .irq_unmask = expio_unmask_irq,
186 static void __init mx31ads_init_expio(void)
190 printk(KERN_INFO "MX31ADS EXPIO(CPLD) hardware\n");
193 * Configure INT line as GPIO input
195 mxc_iomux_alloc_pin(IOMUX_MODE(MX31_PIN_GPIO1_4, IOMUX_CONFIG_GPIO), "expio");
197 /* disable the interrupt and clear the status */
198 __raw_writew(0xFFFF, PBC_INTMASK_CLEAR_REG);
199 __raw_writew(0xFFFF, PBC_INTSTATUS_REG);
200 for (i = MXC_EXP_IO_BASE; i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES);
202 set_irq_chip(i, &expio_irq_chip);
203 set_irq_handler(i, handle_level_irq);
204 set_irq_flags(i, IRQF_VALID);
206 set_irq_type(EXPIO_PARENT_INT, IRQ_TYPE_LEVEL_HIGH);
207 set_irq_chained_handler(EXPIO_PARENT_INT, mx31ads_expio_irq_handler);
210 #ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
211 /* This section defines setup for the Wolfson Microelectronics
212 * 1133-EV1 PMU/audio board. When other PMU boards are supported the
213 * regulator definitions may be shared with them, but for now they can
214 * only be used with this board so would generate warnings about
215 * unused statics and some of the configuration is specific to this
220 static struct regulator_consumer_supply sw1a_consumers[] = {
226 static struct regulator_init_data sw1a_data = {
231 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
232 REGULATOR_CHANGE_MODE,
233 .valid_modes_mask = REGULATOR_MODE_NORMAL |
237 .mode = REGULATOR_MODE_NORMAL,
240 .initial_state = PM_SUSPEND_MEM,
244 .num_consumer_supplies = ARRAY_SIZE(sw1a_consumers),
245 .consumer_supplies = sw1a_consumers,
248 /* System IO - High */
249 static struct regulator_init_data viohi_data = {
256 .mode = REGULATOR_MODE_NORMAL,
259 .initial_state = PM_SUSPEND_MEM,
265 /* System IO - Low */
266 static struct regulator_init_data violo_data = {
273 .mode = REGULATOR_MODE_NORMAL,
276 .initial_state = PM_SUSPEND_MEM,
283 static struct regulator_init_data sw2a_data = {
288 .valid_modes_mask = REGULATOR_MODE_NORMAL,
291 .mode = REGULATOR_MODE_NORMAL,
295 .mode = REGULATOR_MODE_NORMAL,
300 .initial_state = PM_SUSPEND_MEM,
304 static struct regulator_init_data ldo1_data = {
306 .name = "VCAM/VMMC1/VMMC2",
309 .valid_modes_mask = REGULATOR_MODE_NORMAL,
310 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
315 static struct regulator_consumer_supply ldo2_consumers[] = {
316 { .supply = "AVDD", .dev_name = "1-001a" },
317 { .supply = "HPVDD", .dev_name = "1-001a" },
321 static struct regulator_init_data ldo2_data = {
323 .name = "VESIM/VSIM/AVDD",
326 .valid_modes_mask = REGULATOR_MODE_NORMAL,
327 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
330 .num_consumer_supplies = ARRAY_SIZE(ldo2_consumers),
331 .consumer_supplies = ldo2_consumers,
335 static struct regulator_init_data vdig_data = {
340 .valid_modes_mask = REGULATOR_MODE_NORMAL,
348 static struct regulator_init_data ldo4_data = {
350 .name = "VRF1/CVDD_2.775",
353 .valid_modes_mask = REGULATOR_MODE_NORMAL,
360 static struct wm8350_led_platform_data wm8350_led_data = {
361 .name = "wm8350:white",
362 .default_trigger = "heartbeat",
366 static struct wm8350_audio_platform_data imx32ads_wm8350_setup = {
367 .vmid_discharge_msecs = 1000,
369 .cap_discharge_msecs = 700,
370 .vmid_charge_msecs = 700,
371 .vmid_s_curve = WM8350_S_CURVE_SLOW,
372 .dis_out4 = WM8350_DISCHARGE_SLOW,
373 .dis_out3 = WM8350_DISCHARGE_SLOW,
374 .dis_out2 = WM8350_DISCHARGE_SLOW,
375 .dis_out1 = WM8350_DISCHARGE_SLOW,
376 .vroi_out4 = WM8350_TIE_OFF_500R,
377 .vroi_out3 = WM8350_TIE_OFF_500R,
378 .vroi_out2 = WM8350_TIE_OFF_500R,
379 .vroi_out1 = WM8350_TIE_OFF_500R,
381 .codec_current_on = WM8350_CODEC_ISEL_1_0,
382 .codec_current_standby = WM8350_CODEC_ISEL_0_5,
383 .codec_current_charge = WM8350_CODEC_ISEL_1_5,
386 static int mx31_wm8350_init(struct wm8350 *wm8350)
388 wm8350_gpio_config(wm8350, 0, WM8350_GPIO_DIR_IN,
389 WM8350_GPIO0_PWR_ON_IN, WM8350_GPIO_ACTIVE_LOW,
390 WM8350_GPIO_PULL_UP, WM8350_GPIO_INVERT_OFF,
391 WM8350_GPIO_DEBOUNCE_ON);
393 wm8350_gpio_config(wm8350, 3, WM8350_GPIO_DIR_IN,
394 WM8350_GPIO3_PWR_OFF_IN, WM8350_GPIO_ACTIVE_HIGH,
395 WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF,
396 WM8350_GPIO_DEBOUNCE_ON);
398 wm8350_gpio_config(wm8350, 4, WM8350_GPIO_DIR_IN,
399 WM8350_GPIO4_MR_IN, WM8350_GPIO_ACTIVE_HIGH,
400 WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF,
401 WM8350_GPIO_DEBOUNCE_OFF);
403 wm8350_gpio_config(wm8350, 7, WM8350_GPIO_DIR_IN,
404 WM8350_GPIO7_HIBERNATE_IN, WM8350_GPIO_ACTIVE_HIGH,
405 WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF,
406 WM8350_GPIO_DEBOUNCE_OFF);
408 wm8350_gpio_config(wm8350, 6, WM8350_GPIO_DIR_OUT,
409 WM8350_GPIO6_SDOUT_OUT, WM8350_GPIO_ACTIVE_HIGH,
410 WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF,
411 WM8350_GPIO_DEBOUNCE_OFF);
413 wm8350_gpio_config(wm8350, 8, WM8350_GPIO_DIR_OUT,
414 WM8350_GPIO8_VCC_FAULT_OUT, WM8350_GPIO_ACTIVE_LOW,
415 WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF,
416 WM8350_GPIO_DEBOUNCE_OFF);
418 wm8350_gpio_config(wm8350, 9, WM8350_GPIO_DIR_OUT,
419 WM8350_GPIO9_BATT_FAULT_OUT, WM8350_GPIO_ACTIVE_LOW,
420 WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF,
421 WM8350_GPIO_DEBOUNCE_OFF);
423 wm8350_register_regulator(wm8350, WM8350_DCDC_1, &sw1a_data);
424 wm8350_register_regulator(wm8350, WM8350_DCDC_3, &viohi_data);
425 wm8350_register_regulator(wm8350, WM8350_DCDC_4, &violo_data);
426 wm8350_register_regulator(wm8350, WM8350_DCDC_6, &sw2a_data);
427 wm8350_register_regulator(wm8350, WM8350_LDO_1, &ldo1_data);
428 wm8350_register_regulator(wm8350, WM8350_LDO_2, &ldo2_data);
429 wm8350_register_regulator(wm8350, WM8350_LDO_3, &vdig_data);
430 wm8350_register_regulator(wm8350, WM8350_LDO_4, &ldo4_data);
433 wm8350_dcdc_set_slot(wm8350, WM8350_DCDC_5, 1, 1,
434 WM8350_DC5_ERRACT_SHUTDOWN_CONV);
435 wm8350_isink_set_flash(wm8350, WM8350_ISINK_A,
436 WM8350_ISINK_FLASH_DISABLE,
437 WM8350_ISINK_FLASH_TRIG_BIT,
438 WM8350_ISINK_FLASH_DUR_32MS,
439 WM8350_ISINK_FLASH_ON_INSTANT,
440 WM8350_ISINK_FLASH_OFF_INSTANT,
441 WM8350_ISINK_FLASH_MODE_EN);
442 wm8350_dcdc25_set_mode(wm8350, WM8350_DCDC_5,
443 WM8350_ISINK_MODE_BOOST,
444 WM8350_ISINK_ILIM_NORMAL,
446 WM8350_DC5_FBSRC_ISINKA);
447 wm8350_register_led(wm8350, 0, WM8350_DCDC_5, WM8350_ISINK_A,
450 wm8350->codec.platform_data = &imx32ads_wm8350_setup;
452 regulator_has_full_constraints();
457 static struct wm8350_platform_data __initdata mx31_wm8350_pdata = {
458 .init = mx31_wm8350_init,
459 .irq_base = MXC_BOARD_IRQ_START + MXC_MAX_EXP_IO_LINES,
463 static struct i2c_board_info __initdata mx31ads_i2c1_devices[] = {
464 #ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
466 I2C_BOARD_INFO("wm8350", 0x1a),
467 .platform_data = &mx31_wm8350_pdata,
468 .irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
473 static void mxc_init_i2c(void)
475 i2c_register_board_info(1, mx31ads_i2c1_devices,
476 ARRAY_SIZE(mx31ads_i2c1_devices));
478 mxc_iomux_mode(IOMUX_MODE(MX31_PIN_CSPI2_MOSI, IOMUX_CONFIG_ALT1));
479 mxc_iomux_mode(IOMUX_MODE(MX31_PIN_CSPI2_MISO, IOMUX_CONFIG_ALT1));
481 imx31_add_imx_i2c1(NULL);
484 static unsigned int ssi_pins[] = {
487 MX31_PIN_SRXD5__SRXD5,
488 MX31_PIN_STXD5__STXD5,
491 static void mxc_init_audio(void)
493 imx31_add_imx_ssi(0, NULL);
494 mxc_iomux_setup_multiple_pins(ssi_pins, ARRAY_SIZE(ssi_pins), "ssi");
497 /* static mappings */
498 static struct map_desc mx31ads_io_desc[] __initdata = {
500 .virtual = MX31_CS4_BASE_ADDR_VIRT,
501 .pfn = __phys_to_pfn(MX31_CS4_BASE_ADDR),
502 .length = MX31_CS4_SIZE / 2,
507 static void __init mx31ads_map_io(void)
510 iotable_init(mx31ads_io_desc, ARRAY_SIZE(mx31ads_io_desc));
513 static void __init mx31ads_init_irq(void)
516 mx31ads_init_expio();
519 static void __init mx31ads_init(void)
527 static void __init mx31ads_timer_init(void)
529 mx31_clocks_init(26000000);
532 static struct sys_timer mx31ads_timer = {
533 .init = mx31ads_timer_init,
536 MACHINE_START(MX31ADS, "Freescale MX31ADS")
537 /* Maintainer: Freescale Semiconductor, Inc. */
538 .boot_params = MX3x_PHYS_OFFSET + 0x100,
539 .map_io = mx31ads_map_io,
540 .init_early = imx31_init_early,
541 .init_irq = mx31ads_init_irq,
542 .timer = &mx31ads_timer,
543 .init_machine = mx31ads_init,