2 * Copyright (C) 2009 Sascha Hauer, Pengutronix
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
15 #include <linux/types.h>
16 #include <linux/init.h>
18 #include <linux/platform_device.h>
19 #include <linux/mtd/physmap.h>
20 #include <linux/mtd/plat-ram.h>
21 #include <linux/memory.h>
22 #include <linux/gpio.h>
23 #include <linux/smc911x.h>
24 #include <linux/interrupt.h>
25 #include <linux/delay.h>
26 #include <linux/i2c.h>
27 #include <linux/i2c/at24.h>
28 #include <linux/usb/otg.h>
29 #include <linux/usb/ulpi.h>
31 #include <asm/mach-types.h>
32 #include <asm/mach/arch.h>
33 #include <asm/mach/time.h>
34 #include <asm/mach/map.h>
36 #include <mach/hardware.h>
37 #include <mach/common.h>
38 #include <mach/iomux-mx35.h>
40 #include <mach/mx3fb.h>
41 #include <mach/ulpi.h>
42 #include <mach/audmux.h>
44 #include "devices-imx35.h"
47 static const struct fb_videomode fb_modedb[] = {
50 .name = "Sharp-LQ035Q7",
61 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_SHARP_MODE | FB_SYNC_CLK_INVERT | FB_SYNC_CLK_IDLE_EN,
62 .vmode = FB_VMODE_NONINTERLACED,
77 .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_ACT_HIGH,
78 .vmode = FB_VMODE_NONINTERLACED,
83 static struct ipu_platform_data mx3_ipu_data = {
84 .irq_base = MXC_IPU_IRQ_START,
87 static struct mx3fb_platform_data mx3fb_pdata = {
88 .dma_dev = &mx3_ipu.dev,
89 .name = "Sharp-LQ035Q7",
91 .num_modes = ARRAY_SIZE(fb_modedb),
94 static struct physmap_flash_data pcm043_flash_data = {
98 static struct resource pcm043_flash_resource = {
101 .flags = IORESOURCE_MEM,
104 static struct platform_device pcm043_flash = {
105 .name = "physmap-flash",
108 .platform_data = &pcm043_flash_data,
110 .resource = &pcm043_flash_resource,
114 static const struct imxuart_platform_data uart_pdata __initconst = {
115 .flags = IMXUART_HAVE_RTSCTS,
118 #if defined CONFIG_I2C_IMX || defined CONFIG_I2C_IMX_MODULE
119 static const struct imxi2c_platform_data pcm043_i2c0_data __initconst = {
123 static struct at24_platform_data board_eeprom = {
126 .flags = AT24_FLAG_ADDR16,
129 static struct i2c_board_info pcm043_i2c_devices[] = {
131 I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */
132 .platform_data = &board_eeprom,
134 I2C_BOARD_INFO("pcf8563", 0x51),
139 static struct platform_device *devices[] __initdata = {
143 static iomux_v3_cfg_t pcm043_pads[] = {
145 MX35_PAD_CTS1__UART1_CTS,
146 MX35_PAD_RTS1__UART1_RTS,
147 MX35_PAD_TXD1__UART1_TXD_MUX,
148 MX35_PAD_RXD1__UART1_RXD_MUX,
150 MX35_PAD_CTS2__UART2_CTS,
151 MX35_PAD_RTS2__UART2_RTS,
152 MX35_PAD_TXD2__UART2_TXD_MUX,
153 MX35_PAD_RXD2__UART2_RXD_MUX,
155 MX35_PAD_FEC_TX_CLK__FEC_TX_CLK,
156 MX35_PAD_FEC_RX_CLK__FEC_RX_CLK,
157 MX35_PAD_FEC_RX_DV__FEC_RX_DV,
158 MX35_PAD_FEC_COL__FEC_COL,
159 MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
160 MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
161 MX35_PAD_FEC_TX_EN__FEC_TX_EN,
162 MX35_PAD_FEC_MDC__FEC_MDC,
163 MX35_PAD_FEC_MDIO__FEC_MDIO,
164 MX35_PAD_FEC_TX_ERR__FEC_TX_ERR,
165 MX35_PAD_FEC_RX_ERR__FEC_RX_ERR,
166 MX35_PAD_FEC_CRS__FEC_CRS,
167 MX35_PAD_FEC_RDATA1__FEC_RDATA_1,
168 MX35_PAD_FEC_TDATA1__FEC_TDATA_1,
169 MX35_PAD_FEC_RDATA2__FEC_RDATA_2,
170 MX35_PAD_FEC_TDATA2__FEC_TDATA_2,
171 MX35_PAD_FEC_RDATA3__FEC_RDATA_3,
172 MX35_PAD_FEC_TDATA3__FEC_TDATA_3,
174 MX35_PAD_I2C1_CLK__I2C1_SCL,
175 MX35_PAD_I2C1_DAT__I2C1_SDA,
177 MX35_PAD_LD0__IPU_DISPB_DAT_0,
178 MX35_PAD_LD1__IPU_DISPB_DAT_1,
179 MX35_PAD_LD2__IPU_DISPB_DAT_2,
180 MX35_PAD_LD3__IPU_DISPB_DAT_3,
181 MX35_PAD_LD4__IPU_DISPB_DAT_4,
182 MX35_PAD_LD5__IPU_DISPB_DAT_5,
183 MX35_PAD_LD6__IPU_DISPB_DAT_6,
184 MX35_PAD_LD7__IPU_DISPB_DAT_7,
185 MX35_PAD_LD8__IPU_DISPB_DAT_8,
186 MX35_PAD_LD9__IPU_DISPB_DAT_9,
187 MX35_PAD_LD10__IPU_DISPB_DAT_10,
188 MX35_PAD_LD11__IPU_DISPB_DAT_11,
189 MX35_PAD_LD12__IPU_DISPB_DAT_12,
190 MX35_PAD_LD13__IPU_DISPB_DAT_13,
191 MX35_PAD_LD14__IPU_DISPB_DAT_14,
192 MX35_PAD_LD15__IPU_DISPB_DAT_15,
193 MX35_PAD_LD16__IPU_DISPB_DAT_16,
194 MX35_PAD_LD17__IPU_DISPB_DAT_17,
195 MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC,
196 MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK,
197 MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY,
198 MX35_PAD_CONTRAST__IPU_DISPB_CONTR,
199 MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC,
200 MX35_PAD_D3_REV__IPU_DISPB_D3_REV,
201 MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS,
203 MX35_PAD_ATA_CS0__GPIO2_6,
205 MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR,
206 MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC,
208 MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS,
209 MX35_PAD_STXD4__AUDMUX_AUD4_TXD,
210 MX35_PAD_SRXD4__AUDMUX_AUD4_RXD,
211 MX35_PAD_SCK4__AUDMUX_AUD4_TXC,
213 MX35_PAD_TX5_RX0__CAN2_TXCAN,
214 MX35_PAD_TX4_RX1__CAN2_RXCAN,
216 MX35_PAD_SD1_CMD__ESDHC1_CMD,
217 MX35_PAD_SD1_CLK__ESDHC1_CLK,
218 MX35_PAD_SD1_DATA0__ESDHC1_DAT0,
219 MX35_PAD_SD1_DATA1__ESDHC1_DAT1,
220 MX35_PAD_SD1_DATA2__ESDHC1_DAT2,
221 MX35_PAD_SD1_DATA3__ESDHC1_DAT3,
224 #define AC97_GPIO_TXFS (1 * 32 + 31)
225 #define AC97_GPIO_TXD (1 * 32 + 28)
226 #define AC97_GPIO_RESET (1 * 32 + 0)
228 static void pcm043_ac97_warm_reset(struct snd_ac97 *ac97)
230 iomux_v3_cfg_t txfs_gpio = MX35_PAD_STXFS4__GPIO2_31;
231 iomux_v3_cfg_t txfs = MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS;
234 ret = gpio_request(AC97_GPIO_TXFS, "SSI");
236 printk("failed to get GPIO_TXFS: %d\n", ret);
240 mxc_iomux_v3_setup_pad(txfs_gpio);
243 gpio_direction_output(AC97_GPIO_TXFS, 1);
245 gpio_set_value(AC97_GPIO_TXFS, 0);
247 gpio_free(AC97_GPIO_TXFS);
248 mxc_iomux_v3_setup_pad(txfs);
251 static void pcm043_ac97_cold_reset(struct snd_ac97 *ac97)
253 iomux_v3_cfg_t txfs_gpio = MX35_PAD_STXFS4__GPIO2_31;
254 iomux_v3_cfg_t txfs = MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS;
255 iomux_v3_cfg_t txd_gpio = MX35_PAD_STXD4__GPIO2_28;
256 iomux_v3_cfg_t txd = MX35_PAD_STXD4__AUDMUX_AUD4_TXD;
257 iomux_v3_cfg_t reset_gpio = MX35_PAD_SD2_CMD__GPIO2_0;
260 ret = gpio_request(AC97_GPIO_TXFS, "SSI");
264 ret = gpio_request(AC97_GPIO_TXD, "SSI");
268 ret = gpio_request(AC97_GPIO_RESET, "SSI");
272 mxc_iomux_v3_setup_pad(txfs_gpio);
273 mxc_iomux_v3_setup_pad(txd_gpio);
274 mxc_iomux_v3_setup_pad(reset_gpio);
276 gpio_direction_output(AC97_GPIO_TXFS, 0);
277 gpio_direction_output(AC97_GPIO_TXD, 0);
280 gpio_direction_output(AC97_GPIO_RESET, 0);
282 gpio_direction_output(AC97_GPIO_RESET, 1);
284 mxc_iomux_v3_setup_pad(txd);
285 mxc_iomux_v3_setup_pad(txfs);
287 gpio_free(AC97_GPIO_RESET);
289 gpio_free(AC97_GPIO_TXD);
291 gpio_free(AC97_GPIO_TXFS);
294 printk("%s failed with %d\n", __func__, ret);
298 static const struct imx_ssi_platform_data pcm043_ssi_pdata __initconst = {
299 .ac97_reset = pcm043_ac97_cold_reset,
300 .ac97_warm_reset = pcm043_ac97_warm_reset,
301 .flags = IMX_SSI_USE_AC97,
304 static const struct mxc_nand_platform_data
305 pcm037_nand_board_info __initconst = {
310 #if defined(CONFIG_USB_ULPI)
311 static struct mxc_usbh_platform_data otg_pdata __initdata = {
312 .portsc = MXC_EHCI_MODE_UTMI,
313 .flags = MXC_EHCI_INTERFACE_DIFF_UNI,
316 static const struct mxc_usbh_platform_data usbh1_pdata __initconst = {
317 .portsc = MXC_EHCI_MODE_SERIAL,
318 .flags = MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY |
323 static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
324 .operating_mode = FSL_USB2_DR_DEVICE,
325 .phy_mode = FSL_USB2_PHY_UTMI,
328 static int otg_mode_host;
330 static int __init pcm043_otg_mode(char *options)
332 if (!strcmp(options, "host"))
334 else if (!strcmp(options, "device"))
337 pr_info("otg_mode neither \"host\" nor \"device\". "
338 "Defaulting to device\n");
341 __setup("otg_mode=", pcm043_otg_mode);
344 * Board specific initialization.
346 static void __init mxc_board_init(void)
348 mxc_iomux_v3_setup_multiple_pads(pcm043_pads, ARRAY_SIZE(pcm043_pads));
350 mxc_audmux_v2_configure_port(3,
351 MXC_AUDMUX_V2_PTCR_SYN | /* 4wire mode */
352 MXC_AUDMUX_V2_PTCR_TFSEL(0) |
353 MXC_AUDMUX_V2_PTCR_TFSDIR,
354 MXC_AUDMUX_V2_PDCR_RXDSEL(0));
356 mxc_audmux_v2_configure_port(0,
357 MXC_AUDMUX_V2_PTCR_SYN | /* 4wire mode */
358 MXC_AUDMUX_V2_PTCR_TCSEL(3) |
359 MXC_AUDMUX_V2_PTCR_TCLKDIR, /* clock is output */
360 MXC_AUDMUX_V2_PDCR_RXDSEL(3));
363 platform_add_devices(devices, ARRAY_SIZE(devices));
364 imx35_add_imx2_wdt(NULL);
366 imx35_add_imx_uart0(&uart_pdata);
367 imx35_add_mxc_nand(&pcm037_nand_board_info);
368 imx35_add_imx_ssi(0, &pcm043_ssi_pdata);
370 imx35_add_imx_uart1(&uart_pdata);
372 #if defined CONFIG_I2C_IMX || defined CONFIG_I2C_IMX_MODULE
373 i2c_register_board_info(0, pcm043_i2c_devices,
374 ARRAY_SIZE(pcm043_i2c_devices));
376 imx35_add_imx_i2c0(&pcm043_i2c0_data);
379 mxc_register_device(&mx3_ipu, &mx3_ipu_data);
380 mxc_register_device(&mx3_fb, &mx3fb_pdata);
382 #if defined(CONFIG_USB_ULPI)
384 otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
385 ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
387 imx35_add_mxc_ehci_otg(&otg_pdata);
390 imx35_add_mxc_ehci_hs(&usbh1_pdata);
393 imx35_add_fsl_usb2_udc(&otg_device_pdata);
395 imx35_add_flexcan1(NULL);
396 imx35_add_sdhci_esdhc_imx(0, NULL);
399 static void __init pcm043_timer_init(void)
404 struct sys_timer pcm043_timer = {
405 .init = pcm043_timer_init,
408 MACHINE_START(PCM043, "Phytec Phycore pcm043")
409 /* Maintainer: Pengutronix */
410 .boot_params = MX3x_PHYS_OFFSET + 0x100,
411 .map_io = mx35_map_io,
412 .init_irq = mx35_init_irq,
413 .init_machine = mxc_board_init,
414 .timer = &pcm043_timer,