2 * Copyright (C) 2009 Sascha Hauer, Pengutronix
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 #include <linux/types.h>
20 #include <linux/init.h>
22 #include <linux/platform_device.h>
23 #include <linux/mtd/physmap.h>
24 #include <linux/mtd/plat-ram.h>
25 #include <linux/memory.h>
26 #include <linux/gpio.h>
27 #include <linux/smc911x.h>
28 #include <linux/interrupt.h>
29 #include <linux/delay.h>
30 #include <linux/i2c.h>
31 #include <linux/i2c/at24.h>
32 #include <linux/usb/otg.h>
33 #include <linux/usb/ulpi.h>
34 #include <linux/fsl_devices.h>
36 #include <asm/mach-types.h>
37 #include <asm/mach/arch.h>
38 #include <asm/mach/time.h>
39 #include <asm/mach/map.h>
41 #include <mach/hardware.h>
42 #include <mach/common.h>
43 #include <mach/imx-uart.h>
44 #if defined CONFIG_I2C_IMX || defined CONFIG_I2C_IMX_MODULE
47 #include <mach/iomux-mx35.h>
49 #include <mach/mx3fb.h>
50 #include <mach/mxc_nand.h>
51 #include <mach/mxc_ehci.h>
52 #include <mach/ulpi.h>
53 #include <mach/audmux.h>
58 static const struct fb_videomode fb_modedb[] = {
61 .name = "Sharp-LQ035Q7",
72 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_SHARP_MODE | FB_SYNC_CLK_INVERT | FB_SYNC_CLK_IDLE_EN,
73 .vmode = FB_VMODE_NONINTERLACED,
88 .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_ACT_HIGH,
89 .vmode = FB_VMODE_NONINTERLACED,
94 static struct ipu_platform_data mx3_ipu_data = {
95 .irq_base = MXC_IPU_IRQ_START,
98 static struct mx3fb_platform_data mx3fb_pdata = {
99 .dma_dev = &mx3_ipu.dev,
100 .name = "Sharp-LQ035Q7",
102 .num_modes = ARRAY_SIZE(fb_modedb),
105 static struct physmap_flash_data pcm043_flash_data = {
109 static struct resource pcm043_flash_resource = {
112 .flags = IORESOURCE_MEM,
115 static struct platform_device pcm043_flash = {
116 .name = "physmap-flash",
119 .platform_data = &pcm043_flash_data,
121 .resource = &pcm043_flash_resource,
125 static struct imxuart_platform_data uart_pdata = {
126 .flags = IMXUART_HAVE_RTSCTS,
129 #if defined CONFIG_I2C_IMX || defined CONFIG_I2C_IMX_MODULE
130 static struct imxi2c_platform_data pcm043_i2c_1_data = {
134 static struct at24_platform_data board_eeprom = {
137 .flags = AT24_FLAG_ADDR16,
140 static struct i2c_board_info pcm043_i2c_devices[] = {
142 I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */
143 .platform_data = &board_eeprom,
145 I2C_BOARD_INFO("pcf8563", 0x51),
150 static struct platform_device *devices[] __initdata = {
156 static struct pad_desc pcm043_pads[] = {
158 MX35_PAD_CTS1__UART1_CTS,
159 MX35_PAD_RTS1__UART1_RTS,
160 MX35_PAD_TXD1__UART1_TXD_MUX,
161 MX35_PAD_RXD1__UART1_RXD_MUX,
163 MX35_PAD_CTS2__UART2_CTS,
164 MX35_PAD_RTS2__UART2_RTS,
165 MX35_PAD_TXD2__UART2_TXD_MUX,
166 MX35_PAD_RXD2__UART2_RXD_MUX,
168 MX35_PAD_FEC_TX_CLK__FEC_TX_CLK,
169 MX35_PAD_FEC_RX_CLK__FEC_RX_CLK,
170 MX35_PAD_FEC_RX_DV__FEC_RX_DV,
171 MX35_PAD_FEC_COL__FEC_COL,
172 MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
173 MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
174 MX35_PAD_FEC_TX_EN__FEC_TX_EN,
175 MX35_PAD_FEC_MDC__FEC_MDC,
176 MX35_PAD_FEC_MDIO__FEC_MDIO,
177 MX35_PAD_FEC_TX_ERR__FEC_TX_ERR,
178 MX35_PAD_FEC_RX_ERR__FEC_RX_ERR,
179 MX35_PAD_FEC_CRS__FEC_CRS,
180 MX35_PAD_FEC_RDATA1__FEC_RDATA_1,
181 MX35_PAD_FEC_TDATA1__FEC_TDATA_1,
182 MX35_PAD_FEC_RDATA2__FEC_RDATA_2,
183 MX35_PAD_FEC_TDATA2__FEC_TDATA_2,
184 MX35_PAD_FEC_RDATA3__FEC_RDATA_3,
185 MX35_PAD_FEC_TDATA3__FEC_TDATA_3,
187 MX35_PAD_I2C1_CLK__I2C1_SCL,
188 MX35_PAD_I2C1_DAT__I2C1_SDA,
190 MX35_PAD_LD0__IPU_DISPB_DAT_0,
191 MX35_PAD_LD1__IPU_DISPB_DAT_1,
192 MX35_PAD_LD2__IPU_DISPB_DAT_2,
193 MX35_PAD_LD3__IPU_DISPB_DAT_3,
194 MX35_PAD_LD4__IPU_DISPB_DAT_4,
195 MX35_PAD_LD5__IPU_DISPB_DAT_5,
196 MX35_PAD_LD6__IPU_DISPB_DAT_6,
197 MX35_PAD_LD7__IPU_DISPB_DAT_7,
198 MX35_PAD_LD8__IPU_DISPB_DAT_8,
199 MX35_PAD_LD9__IPU_DISPB_DAT_9,
200 MX35_PAD_LD10__IPU_DISPB_DAT_10,
201 MX35_PAD_LD11__IPU_DISPB_DAT_11,
202 MX35_PAD_LD12__IPU_DISPB_DAT_12,
203 MX35_PAD_LD13__IPU_DISPB_DAT_13,
204 MX35_PAD_LD14__IPU_DISPB_DAT_14,
205 MX35_PAD_LD15__IPU_DISPB_DAT_15,
206 MX35_PAD_LD16__IPU_DISPB_DAT_16,
207 MX35_PAD_LD17__IPU_DISPB_DAT_17,
208 MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC,
209 MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK,
210 MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY,
211 MX35_PAD_CONTRAST__IPU_DISPB_CONTR,
212 MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC,
213 MX35_PAD_D3_REV__IPU_DISPB_D3_REV,
214 MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS,
216 MX35_PAD_ATA_CS0__GPIO2_6,
218 MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR,
219 MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC,
221 MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS,
222 MX35_PAD_STXD4__AUDMUX_AUD4_TXD,
223 MX35_PAD_SRXD4__AUDMUX_AUD4_RXD,
224 MX35_PAD_SCK4__AUDMUX_AUD4_TXC,
227 #define AC97_GPIO_TXFS (1 * 32 + 31)
228 #define AC97_GPIO_TXD (1 * 32 + 28)
229 #define AC97_GPIO_RESET (1 * 32 + 0)
231 static void pcm043_ac97_warm_reset(struct snd_ac97 *ac97)
233 struct pad_desc txfs_gpio = MX35_PAD_STXFS4__GPIO2_31;
234 struct pad_desc txfs = MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS;
237 ret = gpio_request(AC97_GPIO_TXFS, "SSI");
239 printk("failed to get GPIO_TXFS: %d\n", ret);
243 mxc_iomux_v3_setup_pad(&txfs_gpio);
246 gpio_direction_output(AC97_GPIO_TXFS, 1);
248 gpio_set_value(AC97_GPIO_TXFS, 0);
250 gpio_free(AC97_GPIO_TXFS);
251 mxc_iomux_v3_setup_pad(&txfs);
254 static void pcm043_ac97_cold_reset(struct snd_ac97 *ac97)
256 struct pad_desc txfs_gpio = MX35_PAD_STXFS4__GPIO2_31;
257 struct pad_desc txfs = MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS;
258 struct pad_desc txd_gpio = MX35_PAD_STXD4__GPIO2_28;
259 struct pad_desc txd = MX35_PAD_STXD4__AUDMUX_AUD4_TXD;
260 struct pad_desc reset_gpio = MX35_PAD_SD2_CMD__GPIO2_0;
263 ret = gpio_request(AC97_GPIO_TXFS, "SSI");
267 ret = gpio_request(AC97_GPIO_TXD, "SSI");
271 ret = gpio_request(AC97_GPIO_RESET, "SSI");
275 mxc_iomux_v3_setup_pad(&txfs_gpio);
276 mxc_iomux_v3_setup_pad(&txd_gpio);
277 mxc_iomux_v3_setup_pad(&reset_gpio);
279 gpio_direction_output(AC97_GPIO_TXFS, 0);
280 gpio_direction_output(AC97_GPIO_TXD, 0);
283 gpio_direction_output(AC97_GPIO_RESET, 0);
285 gpio_direction_output(AC97_GPIO_RESET, 1);
287 mxc_iomux_v3_setup_pad(&txd);
288 mxc_iomux_v3_setup_pad(&txfs);
290 gpio_free(AC97_GPIO_RESET);
292 gpio_free(AC97_GPIO_TXD);
294 gpio_free(AC97_GPIO_TXFS);
297 printk("%s failed with %d\n", __func__, ret);
301 static struct imx_ssi_platform_data pcm043_ssi_pdata = {
302 .ac97_reset = pcm043_ac97_cold_reset,
303 .ac97_warm_reset = pcm043_ac97_warm_reset,
304 .flags = IMX_SSI_USE_AC97,
307 static struct mxc_nand_platform_data pcm037_nand_board_info = {
312 static struct mxc_usbh_platform_data otg_pdata = {
313 .portsc = MXC_EHCI_MODE_UTMI,
314 .flags = MXC_EHCI_INTERFACE_DIFF_UNI,
317 static struct mxc_usbh_platform_data usbh1_pdata = {
318 .portsc = MXC_EHCI_MODE_SERIAL,
319 .flags = MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY |
323 static struct fsl_usb2_platform_data otg_device_pdata = {
324 .operating_mode = FSL_USB2_DR_DEVICE,
325 .phy_mode = FSL_USB2_PHY_UTMI,
328 static int otg_mode_host;
330 static int __init pcm043_otg_mode(char *options)
332 if (!strcmp(options, "host"))
334 else if (!strcmp(options, "device"))
337 pr_info("otg_mode neither \"host\" nor \"device\". "
338 "Defaulting to device\n");
341 __setup("otg_mode=", pcm043_otg_mode);
344 * Board specific initialization.
346 static void __init mxc_board_init(void)
348 mxc_iomux_v3_setup_multiple_pads(pcm043_pads, ARRAY_SIZE(pcm043_pads));
350 mxc_audmux_v2_configure_port(3,
351 MXC_AUDMUX_V2_PTCR_SYN | /* 4wire mode */
352 MXC_AUDMUX_V2_PTCR_TFSEL(0) |
353 MXC_AUDMUX_V2_PTCR_TFSDIR,
354 MXC_AUDMUX_V2_PDCR_RXDSEL(0));
356 mxc_audmux_v2_configure_port(0,
357 MXC_AUDMUX_V2_PTCR_SYN | /* 4wire mode */
358 MXC_AUDMUX_V2_PTCR_TCSEL(3) |
359 MXC_AUDMUX_V2_PTCR_TCLKDIR, /* clock is output */
360 MXC_AUDMUX_V2_PDCR_RXDSEL(3));
362 platform_add_devices(devices, ARRAY_SIZE(devices));
364 mxc_register_device(&mxc_uart_device0, &uart_pdata);
365 mxc_register_device(&mxc_nand_device, &pcm037_nand_board_info);
366 mxc_register_device(&imx_ssi_device0, &pcm043_ssi_pdata);
368 mxc_register_device(&mxc_uart_device1, &uart_pdata);
370 #if defined CONFIG_I2C_IMX || defined CONFIG_I2C_IMX_MODULE
371 i2c_register_board_info(0, pcm043_i2c_devices,
372 ARRAY_SIZE(pcm043_i2c_devices));
374 mxc_register_device(&mxc_i2c_device0, &pcm043_i2c_1_data);
377 mxc_register_device(&mx3_ipu, &mx3_ipu_data);
378 mxc_register_device(&mx3_fb, &mx3fb_pdata);
380 #if defined(CONFIG_USB_ULPI)
382 otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
383 USB_OTG_DRV_VBUS | USB_OTG_DRV_VBUS_EXT);
385 mxc_register_device(&mxc_otg_host, &otg_pdata);
388 mxc_register_device(&mxc_usbh1, &usbh1_pdata);
391 mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata);
395 static void __init pcm043_timer_init(void)
400 struct sys_timer pcm043_timer = {
401 .init = pcm043_timer_init,
404 MACHINE_START(PCM043, "Phytec Phycore pcm043")
405 /* Maintainer: Pengutronix */
406 .phys_io = MX35_AIPS1_BASE_ADDR,
407 .io_pg_offst = ((MX35_AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
408 .boot_params = MX3x_PHYS_OFFSET + 0x100,
409 .map_io = mx35_map_io,
410 .init_irq = mx35_init_irq,
411 .init_machine = mxc_board_init,
412 .timer = &pcm043_timer,