arch/arm/mach-mx5/board-cpuimx51.c

   1 /*
   2  *
   3  * Copyright (C) 2010 Eric Bénard <eric@eukrea.com>
   4  *
   5  * based on board-mx51_babbage.c which is
   6  * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
   7  * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
   8  *
   9  * The code contained herein is licensed under the GNU General Public
  10  * License. You may obtain a copy of the GNU General Public License
  11  * Version 2 or later at the following locations:
  12  *
  13  * http://www.opensource.org/licenses/gpl-license.html
  14  * http://www.gnu.org/copyleft/gpl.html
  15  */
  16
  17 #include <linux/init.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/serial_8250.h>
  20 #include <linux/i2c.h>
  21 #include <linux/gpio.h>
  22 #include <linux/delay.h>
  23 #include <linux/io.h>
  24 #include <linux/interrupt.h>
  25
  26 #include <mach/eukrea-baseboards.h>
  27 #include <mach/common.h>
  28 #include <mach/hardware.h>
  29 #include <mach/iomux-mx51.h>
  30
  31 #include <asm/setup.h>
  32 #include <asm/mach-types.h>
  33 #include <asm/mach/arch.h>
  34 #include <asm/mach/time.h>
  35
  36 #include "devices-imx51.h"
  37 #include "devices.h"
  38
  39 #define CPUIMX51_USBH1_STP      IMX_GPIO_NR(1, 27)
  40 #define CPUIMX51_QUARTA_GPIO    IMX_GPIO_NR(3, 28)
  41 #define CPUIMX51_QUARTB_GPIO    IMX_GPIO_NR(3, 25)
  42 #define CPUIMX51_QUARTC_GPIO    IMX_GPIO_NR(3, 26)
  43 #define CPUIMX51_QUARTD_GPIO    IMX_GPIO_NR(3, 27)
  44 #define CPUIMX51_QUART_XTAL     14745600
  45 #define CPUIMX51_QUART_REGSHIFT 17
  46
  47 /* USB_CTRL_1 */
  48 #define MX51_USB_CTRL_1_OFFSET          0x10
  49 #define MX51_USB_CTRL_UH1_EXT_CLK_EN    (1 << 25)
  50
  51 #define MX51_USB_PLLDIV_12_MHZ          0x00
  52 #define MX51_USB_PLL_DIV_19_2_MHZ       0x01
  53 #define MX51_USB_PLL_DIV_24_MHZ         0x02
  54
  55 static struct plat_serial8250_port serial_platform_data[] = {
  56         {
  57                 .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x400000),
  58                 .irq = gpio_to_irq(CPUIMX51_QUARTA_GPIO),
  59                 .irqflags = IRQF_TRIGGER_HIGH,
  60                 .uartclk = CPUIMX51_QUART_XTAL,
  61                 .regshift = CPUIMX51_QUART_REGSHIFT,
  62                 .iotype = UPIO_MEM,
  63                 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
  64         }, {
  65                 .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x800000),
  66                 .irq = gpio_to_irq(CPUIMX51_QUARTB_GPIO),
  67                 .irqflags = IRQF_TRIGGER_HIGH,
  68                 .uartclk = CPUIMX51_QUART_XTAL,
  69                 .regshift = CPUIMX51_QUART_REGSHIFT,
  70                 .iotype = UPIO_MEM,
  71                 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
  72         }, {
  73                 .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x1000000),
  74                 .irq = gpio_to_irq(CPUIMX51_QUARTC_GPIO),
  75                 .irqflags = IRQF_TRIGGER_HIGH,
  76                 .uartclk = CPUIMX51_QUART_XTAL,
  77                 .regshift = CPUIMX51_QUART_REGSHIFT,
  78                 .iotype = UPIO_MEM,
  79                 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
  80         }, {
  81                 .mapbase = (unsigned long)(MX51_CS1_BASE_ADDR + 0x2000000),
  82                 .irq = gpio_to_irq(CPUIMX51_QUARTD_GPIO),
  83                 .irqflags = IRQF_TRIGGER_HIGH,
  84                 .uartclk = CPUIMX51_QUART_XTAL,
  85                 .regshift = CPUIMX51_QUART_REGSHIFT,
  86                 .iotype = UPIO_MEM,
  87                 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP,
  88         }, {
  89         }
  90 };
  91
  92 static struct platform_device serial_device = {
  93         .name = "serial8250",
  94         .id = 0,
  95         .dev = {
  96                 .platform_data = serial_platform_data,
  97         },
  98 };
  99
 100 static struct platform_device *devices[] __initdata = {
 101         &serial_device,
 102 };
 103
 104 static iomux_v3_cfg_t eukrea_cpuimx51_pads[] = {
 105         /* UART1 */
 106         MX51_PAD_UART1_RXD__UART1_RXD,
 107         MX51_PAD_UART1_TXD__UART1_TXD,
 108         MX51_PAD_UART1_RTS__UART1_RTS,
 109         MX51_PAD_UART1_CTS__UART1_CTS,
 110
 111         /* I2C2 */
 112         MX51_PAD_GPIO1_2__I2C2_SCL,
 113         MX51_PAD_GPIO1_3__I2C2_SDA,
 114         MX51_PAD_NANDF_D10__GPIO3_30,
 115
 116         /* QUART IRQ */
 117         MX51_PAD_NANDF_D15__GPIO3_25,
 118         MX51_PAD_NANDF_D14__GPIO3_26,
 119         MX51_PAD_NANDF_D13__GPIO3_27,
 120         MX51_PAD_NANDF_D12__GPIO3_28,
 121
 122         /* USB HOST1 */
 123         MX51_PAD_USBH1_CLK__USBH1_CLK,
 124         MX51_PAD_USBH1_DIR__USBH1_DIR,
 125         MX51_PAD_USBH1_NXT__USBH1_NXT,
 126         MX51_PAD_USBH1_DATA0__USBH1_DATA0,
 127         MX51_PAD_USBH1_DATA1__USBH1_DATA1,
 128         MX51_PAD_USBH1_DATA2__USBH1_DATA2,
 129         MX51_PAD_USBH1_DATA3__USBH1_DATA3,
 130         MX51_PAD_USBH1_DATA4__USBH1_DATA4,
 131         MX51_PAD_USBH1_DATA5__USBH1_DATA5,
 132         MX51_PAD_USBH1_DATA6__USBH1_DATA6,
 133         MX51_PAD_USBH1_DATA7__USBH1_DATA7,
 134         MX51_PAD_USBH1_STP__USBH1_STP,
 135 };
 136
 137 static const struct mxc_nand_platform_data
 138                 eukrea_cpuimx51_nand_board_info __initconst = {
 139         .width          = 1,
 140         .hw_ecc         = 1,
 141         .flash_bbt      = 1,
 142 };
 143
 144 static const struct imxuart_platform_data uart_pdata __initconst = {
 145         .flags = IMXUART_HAVE_RTSCTS,
 146 };
 147
 148 static const
 149 struct imxi2c_platform_data eukrea_cpuimx51_i2c_data __initconst = {
 150         .bitrate = 100000,
 151 };
 152
 153 static struct i2c_board_info eukrea_cpuimx51_i2c_devices[] = {
 154         {
 155                 I2C_BOARD_INFO("pcf8563", 0x51),
 156         },
 157 };
 158
 159 /* This function is board specific as the bit mask for the plldiv will also
 160 be different for other Freescale SoCs, thus a common bitmask is not
 161 possible and cannot get place in /plat-mxc/ehci.c.*/
 162 static int initialize_otg_port(struct platform_device *pdev)
 163 {
 164         u32 v;
 165         void __iomem *usb_base;
 166         void __iomem *usbother_base;
 167
 168         usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
 169         if (!usb_base)
 170                 return -ENOMEM;
 171         usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
 172
 173         /* Set the PHY clock to 19.2MHz */
 174         v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
 175         v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK;
 176         v |= MX51_USB_PLL_DIV_19_2_MHZ;
 177         __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET);
 178         iounmap(usb_base);
 179
 180         mdelay(10);
 181
 182         return mx51_initialize_usb_hw(0, MXC_EHCI_INTERNAL_PHY);
 183 }
 184
 185 static int initialize_usbh1_port(struct platform_device *pdev)
 186 {
 187         u32 v;
 188         void __iomem *usb_base;
 189         void __iomem *usbother_base;
 190
 191         usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
 192         if (!usb_base)
 193                 return -ENOMEM;
 194         usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
 195
 196         /* The clock for the USBH1 ULPI port will come externally from the PHY. */
 197         v = __raw_readl(usbother_base + MX51_USB_CTRL_1_OFFSET);
 198         __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN, usbother_base + MX51_USB_CTRL_1_OFFSET);
 199         iounmap(usb_base);
 200
 201         mdelay(10);
 202
 203         return mx51_initialize_usb_hw(1, MXC_EHCI_POWER_PINS_ENABLED |
 204                         MXC_EHCI_ITC_NO_THRESHOLD);
 205 }
 206
 207 static struct mxc_usbh_platform_data dr_utmi_config = {
 208         .init           = initialize_otg_port,
 209         .portsc = MXC_EHCI_UTMI_16BIT,
 210 };
 211
 212 static struct fsl_usb2_platform_data usb_pdata = {
 213         .operating_mode = FSL_USB2_DR_DEVICE,
 214         .phy_mode       = FSL_USB2_PHY_UTMI_WIDE,
 215 };
 216
 217 static struct mxc_usbh_platform_data usbh1_config = {
 218         .init           = initialize_usbh1_port,
 219         .portsc = MXC_EHCI_MODE_ULPI,
 220 };
 221
 222 static int otg_mode_host;
 223
 224 static int __init eukrea_cpuimx51_otg_mode(char *options)
 225 {
 226         if (!strcmp(options, "host"))
 227                 otg_mode_host = 1;
 228         else if (!strcmp(options, "device"))
 229                 otg_mode_host = 0;
 230         else
 231                 pr_info("otg_mode neither \"host\" nor \"device\". "
 232                         "Defaulting to device\n");
 233         return 0;
 234 }
 235 __setup("otg_mode=", eukrea_cpuimx51_otg_mode);
 236
 237 /*
 238  * Board specific initialization.
 239  */
 240 static void __init eukrea_cpuimx51_init(void)
 241 {
 242         imx51_soc_init();
 243
 244         mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx51_pads,
 245                                         ARRAY_SIZE(eukrea_cpuimx51_pads));
 246
 247         imx51_add_imx_uart(0, &uart_pdata);
 248         imx51_add_mxc_nand(&eukrea_cpuimx51_nand_board_info);
 249
 250         gpio_request(CPUIMX51_QUARTA_GPIO, "quarta_irq");
 251         gpio_direction_input(CPUIMX51_QUARTA_GPIO);
 252         gpio_free(CPUIMX51_QUARTA_GPIO);
 253         gpio_request(CPUIMX51_QUARTB_GPIO, "quartb_irq");
 254         gpio_direction_input(CPUIMX51_QUARTB_GPIO);
 255         gpio_free(CPUIMX51_QUARTB_GPIO);
 256         gpio_request(CPUIMX51_QUARTC_GPIO, "quartc_irq");
 257         gpio_direction_input(CPUIMX51_QUARTC_GPIO);
 258         gpio_free(CPUIMX51_QUARTC_GPIO);
 259         gpio_request(CPUIMX51_QUARTD_GPIO, "quartd_irq");
 260         gpio_direction_input(CPUIMX51_QUARTD_GPIO);
 261         gpio_free(CPUIMX51_QUARTD_GPIO);
 262
 263         imx51_add_fec(NULL);
 264         platform_add_devices(devices, ARRAY_SIZE(devices));
 265
 266         imx51_add_imx_i2c(1, &eukrea_cpuimx51_i2c_data);
 267         i2c_register_board_info(1, eukrea_cpuimx51_i2c_devices,
 268                                 ARRAY_SIZE(eukrea_cpuimx51_i2c_devices));
 269
 270         if (otg_mode_host)
 271                 mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config);
 272         else {
 273                 initialize_otg_port(NULL);
 274                 mxc_register_device(&mxc_usbdr_udc_device, &usb_pdata);
 275         }
 276         mxc_register_device(&mxc_usbh1_device, &usbh1_config);
 277
 278 #ifdef CONFIG_MACH_EUKREA_MBIMX51_BASEBOARD
 279         eukrea_mbimx51_baseboard_init();
 280 #endif
 281 }
 282
 283 static void __init eukrea_cpuimx51_timer_init(void)
 284 {
 285         mx51_clocks_init(32768, 24000000, 22579200, 0);
 286 }
 287
 288 static struct sys_timer mxc_timer = {
 289         .init   = eukrea_cpuimx51_timer_init,
 290 };
 291
 292 MACHINE_START(EUKREA_CPUIMX51, "Eukrea CPUIMX51 Module")
 293         /* Maintainer: Eric Bénard <eric@eukrea.com> */
 294         .boot_params = MX51_PHYS_OFFSET + 0x100,
 295         .map_io = mx51_map_io,
 296         .init_early = imx51_init_early,
 297         .init_irq = mx51_init_irq,
 298         .timer = &mxc_timer,
 299         .init_machine = eukrea_cpuimx51_init,
 300 MACHINE_END