2 * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
14 #include <linux/delay.h>
15 #include <linux/clk.h>
18 #include <asm/clkdev.h>
19 #include <asm/div64.h>
21 #include <mach/hardware.h>
22 #include <mach/common.h>
23 #include <mach/clock.h>
27 /* External clock values passed-in by the board code */
28 static unsigned long external_high_reference, external_low_reference;
29 static unsigned long oscillator_reference, ckih2_reference;
31 static struct clk osc_clk;
32 static struct clk pll1_main_clk;
33 static struct clk pll1_sw_clk;
34 static struct clk pll2_sw_clk;
35 static struct clk pll3_sw_clk;
36 static struct clk mx53_pll4_sw_clk;
37 static struct clk lp_apm_clk;
38 static struct clk periph_apm_clk;
39 static struct clk ahb_clk;
40 static struct clk ipg_clk;
41 static struct clk usboh3_clk;
43 #define MAX_DPLL_WAIT_TRIES 1000 /* 1000 * udelay(1) = 1ms */
45 /* calculate best pre and post dividers to get the required divider */
46 static void __calc_pre_post_dividers(u32 div, u32 *pre, u32 *post,
47 u32 max_pre, u32 max_post)
49 if (div >= max_pre * max_post) {
52 } else if (div >= max_pre) {
53 u32 min_pre, temp_pre, old_err, err;
54 min_pre = DIV_ROUND_UP(div, max_post);
56 for (temp_pre = max_pre; temp_pre >= min_pre; temp_pre--) {
68 *post = DIV_ROUND_UP(div, *pre);
75 static void _clk_ccgr_setclk(struct clk *clk, unsigned mode)
77 u32 reg = __raw_readl(clk->enable_reg);
79 reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift);
80 reg |= mode << clk->enable_shift;
82 __raw_writel(reg, clk->enable_reg);
85 static int _clk_ccgr_enable(struct clk *clk)
87 _clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_ON);
91 static void _clk_ccgr_disable(struct clk *clk)
93 _clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_OFF);
96 static int _clk_ccgr_enable_inrun(struct clk *clk)
98 _clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_IDLE);
102 static void _clk_ccgr_disable_inwait(struct clk *clk)
104 _clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_IDLE);
108 * For the 4-to-1 muxed input clock
110 static inline u32 _get_mux(struct clk *parent, struct clk *m0,
111 struct clk *m1, struct clk *m2, struct clk *m3)
115 else if (parent == m1)
117 else if (parent == m2)
119 else if (parent == m3)
127 static inline void __iomem *_get_pll_base(struct clk *pll)
129 if (pll == &pll1_main_clk)
130 return MX51_DPLL1_BASE;
131 else if (pll == &pll2_sw_clk)
132 return MX51_DPLL2_BASE;
133 else if (pll == &pll3_sw_clk)
134 return MX51_DPLL3_BASE;
135 else if (pll == &mx53_pll4_sw_clk)
136 return MX53_DPLL4_BASE;
143 static unsigned long clk_pll_get_rate(struct clk *clk)
145 long mfi, mfn, mfd, pdf, ref_clk, mfn_abs;
146 unsigned long dp_op, dp_mfd, dp_mfn, dp_ctl, pll_hfsm, dbl;
147 void __iomem *pllbase;
149 unsigned long parent_rate;
151 parent_rate = clk_get_rate(clk->parent);
153 pllbase = _get_pll_base(clk);
155 dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL);
156 pll_hfsm = dp_ctl & MXC_PLL_DP_CTL_HFSM;
157 dbl = dp_ctl & MXC_PLL_DP_CTL_DPDCK0_2_EN;
160 dp_op = __raw_readl(pllbase + MXC_PLL_DP_OP);
161 dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_MFD);
162 dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_MFN);
164 dp_op = __raw_readl(pllbase + MXC_PLL_DP_HFS_OP);
165 dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFD);
166 dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFN);
168 pdf = dp_op & MXC_PLL_DP_OP_PDF_MASK;
169 mfi = (dp_op & MXC_PLL_DP_OP_MFI_MASK) >> MXC_PLL_DP_OP_MFI_OFFSET;
170 mfi = (mfi <= 5) ? 5 : mfi;
171 mfd = dp_mfd & MXC_PLL_DP_MFD_MASK;
172 mfn = mfn_abs = dp_mfn & MXC_PLL_DP_MFN_MASK;
173 /* Sign extend to 32-bits */
174 if (mfn >= 0x04000000) {
179 ref_clk = 2 * parent_rate;
183 ref_clk /= (pdf + 1);
184 temp = (u64) ref_clk * mfn_abs;
185 do_div(temp, mfd + 1);
188 temp = (ref_clk * mfi) + temp;
193 static int _clk_pll_set_rate(struct clk *clk, unsigned long rate)
196 void __iomem *pllbase;
198 long mfi, pdf, mfn, mfd = 999999;
200 unsigned long quad_parent_rate;
201 unsigned long pll_hfsm, dp_ctl;
202 unsigned long parent_rate;
204 parent_rate = clk_get_rate(clk->parent);
206 pllbase = _get_pll_base(clk);
208 quad_parent_rate = 4 * parent_rate;
210 while (++pdf < 16 && mfi < 5)
211 mfi = rate * (pdf+1) / quad_parent_rate;
216 temp64 = rate * (pdf+1) - quad_parent_rate * mfi;
217 do_div(temp64, quad_parent_rate/1000000);
220 dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL);
222 __raw_writel(dp_ctl | 0x1000L, pllbase + MXC_PLL_DP_CTL);
223 pll_hfsm = dp_ctl & MXC_PLL_DP_CTL_HFSM;
225 reg = mfi << 4 | pdf;
226 __raw_writel(reg, pllbase + MXC_PLL_DP_OP);
227 __raw_writel(mfd, pllbase + MXC_PLL_DP_MFD);
228 __raw_writel(mfn, pllbase + MXC_PLL_DP_MFN);
230 reg = mfi << 4 | pdf;
231 __raw_writel(reg, pllbase + MXC_PLL_DP_HFS_OP);
232 __raw_writel(mfd, pllbase + MXC_PLL_DP_HFS_MFD);
233 __raw_writel(mfn, pllbase + MXC_PLL_DP_HFS_MFN);
239 static int _clk_pll_enable(struct clk *clk)
242 void __iomem *pllbase;
245 pllbase = _get_pll_base(clk);
246 reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) | MXC_PLL_DP_CTL_UPEN;
247 __raw_writel(reg, pllbase + MXC_PLL_DP_CTL);
251 reg = __raw_readl(pllbase + MXC_PLL_DP_CTL);
252 if (reg & MXC_PLL_DP_CTL_LRF)
256 } while (++i < MAX_DPLL_WAIT_TRIES);
258 if (i == MAX_DPLL_WAIT_TRIES) {
259 pr_err("MX5: pll locking failed\n");
266 static void _clk_pll_disable(struct clk *clk)
269 void __iomem *pllbase;
271 pllbase = _get_pll_base(clk);
272 reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) & ~MXC_PLL_DP_CTL_UPEN;
273 __raw_writel(reg, pllbase + MXC_PLL_DP_CTL);
276 static int _clk_pll1_sw_set_parent(struct clk *clk, struct clk *parent)
280 reg = __raw_readl(MXC_CCM_CCSR);
282 /* When switching from pll_main_clk to a bypass clock, first select a
283 * multiplexed clock in 'step_sel', then shift the glitchless mux
286 * When switching back, do it in reverse order
288 if (parent == &pll1_main_clk) {
289 /* Switch to pll1_main_clk */
290 reg &= ~MXC_CCM_CCSR_PLL1_SW_CLK_SEL;
291 __raw_writel(reg, MXC_CCM_CCSR);
292 /* step_clk mux switched to lp_apm, to save power. */
293 reg = __raw_readl(MXC_CCM_CCSR);
294 reg &= ~MXC_CCM_CCSR_STEP_SEL_MASK;
295 reg |= (MXC_CCM_CCSR_STEP_SEL_LP_APM <<
296 MXC_CCM_CCSR_STEP_SEL_OFFSET);
298 if (parent == &lp_apm_clk) {
299 step = MXC_CCM_CCSR_STEP_SEL_LP_APM;
300 } else if (parent == &pll2_sw_clk) {
301 step = MXC_CCM_CCSR_STEP_SEL_PLL2_DIVIDED;
302 } else if (parent == &pll3_sw_clk) {
303 step = MXC_CCM_CCSR_STEP_SEL_PLL3_DIVIDED;
307 reg &= ~MXC_CCM_CCSR_STEP_SEL_MASK;
308 reg |= (step << MXC_CCM_CCSR_STEP_SEL_OFFSET);
310 __raw_writel(reg, MXC_CCM_CCSR);
311 /* Switch to step_clk */
312 reg = __raw_readl(MXC_CCM_CCSR);
313 reg |= MXC_CCM_CCSR_PLL1_SW_CLK_SEL;
315 __raw_writel(reg, MXC_CCM_CCSR);
319 static unsigned long clk_pll1_sw_get_rate(struct clk *clk)
322 unsigned long parent_rate;
324 parent_rate = clk_get_rate(clk->parent);
326 reg = __raw_readl(MXC_CCM_CCSR);
328 if (clk->parent == &pll2_sw_clk) {
329 div = ((reg & MXC_CCM_CCSR_PLL2_PODF_MASK) >>
330 MXC_CCM_CCSR_PLL2_PODF_OFFSET) + 1;
331 } else if (clk->parent == &pll3_sw_clk) {
332 div = ((reg & MXC_CCM_CCSR_PLL3_PODF_MASK) >>
333 MXC_CCM_CCSR_PLL3_PODF_OFFSET) + 1;
336 return parent_rate / div;
339 static int _clk_pll2_sw_set_parent(struct clk *clk, struct clk *parent)
343 reg = __raw_readl(MXC_CCM_CCSR);
345 if (parent == &pll2_sw_clk)
346 reg &= ~MXC_CCM_CCSR_PLL2_SW_CLK_SEL;
348 reg |= MXC_CCM_CCSR_PLL2_SW_CLK_SEL;
350 __raw_writel(reg, MXC_CCM_CCSR);
354 static int _clk_lp_apm_set_parent(struct clk *clk, struct clk *parent)
358 if (parent == &osc_clk)
359 reg = __raw_readl(MXC_CCM_CCSR) & ~MXC_CCM_CCSR_LP_APM_SEL;
363 __raw_writel(reg, MXC_CCM_CCSR);
368 static unsigned long clk_cpu_get_rate(struct clk *clk)
371 unsigned long parent_rate;
373 parent_rate = clk_get_rate(clk->parent);
374 cacrr = __raw_readl(MXC_CCM_CACRR);
375 div = (cacrr & MXC_CCM_CACRR_ARM_PODF_MASK) + 1;
377 return parent_rate / div;
380 static int clk_cpu_set_rate(struct clk *clk, unsigned long rate)
383 unsigned long parent_rate;
385 parent_rate = clk_get_rate(clk->parent);
386 cpu_podf = parent_rate / rate - 1;
387 /* use post divider to change freq */
388 reg = __raw_readl(MXC_CCM_CACRR);
389 reg &= ~MXC_CCM_CACRR_ARM_PODF_MASK;
390 reg |= cpu_podf << MXC_CCM_CACRR_ARM_PODF_OFFSET;
391 __raw_writel(reg, MXC_CCM_CACRR);
396 static int _clk_periph_apm_set_parent(struct clk *clk, struct clk *parent)
401 mux = _get_mux(parent, &pll1_sw_clk, &pll3_sw_clk, &lp_apm_clk, NULL);
403 reg = __raw_readl(MXC_CCM_CBCMR) & ~MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK;
404 reg |= mux << MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET;
405 __raw_writel(reg, MXC_CCM_CBCMR);
409 reg = __raw_readl(MXC_CCM_CDHIPR);
410 if (!(reg & MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY))
414 } while (++i < MAX_DPLL_WAIT_TRIES);
416 if (i == MAX_DPLL_WAIT_TRIES) {
417 pr_err("MX5: Set parent for periph_apm clock failed\n");
424 static int _clk_main_bus_set_parent(struct clk *clk, struct clk *parent)
428 reg = __raw_readl(MXC_CCM_CBCDR);
430 if (parent == &pll2_sw_clk)
431 reg &= ~MXC_CCM_CBCDR_PERIPH_CLK_SEL;
432 else if (parent == &periph_apm_clk)
433 reg |= MXC_CCM_CBCDR_PERIPH_CLK_SEL;
437 __raw_writel(reg, MXC_CCM_CBCDR);
442 static struct clk main_bus_clk = {
443 .parent = &pll2_sw_clk,
444 .set_parent = _clk_main_bus_set_parent,
447 static unsigned long clk_ahb_get_rate(struct clk *clk)
450 unsigned long parent_rate;
452 parent_rate = clk_get_rate(clk->parent);
454 reg = __raw_readl(MXC_CCM_CBCDR);
455 div = ((reg & MXC_CCM_CBCDR_AHB_PODF_MASK) >>
456 MXC_CCM_CBCDR_AHB_PODF_OFFSET) + 1;
457 return parent_rate / div;
461 static int _clk_ahb_set_rate(struct clk *clk, unsigned long rate)
464 unsigned long parent_rate;
467 parent_rate = clk_get_rate(clk->parent);
469 div = parent_rate / rate;
470 if (div > 8 || div < 1 || ((parent_rate / div) != rate))
473 reg = __raw_readl(MXC_CCM_CBCDR);
474 reg &= ~MXC_CCM_CBCDR_AHB_PODF_MASK;
475 reg |= (div - 1) << MXC_CCM_CBCDR_AHB_PODF_OFFSET;
476 __raw_writel(reg, MXC_CCM_CBCDR);
480 reg = __raw_readl(MXC_CCM_CDHIPR);
481 if (!(reg & MXC_CCM_CDHIPR_AHB_PODF_BUSY))
485 } while (++i < MAX_DPLL_WAIT_TRIES);
487 if (i == MAX_DPLL_WAIT_TRIES) {
488 pr_err("MX5: clk_ahb_set_rate failed\n");
495 static unsigned long _clk_ahb_round_rate(struct clk *clk,
499 unsigned long parent_rate;
501 parent_rate = clk_get_rate(clk->parent);
503 div = parent_rate / rate;
508 return parent_rate / div;
512 static int _clk_max_enable(struct clk *clk)
516 _clk_ccgr_enable(clk);
518 /* Handshake with MAX when LPM is entered. */
519 reg = __raw_readl(MXC_CCM_CLPCR);
521 reg &= ~MX51_CCM_CLPCR_BYPASS_MAX_LPM_HS;
522 else if (cpu_is_mx53())
523 reg &= ~MX53_CCM_CLPCR_BYPASS_MAX_LPM_HS;
524 __raw_writel(reg, MXC_CCM_CLPCR);
529 static void _clk_max_disable(struct clk *clk)
533 _clk_ccgr_disable_inwait(clk);
535 /* No Handshake with MAX when LPM is entered as its disabled. */
536 reg = __raw_readl(MXC_CCM_CLPCR);
538 reg |= MX51_CCM_CLPCR_BYPASS_MAX_LPM_HS;
539 else if (cpu_is_mx53())
540 reg &= ~MX53_CCM_CLPCR_BYPASS_MAX_LPM_HS;
541 __raw_writel(reg, MXC_CCM_CLPCR);
544 static unsigned long clk_ipg_get_rate(struct clk *clk)
547 unsigned long parent_rate;
549 parent_rate = clk_get_rate(clk->parent);
551 reg = __raw_readl(MXC_CCM_CBCDR);
552 div = ((reg & MXC_CCM_CBCDR_IPG_PODF_MASK) >>
553 MXC_CCM_CBCDR_IPG_PODF_OFFSET) + 1;
555 return parent_rate / div;
558 static unsigned long clk_ipg_per_get_rate(struct clk *clk)
560 u32 reg, prediv1, prediv2, podf;
561 unsigned long parent_rate;
563 parent_rate = clk_get_rate(clk->parent);
565 if (clk->parent == &main_bus_clk || clk->parent == &lp_apm_clk) {
566 /* the main_bus_clk is the one before the DVFS engine */
567 reg = __raw_readl(MXC_CCM_CBCDR);
568 prediv1 = ((reg & MXC_CCM_CBCDR_PERCLK_PRED1_MASK) >>
569 MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET) + 1;
570 prediv2 = ((reg & MXC_CCM_CBCDR_PERCLK_PRED2_MASK) >>
571 MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET) + 1;
572 podf = ((reg & MXC_CCM_CBCDR_PERCLK_PODF_MASK) >>
573 MXC_CCM_CBCDR_PERCLK_PODF_OFFSET) + 1;
574 return parent_rate / (prediv1 * prediv2 * podf);
575 } else if (clk->parent == &ipg_clk)
581 static int _clk_ipg_per_set_parent(struct clk *clk, struct clk *parent)
585 reg = __raw_readl(MXC_CCM_CBCMR);
587 reg &= ~MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL;
588 reg &= ~MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL;
590 if (parent == &ipg_clk)
591 reg |= MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL;
592 else if (parent == &lp_apm_clk)
593 reg |= MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL;
594 else if (parent != &main_bus_clk)
597 __raw_writel(reg, MXC_CCM_CBCMR);
602 #define clk_nfc_set_parent NULL
604 static unsigned long clk_nfc_get_rate(struct clk *clk)
609 reg = __raw_readl(MXC_CCM_CBCDR);
610 div = ((reg & MXC_CCM_CBCDR_NFC_PODF_MASK) >>
611 MXC_CCM_CBCDR_NFC_PODF_OFFSET) + 1;
612 rate = clk_get_rate(clk->parent) / div;
617 static unsigned long clk_nfc_round_rate(struct clk *clk,
621 unsigned long parent_rate = clk_get_rate(clk->parent);
626 div = parent_rate / rate;
628 if (parent_rate % rate)
634 return parent_rate / div;
638 static int clk_nfc_set_rate(struct clk *clk, unsigned long rate)
642 div = clk_get_rate(clk->parent) / rate;
645 if (((clk_get_rate(clk->parent) / div) != rate) || (div > 8))
648 reg = __raw_readl(MXC_CCM_CBCDR);
649 reg &= ~MXC_CCM_CBCDR_NFC_PODF_MASK;
650 reg |= (div - 1) << MXC_CCM_CBCDR_NFC_PODF_OFFSET;
651 __raw_writel(reg, MXC_CCM_CBCDR);
653 while (__raw_readl(MXC_CCM_CDHIPR) &
654 MXC_CCM_CDHIPR_NFC_IPG_INT_MEM_PODF_BUSY){
660 static unsigned long get_high_reference_clock_rate(struct clk *clk)
662 return external_high_reference;
665 static unsigned long get_low_reference_clock_rate(struct clk *clk)
667 return external_low_reference;
670 static unsigned long get_oscillator_reference_clock_rate(struct clk *clk)
672 return oscillator_reference;
675 static unsigned long get_ckih2_reference_clock_rate(struct clk *clk)
677 return ckih2_reference;
680 static unsigned long clk_emi_slow_get_rate(struct clk *clk)
684 reg = __raw_readl(MXC_CCM_CBCDR);
685 div = ((reg & MXC_CCM_CBCDR_EMI_PODF_MASK) >>
686 MXC_CCM_CBCDR_EMI_PODF_OFFSET) + 1;
688 return clk_get_rate(clk->parent) / div;
691 /* External high frequency clock */
692 static struct clk ckih_clk = {
693 .get_rate = get_high_reference_clock_rate,
696 static struct clk ckih2_clk = {
697 .get_rate = get_ckih2_reference_clock_rate,
700 static struct clk osc_clk = {
701 .get_rate = get_oscillator_reference_clock_rate,
704 /* External low frequency (32kHz) clock */
705 static struct clk ckil_clk = {
706 .get_rate = get_low_reference_clock_rate,
709 static struct clk pll1_main_clk = {
711 .get_rate = clk_pll_get_rate,
712 .enable = _clk_pll_enable,
713 .disable = _clk_pll_disable,
716 /* Clock tree block diagram (WIP):
717 * CCM: Clock Controller Module
720 * | CCM Switcher -> CCM_CLK_ROOT_GEN ->
725 /* PLL1 SW supplies to ARM core */
726 static struct clk pll1_sw_clk = {
727 .parent = &pll1_main_clk,
728 .set_parent = _clk_pll1_sw_set_parent,
729 .get_rate = clk_pll1_sw_get_rate,
732 /* PLL2 SW supplies to AXI/AHB/IP buses */
733 static struct clk pll2_sw_clk = {
735 .get_rate = clk_pll_get_rate,
736 .set_rate = _clk_pll_set_rate,
737 .set_parent = _clk_pll2_sw_set_parent,
738 .enable = _clk_pll_enable,
739 .disable = _clk_pll_disable,
742 /* PLL3 SW supplies to serial clocks like USB, SSI, etc. */
743 static struct clk pll3_sw_clk = {
745 .set_rate = _clk_pll_set_rate,
746 .get_rate = clk_pll_get_rate,
747 .enable = _clk_pll_enable,
748 .disable = _clk_pll_disable,
751 /* PLL4 SW supplies to LVDS Display Bridge(LDB) */
752 static struct clk mx53_pll4_sw_clk = {
754 .set_rate = _clk_pll_set_rate,
755 .enable = _clk_pll_enable,
756 .disable = _clk_pll_disable,
759 /* Low-power Audio Playback Mode clock */
760 static struct clk lp_apm_clk = {
762 .set_parent = _clk_lp_apm_set_parent,
765 static struct clk periph_apm_clk = {
766 .parent = &pll1_sw_clk,
767 .set_parent = _clk_periph_apm_set_parent,
770 static struct clk cpu_clk = {
771 .parent = &pll1_sw_clk,
772 .get_rate = clk_cpu_get_rate,
773 .set_rate = clk_cpu_set_rate,
776 static struct clk ahb_clk = {
777 .parent = &main_bus_clk,
778 .get_rate = clk_ahb_get_rate,
779 .set_rate = _clk_ahb_set_rate,
780 .round_rate = _clk_ahb_round_rate,
783 static struct clk iim_clk = {
785 .enable_reg = MXC_CCM_CCGR0,
786 .enable_shift = MXC_CCM_CCGRx_CG15_OFFSET,
789 /* Main IP interface clock for access to registers */
790 static struct clk ipg_clk = {
792 .get_rate = clk_ipg_get_rate,
795 static struct clk ipg_perclk = {
796 .parent = &lp_apm_clk,
797 .get_rate = clk_ipg_per_get_rate,
798 .set_parent = _clk_ipg_per_set_parent,
801 static struct clk ahb_max_clk = {
803 .enable_reg = MXC_CCM_CCGR0,
804 .enable_shift = MXC_CCM_CCGRx_CG14_OFFSET,
805 .enable = _clk_max_enable,
806 .disable = _clk_max_disable,
809 static struct clk aips_tz1_clk = {
811 .secondary = &ahb_max_clk,
812 .enable_reg = MXC_CCM_CCGR0,
813 .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET,
814 .enable = _clk_ccgr_enable,
815 .disable = _clk_ccgr_disable_inwait,
818 static struct clk aips_tz2_clk = {
820 .secondary = &ahb_max_clk,
821 .enable_reg = MXC_CCM_CCGR0,
822 .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
823 .enable = _clk_ccgr_enable,
824 .disable = _clk_ccgr_disable_inwait,
827 static struct clk gpt_32k_clk = {
832 static struct clk kpp_clk = {
836 static struct clk dummy_clk = {
840 static struct clk emi_slow_clk = {
841 .parent = &pll2_sw_clk,
842 .enable_reg = MXC_CCM_CCGR5,
843 .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET,
844 .enable = _clk_ccgr_enable,
845 .disable = _clk_ccgr_disable_inwait,
846 .get_rate = clk_emi_slow_get_rate,
849 #define DEFINE_CLOCK_CCGR(name, i, er, es, pfx, p, s) \
850 static struct clk name = { \
853 .enable_shift = es, \
854 .get_rate = pfx##_get_rate, \
855 .set_rate = pfx##_set_rate, \
856 .round_rate = pfx##_round_rate, \
857 .set_parent = pfx##_set_parent, \
858 .enable = _clk_ccgr_enable, \
859 .disable = _clk_ccgr_disable, \
864 #define DEFINE_CLOCK_MAX(name, i, er, es, pfx, p, s) \
865 static struct clk name = { \
868 .enable_shift = es, \
869 .get_rate = pfx##_get_rate, \
870 .set_rate = pfx##_set_rate, \
871 .set_parent = pfx##_set_parent, \
872 .enable = _clk_max_enable, \
873 .disable = _clk_max_disable, \
878 #define CLK_GET_RATE(name, nr, bitsname) \
879 static unsigned long clk_##name##_get_rate(struct clk *clk) \
881 u32 reg, pred, podf; \
883 reg = __raw_readl(MXC_CCM_CSCDR##nr); \
884 pred = (reg & MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_MASK) \
885 >> MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_OFFSET; \
886 podf = (reg & MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_MASK) \
887 >> MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_OFFSET; \
889 return DIV_ROUND_CLOSEST(clk_get_rate(clk->parent), \
890 (pred + 1) * (podf + 1)); \
893 #define CLK_SET_PARENT(name, nr, bitsname) \
894 static int clk_##name##_set_parent(struct clk *clk, struct clk *parent) \
898 mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, \
899 &pll3_sw_clk, &lp_apm_clk); \
900 reg = __raw_readl(MXC_CCM_CSCMR##nr) & \
901 ~MXC_CCM_CSCMR##nr##_##bitsname##_CLK_SEL_MASK; \
902 reg |= mux << MXC_CCM_CSCMR##nr##_##bitsname##_CLK_SEL_OFFSET; \
903 __raw_writel(reg, MXC_CCM_CSCMR##nr); \
908 #define CLK_SET_RATE(name, nr, bitsname) \
909 static int clk_##name##_set_rate(struct clk *clk, unsigned long rate) \
911 u32 reg, div, parent_rate; \
912 u32 pre = 0, post = 0; \
914 parent_rate = clk_get_rate(clk->parent); \
915 div = parent_rate / rate; \
917 if ((parent_rate / div) != rate) \
920 __calc_pre_post_dividers(div, &pre, &post, \
921 (MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_MASK >> \
922 MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_OFFSET) + 1, \
923 (MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_MASK >> \
924 MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_OFFSET) + 1);\
926 /* Set sdhc1 clock divider */ \
927 reg = __raw_readl(MXC_CCM_CSCDR##nr) & \
928 ~(MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_MASK \
929 | MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_MASK); \
930 reg |= (post - 1) << \
931 MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_OFFSET; \
932 reg |= (pre - 1) << \
933 MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_OFFSET; \
934 __raw_writel(reg, MXC_CCM_CSCDR##nr); \
940 CLK_GET_RATE(uart, 1, UART)
941 CLK_SET_PARENT(uart, 1, UART)
943 static struct clk uart_root_clk = {
944 .parent = &pll2_sw_clk,
945 .get_rate = clk_uart_get_rate,
946 .set_parent = clk_uart_set_parent,
950 CLK_GET_RATE(usboh3, 1, USBOH3)
951 CLK_SET_PARENT(usboh3, 1, USBOH3)
953 static struct clk usboh3_clk = {
954 .parent = &pll2_sw_clk,
955 .get_rate = clk_usboh3_get_rate,
956 .set_parent = clk_usboh3_set_parent,
960 CLK_GET_RATE(ecspi, 2, CSPI)
961 CLK_SET_PARENT(ecspi, 1, CSPI)
963 static struct clk ecspi_main_clk = {
964 .parent = &pll3_sw_clk,
965 .get_rate = clk_ecspi_get_rate,
966 .set_parent = clk_ecspi_set_parent,
970 CLK_GET_RATE(esdhc1, 1, ESDHC1_MSHC1)
971 CLK_SET_PARENT(esdhc1, 1, ESDHC1_MSHC1)
972 CLK_SET_RATE(esdhc1, 1, ESDHC1_MSHC1)
974 CLK_GET_RATE(esdhc2, 1, ESDHC2_MSHC2)
975 CLK_SET_PARENT(esdhc2, 1, ESDHC2_MSHC2)
976 CLK_SET_RATE(esdhc2, 1, ESDHC2_MSHC2)
978 #define DEFINE_CLOCK_FULL(name, i, er, es, gr, sr, e, d, p, s) \
979 static struct clk name = { \
982 .enable_shift = es, \
991 #define DEFINE_CLOCK(name, i, er, es, gr, sr, p, s) \
992 DEFINE_CLOCK_FULL(name, i, er, es, gr, sr, _clk_ccgr_enable, _clk_ccgr_disable, p, s)
994 /* Shared peripheral bus arbiter */
995 DEFINE_CLOCK(spba_clk, 0, MXC_CCM_CCGR5, MXC_CCM_CCGRx_CG0_OFFSET,
996 NULL, NULL, &ipg_clk, NULL);
999 DEFINE_CLOCK(uart1_ipg_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG3_OFFSET,
1000 NULL, NULL, &ipg_clk, &aips_tz1_clk);
1001 DEFINE_CLOCK(uart2_ipg_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG5_OFFSET,
1002 NULL, NULL, &ipg_clk, &aips_tz1_clk);
1003 DEFINE_CLOCK(uart3_ipg_clk, 2, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG7_OFFSET,
1004 NULL, NULL, &ipg_clk, &spba_clk);
1005 DEFINE_CLOCK(uart1_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG4_OFFSET,
1006 NULL, NULL, &uart_root_clk, &uart1_ipg_clk);
1007 DEFINE_CLOCK(uart2_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG6_OFFSET,
1008 NULL, NULL, &uart_root_clk, &uart2_ipg_clk);
1009 DEFINE_CLOCK(uart3_clk, 2, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG8_OFFSET,
1010 NULL, NULL, &uart_root_clk, &uart3_ipg_clk);
1013 DEFINE_CLOCK(gpt_ipg_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG10_OFFSET,
1014 NULL, NULL, &ipg_clk, NULL);
1015 DEFINE_CLOCK(gpt_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG9_OFFSET,
1016 NULL, NULL, &ipg_clk, &gpt_ipg_clk);
1019 DEFINE_CLOCK(i2c1_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG9_OFFSET,
1020 NULL, NULL, &ipg_clk, NULL);
1021 DEFINE_CLOCK(i2c2_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG10_OFFSET,
1022 NULL, NULL, &ipg_clk, NULL);
1023 DEFINE_CLOCK(hsi2c_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG11_OFFSET,
1024 NULL, NULL, &ipg_clk, NULL);
1027 DEFINE_CLOCK(fec_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG12_OFFSET,
1028 NULL, NULL, &ipg_clk, NULL);
1031 DEFINE_CLOCK_CCGR(nfc_clk, 0, MXC_CCM_CCGR5, MXC_CCM_CCGRx_CG10_OFFSET,
1032 clk_nfc, &emi_slow_clk, NULL);
1035 DEFINE_CLOCK(ssi1_ipg_clk, 0, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG8_OFFSET,
1036 NULL, NULL, &ipg_clk, NULL);
1037 DEFINE_CLOCK(ssi1_clk, 0, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG9_OFFSET,
1038 NULL, NULL, &pll3_sw_clk, &ssi1_ipg_clk);
1039 DEFINE_CLOCK(ssi2_ipg_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG10_OFFSET,
1040 NULL, NULL, &ipg_clk, NULL);
1041 DEFINE_CLOCK(ssi2_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG11_OFFSET,
1042 NULL, NULL, &pll3_sw_clk, &ssi2_ipg_clk);
1045 DEFINE_CLOCK_FULL(ecspi1_ipg_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG9_OFFSET,
1046 NULL, NULL, _clk_ccgr_enable_inrun, _clk_ccgr_disable,
1047 &ipg_clk, &spba_clk);
1048 DEFINE_CLOCK(ecspi1_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG10_OFFSET,
1049 NULL, NULL, &ecspi_main_clk, &ecspi1_ipg_clk);
1050 DEFINE_CLOCK_FULL(ecspi2_ipg_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG11_OFFSET,
1051 NULL, NULL, _clk_ccgr_enable_inrun, _clk_ccgr_disable,
1052 &ipg_clk, &aips_tz2_clk);
1053 DEFINE_CLOCK(ecspi2_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG12_OFFSET,
1054 NULL, NULL, &ecspi_main_clk, &ecspi2_ipg_clk);
1057 DEFINE_CLOCK(cspi_ipg_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG9_OFFSET,
1058 NULL, NULL, &ipg_clk, &aips_tz2_clk);
1059 DEFINE_CLOCK(cspi_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG13_OFFSET,
1060 NULL, NULL, &ipg_clk, &cspi_ipg_clk);
1063 DEFINE_CLOCK(sdma_clk, 1, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG15_OFFSET,
1064 NULL, NULL, &ahb_clk, NULL);
1067 DEFINE_CLOCK_FULL(esdhc1_ipg_clk, 0, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG0_OFFSET,
1068 NULL, NULL, _clk_max_enable, _clk_max_disable, &ipg_clk, NULL);
1069 DEFINE_CLOCK_MAX(esdhc1_clk, 0, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG1_OFFSET,
1070 clk_esdhc1, &pll2_sw_clk, &esdhc1_ipg_clk);
1071 DEFINE_CLOCK_FULL(esdhc2_ipg_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG2_OFFSET,
1072 NULL, NULL, _clk_max_enable, _clk_max_disable, &ipg_clk, NULL);
1073 DEFINE_CLOCK_MAX(esdhc2_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG3_OFFSET,
1074 clk_esdhc2, &pll2_sw_clk, &esdhc2_ipg_clk);
1076 #define _REGISTER_CLOCK(d, n, c) \
1083 static struct clk_lookup mx51_lookups[] = {
1084 _REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk)
1085 _REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk)
1086 _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk)
1087 _REGISTER_CLOCK(NULL, "gpt", gpt_clk)
1088 _REGISTER_CLOCK("fec.0", NULL, fec_clk)
1089 _REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk)
1090 _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk)
1091 _REGISTER_CLOCK("imx-i2c.2", NULL, hsi2c_clk)
1092 _REGISTER_CLOCK("mxc-ehci.0", "usb", usboh3_clk)
1093 _REGISTER_CLOCK("mxc-ehci.0", "usb_ahb", ahb_clk)
1094 _REGISTER_CLOCK("mxc-ehci.1", "usb", usboh3_clk)
1095 _REGISTER_CLOCK("mxc-ehci.1", "usb_ahb", ahb_clk)
1096 _REGISTER_CLOCK("fsl-usb2-udc", "usb", usboh3_clk)
1097 _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", ahb_clk)
1098 _REGISTER_CLOCK("imx-keypad.0", NULL, kpp_clk)
1099 _REGISTER_CLOCK("mxc_nand", NULL, nfc_clk)
1100 _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
1101 _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
1102 _REGISTER_CLOCK("imx-sdma", NULL, sdma_clk)
1103 _REGISTER_CLOCK(NULL, "ckih", ckih_clk)
1104 _REGISTER_CLOCK(NULL, "ckih2", ckih2_clk)
1105 _REGISTER_CLOCK(NULL, "gpt_32k", gpt_32k_clk)
1106 _REGISTER_CLOCK("imx51-ecspi.0", NULL, ecspi1_clk)
1107 _REGISTER_CLOCK("imx51-ecspi.1", NULL, ecspi2_clk)
1108 _REGISTER_CLOCK("imx51-cspi.0", NULL, cspi_clk)
1109 _REGISTER_CLOCK("sdhci-esdhc-imx.0", NULL, esdhc1_clk)
1110 _REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL, esdhc2_clk)
1111 _REGISTER_CLOCK(NULL, "cpu_clk", cpu_clk)
1112 _REGISTER_CLOCK(NULL, "iim_clk", iim_clk)
1113 _REGISTER_CLOCK("imx2-wdt.0", NULL, dummy_clk)
1114 _REGISTER_CLOCK("imx2-wdt.1", NULL, dummy_clk)
1117 static struct clk_lookup mx53_lookups[] = {
1118 _REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk)
1119 _REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk)
1120 _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk)
1121 _REGISTER_CLOCK(NULL, "gpt", gpt_clk)
1122 _REGISTER_CLOCK("fec.0", NULL, fec_clk)
1123 _REGISTER_CLOCK(NULL, "iim_clk", iim_clk)
1126 static void clk_tree_init(void)
1130 ipg_perclk.set_parent(&ipg_perclk, &lp_apm_clk);
1133 * Initialise the IPG PER CLK dividers to 3. IPG_PER_CLK should be at
1134 * 8MHz, its derived from lp_apm.
1136 * FIXME: Verify if true for all boards
1138 reg = __raw_readl(MXC_CCM_CBCDR);
1139 reg &= ~MXC_CCM_CBCDR_PERCLK_PRED1_MASK;
1140 reg &= ~MXC_CCM_CBCDR_PERCLK_PRED2_MASK;
1141 reg &= ~MXC_CCM_CBCDR_PERCLK_PODF_MASK;
1142 reg |= (2 << MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET);
1143 __raw_writel(reg, MXC_CCM_CBCDR);
1146 int __init mx51_clocks_init(unsigned long ckil, unsigned long osc,
1147 unsigned long ckih1, unsigned long ckih2)
1151 external_low_reference = ckil;
1152 external_high_reference = ckih1;
1153 ckih2_reference = ckih2;
1154 oscillator_reference = osc;
1156 for (i = 0; i < ARRAY_SIZE(mx51_lookups); i++)
1157 clkdev_add(&mx51_lookups[i]);
1161 clk_enable(&cpu_clk);
1162 clk_enable(&main_bus_clk);
1164 clk_enable(&iim_clk);
1166 clk_disable(&iim_clk);
1168 /* set the usboh3_clk parent to pll2_sw_clk */
1169 clk_set_parent(&usboh3_clk, &pll2_sw_clk);
1171 /* Set SDHC parents to be PLL2 */
1172 clk_set_parent(&esdhc1_clk, &pll2_sw_clk);
1173 clk_set_parent(&esdhc2_clk, &pll2_sw_clk);
1175 /* set SDHC root clock as 166.25MHZ*/
1176 clk_set_rate(&esdhc1_clk, 166250000);
1177 clk_set_rate(&esdhc2_clk, 166250000);
1180 mxc_timer_init(&gpt_clk, MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR),
1185 int __init mx53_clocks_init(unsigned long ckil, unsigned long osc,
1186 unsigned long ckih1, unsigned long ckih2)
1190 external_low_reference = ckil;
1191 external_high_reference = ckih1;
1192 ckih2_reference = ckih2;
1193 oscillator_reference = osc;
1195 for (i = 0; i < ARRAY_SIZE(mx53_lookups); i++)
1196 clkdev_add(&mx53_lookups[i]);
1200 clk_enable(&cpu_clk);
1201 clk_enable(&main_bus_clk);
1203 clk_enable(&iim_clk);
1205 clk_disable(&iim_clk);
1208 mxc_timer_init(&gpt_clk, MX53_IO_ADDRESS(MX53_GPT1_BASE_ADDR),