arch/arm/mach-mx5/clock-mx51-mx53.c

   1 /*
   2  * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
   3  * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
   4  *
   5  * The code contained herein is licensed under the GNU General Public
   6  * License. You may obtain a copy of the GNU General Public License
   7  * Version 2 or later at the following locations:
   8  *
   9  * http://www.opensource.org/licenses/gpl-license.html
  10  * http://www.gnu.org/copyleft/gpl.html
  11  */
  12
  13 #include <linux/mm.h>
  14 #include <linux/delay.h>
  15 #include <linux/clk.h>
  16 #include <linux/io.h>
  17
  18 #include <asm/clkdev.h>
  19 #include <asm/div64.h>
  20
  21 #include <mach/hardware.h>
  22 #include <mach/common.h>
  23 #include <mach/clock.h>
  24
  25 #include "crm_regs.h"
  26
  27 /* External clock values passed-in by the board code */
  28 static unsigned long external_high_reference, external_low_reference;
  29 static unsigned long oscillator_reference, ckih2_reference;
  30
  31 static struct clk osc_clk;
  32 static struct clk pll1_main_clk;
  33 static struct clk pll1_sw_clk;
  34 static struct clk pll2_sw_clk;
  35 static struct clk pll3_sw_clk;
  36 static struct clk mx53_pll4_sw_clk;
  37 static struct clk lp_apm_clk;
  38 static struct clk periph_apm_clk;
  39 static struct clk ahb_clk;
  40 static struct clk ipg_clk;
  41 static struct clk usboh3_clk;
  42
  43 #define MAX_DPLL_WAIT_TRIES     1000 /* 1000 * udelay(1) = 1ms */
  44
  45 /* calculate best pre and post dividers to get the required divider */
  46 static void __calc_pre_post_dividers(u32 div, u32 *pre, u32 *post,
  47         u32 max_pre, u32 max_post)
  48 {
  49         if (div >= max_pre * max_post) {
  50                 *pre = max_pre;
  51                 *post = max_post;
  52         } else if (div >= max_pre) {
  53                 u32 min_pre, temp_pre, old_err, err;
  54                 min_pre = DIV_ROUND_UP(div, max_post);
  55                 old_err = max_pre;
  56                 for (temp_pre = max_pre; temp_pre >= min_pre; temp_pre--) {
  57                         err = div % temp_pre;
  58                         if (err == 0) {
  59                                 *pre = temp_pre;
  60                                 break;
  61                         }
  62                         err = temp_pre - err;
  63                         if (err < old_err) {
  64                                 old_err = err;
  65                                 *pre = temp_pre;
  66                         }
  67                 }
  68                 *post = DIV_ROUND_UP(div, *pre);
  69         } else {
  70                 *pre = div;
  71                 *post = 1;
  72         }
  73 }
  74
  75 static void _clk_ccgr_setclk(struct clk *clk, unsigned mode)
  76 {
  77         u32 reg = __raw_readl(clk->enable_reg);
  78
  79         reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift);
  80         reg |= mode << clk->enable_shift;
  81
  82         __raw_writel(reg, clk->enable_reg);
  83 }
  84
  85 static int _clk_ccgr_enable(struct clk *clk)
  86 {
  87         _clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_ON);
  88         return 0;
  89 }
  90
  91 static void _clk_ccgr_disable(struct clk *clk)
  92 {
  93         _clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_OFF);
  94 }
  95
  96 static int _clk_ccgr_enable_inrun(struct clk *clk)
  97 {
  98         _clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_IDLE);
  99         return 0;
 100 }
 101
 102 static void _clk_ccgr_disable_inwait(struct clk *clk)
 103 {
 104         _clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_IDLE);
 105 }
 106
 107 /*
 108  * For the 4-to-1 muxed input clock
 109  */
 110 static inline u32 _get_mux(struct clk *parent, struct clk *m0,
 111                            struct clk *m1, struct clk *m2, struct clk *m3)
 112 {
 113         if (parent == m0)
 114                 return 0;
 115         else if (parent == m1)
 116                 return 1;
 117         else if (parent == m2)
 118                 return 2;
 119         else if (parent == m3)
 120                 return 3;
 121         else
 122                 BUG();
 123
 124         return -EINVAL;
 125 }
 126
 127 static inline void __iomem *_get_pll_base(struct clk *pll)
 128 {
 129         if (pll == &pll1_main_clk)
 130                 return MX51_DPLL1_BASE;
 131         else if (pll == &pll2_sw_clk)
 132                 return MX51_DPLL2_BASE;
 133         else if (pll == &pll3_sw_clk)
 134                 return MX51_DPLL3_BASE;
 135         else if (pll == &mx53_pll4_sw_clk)
 136                 return MX53_DPLL4_BASE;
 137         else
 138                 BUG();
 139
 140         return NULL;
 141 }
 142
 143 static unsigned long clk_pll_get_rate(struct clk *clk)
 144 {
 145         long mfi, mfn, mfd, pdf, ref_clk, mfn_abs;
 146         unsigned long dp_op, dp_mfd, dp_mfn, dp_ctl, pll_hfsm, dbl;
 147         void __iomem *pllbase;
 148         s64 temp;
 149         unsigned long parent_rate;
 150
 151         parent_rate = clk_get_rate(clk->parent);
 152
 153         pllbase = _get_pll_base(clk);
 154
 155         dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL);
 156         pll_hfsm = dp_ctl & MXC_PLL_DP_CTL_HFSM;
 157         dbl = dp_ctl & MXC_PLL_DP_CTL_DPDCK0_2_EN;
 158
 159         if (pll_hfsm == 0) {
 160                 dp_op = __raw_readl(pllbase + MXC_PLL_DP_OP);
 161                 dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_MFD);
 162                 dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_MFN);
 163         } else {
 164                 dp_op = __raw_readl(pllbase + MXC_PLL_DP_HFS_OP);
 165                 dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFD);
 166                 dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFN);
 167         }
 168         pdf = dp_op & MXC_PLL_DP_OP_PDF_MASK;
 169         mfi = (dp_op & MXC_PLL_DP_OP_MFI_MASK) >> MXC_PLL_DP_OP_MFI_OFFSET;
 170         mfi = (mfi <= 5) ? 5 : mfi;
 171         mfd = dp_mfd & MXC_PLL_DP_MFD_MASK;
 172         mfn = mfn_abs = dp_mfn & MXC_PLL_DP_MFN_MASK;
 173         /* Sign extend to 32-bits */
 174         if (mfn >= 0x04000000) {
 175                 mfn |= 0xFC000000;
 176                 mfn_abs = -mfn;
 177         }
 178
 179         ref_clk = 2 * parent_rate;
 180         if (dbl != 0)
 181                 ref_clk *= 2;
 182
 183         ref_clk /= (pdf + 1);
 184         temp = (u64) ref_clk * mfn_abs;
 185         do_div(temp, mfd + 1);
 186         if (mfn < 0)
 187                 temp = -temp;
 188         temp = (ref_clk * mfi) + temp;
 189
 190         return temp;
 191 }
 192
 193 static int _clk_pll_set_rate(struct clk *clk, unsigned long rate)
 194 {
 195         u32 reg;
 196         void __iomem *pllbase;
 197
 198         long mfi, pdf, mfn, mfd = 999999;
 199         s64 temp64;
 200         unsigned long quad_parent_rate;
 201         unsigned long pll_hfsm, dp_ctl;
 202         unsigned long parent_rate;
 203
 204         parent_rate = clk_get_rate(clk->parent);
 205
 206         pllbase = _get_pll_base(clk);
 207
 208         quad_parent_rate = 4 * parent_rate;
 209         pdf = mfi = -1;
 210         while (++pdf < 16 && mfi < 5)
 211                 mfi = rate * (pdf+1) / quad_parent_rate;
 212         if (mfi > 15)
 213                 return -EINVAL;
 214         pdf--;
 215
 216         temp64 = rate * (pdf+1) - quad_parent_rate * mfi;
 217         do_div(temp64, quad_parent_rate/1000000);
 218         mfn = (long)temp64;
 219
 220         dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL);
 221         /* use dpdck0_2 */
 222         __raw_writel(dp_ctl | 0x1000L, pllbase + MXC_PLL_DP_CTL);
 223         pll_hfsm = dp_ctl & MXC_PLL_DP_CTL_HFSM;
 224         if (pll_hfsm == 0) {
 225                 reg = mfi << 4 | pdf;
 226                 __raw_writel(reg, pllbase + MXC_PLL_DP_OP);
 227                 __raw_writel(mfd, pllbase + MXC_PLL_DP_MFD);
 228                 __raw_writel(mfn, pllbase + MXC_PLL_DP_MFN);
 229         } else {
 230                 reg = mfi << 4 | pdf;
 231                 __raw_writel(reg, pllbase + MXC_PLL_DP_HFS_OP);
 232                 __raw_writel(mfd, pllbase + MXC_PLL_DP_HFS_MFD);
 233                 __raw_writel(mfn, pllbase + MXC_PLL_DP_HFS_MFN);
 234         }
 235
 236         return 0;
 237 }
 238
 239 static int _clk_pll_enable(struct clk *clk)
 240 {
 241         u32 reg;
 242         void __iomem *pllbase;
 243         int i = 0;
 244
 245         pllbase = _get_pll_base(clk);
 246         reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) | MXC_PLL_DP_CTL_UPEN;
 247         __raw_writel(reg, pllbase + MXC_PLL_DP_CTL);
 248
 249         /* Wait for lock */
 250         do {
 251                 reg = __raw_readl(pllbase + MXC_PLL_DP_CTL);
 252                 if (reg & MXC_PLL_DP_CTL_LRF)
 253                         break;
 254
 255                 udelay(1);
 256         } while (++i < MAX_DPLL_WAIT_TRIES);
 257
 258         if (i == MAX_DPLL_WAIT_TRIES) {
 259                 pr_err("MX5: pll locking failed\n");
 260                 return -EINVAL;
 261         }
 262
 263         return 0;
 264 }
 265
 266 static void _clk_pll_disable(struct clk *clk)
 267 {
 268         u32 reg;
 269         void __iomem *pllbase;
 270
 271         pllbase = _get_pll_base(clk);
 272         reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) & ~MXC_PLL_DP_CTL_UPEN;
 273         __raw_writel(reg, pllbase + MXC_PLL_DP_CTL);
 274 }
 275
 276 static int _clk_pll1_sw_set_parent(struct clk *clk, struct clk *parent)
 277 {
 278         u32 reg, step;
 279
 280         reg = __raw_readl(MXC_CCM_CCSR);
 281
 282         /* When switching from pll_main_clk to a bypass clock, first select a
 283          * multiplexed clock in 'step_sel', then shift the glitchless mux
 284          * 'pll1_sw_clk_sel'.
 285          *
 286          * When switching back, do it in reverse order
 287          */
 288         if (parent == &pll1_main_clk) {
 289                 /* Switch to pll1_main_clk */
 290                 reg &= ~MXC_CCM_CCSR_PLL1_SW_CLK_SEL;
 291                 __raw_writel(reg, MXC_CCM_CCSR);
 292                 /* step_clk mux switched to lp_apm, to save power. */
 293                 reg = __raw_readl(MXC_CCM_CCSR);
 294                 reg &= ~MXC_CCM_CCSR_STEP_SEL_MASK;
 295                 reg |= (MXC_CCM_CCSR_STEP_SEL_LP_APM <<
 296                                 MXC_CCM_CCSR_STEP_SEL_OFFSET);
 297         } else {
 298                 if (parent == &lp_apm_clk) {
 299                         step = MXC_CCM_CCSR_STEP_SEL_LP_APM;
 300                 } else  if (parent == &pll2_sw_clk) {
 301                         step = MXC_CCM_CCSR_STEP_SEL_PLL2_DIVIDED;
 302                 } else  if (parent == &pll3_sw_clk) {
 303                         step = MXC_CCM_CCSR_STEP_SEL_PLL3_DIVIDED;
 304                 } else
 305                         return -EINVAL;
 306
 307                 reg &= ~MXC_CCM_CCSR_STEP_SEL_MASK;
 308                 reg |= (step << MXC_CCM_CCSR_STEP_SEL_OFFSET);
 309
 310                 __raw_writel(reg, MXC_CCM_CCSR);
 311                 /* Switch to step_clk */
 312                 reg = __raw_readl(MXC_CCM_CCSR);
 313                 reg |= MXC_CCM_CCSR_PLL1_SW_CLK_SEL;
 314         }
 315         __raw_writel(reg, MXC_CCM_CCSR);
 316         return 0;
 317 }
 318
 319 static unsigned long clk_pll1_sw_get_rate(struct clk *clk)
 320 {
 321         u32 reg, div;
 322         unsigned long parent_rate;
 323
 324         parent_rate = clk_get_rate(clk->parent);
 325
 326         reg = __raw_readl(MXC_CCM_CCSR);
 327
 328         if (clk->parent == &pll2_sw_clk) {
 329                 div = ((reg & MXC_CCM_CCSR_PLL2_PODF_MASK) >>
 330                        MXC_CCM_CCSR_PLL2_PODF_OFFSET) + 1;
 331         } else if (clk->parent == &pll3_sw_clk) {
 332                 div = ((reg & MXC_CCM_CCSR_PLL3_PODF_MASK) >>
 333                        MXC_CCM_CCSR_PLL3_PODF_OFFSET) + 1;
 334         } else
 335                 div = 1;
 336         return parent_rate / div;
 337 }
 338
 339 static int _clk_pll2_sw_set_parent(struct clk *clk, struct clk *parent)
 340 {
 341         u32 reg;
 342
 343         reg = __raw_readl(MXC_CCM_CCSR);
 344
 345         if (parent == &pll2_sw_clk)
 346                 reg &= ~MXC_CCM_CCSR_PLL2_SW_CLK_SEL;
 347         else
 348                 reg |= MXC_CCM_CCSR_PLL2_SW_CLK_SEL;
 349
 350         __raw_writel(reg, MXC_CCM_CCSR);
 351         return 0;
 352 }
 353
 354 static int _clk_lp_apm_set_parent(struct clk *clk, struct clk *parent)
 355 {
 356         u32 reg;
 357
 358         if (parent == &osc_clk)
 359                 reg = __raw_readl(MXC_CCM_CCSR) & ~MXC_CCM_CCSR_LP_APM_SEL;
 360         else
 361                 return -EINVAL;
 362
 363         __raw_writel(reg, MXC_CCM_CCSR);
 364
 365         return 0;
 366 }
 367
 368 static unsigned long clk_cpu_get_rate(struct clk *clk)
 369 {
 370         u32 cacrr, div;
 371         unsigned long parent_rate;
 372
 373         parent_rate = clk_get_rate(clk->parent);
 374         cacrr = __raw_readl(MXC_CCM_CACRR);
 375         div = (cacrr & MXC_CCM_CACRR_ARM_PODF_MASK) + 1;
 376
 377         return parent_rate / div;
 378 }
 379
 380 static int clk_cpu_set_rate(struct clk *clk, unsigned long rate)
 381 {
 382         u32 reg, cpu_podf;
 383         unsigned long parent_rate;
 384
 385         parent_rate = clk_get_rate(clk->parent);
 386         cpu_podf = parent_rate / rate - 1;
 387         /* use post divider to change freq */
 388         reg = __raw_readl(MXC_CCM_CACRR);
 389         reg &= ~MXC_CCM_CACRR_ARM_PODF_MASK;
 390         reg |= cpu_podf << MXC_CCM_CACRR_ARM_PODF_OFFSET;
 391         __raw_writel(reg, MXC_CCM_CACRR);
 392
 393         return 0;
 394 }
 395
 396 static int _clk_periph_apm_set_parent(struct clk *clk, struct clk *parent)
 397 {
 398         u32 reg, mux;
 399         int i = 0;
 400
 401         mux = _get_mux(parent, &pll1_sw_clk, &pll3_sw_clk, &lp_apm_clk, NULL);
 402
 403         reg = __raw_readl(MXC_CCM_CBCMR) & ~MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK;
 404         reg |= mux << MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET;
 405         __raw_writel(reg, MXC_CCM_CBCMR);
 406
 407         /* Wait for lock */
 408         do {
 409                 reg = __raw_readl(MXC_CCM_CDHIPR);
 410                 if (!(reg &  MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY))
 411                         break;
 412
 413                 udelay(1);
 414         } while (++i < MAX_DPLL_WAIT_TRIES);
 415
 416         if (i == MAX_DPLL_WAIT_TRIES) {
 417                 pr_err("MX5: Set parent for periph_apm clock failed\n");
 418                 return -EINVAL;
 419         }
 420
 421         return 0;
 422 }
 423
 424 static int _clk_main_bus_set_parent(struct clk *clk, struct clk *parent)
 425 {
 426         u32 reg;
 427
 428         reg = __raw_readl(MXC_CCM_CBCDR);
 429
 430         if (parent == &pll2_sw_clk)
 431                 reg &= ~MXC_CCM_CBCDR_PERIPH_CLK_SEL;
 432         else if (parent == &periph_apm_clk)
 433                 reg |= MXC_CCM_CBCDR_PERIPH_CLK_SEL;
 434         else
 435                 return -EINVAL;
 436
 437         __raw_writel(reg, MXC_CCM_CBCDR);
 438
 439         return 0;
 440 }
 441
 442 static struct clk main_bus_clk = {
 443         .parent = &pll2_sw_clk,
 444         .set_parent = _clk_main_bus_set_parent,
 445 };
 446
 447 static unsigned long clk_ahb_get_rate(struct clk *clk)
 448 {
 449         u32 reg, div;
 450         unsigned long parent_rate;
 451
 452         parent_rate = clk_get_rate(clk->parent);
 453
 454         reg = __raw_readl(MXC_CCM_CBCDR);
 455         div = ((reg & MXC_CCM_CBCDR_AHB_PODF_MASK) >>
 456                MXC_CCM_CBCDR_AHB_PODF_OFFSET) + 1;
 457         return parent_rate / div;
 458 }
 459
 460
 461 static int _clk_ahb_set_rate(struct clk *clk, unsigned long rate)
 462 {
 463         u32 reg, div;
 464         unsigned long parent_rate;
 465         int i = 0;
 466
 467         parent_rate = clk_get_rate(clk->parent);
 468
 469         div = parent_rate / rate;
 470         if (div > 8 || div < 1 || ((parent_rate / div) != rate))
 471                 return -EINVAL;
 472
 473         reg = __raw_readl(MXC_CCM_CBCDR);
 474         reg &= ~MXC_CCM_CBCDR_AHB_PODF_MASK;
 475         reg |= (div - 1) << MXC_CCM_CBCDR_AHB_PODF_OFFSET;
 476         __raw_writel(reg, MXC_CCM_CBCDR);
 477
 478         /* Wait for lock */
 479         do {
 480                 reg = __raw_readl(MXC_CCM_CDHIPR);
 481                 if (!(reg & MXC_CCM_CDHIPR_AHB_PODF_BUSY))
 482                         break;
 483
 484                 udelay(1);
 485         } while (++i < MAX_DPLL_WAIT_TRIES);
 486
 487         if (i == MAX_DPLL_WAIT_TRIES) {
 488                 pr_err("MX5: clk_ahb_set_rate failed\n");
 489                 return -EINVAL;
 490         }
 491
 492         return 0;
 493 }
 494
 495 static unsigned long _clk_ahb_round_rate(struct clk *clk,
 496                                                 unsigned long rate)
 497 {
 498         u32 div;
 499         unsigned long parent_rate;
 500
 501         parent_rate = clk_get_rate(clk->parent);
 502
 503         div = parent_rate / rate;
 504         if (div > 8)
 505                 div = 8;
 506         else if (div == 0)
 507                 div++;
 508         return parent_rate / div;
 509 }
 510
 511
 512 static int _clk_max_enable(struct clk *clk)
 513 {
 514         u32 reg;
 515
 516         _clk_ccgr_enable(clk);
 517
 518         /* Handshake with MAX when LPM is entered. */
 519         reg = __raw_readl(MXC_CCM_CLPCR);
 520         if (cpu_is_mx51())
 521                 reg &= ~MX51_CCM_CLPCR_BYPASS_MAX_LPM_HS;
 522         else if (cpu_is_mx53())
 523                 reg &= ~MX53_CCM_CLPCR_BYPASS_MAX_LPM_HS;
 524         __raw_writel(reg, MXC_CCM_CLPCR);
 525
 526         return 0;
 527 }
 528
 529 static void _clk_max_disable(struct clk *clk)
 530 {
 531         u32 reg;
 532
 533         _clk_ccgr_disable_inwait(clk);
 534
 535         /* No Handshake with MAX when LPM is entered as its disabled. */
 536         reg = __raw_readl(MXC_CCM_CLPCR);
 537         if (cpu_is_mx51())
 538                 reg |= MX51_CCM_CLPCR_BYPASS_MAX_LPM_HS;
 539         else if (cpu_is_mx53())
 540                 reg &= ~MX53_CCM_CLPCR_BYPASS_MAX_LPM_HS;
 541         __raw_writel(reg, MXC_CCM_CLPCR);
 542 }
 543
 544 static unsigned long clk_ipg_get_rate(struct clk *clk)
 545 {
 546         u32 reg, div;
 547         unsigned long parent_rate;
 548
 549         parent_rate = clk_get_rate(clk->parent);
 550
 551         reg = __raw_readl(MXC_CCM_CBCDR);
 552         div = ((reg & MXC_CCM_CBCDR_IPG_PODF_MASK) >>
 553                MXC_CCM_CBCDR_IPG_PODF_OFFSET) + 1;
 554
 555         return parent_rate / div;
 556 }
 557
 558 static unsigned long clk_ipg_per_get_rate(struct clk *clk)
 559 {
 560         u32 reg, prediv1, prediv2, podf;
 561         unsigned long parent_rate;
 562
 563         parent_rate = clk_get_rate(clk->parent);
 564
 565         if (clk->parent == &main_bus_clk || clk->parent == &lp_apm_clk) {
 566                 /* the main_bus_clk is the one before the DVFS engine */
 567                 reg = __raw_readl(MXC_CCM_CBCDR);
 568                 prediv1 = ((reg & MXC_CCM_CBCDR_PERCLK_PRED1_MASK) >>
 569                            MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET) + 1;
 570                 prediv2 = ((reg & MXC_CCM_CBCDR_PERCLK_PRED2_MASK) >>
 571                            MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET) + 1;
 572                 podf = ((reg & MXC_CCM_CBCDR_PERCLK_PODF_MASK) >>
 573                         MXC_CCM_CBCDR_PERCLK_PODF_OFFSET) + 1;
 574                 return parent_rate / (prediv1 * prediv2 * podf);
 575         } else if (clk->parent == &ipg_clk)
 576                 return parent_rate;
 577         else
 578                 BUG();
 579 }
 580
 581 static int _clk_ipg_per_set_parent(struct clk *clk, struct clk *parent)
 582 {
 583         u32 reg;
 584
 585         reg = __raw_readl(MXC_CCM_CBCMR);
 586
 587         reg &= ~MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL;
 588         reg &= ~MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL;
 589
 590         if (parent == &ipg_clk)
 591                 reg |= MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL;
 592         else if (parent == &lp_apm_clk)
 593                 reg |= MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL;
 594         else if (parent != &main_bus_clk)
 595                 return -EINVAL;
 596
 597         __raw_writel(reg, MXC_CCM_CBCMR);
 598
 599         return 0;
 600 }
 601
 602 #define clk_nfc_set_parent      NULL
 603
 604 static unsigned long clk_nfc_get_rate(struct clk *clk)
 605 {
 606         unsigned long rate;
 607         u32 reg, div;
 608
 609         reg = __raw_readl(MXC_CCM_CBCDR);
 610         div = ((reg & MXC_CCM_CBCDR_NFC_PODF_MASK) >>
 611                MXC_CCM_CBCDR_NFC_PODF_OFFSET) + 1;
 612         rate = clk_get_rate(clk->parent) / div;
 613         WARN_ON(rate == 0);
 614         return rate;
 615 }
 616
 617 static unsigned long clk_nfc_round_rate(struct clk *clk,
 618                                                 unsigned long rate)
 619 {
 620         u32 div;
 621         unsigned long parent_rate = clk_get_rate(clk->parent);
 622
 623         if (!rate)
 624                 return -EINVAL;
 625
 626         div = parent_rate / rate;
 627
 628         if (parent_rate % rate)
 629                 div++;
 630
 631         if (div > 8)
 632                 return -EINVAL;
 633
 634         return parent_rate / div;
 635
 636 }
 637
 638 static int clk_nfc_set_rate(struct clk *clk, unsigned long rate)
 639 {
 640         u32 reg, div;
 641
 642         div = clk_get_rate(clk->parent) / rate;
 643         if (div == 0)
 644                 div++;
 645         if (((clk_get_rate(clk->parent) / div) != rate) || (div > 8))
 646                 return -EINVAL;
 647
 648         reg = __raw_readl(MXC_CCM_CBCDR);
 649         reg &= ~MXC_CCM_CBCDR_NFC_PODF_MASK;
 650         reg |= (div - 1) << MXC_CCM_CBCDR_NFC_PODF_OFFSET;
 651         __raw_writel(reg, MXC_CCM_CBCDR);
 652
 653         while (__raw_readl(MXC_CCM_CDHIPR) &
 654                         MXC_CCM_CDHIPR_NFC_IPG_INT_MEM_PODF_BUSY){
 655         }
 656
 657         return 0;
 658 }
 659
 660 static unsigned long get_high_reference_clock_rate(struct clk *clk)
 661 {
 662         return external_high_reference;
 663 }
 664
 665 static unsigned long get_low_reference_clock_rate(struct clk *clk)
 666 {
 667         return external_low_reference;
 668 }
 669
 670 static unsigned long get_oscillator_reference_clock_rate(struct clk *clk)
 671 {
 672         return oscillator_reference;
 673 }
 674
 675 static unsigned long get_ckih2_reference_clock_rate(struct clk *clk)
 676 {
 677         return ckih2_reference;
 678 }
 679
 680 static unsigned long clk_emi_slow_get_rate(struct clk *clk)
 681 {
 682         u32 reg, div;
 683
 684         reg = __raw_readl(MXC_CCM_CBCDR);
 685         div = ((reg & MXC_CCM_CBCDR_EMI_PODF_MASK) >>
 686                MXC_CCM_CBCDR_EMI_PODF_OFFSET) + 1;
 687
 688         return clk_get_rate(clk->parent) / div;
 689 }
 690
 691 /* External high frequency clock */
 692 static struct clk ckih_clk = {
 693         .get_rate = get_high_reference_clock_rate,
 694 };
 695
 696 static struct clk ckih2_clk = {
 697         .get_rate = get_ckih2_reference_clock_rate,
 698 };
 699
 700 static struct clk osc_clk = {
 701         .get_rate = get_oscillator_reference_clock_rate,
 702 };
 703
 704 /* External low frequency (32kHz) clock */
 705 static struct clk ckil_clk = {
 706         .get_rate = get_low_reference_clock_rate,
 707 };
 708
 709 static struct clk pll1_main_clk = {
 710         .parent = &osc_clk,
 711         .get_rate = clk_pll_get_rate,
 712         .enable = _clk_pll_enable,
 713         .disable = _clk_pll_disable,
 714 };
 715
 716 /* Clock tree block diagram (WIP):
 717  *      CCM: Clock Controller Module
 718  *
 719  * PLL output -> |
 720  *               | CCM Switcher -> CCM_CLK_ROOT_GEN ->
 721  * PLL bypass -> |
 722  *
 723  */
 724
 725 /* PLL1 SW supplies to ARM core */
 726 static struct clk pll1_sw_clk = {
 727         .parent = &pll1_main_clk,
 728         .set_parent = _clk_pll1_sw_set_parent,
 729         .get_rate = clk_pll1_sw_get_rate,
 730 };
 731
 732 /* PLL2 SW supplies to AXI/AHB/IP buses */
 733 static struct clk pll2_sw_clk = {
 734         .parent = &osc_clk,
 735         .get_rate = clk_pll_get_rate,
 736         .set_rate = _clk_pll_set_rate,
 737         .set_parent = _clk_pll2_sw_set_parent,
 738         .enable = _clk_pll_enable,
 739         .disable = _clk_pll_disable,
 740 };
 741
 742 /* PLL3 SW supplies to serial clocks like USB, SSI, etc. */
 743 static struct clk pll3_sw_clk = {
 744         .parent = &osc_clk,
 745         .set_rate = _clk_pll_set_rate,
 746         .get_rate = clk_pll_get_rate,
 747         .enable = _clk_pll_enable,
 748         .disable = _clk_pll_disable,
 749 };
 750
 751 /* PLL4 SW supplies to LVDS Display Bridge(LDB) */
 752 static struct clk mx53_pll4_sw_clk = {
 753         .parent = &osc_clk,
 754         .set_rate = _clk_pll_set_rate,
 755         .enable = _clk_pll_enable,
 756         .disable = _clk_pll_disable,
 757 };
 758
 759 /* Low-power Audio Playback Mode clock */
 760 static struct clk lp_apm_clk = {
 761         .parent = &osc_clk,
 762         .set_parent = _clk_lp_apm_set_parent,
 763 };
 764
 765 static struct clk periph_apm_clk = {
 766         .parent = &pll1_sw_clk,
 767         .set_parent = _clk_periph_apm_set_parent,
 768 };
 769
 770 static struct clk cpu_clk = {
 771         .parent = &pll1_sw_clk,
 772         .get_rate = clk_cpu_get_rate,
 773         .set_rate = clk_cpu_set_rate,
 774 };
 775
 776 static struct clk ahb_clk = {
 777         .parent = &main_bus_clk,
 778         .get_rate = clk_ahb_get_rate,
 779         .set_rate = _clk_ahb_set_rate,
 780         .round_rate = _clk_ahb_round_rate,
 781 };
 782
 783 static struct clk iim_clk = {
 784         .parent = &ipg_clk,
 785         .enable_reg = MXC_CCM_CCGR0,
 786         .enable_shift = MXC_CCM_CCGRx_CG15_OFFSET,
 787 };
 788
 789 /* Main IP interface clock for access to registers */
 790 static struct clk ipg_clk = {
 791         .parent = &ahb_clk,
 792         .get_rate = clk_ipg_get_rate,
 793 };
 794
 795 static struct clk ipg_perclk = {
 796         .parent = &lp_apm_clk,
 797         .get_rate = clk_ipg_per_get_rate,
 798         .set_parent = _clk_ipg_per_set_parent,
 799 };
 800
 801 static struct clk ahb_max_clk = {
 802         .parent = &ahb_clk,
 803         .enable_reg = MXC_CCM_CCGR0,
 804         .enable_shift = MXC_CCM_CCGRx_CG14_OFFSET,
 805         .enable = _clk_max_enable,
 806         .disable = _clk_max_disable,
 807 };
 808
 809 static struct clk aips_tz1_clk = {
 810         .parent = &ahb_clk,
 811         .secondary = &ahb_max_clk,
 812         .enable_reg = MXC_CCM_CCGR0,
 813         .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET,
 814         .enable = _clk_ccgr_enable,
 815         .disable = _clk_ccgr_disable_inwait,
 816 };
 817
 818 static struct clk aips_tz2_clk = {
 819         .parent = &ahb_clk,
 820         .secondary = &ahb_max_clk,
 821         .enable_reg = MXC_CCM_CCGR0,
 822         .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
 823         .enable = _clk_ccgr_enable,
 824         .disable = _clk_ccgr_disable_inwait,
 825 };
 826
 827 static struct clk gpt_32k_clk = {
 828         .id = 0,
 829         .parent = &ckil_clk,
 830 };
 831
 832 static struct clk kpp_clk = {
 833         .id = 0,
 834 };
 835
 836 static struct clk emi_slow_clk = {
 837         .parent = &pll2_sw_clk,
 838         .enable_reg = MXC_CCM_CCGR5,
 839         .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET,
 840         .enable = _clk_ccgr_enable,
 841         .disable = _clk_ccgr_disable_inwait,
 842         .get_rate = clk_emi_slow_get_rate,
 843 };
 844
 845 #define DEFINE_CLOCK_CCGR(name, i, er, es, pfx, p, s)   \
 846         static struct clk name = {                      \
 847                 .id             = i,                    \
 848                 .enable_reg     = er,                   \
 849                 .enable_shift   = es,                   \
 850                 .get_rate       = pfx##_get_rate,       \
 851                 .set_rate       = pfx##_set_rate,       \
 852                 .round_rate     = pfx##_round_rate,     \
 853                 .set_parent     = pfx##_set_parent,     \
 854                 .enable         = _clk_ccgr_enable,     \
 855                 .disable        = _clk_ccgr_disable,    \
 856                 .parent         = p,                    \
 857                 .secondary      = s,                    \
 858         }
 859
 860 #define DEFINE_CLOCK_MAX(name, i, er, es, pfx, p, s)    \
 861         static struct clk name = {                      \
 862                 .id             = i,                    \
 863                 .enable_reg     = er,                   \
 864                 .enable_shift   = es,                   \
 865                 .get_rate       = pfx##_get_rate,       \
 866                 .set_rate       = pfx##_set_rate,       \
 867                 .set_parent     = pfx##_set_parent,     \
 868                 .enable         = _clk_max_enable,      \
 869                 .disable        = _clk_max_disable,     \
 870                 .parent         = p,                    \
 871                 .secondary      = s,                    \
 872         }
 873
 874 #define CLK_GET_RATE(name, nr, bitsname)                                \
 875 static unsigned long clk_##name##_get_rate(struct clk *clk)             \
 876 {                                                                       \
 877         u32 reg, pred, podf;                                            \
 878                                                                         \
 879         reg = __raw_readl(MXC_CCM_CSCDR##nr);                           \
 880         pred = (reg & MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_MASK)   \
 881                 >> MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_OFFSET;    \
 882         podf = (reg & MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_MASK)   \
 883                 >> MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_OFFSET;    \
 884                                                                         \
 885         return DIV_ROUND_CLOSEST(clk_get_rate(clk->parent),             \
 886                         (pred + 1) * (podf + 1));                       \
 887 }
 888
 889 #define CLK_SET_PARENT(name, nr, bitsname)                              \
 890 static int clk_##name##_set_parent(struct clk *clk, struct clk *parent) \
 891 {                                                                       \
 892         u32 reg, mux;                                                   \
 893                                                                         \
 894         mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk,              \
 895                         &pll3_sw_clk, &lp_apm_clk);                     \
 896         reg = __raw_readl(MXC_CCM_CSCMR##nr) &                          \
 897                 ~MXC_CCM_CSCMR##nr##_##bitsname##_CLK_SEL_MASK;         \
 898         reg |= mux << MXC_CCM_CSCMR##nr##_##bitsname##_CLK_SEL_OFFSET;  \
 899         __raw_writel(reg, MXC_CCM_CSCMR##nr);                           \
 900                                                                         \
 901         return 0;                                                       \
 902 }
 903
 904 #define CLK_SET_RATE(name, nr, bitsname)                                \
 905 static int clk_##name##_set_rate(struct clk *clk, unsigned long rate)   \
 906 {                                                                       \
 907         u32 reg, div, parent_rate;                                      \
 908         u32 pre = 0, post = 0;                                          \
 909                                                                         \
 910         parent_rate = clk_get_rate(clk->parent);                        \
 911         div = parent_rate / rate;                                       \
 912                                                                         \
 913         if ((parent_rate / div) != rate)                                \
 914                 return -EINVAL;                                         \
 915                                                                         \
 916         __calc_pre_post_dividers(div, &pre, &post,                      \
 917                 (MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_MASK >>      \
 918                 MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_OFFSET) + 1,  \
 919                 (MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_MASK >>      \
 920                 MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_OFFSET) + 1);\
 921                                                                         \
 922         /* Set sdhc1 clock divider */                                   \
 923         reg = __raw_readl(MXC_CCM_CSCDR##nr) &                          \
 924                 ~(MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_MASK        \
 925                 | MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_MASK);      \
 926         reg |= (post - 1) <<                                            \
 927                 MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_OFFSET;       \
 928         reg |= (pre - 1) <<                                             \
 929                 MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_OFFSET;       \
 930         __raw_writel(reg, MXC_CCM_CSCDR##nr);                           \
 931                                                                         \
 932         return 0;                                                       \
 933 }
 934
 935 /* UART */
 936 CLK_GET_RATE(uart, 1, UART)
 937 CLK_SET_PARENT(uart, 1, UART)
 938
 939 static struct clk uart_root_clk = {
 940         .parent = &pll2_sw_clk,
 941         .get_rate = clk_uart_get_rate,
 942         .set_parent = clk_uart_set_parent,
 943 };
 944
 945 /* USBOH3 */
 946 CLK_GET_RATE(usboh3, 1, USBOH3)
 947 CLK_SET_PARENT(usboh3, 1, USBOH3)
 948
 949 static struct clk usboh3_clk = {
 950         .parent = &pll2_sw_clk,
 951         .get_rate = clk_usboh3_get_rate,
 952         .set_parent = clk_usboh3_set_parent,
 953 };
 954
 955 /* eCSPI */
 956 CLK_GET_RATE(ecspi, 2, CSPI)
 957 CLK_SET_PARENT(ecspi, 1, CSPI)
 958
 959 static struct clk ecspi_main_clk = {
 960         .parent = &pll3_sw_clk,
 961         .get_rate = clk_ecspi_get_rate,
 962         .set_parent = clk_ecspi_set_parent,
 963 };
 964
 965 /* eSDHC */
 966 CLK_GET_RATE(esdhc1, 1, ESDHC1_MSHC1)
 967 CLK_SET_PARENT(esdhc1, 1, ESDHC1_MSHC1)
 968 CLK_SET_RATE(esdhc1, 1, ESDHC1_MSHC1)
 969
 970 CLK_GET_RATE(esdhc2, 1, ESDHC2_MSHC2)
 971 CLK_SET_PARENT(esdhc2, 1, ESDHC2_MSHC2)
 972 CLK_SET_RATE(esdhc2, 1, ESDHC2_MSHC2)
 973
 974 #define DEFINE_CLOCK_FULL(name, i, er, es, gr, sr, e, d, p, s)          \
 975         static struct clk name = {                                      \
 976                 .id             = i,                                    \
 977                 .enable_reg     = er,                                   \
 978                 .enable_shift   = es,                                   \
 979                 .get_rate       = gr,                                   \
 980                 .set_rate       = sr,                                   \
 981                 .enable         = e,                                    \
 982                 .disable        = d,                                    \
 983                 .parent         = p,                                    \
 984                 .secondary      = s,                                    \
 985         }
 986
 987 #define DEFINE_CLOCK(name, i, er, es, gr, sr, p, s)                     \
 988         DEFINE_CLOCK_FULL(name, i, er, es, gr, sr, _clk_ccgr_enable, _clk_ccgr_disable, p, s)
 989
 990 /* Shared peripheral bus arbiter */
 991 DEFINE_CLOCK(spba_clk, 0, MXC_CCM_CCGR5, MXC_CCM_CCGRx_CG0_OFFSET,
 992         NULL,  NULL, &ipg_clk, NULL);
 993
 994 /* UART */
 995 DEFINE_CLOCK(uart1_ipg_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG3_OFFSET,
 996         NULL,  NULL, &ipg_clk, &aips_tz1_clk);
 997 DEFINE_CLOCK(uart2_ipg_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG5_OFFSET,
 998         NULL,  NULL, &ipg_clk, &aips_tz1_clk);
 999 DEFINE_CLOCK(uart3_ipg_clk, 2, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG7_OFFSET,
1000         NULL,  NULL, &ipg_clk, &spba_clk);
1001 DEFINE_CLOCK(uart1_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG4_OFFSET,
1002         NULL,  NULL, &uart_root_clk, &uart1_ipg_clk);
1003 DEFINE_CLOCK(uart2_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG6_OFFSET,
1004         NULL,  NULL, &uart_root_clk, &uart2_ipg_clk);
1005 DEFINE_CLOCK(uart3_clk, 2, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG8_OFFSET,
1006         NULL,  NULL, &uart_root_clk, &uart3_ipg_clk);
1007
1008 /* GPT */
1009 DEFINE_CLOCK(gpt_ipg_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG10_OFFSET,
1010         NULL,  NULL, &ipg_clk, NULL);
1011 DEFINE_CLOCK(gpt_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG9_OFFSET,
1012         NULL,  NULL, &ipg_clk, &gpt_ipg_clk);
1013
1014 /* I2C */
1015 DEFINE_CLOCK(i2c1_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG9_OFFSET,
1016         NULL, NULL, &ipg_clk, NULL);
1017 DEFINE_CLOCK(i2c2_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG10_OFFSET,
1018         NULL, NULL, &ipg_clk, NULL);
1019 DEFINE_CLOCK(hsi2c_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG11_OFFSET,
1020         NULL, NULL, &ipg_clk, NULL);
1021
1022 /* FEC */
1023 DEFINE_CLOCK(fec_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG12_OFFSET,
1024         NULL,  NULL, &ipg_clk, NULL);
1025
1026 /* NFC */
1027 DEFINE_CLOCK_CCGR(nfc_clk, 0, MXC_CCM_CCGR5, MXC_CCM_CCGRx_CG10_OFFSET,
1028         clk_nfc, &emi_slow_clk, NULL);
1029
1030 /* SSI */
1031 DEFINE_CLOCK(ssi1_ipg_clk, 0, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG8_OFFSET,
1032         NULL, NULL, &ipg_clk, NULL);
1033 DEFINE_CLOCK(ssi1_clk, 0, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG9_OFFSET,
1034         NULL, NULL, &pll3_sw_clk, &ssi1_ipg_clk);
1035 DEFINE_CLOCK(ssi2_ipg_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG10_OFFSET,
1036         NULL, NULL, &ipg_clk, NULL);
1037 DEFINE_CLOCK(ssi2_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG11_OFFSET,
1038         NULL, NULL, &pll3_sw_clk, &ssi2_ipg_clk);
1039
1040 /* eCSPI */
1041 DEFINE_CLOCK_FULL(ecspi1_ipg_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG9_OFFSET,
1042                 NULL, NULL, _clk_ccgr_enable_inrun, _clk_ccgr_disable,
1043                 &ipg_clk, &spba_clk);
1044 DEFINE_CLOCK(ecspi1_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG10_OFFSET,
1045                 NULL, NULL, &ecspi_main_clk, &ecspi1_ipg_clk);
1046 DEFINE_CLOCK_FULL(ecspi2_ipg_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG11_OFFSET,
1047                 NULL, NULL, _clk_ccgr_enable_inrun, _clk_ccgr_disable,
1048                 &ipg_clk, &aips_tz2_clk);
1049 DEFINE_CLOCK(ecspi2_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG12_OFFSET,
1050                 NULL, NULL, &ecspi_main_clk, &ecspi2_ipg_clk);
1051
1052 /* CSPI */
1053 DEFINE_CLOCK(cspi_ipg_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG9_OFFSET,
1054                 NULL, NULL, &ipg_clk, &aips_tz2_clk);
1055 DEFINE_CLOCK(cspi_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG13_OFFSET,
1056                 NULL, NULL, &ipg_clk, &cspi_ipg_clk);
1057
1058 /* SDMA */
1059 DEFINE_CLOCK(sdma_clk, 1, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG15_OFFSET,
1060                 NULL, NULL, &ahb_clk, NULL);
1061
1062 /* eSDHC */
1063 DEFINE_CLOCK_FULL(esdhc1_ipg_clk, 0, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG0_OFFSET,
1064         NULL,  NULL, _clk_max_enable, _clk_max_disable, &ipg_clk, NULL);
1065 DEFINE_CLOCK_MAX(esdhc1_clk, 0, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG1_OFFSET,
1066         clk_esdhc1, &pll2_sw_clk, &esdhc1_ipg_clk);
1067 DEFINE_CLOCK_FULL(esdhc2_ipg_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG2_OFFSET,
1068         NULL,  NULL, _clk_max_enable, _clk_max_disable, &ipg_clk, NULL);
1069 DEFINE_CLOCK_MAX(esdhc2_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG3_OFFSET,
1070         clk_esdhc2, &pll2_sw_clk, &esdhc2_ipg_clk);
1071
1072 #define _REGISTER_CLOCK(d, n, c) \
1073        { \
1074                 .dev_id = d, \
1075                 .con_id = n, \
1076                 .clk = &c,   \
1077        },
1078
1079 static struct clk_lookup mx51_lookups[] = {
1080         _REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk)
1081         _REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk)
1082         _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk)
1083         _REGISTER_CLOCK(NULL, "gpt", gpt_clk)
1084         _REGISTER_CLOCK("fec.0", NULL, fec_clk)
1085         _REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk)
1086         _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk)
1087         _REGISTER_CLOCK("imx-i2c.2", NULL, hsi2c_clk)
1088         _REGISTER_CLOCK("mxc-ehci.0", "usb", usboh3_clk)
1089         _REGISTER_CLOCK("mxc-ehci.0", "usb_ahb", ahb_clk)
1090         _REGISTER_CLOCK("mxc-ehci.1", "usb", usboh3_clk)
1091         _REGISTER_CLOCK("mxc-ehci.1", "usb_ahb", ahb_clk)
1092         _REGISTER_CLOCK("fsl-usb2-udc", "usb", usboh3_clk)
1093         _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", ahb_clk)
1094         _REGISTER_CLOCK("imx-keypad.0", NULL, kpp_clk)
1095         _REGISTER_CLOCK("mxc_nand", NULL, nfc_clk)
1096         _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
1097         _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
1098         _REGISTER_CLOCK("imx-sdma", NULL, sdma_clk)
1099         _REGISTER_CLOCK(NULL, "ckih", ckih_clk)
1100         _REGISTER_CLOCK(NULL, "ckih2", ckih2_clk)
1101         _REGISTER_CLOCK(NULL, "gpt_32k", gpt_32k_clk)
1102         _REGISTER_CLOCK("imx51-ecspi.0", NULL, ecspi1_clk)
1103         _REGISTER_CLOCK("imx51-ecspi.1", NULL, ecspi2_clk)
1104         _REGISTER_CLOCK("imx51-cspi.0", NULL, cspi_clk)
1105         _REGISTER_CLOCK("sdhci-esdhc-imx.0", NULL, esdhc1_clk)
1106         _REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL, esdhc2_clk)
1107         _REGISTER_CLOCK(NULL, "cpu_clk", cpu_clk)
1108         _REGISTER_CLOCK(NULL, "iim_clk", iim_clk)
1109 };
1110
1111 static struct clk_lookup mx53_lookups[] = {
1112         _REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk)
1113         _REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk)
1114         _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk)
1115         _REGISTER_CLOCK(NULL, "gpt", gpt_clk)
1116         _REGISTER_CLOCK("fec.0", NULL, fec_clk)
1117         _REGISTER_CLOCK(NULL, "iim_clk", iim_clk)
1118 };
1119
1120 static void clk_tree_init(void)
1121 {
1122         u32 reg;
1123
1124         ipg_perclk.set_parent(&ipg_perclk, &lp_apm_clk);
1125
1126         /*
1127          * Initialise the IPG PER CLK dividers to 3. IPG_PER_CLK should be at
1128          * 8MHz, its derived from lp_apm.
1129          *
1130          * FIXME: Verify if true for all boards
1131          */
1132         reg = __raw_readl(MXC_CCM_CBCDR);
1133         reg &= ~MXC_CCM_CBCDR_PERCLK_PRED1_MASK;
1134         reg &= ~MXC_CCM_CBCDR_PERCLK_PRED2_MASK;
1135         reg &= ~MXC_CCM_CBCDR_PERCLK_PODF_MASK;
1136         reg |= (2 << MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET);
1137         __raw_writel(reg, MXC_CCM_CBCDR);
1138 }
1139
1140 int __init mx51_clocks_init(unsigned long ckil, unsigned long osc,
1141                         unsigned long ckih1, unsigned long ckih2)
1142 {
1143         int i;
1144
1145         external_low_reference = ckil;
1146         external_high_reference = ckih1;
1147         ckih2_reference = ckih2;
1148         oscillator_reference = osc;
1149
1150         for (i = 0; i < ARRAY_SIZE(mx51_lookups); i++)
1151                 clkdev_add(&mx51_lookups[i]);
1152
1153         clk_tree_init();
1154
1155         clk_enable(&cpu_clk);
1156         clk_enable(&main_bus_clk);
1157
1158         clk_enable(&iim_clk);
1159         mx51_revision();
1160         clk_disable(&iim_clk);
1161
1162         /* set the usboh3_clk parent to pll2_sw_clk */
1163         clk_set_parent(&usboh3_clk, &pll2_sw_clk);
1164
1165         /* Set SDHC parents to be PLL2 */
1166         clk_set_parent(&esdhc1_clk, &pll2_sw_clk);
1167         clk_set_parent(&esdhc2_clk, &pll2_sw_clk);
1168
1169         /* set SDHC root clock as 166.25MHZ*/
1170         clk_set_rate(&esdhc1_clk, 166250000);
1171         clk_set_rate(&esdhc2_clk, 166250000);
1172
1173         /* System timer */
1174         mxc_timer_init(&gpt_clk, MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR),
1175                 MX51_MXC_INT_GPT);
1176         return 0;
1177 }
1178
1179 int __init mx53_clocks_init(unsigned long ckil, unsigned long osc,
1180                         unsigned long ckih1, unsigned long ckih2)
1181 {
1182         int i;
1183
1184         external_low_reference = ckil;
1185         external_high_reference = ckih1;
1186         ckih2_reference = ckih2;
1187         oscillator_reference = osc;
1188
1189         for (i = 0; i < ARRAY_SIZE(mx53_lookups); i++)
1190                 clkdev_add(&mx53_lookups[i]);
1191
1192         clk_tree_init();
1193
1194         clk_enable(&cpu_clk);
1195         clk_enable(&main_bus_clk);
1196
1197         clk_enable(&iim_clk);
1198         mx53_revision();
1199         clk_disable(&iim_clk);
1200
1201         /* System timer */
1202         mxc_timer_init(&gpt_clk, MX53_IO_ADDRESS(MX53_GPT1_BASE_ADDR),
1203                 MX53_INT_GPT);
1204         return 0;
1205 }