2 * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
14 #include <linux/delay.h>
15 #include <linux/clk.h>
18 #include <asm/clkdev.h>
19 #include <asm/div64.h>
21 #include <mach/hardware.h>
22 #include <mach/common.h>
23 #include <mach/clock.h>
27 /* External clock values passed-in by the board code */
28 static unsigned long external_high_reference, external_low_reference;
29 static unsigned long oscillator_reference, ckih2_reference;
31 static struct clk osc_clk;
32 static struct clk pll1_main_clk;
33 static struct clk pll1_sw_clk;
34 static struct clk pll2_sw_clk;
35 static struct clk pll3_sw_clk;
36 static struct clk lp_apm_clk;
37 static struct clk periph_apm_clk;
38 static struct clk ahb_clk;
39 static struct clk ipg_clk;
40 static struct clk usboh3_clk;
42 #define MAX_DPLL_WAIT_TRIES 1000 /* 1000 * udelay(1) = 1ms */
44 /* calculate best pre and post dividers to get the required divider */
45 static void __calc_pre_post_dividers(u32 div, u32 *pre, u32 *post,
46 u32 max_pre, u32 max_post)
48 if (div >= max_pre * max_post) {
51 } else if (div >= max_pre) {
52 u32 min_pre, temp_pre, old_err, err;
53 min_pre = DIV_ROUND_UP(div, max_post);
55 for (temp_pre = max_pre; temp_pre >= min_pre; temp_pre--) {
67 *post = DIV_ROUND_UP(div, *pre);
74 static void _clk_ccgr_setclk(struct clk *clk, unsigned mode)
76 u32 reg = __raw_readl(clk->enable_reg);
78 reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift);
79 reg |= mode << clk->enable_shift;
81 __raw_writel(reg, clk->enable_reg);
84 static int _clk_ccgr_enable(struct clk *clk)
86 _clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_ON);
90 static void _clk_ccgr_disable(struct clk *clk)
92 _clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_OFF);
95 static int _clk_ccgr_enable_inrun(struct clk *clk)
97 _clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_IDLE);
101 static void _clk_ccgr_disable_inwait(struct clk *clk)
103 _clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_IDLE);
107 * For the 4-to-1 muxed input clock
109 static inline u32 _get_mux(struct clk *parent, struct clk *m0,
110 struct clk *m1, struct clk *m2, struct clk *m3)
114 else if (parent == m1)
116 else if (parent == m2)
118 else if (parent == m3)
126 static inline void __iomem *_get_pll_base(struct clk *pll)
128 if (pll == &pll1_main_clk)
129 return MX51_DPLL1_BASE;
130 else if (pll == &pll2_sw_clk)
131 return MX51_DPLL2_BASE;
132 else if (pll == &pll3_sw_clk)
133 return MX51_DPLL3_BASE;
140 static unsigned long clk_pll_get_rate(struct clk *clk)
142 long mfi, mfn, mfd, pdf, ref_clk, mfn_abs;
143 unsigned long dp_op, dp_mfd, dp_mfn, dp_ctl, pll_hfsm, dbl;
144 void __iomem *pllbase;
146 unsigned long parent_rate;
148 parent_rate = clk_get_rate(clk->parent);
150 pllbase = _get_pll_base(clk);
152 dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL);
153 pll_hfsm = dp_ctl & MXC_PLL_DP_CTL_HFSM;
154 dbl = dp_ctl & MXC_PLL_DP_CTL_DPDCK0_2_EN;
157 dp_op = __raw_readl(pllbase + MXC_PLL_DP_OP);
158 dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_MFD);
159 dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_MFN);
161 dp_op = __raw_readl(pllbase + MXC_PLL_DP_HFS_OP);
162 dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFD);
163 dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFN);
165 pdf = dp_op & MXC_PLL_DP_OP_PDF_MASK;
166 mfi = (dp_op & MXC_PLL_DP_OP_MFI_MASK) >> MXC_PLL_DP_OP_MFI_OFFSET;
167 mfi = (mfi <= 5) ? 5 : mfi;
168 mfd = dp_mfd & MXC_PLL_DP_MFD_MASK;
169 mfn = mfn_abs = dp_mfn & MXC_PLL_DP_MFN_MASK;
170 /* Sign extend to 32-bits */
171 if (mfn >= 0x04000000) {
176 ref_clk = 2 * parent_rate;
180 ref_clk /= (pdf + 1);
181 temp = (u64) ref_clk * mfn_abs;
182 do_div(temp, mfd + 1);
185 temp = (ref_clk * mfi) + temp;
190 static int _clk_pll_set_rate(struct clk *clk, unsigned long rate)
193 void __iomem *pllbase;
195 long mfi, pdf, mfn, mfd = 999999;
197 unsigned long quad_parent_rate;
198 unsigned long pll_hfsm, dp_ctl;
199 unsigned long parent_rate;
201 parent_rate = clk_get_rate(clk->parent);
203 pllbase = _get_pll_base(clk);
205 quad_parent_rate = 4 * parent_rate;
207 while (++pdf < 16 && mfi < 5)
208 mfi = rate * (pdf+1) / quad_parent_rate;
213 temp64 = rate * (pdf+1) - quad_parent_rate * mfi;
214 do_div(temp64, quad_parent_rate/1000000);
217 dp_ctl = __raw_readl(pllbase + MXC_PLL_DP_CTL);
219 __raw_writel(dp_ctl | 0x1000L, pllbase + MXC_PLL_DP_CTL);
220 pll_hfsm = dp_ctl & MXC_PLL_DP_CTL_HFSM;
222 reg = mfi << 4 | pdf;
223 __raw_writel(reg, pllbase + MXC_PLL_DP_OP);
224 __raw_writel(mfd, pllbase + MXC_PLL_DP_MFD);
225 __raw_writel(mfn, pllbase + MXC_PLL_DP_MFN);
227 reg = mfi << 4 | pdf;
228 __raw_writel(reg, pllbase + MXC_PLL_DP_HFS_OP);
229 __raw_writel(mfd, pllbase + MXC_PLL_DP_HFS_MFD);
230 __raw_writel(mfn, pllbase + MXC_PLL_DP_HFS_MFN);
236 static int _clk_pll_enable(struct clk *clk)
239 void __iomem *pllbase;
242 pllbase = _get_pll_base(clk);
243 reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) | MXC_PLL_DP_CTL_UPEN;
244 __raw_writel(reg, pllbase + MXC_PLL_DP_CTL);
248 reg = __raw_readl(pllbase + MXC_PLL_DP_CTL);
249 if (reg & MXC_PLL_DP_CTL_LRF)
253 } while (++i < MAX_DPLL_WAIT_TRIES);
255 if (i == MAX_DPLL_WAIT_TRIES) {
256 pr_err("MX5: pll locking failed\n");
263 static void _clk_pll_disable(struct clk *clk)
266 void __iomem *pllbase;
268 pllbase = _get_pll_base(clk);
269 reg = __raw_readl(pllbase + MXC_PLL_DP_CTL) & ~MXC_PLL_DP_CTL_UPEN;
270 __raw_writel(reg, pllbase + MXC_PLL_DP_CTL);
273 static int _clk_pll1_sw_set_parent(struct clk *clk, struct clk *parent)
277 reg = __raw_readl(MXC_CCM_CCSR);
279 /* When switching from pll_main_clk to a bypass clock, first select a
280 * multiplexed clock in 'step_sel', then shift the glitchless mux
283 * When switching back, do it in reverse order
285 if (parent == &pll1_main_clk) {
286 /* Switch to pll1_main_clk */
287 reg &= ~MXC_CCM_CCSR_PLL1_SW_CLK_SEL;
288 __raw_writel(reg, MXC_CCM_CCSR);
289 /* step_clk mux switched to lp_apm, to save power. */
290 reg = __raw_readl(MXC_CCM_CCSR);
291 reg &= ~MXC_CCM_CCSR_STEP_SEL_MASK;
292 reg |= (MXC_CCM_CCSR_STEP_SEL_LP_APM <<
293 MXC_CCM_CCSR_STEP_SEL_OFFSET);
295 if (parent == &lp_apm_clk) {
296 step = MXC_CCM_CCSR_STEP_SEL_LP_APM;
297 } else if (parent == &pll2_sw_clk) {
298 step = MXC_CCM_CCSR_STEP_SEL_PLL2_DIVIDED;
299 } else if (parent == &pll3_sw_clk) {
300 step = MXC_CCM_CCSR_STEP_SEL_PLL3_DIVIDED;
304 reg &= ~MXC_CCM_CCSR_STEP_SEL_MASK;
305 reg |= (step << MXC_CCM_CCSR_STEP_SEL_OFFSET);
307 __raw_writel(reg, MXC_CCM_CCSR);
308 /* Switch to step_clk */
309 reg = __raw_readl(MXC_CCM_CCSR);
310 reg |= MXC_CCM_CCSR_PLL1_SW_CLK_SEL;
312 __raw_writel(reg, MXC_CCM_CCSR);
316 static unsigned long clk_pll1_sw_get_rate(struct clk *clk)
319 unsigned long parent_rate;
321 parent_rate = clk_get_rate(clk->parent);
323 reg = __raw_readl(MXC_CCM_CCSR);
325 if (clk->parent == &pll2_sw_clk) {
326 div = ((reg & MXC_CCM_CCSR_PLL2_PODF_MASK) >>
327 MXC_CCM_CCSR_PLL2_PODF_OFFSET) + 1;
328 } else if (clk->parent == &pll3_sw_clk) {
329 div = ((reg & MXC_CCM_CCSR_PLL3_PODF_MASK) >>
330 MXC_CCM_CCSR_PLL3_PODF_OFFSET) + 1;
333 return parent_rate / div;
336 static int _clk_pll2_sw_set_parent(struct clk *clk, struct clk *parent)
340 reg = __raw_readl(MXC_CCM_CCSR);
342 if (parent == &pll2_sw_clk)
343 reg &= ~MXC_CCM_CCSR_PLL2_SW_CLK_SEL;
345 reg |= MXC_CCM_CCSR_PLL2_SW_CLK_SEL;
347 __raw_writel(reg, MXC_CCM_CCSR);
351 static int _clk_lp_apm_set_parent(struct clk *clk, struct clk *parent)
355 if (parent == &osc_clk)
356 reg = __raw_readl(MXC_CCM_CCSR) & ~MXC_CCM_CCSR_LP_APM_SEL;
360 __raw_writel(reg, MXC_CCM_CCSR);
365 static unsigned long clk_arm_get_rate(struct clk *clk)
368 unsigned long parent_rate;
370 parent_rate = clk_get_rate(clk->parent);
371 cacrr = __raw_readl(MXC_CCM_CACRR);
372 div = (cacrr & MXC_CCM_CACRR_ARM_PODF_MASK) + 1;
374 return parent_rate / div;
377 static int _clk_periph_apm_set_parent(struct clk *clk, struct clk *parent)
382 mux = _get_mux(parent, &pll1_sw_clk, &pll3_sw_clk, &lp_apm_clk, NULL);
384 reg = __raw_readl(MXC_CCM_CBCMR) & ~MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK;
385 reg |= mux << MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET;
386 __raw_writel(reg, MXC_CCM_CBCMR);
390 reg = __raw_readl(MXC_CCM_CDHIPR);
391 if (!(reg & MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY))
395 } while (++i < MAX_DPLL_WAIT_TRIES);
397 if (i == MAX_DPLL_WAIT_TRIES) {
398 pr_err("MX5: Set parent for periph_apm clock failed\n");
405 static int _clk_main_bus_set_parent(struct clk *clk, struct clk *parent)
409 reg = __raw_readl(MXC_CCM_CBCDR);
411 if (parent == &pll2_sw_clk)
412 reg &= ~MXC_CCM_CBCDR_PERIPH_CLK_SEL;
413 else if (parent == &periph_apm_clk)
414 reg |= MXC_CCM_CBCDR_PERIPH_CLK_SEL;
418 __raw_writel(reg, MXC_CCM_CBCDR);
423 static struct clk main_bus_clk = {
424 .parent = &pll2_sw_clk,
425 .set_parent = _clk_main_bus_set_parent,
428 static unsigned long clk_ahb_get_rate(struct clk *clk)
431 unsigned long parent_rate;
433 parent_rate = clk_get_rate(clk->parent);
435 reg = __raw_readl(MXC_CCM_CBCDR);
436 div = ((reg & MXC_CCM_CBCDR_AHB_PODF_MASK) >>
437 MXC_CCM_CBCDR_AHB_PODF_OFFSET) + 1;
438 return parent_rate / div;
442 static int _clk_ahb_set_rate(struct clk *clk, unsigned long rate)
445 unsigned long parent_rate;
448 parent_rate = clk_get_rate(clk->parent);
450 div = parent_rate / rate;
451 if (div > 8 || div < 1 || ((parent_rate / div) != rate))
454 reg = __raw_readl(MXC_CCM_CBCDR);
455 reg &= ~MXC_CCM_CBCDR_AHB_PODF_MASK;
456 reg |= (div - 1) << MXC_CCM_CBCDR_AHB_PODF_OFFSET;
457 __raw_writel(reg, MXC_CCM_CBCDR);
461 reg = __raw_readl(MXC_CCM_CDHIPR);
462 if (!(reg & MXC_CCM_CDHIPR_AHB_PODF_BUSY))
466 } while (++i < MAX_DPLL_WAIT_TRIES);
468 if (i == MAX_DPLL_WAIT_TRIES) {
469 pr_err("MX5: clk_ahb_set_rate failed\n");
476 static unsigned long _clk_ahb_round_rate(struct clk *clk,
480 unsigned long parent_rate;
482 parent_rate = clk_get_rate(clk->parent);
484 div = parent_rate / rate;
489 return parent_rate / div;
493 static int _clk_max_enable(struct clk *clk)
497 _clk_ccgr_enable(clk);
499 /* Handshake with MAX when LPM is entered. */
500 reg = __raw_readl(MXC_CCM_CLPCR);
501 reg &= ~MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS;
502 __raw_writel(reg, MXC_CCM_CLPCR);
507 static void _clk_max_disable(struct clk *clk)
511 _clk_ccgr_disable_inwait(clk);
513 /* No Handshake with MAX when LPM is entered as its disabled. */
514 reg = __raw_readl(MXC_CCM_CLPCR);
515 reg |= MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS;
516 __raw_writel(reg, MXC_CCM_CLPCR);
519 static unsigned long clk_ipg_get_rate(struct clk *clk)
522 unsigned long parent_rate;
524 parent_rate = clk_get_rate(clk->parent);
526 reg = __raw_readl(MXC_CCM_CBCDR);
527 div = ((reg & MXC_CCM_CBCDR_IPG_PODF_MASK) >>
528 MXC_CCM_CBCDR_IPG_PODF_OFFSET) + 1;
530 return parent_rate / div;
533 static unsigned long clk_ipg_per_get_rate(struct clk *clk)
535 u32 reg, prediv1, prediv2, podf;
536 unsigned long parent_rate;
538 parent_rate = clk_get_rate(clk->parent);
540 if (clk->parent == &main_bus_clk || clk->parent == &lp_apm_clk) {
541 /* the main_bus_clk is the one before the DVFS engine */
542 reg = __raw_readl(MXC_CCM_CBCDR);
543 prediv1 = ((reg & MXC_CCM_CBCDR_PERCLK_PRED1_MASK) >>
544 MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET) + 1;
545 prediv2 = ((reg & MXC_CCM_CBCDR_PERCLK_PRED2_MASK) >>
546 MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET) + 1;
547 podf = ((reg & MXC_CCM_CBCDR_PERCLK_PODF_MASK) >>
548 MXC_CCM_CBCDR_PERCLK_PODF_OFFSET) + 1;
549 return parent_rate / (prediv1 * prediv2 * podf);
550 } else if (clk->parent == &ipg_clk)
556 static int _clk_ipg_per_set_parent(struct clk *clk, struct clk *parent)
560 reg = __raw_readl(MXC_CCM_CBCMR);
562 reg &= ~MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL;
563 reg &= ~MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL;
565 if (parent == &ipg_clk)
566 reg |= MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL;
567 else if (parent == &lp_apm_clk)
568 reg |= MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL;
569 else if (parent != &main_bus_clk)
572 __raw_writel(reg, MXC_CCM_CBCMR);
577 #define clk_nfc_set_parent NULL
579 static unsigned long clk_nfc_get_rate(struct clk *clk)
584 reg = __raw_readl(MXC_CCM_CBCDR);
585 div = ((reg & MXC_CCM_CBCDR_NFC_PODF_MASK) >>
586 MXC_CCM_CBCDR_NFC_PODF_OFFSET) + 1;
587 rate = clk_get_rate(clk->parent) / div;
592 static unsigned long clk_nfc_round_rate(struct clk *clk,
596 unsigned long parent_rate = clk_get_rate(clk->parent);
601 div = parent_rate / rate;
603 if (parent_rate % rate)
609 return parent_rate / div;
613 static int clk_nfc_set_rate(struct clk *clk, unsigned long rate)
617 div = clk_get_rate(clk->parent) / rate;
620 if (((clk_get_rate(clk->parent) / div) != rate) || (div > 8))
623 reg = __raw_readl(MXC_CCM_CBCDR);
624 reg &= ~MXC_CCM_CBCDR_NFC_PODF_MASK;
625 reg |= (div - 1) << MXC_CCM_CBCDR_NFC_PODF_OFFSET;
626 __raw_writel(reg, MXC_CCM_CBCDR);
628 while (__raw_readl(MXC_CCM_CDHIPR) &
629 MXC_CCM_CDHIPR_NFC_IPG_INT_MEM_PODF_BUSY){
635 static unsigned long get_high_reference_clock_rate(struct clk *clk)
637 return external_high_reference;
640 static unsigned long get_low_reference_clock_rate(struct clk *clk)
642 return external_low_reference;
645 static unsigned long get_oscillator_reference_clock_rate(struct clk *clk)
647 return oscillator_reference;
650 static unsigned long get_ckih2_reference_clock_rate(struct clk *clk)
652 return ckih2_reference;
655 static unsigned long clk_emi_slow_get_rate(struct clk *clk)
659 reg = __raw_readl(MXC_CCM_CBCDR);
660 div = ((reg & MXC_CCM_CBCDR_EMI_PODF_MASK) >>
661 MXC_CCM_CBCDR_EMI_PODF_OFFSET) + 1;
663 return clk_get_rate(clk->parent) / div;
666 /* External high frequency clock */
667 static struct clk ckih_clk = {
668 .get_rate = get_high_reference_clock_rate,
671 static struct clk ckih2_clk = {
672 .get_rate = get_ckih2_reference_clock_rate,
675 static struct clk osc_clk = {
676 .get_rate = get_oscillator_reference_clock_rate,
679 /* External low frequency (32kHz) clock */
680 static struct clk ckil_clk = {
681 .get_rate = get_low_reference_clock_rate,
684 static struct clk pll1_main_clk = {
686 .get_rate = clk_pll_get_rate,
687 .enable = _clk_pll_enable,
688 .disable = _clk_pll_disable,
691 /* Clock tree block diagram (WIP):
692 * CCM: Clock Controller Module
695 * | CCM Switcher -> CCM_CLK_ROOT_GEN ->
700 /* PLL1 SW supplies to ARM core */
701 static struct clk pll1_sw_clk = {
702 .parent = &pll1_main_clk,
703 .set_parent = _clk_pll1_sw_set_parent,
704 .get_rate = clk_pll1_sw_get_rate,
707 /* PLL2 SW supplies to AXI/AHB/IP buses */
708 static struct clk pll2_sw_clk = {
710 .get_rate = clk_pll_get_rate,
711 .set_rate = _clk_pll_set_rate,
712 .set_parent = _clk_pll2_sw_set_parent,
713 .enable = _clk_pll_enable,
714 .disable = _clk_pll_disable,
717 /* PLL3 SW supplies to serial clocks like USB, SSI, etc. */
718 static struct clk pll3_sw_clk = {
720 .set_rate = _clk_pll_set_rate,
721 .get_rate = clk_pll_get_rate,
722 .enable = _clk_pll_enable,
723 .disable = _clk_pll_disable,
726 /* Low-power Audio Playback Mode clock */
727 static struct clk lp_apm_clk = {
729 .set_parent = _clk_lp_apm_set_parent,
732 static struct clk periph_apm_clk = {
733 .parent = &pll1_sw_clk,
734 .set_parent = _clk_periph_apm_set_parent,
737 static struct clk cpu_clk = {
738 .parent = &pll1_sw_clk,
739 .get_rate = clk_arm_get_rate,
742 static struct clk ahb_clk = {
743 .parent = &main_bus_clk,
744 .get_rate = clk_ahb_get_rate,
745 .set_rate = _clk_ahb_set_rate,
746 .round_rate = _clk_ahb_round_rate,
749 /* Main IP interface clock for access to registers */
750 static struct clk ipg_clk = {
752 .get_rate = clk_ipg_get_rate,
755 static struct clk ipg_perclk = {
756 .parent = &lp_apm_clk,
757 .get_rate = clk_ipg_per_get_rate,
758 .set_parent = _clk_ipg_per_set_parent,
761 static struct clk ahb_max_clk = {
763 .enable_reg = MXC_CCM_CCGR0,
764 .enable_shift = MXC_CCM_CCGRx_CG14_OFFSET,
765 .enable = _clk_max_enable,
766 .disable = _clk_max_disable,
769 static struct clk aips_tz1_clk = {
771 .secondary = &ahb_max_clk,
772 .enable_reg = MXC_CCM_CCGR0,
773 .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET,
774 .enable = _clk_ccgr_enable,
775 .disable = _clk_ccgr_disable_inwait,
778 static struct clk aips_tz2_clk = {
780 .secondary = &ahb_max_clk,
781 .enable_reg = MXC_CCM_CCGR0,
782 .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
783 .enable = _clk_ccgr_enable,
784 .disable = _clk_ccgr_disable_inwait,
787 static struct clk gpt_32k_clk = {
792 static struct clk kpp_clk = {
796 static struct clk emi_slow_clk = {
797 .parent = &pll2_sw_clk,
798 .enable_reg = MXC_CCM_CCGR5,
799 .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET,
800 .enable = _clk_ccgr_enable,
801 .disable = _clk_ccgr_disable_inwait,
802 .get_rate = clk_emi_slow_get_rate,
805 #define DEFINE_CLOCK_CCGR(name, i, er, es, pfx, p, s) \
806 static struct clk name = { \
809 .enable_shift = es, \
810 .get_rate = pfx##_get_rate, \
811 .set_rate = pfx##_set_rate, \
812 .round_rate = pfx##_round_rate, \
813 .set_parent = pfx##_set_parent, \
814 .enable = _clk_ccgr_enable, \
815 .disable = _clk_ccgr_disable, \
820 #define DEFINE_CLOCK_MAX(name, i, er, es, pfx, p, s) \
821 static struct clk name = { \
824 .enable_shift = es, \
825 .get_rate = pfx##_get_rate, \
826 .set_rate = pfx##_set_rate, \
827 .set_parent = pfx##_set_parent, \
828 .enable = _clk_max_enable, \
829 .disable = _clk_max_disable, \
834 #define CLK_GET_RATE(name, nr, bitsname) \
835 static unsigned long clk_##name##_get_rate(struct clk *clk) \
837 u32 reg, pred, podf; \
839 reg = __raw_readl(MXC_CCM_CSCDR##nr); \
840 pred = (reg & MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_MASK) \
841 >> MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_OFFSET; \
842 podf = (reg & MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_MASK) \
843 >> MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_OFFSET; \
845 return DIV_ROUND_CLOSEST(clk_get_rate(clk->parent), \
846 (pred + 1) * (podf + 1)); \
849 #define CLK_SET_PARENT(name, nr, bitsname) \
850 static int clk_##name##_set_parent(struct clk *clk, struct clk *parent) \
854 mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, \
855 &pll3_sw_clk, &lp_apm_clk); \
856 reg = __raw_readl(MXC_CCM_CSCMR##nr) & \
857 ~MXC_CCM_CSCMR##nr##_##bitsname##_CLK_SEL_MASK; \
858 reg |= mux << MXC_CCM_CSCMR##nr##_##bitsname##_CLK_SEL_OFFSET; \
859 __raw_writel(reg, MXC_CCM_CSCMR##nr); \
864 #define CLK_SET_RATE(name, nr, bitsname) \
865 static int clk_##name##_set_rate(struct clk *clk, unsigned long rate) \
867 u32 reg, div, parent_rate; \
868 u32 pre = 0, post = 0; \
870 parent_rate = clk_get_rate(clk->parent); \
871 div = parent_rate / rate; \
873 if ((parent_rate / div) != rate) \
876 __calc_pre_post_dividers(div, &pre, &post, \
877 (MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_MASK >> \
878 MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_OFFSET) + 1, \
879 (MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_MASK >> \
880 MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_OFFSET) + 1);\
882 /* Set sdhc1 clock divider */ \
883 reg = __raw_readl(MXC_CCM_CSCDR##nr) & \
884 ~(MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_MASK \
885 | MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_MASK); \
886 reg |= (post - 1) << \
887 MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PODF_OFFSET; \
888 reg |= (pre - 1) << \
889 MXC_CCM_CSCDR##nr##_##bitsname##_CLK_PRED_OFFSET; \
890 __raw_writel(reg, MXC_CCM_CSCDR##nr); \
896 CLK_GET_RATE(uart, 1, UART)
897 CLK_SET_PARENT(uart, 1, UART)
899 static struct clk uart_root_clk = {
900 .parent = &pll2_sw_clk,
901 .get_rate = clk_uart_get_rate,
902 .set_parent = clk_uart_set_parent,
906 CLK_GET_RATE(usboh3, 1, USBOH3)
907 CLK_SET_PARENT(usboh3, 1, USBOH3)
909 static struct clk usboh3_clk = {
910 .parent = &pll2_sw_clk,
911 .get_rate = clk_usboh3_get_rate,
912 .set_parent = clk_usboh3_set_parent,
916 CLK_GET_RATE(ecspi, 2, CSPI)
917 CLK_SET_PARENT(ecspi, 1, CSPI)
919 static struct clk ecspi_main_clk = {
920 .parent = &pll3_sw_clk,
921 .get_rate = clk_ecspi_get_rate,
922 .set_parent = clk_ecspi_set_parent,
926 CLK_GET_RATE(esdhc1, 1, ESDHC1_MSHC1)
927 CLK_SET_PARENT(esdhc1, 1, ESDHC1_MSHC1)
928 CLK_SET_RATE(esdhc1, 1, ESDHC1_MSHC1)
930 CLK_GET_RATE(esdhc2, 1, ESDHC2_MSHC2)
931 CLK_SET_PARENT(esdhc2, 1, ESDHC2_MSHC2)
932 CLK_SET_RATE(esdhc2, 1, ESDHC2_MSHC2)
934 #define DEFINE_CLOCK_FULL(name, i, er, es, gr, sr, e, d, p, s) \
935 static struct clk name = { \
938 .enable_shift = es, \
947 #define DEFINE_CLOCK(name, i, er, es, gr, sr, p, s) \
948 DEFINE_CLOCK_FULL(name, i, er, es, gr, sr, _clk_ccgr_enable, _clk_ccgr_disable, p, s)
950 /* Shared peripheral bus arbiter */
951 DEFINE_CLOCK(spba_clk, 0, MXC_CCM_CCGR5, MXC_CCM_CCGRx_CG0_OFFSET,
952 NULL, NULL, &ipg_clk, NULL);
955 DEFINE_CLOCK(uart1_ipg_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG3_OFFSET,
956 NULL, NULL, &ipg_clk, &aips_tz1_clk);
957 DEFINE_CLOCK(uart2_ipg_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG5_OFFSET,
958 NULL, NULL, &ipg_clk, &aips_tz1_clk);
959 DEFINE_CLOCK(uart3_ipg_clk, 2, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG7_OFFSET,
960 NULL, NULL, &ipg_clk, &spba_clk);
961 DEFINE_CLOCK(uart1_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG4_OFFSET,
962 NULL, NULL, &uart_root_clk, &uart1_ipg_clk);
963 DEFINE_CLOCK(uart2_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG6_OFFSET,
964 NULL, NULL, &uart_root_clk, &uart2_ipg_clk);
965 DEFINE_CLOCK(uart3_clk, 2, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG8_OFFSET,
966 NULL, NULL, &uart_root_clk, &uart3_ipg_clk);
969 DEFINE_CLOCK(gpt_ipg_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG10_OFFSET,
970 NULL, NULL, &ipg_clk, NULL);
971 DEFINE_CLOCK(gpt_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG9_OFFSET,
972 NULL, NULL, &ipg_clk, &gpt_ipg_clk);
975 DEFINE_CLOCK(i2c1_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG9_OFFSET,
976 NULL, NULL, &ipg_clk, NULL);
977 DEFINE_CLOCK(i2c2_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG10_OFFSET,
978 NULL, NULL, &ipg_clk, NULL);
979 DEFINE_CLOCK(hsi2c_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG11_OFFSET,
980 NULL, NULL, &ipg_clk, NULL);
983 DEFINE_CLOCK(fec_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG12_OFFSET,
984 NULL, NULL, &ipg_clk, NULL);
987 DEFINE_CLOCK_CCGR(nfc_clk, 0, MXC_CCM_CCGR5, MXC_CCM_CCGRx_CG10_OFFSET,
988 clk_nfc, &emi_slow_clk, NULL);
991 DEFINE_CLOCK(ssi1_ipg_clk, 0, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG8_OFFSET,
992 NULL, NULL, &ipg_clk, NULL);
993 DEFINE_CLOCK(ssi1_clk, 0, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG9_OFFSET,
994 NULL, NULL, &pll3_sw_clk, &ssi1_ipg_clk);
995 DEFINE_CLOCK(ssi2_ipg_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG10_OFFSET,
996 NULL, NULL, &ipg_clk, NULL);
997 DEFINE_CLOCK(ssi2_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG11_OFFSET,
998 NULL, NULL, &pll3_sw_clk, &ssi2_ipg_clk);
1001 DEFINE_CLOCK_FULL(ecspi1_ipg_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG9_OFFSET,
1002 NULL, NULL, _clk_ccgr_enable_inrun, _clk_ccgr_disable,
1003 &ipg_clk, &spba_clk);
1004 DEFINE_CLOCK(ecspi1_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG10_OFFSET,
1005 NULL, NULL, &ecspi_main_clk, &ecspi1_ipg_clk);
1006 DEFINE_CLOCK_FULL(ecspi2_ipg_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG11_OFFSET,
1007 NULL, NULL, _clk_ccgr_enable_inrun, _clk_ccgr_disable,
1008 &ipg_clk, &aips_tz2_clk);
1009 DEFINE_CLOCK(ecspi2_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG12_OFFSET,
1010 NULL, NULL, &ecspi_main_clk, &ecspi2_ipg_clk);
1013 DEFINE_CLOCK(cspi_ipg_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG9_OFFSET,
1014 NULL, NULL, &ipg_clk, &aips_tz2_clk);
1015 DEFINE_CLOCK(cspi_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG13_OFFSET,
1016 NULL, NULL, &ipg_clk, &cspi_ipg_clk);
1019 DEFINE_CLOCK(sdma_clk, 1, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG15_OFFSET,
1020 NULL, NULL, &ahb_clk, NULL);
1023 DEFINE_CLOCK_FULL(esdhc1_ipg_clk, 0, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG0_OFFSET,
1024 NULL, NULL, _clk_max_enable, _clk_max_disable, &ipg_clk, NULL);
1025 DEFINE_CLOCK_MAX(esdhc1_clk, 0, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG1_OFFSET,
1026 clk_esdhc1, &pll2_sw_clk, &esdhc1_ipg_clk);
1027 DEFINE_CLOCK_FULL(esdhc2_ipg_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG2_OFFSET,
1028 NULL, NULL, _clk_max_enable, _clk_max_disable, &ipg_clk, NULL);
1029 DEFINE_CLOCK_MAX(esdhc2_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG3_OFFSET,
1030 clk_esdhc2, &pll2_sw_clk, &esdhc2_ipg_clk);
1032 #define _REGISTER_CLOCK(d, n, c) \
1039 static struct clk_lookup lookups[] = {
1040 _REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk)
1041 _REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk)
1042 _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk)
1043 _REGISTER_CLOCK(NULL, "gpt", gpt_clk)
1044 _REGISTER_CLOCK("fec.0", NULL, fec_clk)
1045 _REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk)
1046 _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk)
1047 _REGISTER_CLOCK("imx-i2c.2", NULL, hsi2c_clk)
1048 _REGISTER_CLOCK("mxc-ehci.0", "usb", usboh3_clk)
1049 _REGISTER_CLOCK("mxc-ehci.0", "usb_ahb", ahb_clk)
1050 _REGISTER_CLOCK("mxc-ehci.1", "usb", usboh3_clk)
1051 _REGISTER_CLOCK("mxc-ehci.1", "usb_ahb", ahb_clk)
1052 _REGISTER_CLOCK("fsl-usb2-udc", "usb", usboh3_clk)
1053 _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", ahb_clk)
1054 _REGISTER_CLOCK("imx-keypad.0", NULL, kpp_clk)
1055 _REGISTER_CLOCK("mxc_nand", NULL, nfc_clk)
1056 _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
1057 _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
1058 _REGISTER_CLOCK("imx-sdma", NULL, sdma_clk)
1059 _REGISTER_CLOCK(NULL, "ckih", ckih_clk)
1060 _REGISTER_CLOCK(NULL, "ckih2", ckih2_clk)
1061 _REGISTER_CLOCK(NULL, "gpt_32k", gpt_32k_clk)
1062 _REGISTER_CLOCK("imx51-ecspi.0", NULL, ecspi1_clk)
1063 _REGISTER_CLOCK("imx51-ecspi.1", NULL, ecspi2_clk)
1064 _REGISTER_CLOCK("imx51-cspi.0", NULL, cspi_clk)
1065 _REGISTER_CLOCK("sdhci-esdhc-imx.0", NULL, esdhc1_clk)
1066 _REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL, esdhc2_clk)
1069 static void clk_tree_init(void)
1073 ipg_perclk.set_parent(&ipg_perclk, &lp_apm_clk);
1076 * Initialise the IPG PER CLK dividers to 3. IPG_PER_CLK should be at
1077 * 8MHz, its derived from lp_apm.
1079 * FIXME: Verify if true for all boards
1081 reg = __raw_readl(MXC_CCM_CBCDR);
1082 reg &= ~MXC_CCM_CBCDR_PERCLK_PRED1_MASK;
1083 reg &= ~MXC_CCM_CBCDR_PERCLK_PRED2_MASK;
1084 reg &= ~MXC_CCM_CBCDR_PERCLK_PODF_MASK;
1085 reg |= (2 << MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET);
1086 __raw_writel(reg, MXC_CCM_CBCDR);
1089 int __init mx51_clocks_init(unsigned long ckil, unsigned long osc,
1090 unsigned long ckih1, unsigned long ckih2)
1094 external_low_reference = ckil;
1095 external_high_reference = ckih1;
1096 ckih2_reference = ckih2;
1097 oscillator_reference = osc;
1099 for (i = 0; i < ARRAY_SIZE(lookups); i++)
1100 clkdev_add(&lookups[i]);
1104 clk_enable(&cpu_clk);
1105 clk_enable(&main_bus_clk);
1107 /* set the usboh3_clk parent to pll2_sw_clk */
1108 clk_set_parent(&usboh3_clk, &pll2_sw_clk);
1110 /* Set SDHC parents to be PLL2 */
1111 clk_set_parent(&esdhc1_clk, &pll2_sw_clk);
1112 clk_set_parent(&esdhc2_clk, &pll2_sw_clk);
1114 /* set SDHC root clock as 166.25MHZ*/
1115 clk_set_rate(&esdhc1_clk, 166250000);
1116 clk_set_rate(&esdhc2_clk, 166250000);
1119 mxc_timer_init(&gpt_clk, MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR),