2 * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 #include <linux/types.h>
20 #include <linux/sched.h>
21 #include <linux/delay.h>
23 #include <linux/interrupt.h>
24 #include <linux/irq.h>
25 #include <linux/init.h>
26 #include <linux/input.h>
27 #include <linux/nodemask.h>
28 #include <linux/clk.h>
29 #include <linux/platform_device.h>
30 #include <linux/fsl_devices.h>
31 #include <linux/smsc911x.h>
32 #include <linux/spi/spi.h>
33 #include <linux/spi/flash.h>
34 #include <linux/i2c.h>
35 #include <linux/i2c/pca953x.h>
36 #include <linux/ata.h>
37 #include <linux/mtd/mtd.h>
38 #include <linux/mtd/map.h>
39 #include <linux/mtd/partitions.h>
40 #include <linux/regulator/consumer.h>
41 #include <linux/pmic_external.h>
42 #include <linux/pmic_status.h>
43 #include <linux/ipu.h>
44 #include <linux/mxcfb.h>
45 #include <linux/pwm_backlight.h>
46 #include <linux/fec.h>
47 #include <linux/memblock.h>
48 #include <linux/gpio.h>
49 #include <linux/etherdevice.h>
50 #include <linux/regulator/anatop-regulator.h>
51 #include <linux/regulator/consumer.h>
52 #include <linux/regulator/machine.h>
53 #include <linux/regulator/fixed.h>
55 #include <mach/common.h>
56 #include <mach/hardware.h>
57 #include <mach/mxc_dvfs.h>
58 #include <mach/memory.h>
59 #include <mach/iomux-mx6q.h>
60 #include <mach/imx-uart.h>
61 #include <mach/viv_gpu.h>
62 #include <mach/ahci_sata.h>
63 #include <mach/ipu-v3.h>
64 #include <mach/mxc_hdmi.h>
65 #include <mach/mxc_asrc.h>
66 #include <mach/mipi_dsi.h>
67 #include <mach/mipi_csi2.h>
70 #include <asm/setup.h>
71 #include <asm/mach-types.h>
72 #include <asm/mach/arch.h>
73 #include <asm/mach/time.h>
76 #include "devices-imx6q.h"
78 #include "cpu_op-mx6.h"
80 #define MX6Q_ARM2_LDB_BACKLIGHT IMX_GPIO_NR(1, 9)
81 #define MX6Q_ARM2_ECSPI1_CS0 IMX_GPIO_NR(2, 30)
82 #define MX6Q_ARM2_ECSPI1_CS1 IMX_GPIO_NR(3, 19)
83 #define MX6Q_ARM2_DISP0_PWR IMX_GPIO_NR(3, 24)
84 #define MX6Q_ARM2_DISP0_I2C_EN IMX_GPIO_NR(3, 28)
85 #define MX6Q_ARM2_DISP0_DET_INT IMX_GPIO_NR(3, 31)
86 #define MX6Q_ARM2_DISP0_RESET IMX_GPIO_NR(5, 0)
87 #define MX6Q_ARM2_SD3_CD IMX_GPIO_NR(6, 11)
88 #define MX6Q_ARM2_SD3_WP IMX_GPIO_NR(6, 14)
89 #define MX6Q_ARM2_USB_OTG_PWR IMX_GPIO_NR(3, 22)
90 #define MX6Q_ARM2_MAX7310_1_BASE_ADDR IMX_GPIO_NR(8, 0)
91 #define MX6Q_ARM2_MAX7310_2_BASE_ADDR IMX_GPIO_NR(8, 8)
92 #define MX6Q_ARM2_CAP_TCH_INT IMX_GPIO_NR(3, 31)
94 #define MX6Q_ARM2_IO_EXP_GPIO1(x) \
95 (MX6Q_ARM2_MAX7310_1_BASE_ADDR + (x))
96 #define MX6Q_ARM2_IO_EXP_GPIO2(x) \
97 (MX6Q_ARM2_MAX7310_2_BASE_ADDR + (x))
99 #define MX6Q_ARM2_CAN1_STBY IMX_GPIO_NR(7, 12)
100 #define MX6Q_ARM2_CAN1_EN IMX_GPIO_NR(7, 13)
101 #define MX6Q_ARM2_CAN2_STBY MX6Q_ARM2_IO_EXP_GPIO2(1)
102 #define MX6Q_ARM2_CAN2_EN IMX_GPIO_NR(5, 24)
104 #define MX6Q_SMD_CSI0_RST IMX_GPIO_NR(4, 5)
105 #define MX6Q_SMD_CSI0_PWN IMX_GPIO_NR(5, 23)
107 #define BMCR_PDOWN 0x0800 /* PHY Powerdown */
109 void __init early_console_setup(unsigned long base, struct clk *clk);
110 static struct clk *sata_clk;
111 static int esai_record;
113 static int flexcan_en;
115 extern struct regulator *(*get_cpu_regulator)(void);
116 extern void (*put_cpu_regulator)(void);
117 extern int (*set_cpu_voltage)(u32 volt);
118 extern int mx6_set_cpu_voltage(u32 cpu_volt);
119 static struct regulator *cpu_regulator;
120 static char *gp_reg_id;
122 static iomux_v3_cfg_t mx6q_arm2_pads[] = {
124 /* UART4 for debug */
125 MX6Q_PAD_KEY_COL0__UART4_TXD,
126 MX6Q_PAD_KEY_ROW0__UART4_RXD,
127 /* USB HSIC ports use the same pin with ENET */
128 #ifdef CONFIG_USB_EHCI_ARC_HSIC
129 /* USB H2 strobe/data pin */
130 MX6Q_PAD_RGMII_TX_CTL__USBOH3_H2_STROBE,
131 MX6Q_PAD_RGMII_TXC__USBOH3_H2_DATA,
133 /* USB H3 strobe/data pin */
134 MX6Q_PAD_RGMII_RXC__USBOH3_H3_STROBE,
135 MX6Q_PAD_RGMII_RX_CTL__USBOH3_H3_DATA,
138 MX6Q_PAD_KEY_COL1__ENET_MDIO,
139 MX6Q_PAD_KEY_COL2__ENET_MDC,
140 MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC,
141 MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0,
142 MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1,
143 MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2,
144 MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3,
145 MX6Q_PAD_RGMII_TX_CTL__ENET_RGMII_TX_CTL,
146 MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK,
147 MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC,
148 MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0,
149 MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1,
150 MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2,
151 MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3,
152 MX6Q_PAD_RGMII_RX_CTL__ENET_RGMII_RX_CTL,
155 MX6Q_PAD_GPIO_0__CCM_CLKO,
156 MX6Q_PAD_GPIO_3__CCM_CLKO2,
159 MX6Q_PAD_SD1_CLK__USDHC1_CLK,
160 MX6Q_PAD_SD1_CMD__USDHC1_CMD,
161 MX6Q_PAD_SD1_DAT0__USDHC1_DAT0,
162 MX6Q_PAD_SD1_DAT1__USDHC1_DAT1,
163 MX6Q_PAD_SD1_DAT2__USDHC1_DAT2,
164 MX6Q_PAD_SD1_DAT3__USDHC1_DAT3,
166 MX6Q_PAD_SD2_CLK__USDHC2_CLK,
167 MX6Q_PAD_SD2_CMD__USDHC2_CMD,
168 MX6Q_PAD_SD2_DAT0__USDHC2_DAT0,
169 MX6Q_PAD_SD2_DAT1__USDHC2_DAT1,
170 MX6Q_PAD_SD2_DAT2__USDHC2_DAT2,
171 MX6Q_PAD_SD2_DAT3__USDHC2_DAT3,
173 MX6Q_PAD_SD3_CLK__USDHC3_CLK_50MHZ,
174 MX6Q_PAD_SD3_CMD__USDHC3_CMD_50MHZ,
175 MX6Q_PAD_SD3_DAT0__USDHC3_DAT0_50MHZ,
176 MX6Q_PAD_SD3_DAT1__USDHC3_DAT1_50MHZ,
177 MX6Q_PAD_SD3_DAT2__USDHC3_DAT2_50MHZ,
178 MX6Q_PAD_SD3_DAT3__USDHC3_DAT3_50MHZ,
179 MX6Q_PAD_SD3_DAT4__USDHC3_DAT4_50MHZ,
180 MX6Q_PAD_SD3_DAT5__USDHC3_DAT5_50MHZ,
181 MX6Q_PAD_SD3_DAT6__USDHC3_DAT6_50MHZ,
182 MX6Q_PAD_SD3_DAT7__USDHC3_DAT7_50MHZ,
183 MX6Q_PAD_SD3_RST__USDHC3_RST,
185 MX6Q_PAD_GPIO_18__USDHC3_VSELECT,
186 /* SD3_CD and SD3_WP */
187 MX6Q_PAD_NANDF_CS0__GPIO_6_11,
188 MX6Q_PAD_NANDF_CS1__GPIO_6_14,
190 MX6Q_PAD_SD4_CLK__USDHC4_CLK_50MHZ,
191 MX6Q_PAD_SD4_CMD__USDHC4_CMD_50MHZ,
192 MX6Q_PAD_SD4_DAT0__USDHC4_DAT0_50MHZ,
193 MX6Q_PAD_SD4_DAT1__USDHC4_DAT1_50MHZ,
194 MX6Q_PAD_SD4_DAT2__USDHC4_DAT2_50MHZ,
195 MX6Q_PAD_SD4_DAT3__USDHC4_DAT3_50MHZ,
196 MX6Q_PAD_SD4_DAT4__USDHC4_DAT4_50MHZ,
197 MX6Q_PAD_SD4_DAT5__USDHC4_DAT5_50MHZ,
198 MX6Q_PAD_SD4_DAT6__USDHC4_DAT6_50MHZ,
199 MX6Q_PAD_SD4_DAT7__USDHC4_DAT7_50MHZ,
200 MX6Q_PAD_NANDF_ALE__USDHC4_RST,
202 MX6Q_PAD_EIM_EB2__ECSPI1_SS0,
203 MX6Q_PAD_EIM_D16__ECSPI1_SCLK,
204 MX6Q_PAD_EIM_D17__ECSPI1_MISO,
205 MX6Q_PAD_EIM_D18__ECSPI1_MOSI,
206 MX6Q_PAD_EIM_D19__ECSPI1_SS1,
207 MX6Q_PAD_EIM_EB2__GPIO_2_30, /*SS0*/
208 MX6Q_PAD_EIM_D19__GPIO_3_19, /*SS1*/
211 MX6Q_PAD_ENET_RXD0__ESAI1_HCKT,
212 MX6Q_PAD_ENET_CRS_DV__ESAI1_SCKT,
213 MX6Q_PAD_ENET_RXD1__ESAI1_FST,
214 MX6Q_PAD_ENET_TX_EN__ESAI1_TX3_RX2,
215 MX6Q_PAD_ENET_TXD1__ESAI1_TX2_RX3,
216 MX6Q_PAD_ENET_TXD0__ESAI1_TX4_RX1,
217 MX6Q_PAD_ENET_MDC__ESAI1_TX5_RX0,
218 MX6Q_PAD_NANDF_CS2__ESAI1_TX0,
219 MX6Q_PAD_NANDF_CS3__ESAI1_TX1,
222 MX6Q_PAD_CSI0_DAT8__I2C1_SDA,
223 MX6Q_PAD_CSI0_DAT9__I2C1_SCL,
226 MX6Q_PAD_KEY_COL3__I2C2_SCL,
227 MX6Q_PAD_KEY_ROW3__I2C2_SDA,
230 MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,
231 MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15,
232 MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2,
233 MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3,
234 MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0,
235 MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1,
236 MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2,
237 MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3,
238 MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4,
239 MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5,
240 MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6,
241 MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7,
242 MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8,
243 MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9,
244 MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10,
245 MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11,
246 MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12,
247 MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13,
248 MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14,
249 MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15,
250 MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16,
251 MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17,
252 MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18,
253 MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19,
254 MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20,
255 MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21,
256 MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22,
257 MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23,
259 MX6Q_PAD_EIM_D24__GPIO_3_24,
262 MX6Q_PAD_EIM_D26__UART2_RXD,
263 MX6Q_PAD_EIM_D27__UART2_TXD,
264 MX6Q_PAD_EIM_D28__UART2_RTS,
265 MX6Q_PAD_EIM_D29__UART2_CTS,
268 MX6Q_PAD_GPIO_9__PWM1_PWMO,
271 MX6Q_PAD_EIM_D31__GPIO_3_31,
274 MX6Q_PAD_EIM_WAIT__GPIO_5_0,
277 MX6Q_PAD_EIM_A25__HDMI_TX_CEC_LINE,
278 MX6Q_PAD_SD1_DAT1__HDMI_TX_OPHYDTB_0,
279 MX6Q_PAD_SD1_DAT0__HDMI_TX_OPHYDTB_1,
282 MX6Q_PAD_GPIO_1__USBOTG_ID,
285 static iomux_v3_cfg_t mx6q_arm2_i2c3_pads[] = {
286 MX6Q_PAD_GPIO_5__I2C3_SCL,
287 MX6Q_PAD_GPIO_16__I2C3_SDA,
290 static iomux_v3_cfg_t mx6q_arm2_spdif_pads[] = {
292 MX6Q_PAD_GPIO_16__SPDIF_IN1,
293 MX6Q_PAD_GPIO_17__SPDIF_OUT1,
296 static iomux_v3_cfg_t mx6q_arm2_can_pads[] = {
298 MX6Q_PAD_GPIO_7__CAN1_TXCAN,
299 MX6Q_PAD_KEY_ROW2__CAN1_RXCAN,
300 MX6Q_PAD_GPIO_17__GPIO_7_12, /* CAN1 STBY */
301 MX6Q_PAD_GPIO_18__GPIO_7_13, /* CAN1 EN */
304 MX6Q_PAD_KEY_COL4__CAN2_TXCAN,
305 MX6Q_PAD_KEY_ROW4__CAN2_RXCAN,
306 MX6Q_PAD_CSI0_DAT6__GPIO_5_24, /* CAN2 EN */
309 static iomux_v3_cfg_t mx6q_arm2_esai_record_pads[] = {
310 MX6Q_PAD_ENET_RX_ER__ESAI1_HCKR,
311 MX6Q_PAD_ENET_MDIO__ESAI1_SCKR,
312 MX6Q_PAD_ENET_REF_CLK__ESAI1_FSR,
315 static iomux_v3_cfg_t mx6q_arm2_csi0_sensor_pads[] = {
316 MX6Q_PAD_GPIO_0__CCM_CLKO,
318 MX6Q_PAD_CSI0_DAT12__IPU1_CSI0_D_12,
319 MX6Q_PAD_CSI0_DAT13__IPU1_CSI0_D_13,
320 MX6Q_PAD_CSI0_DAT14__IPU1_CSI0_D_14,
321 MX6Q_PAD_CSI0_DAT15__IPU1_CSI0_D_15,
322 MX6Q_PAD_CSI0_DAT16__IPU1_CSI0_D_16,
323 MX6Q_PAD_CSI0_DAT17__IPU1_CSI0_D_17,
324 MX6Q_PAD_CSI0_DAT18__IPU1_CSI0_D_18,
325 MX6Q_PAD_CSI0_DAT19__IPU1_CSI0_D_19,
326 MX6Q_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC,
327 MX6Q_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC,
328 MX6Q_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK,
330 MX6Q_PAD_GPIO_19__GPIO_4_5,
331 /* camera powerdown */
332 MX6Q_PAD_CSI0_DAT5__GPIO_5_23,
335 static iomux_v3_cfg_t mx6q_arm2_mipi_sensor_pads[] = {
336 MX6Q_PAD_CSI0_MCLK__CCM_CLKO,
339 #define MX6Q_USDHC_PAD_SETTING(id, speed) \
340 mx6q_sd##id##_##speed##mhz[] = { \
341 MX6Q_PAD_SD##id##_CLK__USDHC##id##_CLK_##speed##MHZ, \
342 MX6Q_PAD_SD##id##_CMD__USDHC##id##_CMD_##speed##MHZ, \
343 MX6Q_PAD_SD##id##_DAT0__USDHC##id##_DAT0_##speed##MHZ, \
344 MX6Q_PAD_SD##id##_DAT1__USDHC##id##_DAT1_##speed##MHZ, \
345 MX6Q_PAD_SD##id##_DAT2__USDHC##id##_DAT2_##speed##MHZ, \
346 MX6Q_PAD_SD##id##_DAT3__USDHC##id##_DAT3_##speed##MHZ, \
347 MX6Q_PAD_SD##id##_DAT4__USDHC##id##_DAT4_##speed##MHZ, \
348 MX6Q_PAD_SD##id##_DAT5__USDHC##id##_DAT5_##speed##MHZ, \
349 MX6Q_PAD_SD##id##_DAT6__USDHC##id##_DAT6_##speed##MHZ, \
350 MX6Q_PAD_SD##id##_DAT7__USDHC##id##_DAT7_##speed##MHZ, \
353 static iomux_v3_cfg_t MX6Q_USDHC_PAD_SETTING(3, 50);
354 static iomux_v3_cfg_t MX6Q_USDHC_PAD_SETTING(3, 100);
355 static iomux_v3_cfg_t MX6Q_USDHC_PAD_SETTING(3, 200);
356 static iomux_v3_cfg_t MX6Q_USDHC_PAD_SETTING(4, 50);
357 static iomux_v3_cfg_t MX6Q_USDHC_PAD_SETTING(4, 100);
358 static iomux_v3_cfg_t MX6Q_USDHC_PAD_SETTING(4, 200);
361 SD_PAD_MODE_LOW_SPEED,
362 SD_PAD_MODE_MED_SPEED,
363 SD_PAD_MODE_HIGH_SPEED,
366 static int plt_sd3_pad_change(int clock)
368 static enum sd_pad_mode pad_mode = SD_PAD_MODE_LOW_SPEED;
370 if (clock > 100000000) {
371 if (pad_mode == SD_PAD_MODE_HIGH_SPEED)
374 pad_mode = SD_PAD_MODE_HIGH_SPEED;
375 return mxc_iomux_v3_setup_multiple_pads(mx6q_sd3_200mhz,
376 ARRAY_SIZE(mx6q_sd3_200mhz));
377 } else if (clock > 52000000) {
378 if (pad_mode == SD_PAD_MODE_MED_SPEED)
381 pad_mode = SD_PAD_MODE_MED_SPEED;
382 return mxc_iomux_v3_setup_multiple_pads(mx6q_sd3_100mhz,
383 ARRAY_SIZE(mx6q_sd3_100mhz));
385 if (pad_mode == SD_PAD_MODE_LOW_SPEED)
388 pad_mode = SD_PAD_MODE_LOW_SPEED;
389 return mxc_iomux_v3_setup_multiple_pads(mx6q_sd3_50mhz,
390 ARRAY_SIZE(mx6q_sd3_50mhz));
394 static int plt_sd4_pad_change(int clock)
396 static enum sd_pad_mode pad_mode = SD_PAD_MODE_LOW_SPEED;
398 if (clock > 100000000) {
399 if (pad_mode == SD_PAD_MODE_HIGH_SPEED)
402 pad_mode = SD_PAD_MODE_HIGH_SPEED;
403 return mxc_iomux_v3_setup_multiple_pads(mx6q_sd4_200mhz,
404 ARRAY_SIZE(mx6q_sd4_200mhz));
405 } else if (clock > 52000000) {
406 if (pad_mode == SD_PAD_MODE_MED_SPEED)
409 pad_mode = SD_PAD_MODE_MED_SPEED;
410 return mxc_iomux_v3_setup_multiple_pads(mx6q_sd4_100mhz,
411 ARRAY_SIZE(mx6q_sd4_100mhz));
413 if (pad_mode == SD_PAD_MODE_LOW_SPEED)
416 pad_mode = SD_PAD_MODE_LOW_SPEED;
417 return mxc_iomux_v3_setup_multiple_pads(mx6q_sd4_50mhz,
418 ARRAY_SIZE(mx6q_sd4_50mhz));
422 static const struct esdhc_platform_data mx6q_arm2_sd3_data __initconst = {
423 .cd_gpio = MX6Q_ARM2_SD3_CD,
424 .wp_gpio = MX6Q_ARM2_SD3_WP,
427 .keep_power_at_suspend = 1,
429 .platform_pad_change = plt_sd3_pad_change,
432 /* No card detect signal for SD4 */
433 static const struct esdhc_platform_data mx6q_arm2_sd4_data __initconst = {
436 .keep_power_at_suspend = 1,
437 .platform_pad_change = plt_sd4_pad_change,
440 /* The GPMI is conflicted with SD3, so init this in the driver. */
441 static iomux_v3_cfg_t mx6q_gpmi_nand[] __initdata = {
442 MX6Q_PAD_NANDF_CLE__RAWNAND_CLE,
443 MX6Q_PAD_NANDF_ALE__RAWNAND_ALE,
444 MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N,
445 MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N,
446 MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N,
447 MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N,
448 MX6Q_PAD_NANDF_RB0__RAWNAND_READY0,
449 MX6Q_PAD_SD4_DAT0__RAWNAND_DQS,
450 MX6Q_PAD_NANDF_D0__RAWNAND_D0,
451 MX6Q_PAD_NANDF_D1__RAWNAND_D1,
452 MX6Q_PAD_NANDF_D2__RAWNAND_D2,
453 MX6Q_PAD_NANDF_D3__RAWNAND_D3,
454 MX6Q_PAD_NANDF_D4__RAWNAND_D4,
455 MX6Q_PAD_NANDF_D5__RAWNAND_D5,
456 MX6Q_PAD_NANDF_D6__RAWNAND_D6,
457 MX6Q_PAD_NANDF_D7__RAWNAND_D7,
458 MX6Q_PAD_SD4_CMD__RAWNAND_RDN,
459 MX6Q_PAD_SD4_CLK__RAWNAND_WRN,
460 MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN,
463 static int gpmi_nfc_platform_init(void)
465 return mxc_iomux_v3_setup_multiple_pads(mx6q_gpmi_nand,
466 ARRAY_SIZE(mx6q_gpmi_nand));
469 static const struct gpmi_nfc_platform_data
470 mx6q_gpmi_nfc_platform_data __initconst = {
471 .platform_init = gpmi_nfc_platform_init,
472 .min_prop_delay_in_ns = 5,
473 .max_prop_delay_in_ns = 9,
477 static const struct anatop_thermal_platform_data
478 mx6q_arm2_anatop_thermal_data __initconst = {
479 .name = "anatop_thermal",
482 static const struct imxuart_platform_data mx6q_uart1_data __initconst = {
483 .flags = IMXUART_HAVE_RTSCTS | IMXUART_USE_DCEDTE,
486 static inline void mx6q_arm2_init_uart(void)
488 imx6q_add_imx_uart(0, NULL);
489 imx6q_add_imx_uart(1, &mx6q_uart1_data);
490 imx6q_add_imx_uart(3, NULL);
493 static int mx6q_arm2_fec_phy_init(struct phy_device *phydev)
497 /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
498 phy_write(phydev, 0xd, 0x7);
499 phy_write(phydev, 0xe, 0x8016);
500 phy_write(phydev, 0xd, 0x4007);
501 val = phy_read(phydev, 0xe);
505 phy_write(phydev, 0xe, val);
507 /* introduce tx clock delay */
508 phy_write(phydev, 0x1d, 0x5);
509 val = phy_read(phydev, 0x1e);
511 phy_write(phydev, 0x1e, val);
514 val = phy_read(phydev, 0x0);
515 if (val & BMCR_PDOWN)
516 phy_write(phydev, 0x0, (val & ~BMCR_PDOWN));
520 static int mx6q_arm2_fec_power_hibernate(struct phy_device *phydev)
524 /*set AR8031 debug reg 0xb to hibernate power*/
525 phy_write(phydev, 0x1d, 0xb);
526 val = phy_read(phydev, 0x1e);
529 phy_write(phydev, 0x1e, val);
534 static struct fec_platform_data fec_data __initdata = {
535 .init = mx6q_arm2_fec_phy_init,
536 .power_hibernate = mx6q_arm2_fec_power_hibernate,
537 .phy = PHY_INTERFACE_MODE_RGMII,
540 static int mx6q_arm2_spi_cs[] = {
541 MX6Q_ARM2_ECSPI1_CS0,
542 MX6Q_ARM2_ECSPI1_CS1,
545 static const struct spi_imx_master mx6q_arm2_spi_data __initconst = {
546 .chipselect = mx6q_arm2_spi_cs,
547 .num_chipselect = ARRAY_SIZE(mx6q_arm2_spi_cs),
550 #if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
551 static struct mtd_partition m25p32_partitions[] = {
553 .name = "bootloader",
559 .offset = MTDPART_OFS_APPEND,
560 .size = MTDPART_SIZ_FULL,
564 static struct flash_platform_data m25p32_spi_flash_data = {
566 .parts = m25p32_partitions,
567 .nr_parts = ARRAY_SIZE(m25p32_partitions),
572 static struct spi_board_info m25p32_spi0_board_info[] __initdata = {
573 #if defined(CONFIG_MTD_M25P80)
575 /* The modalias must be the same as spi device driver name */
576 .modalias = "m25p80",
577 .max_speed_hz = 20000000,
580 .platform_data = &m25p32_spi_flash_data,
585 static void spi_device_init(void)
587 spi_register_board_info(m25p32_spi0_board_info,
588 ARRAY_SIZE(m25p32_spi0_board_info));
591 static int max7310_1_setup(struct i2c_client *client,
592 unsigned gpio_base, unsigned ngpio,
595 int max7310_gpio_value[] = {
596 0, 1, 0, 1, 0, 0, 0, 0,
601 for (n = 0; n < ARRAY_SIZE(max7310_gpio_value); ++n) {
602 gpio_request(gpio_base + n, "MAX7310 1 GPIO Expander");
603 if (max7310_gpio_value[n] < 0)
604 gpio_direction_input(gpio_base + n);
606 gpio_direction_output(gpio_base + n,
607 max7310_gpio_value[n]);
608 gpio_export(gpio_base + n, 0);
614 static struct pca953x_platform_data max7310_platdata = {
615 .gpio_base = MX6Q_ARM2_MAX7310_1_BASE_ADDR,
617 .setup = max7310_1_setup,
620 static int max7310_u48_setup(struct i2c_client *client,
621 unsigned gpio_base, unsigned ngpio,
624 int max7310_gpio_value[] = {
625 1, 1, 1, 1, 0, 0, 0, 0,
630 for (n = 0; n < ARRAY_SIZE(max7310_gpio_value); ++n) {
631 gpio_request(gpio_base + n, "MAX7310 U48 GPIO Expander");
632 if (max7310_gpio_value[n] < 0)
633 gpio_direction_input(gpio_base + n);
635 gpio_direction_output(gpio_base + n,
636 max7310_gpio_value[n]);
637 gpio_export(gpio_base + n, 0);
643 static struct pca953x_platform_data max7310_u48_platdata = {
644 .gpio_base = MX6Q_ARM2_MAX7310_2_BASE_ADDR,
646 .setup = max7310_u48_setup,
649 static void ddc_dvi_init(void)
652 gpio_set_value(MX6Q_ARM2_DISP0_I2C_EN, 1);
655 static int ddc_dvi_update(void)
657 /* DVI cable state */
658 if (gpio_get_value(MX6Q_ARM2_DISP0_DET_INT) == 1)
664 static struct fsl_mxc_dvi_platform_data sabr_ddc_dvi_data = {
667 .init = ddc_dvi_init,
668 .update = ddc_dvi_update,
671 static void mx6q_csi0_io_init(void)
673 mxc_iomux_v3_setup_multiple_pads(mx6q_arm2_csi0_sensor_pads,
674 ARRAY_SIZE(mx6q_arm2_csi0_sensor_pads));
677 gpio_request(MX6Q_SMD_CSI0_RST, "cam-reset");
678 gpio_direction_output(MX6Q_SMD_CSI0_RST, 1);
680 /* Camera power down */
681 gpio_request(MX6Q_SMD_CSI0_PWN, "cam-pwdn");
682 gpio_direction_output(MX6Q_SMD_CSI0_PWN, 1);
684 gpio_set_value(MX6Q_SMD_CSI0_PWN, 0);
686 /* For MX6Q GPR1 bit19 and bit20 meaning:
687 * Bit19: 0 - Enable mipi to IPU1 CSI0
688 * virtual channel is fixed to 0
689 * 1 - Enable parallel interface to IPU1 CSI0
690 * Bit20: 0 - Enable mipi to IPU2 CSI1
691 * virtual channel is fixed to 3
692 * 1 - Enable parallel interface to IPU2 CSI1
693 * IPU1 CSI1 directly connect to mipi csi2,
694 * virtual channel is fixed to 1
695 * IPU2 CSI0 directly connect to mipi csi2,
696 * virtual channel is fixed to 2
698 mxc_iomux_set_gpr_register(1, 19, 1, 1);
701 static struct fsl_mxc_camera_platform_data camera_data = {
702 .analog_regulator = "DA9052_LDO7",
703 .core_regulator = "DA9052_LDO9",
706 .io_init = mx6q_csi0_io_init,
709 static void mx6q_mipi_sensor_io_init(void)
711 mxc_iomux_v3_setup_multiple_pads(mx6q_arm2_mipi_sensor_pads,
712 ARRAY_SIZE(mx6q_arm2_mipi_sensor_pads));
714 mxc_iomux_set_gpr_register(1, 19, 1, 0);
717 static struct fsl_mxc_camera_platform_data ov5640_mipi_data = {
720 .io_init = mx6q_mipi_sensor_io_init,
723 static struct i2c_board_info mxc_i2c0_board_info[] __initdata = {
725 I2C_BOARD_INFO("cs42888", 0x48),
728 I2C_BOARD_INFO("ov3640", 0x3c),
729 .platform_data = (void *)&camera_data,
733 static struct imxi2c_platform_data mx6q_arm2_i2c_data = {
737 static struct imxi2c_platform_data mx6q_arm2_i2c0_data = {
741 static struct i2c_board_info mxc_i2c2_board_info[] __initdata = {
743 I2C_BOARD_INFO("max7310", 0x1F),
744 .platform_data = &max7310_platdata,
747 I2C_BOARD_INFO("max7310", 0x1B),
748 .platform_data = &max7310_u48_platdata,
751 I2C_BOARD_INFO("mxc_dvi", 0x50),
752 .platform_data = &sabr_ddc_dvi_data,
753 .irq = gpio_to_irq(MX6Q_ARM2_DISP0_DET_INT),
756 I2C_BOARD_INFO("egalax_ts", 0x4),
757 .irq = gpio_to_irq(MX6Q_ARM2_CAP_TCH_INT),
762 static struct i2c_board_info mxc_i2c1_board_info[] __initdata = {
764 I2C_BOARD_INFO("egalax_ts", 0x4),
765 .irq = gpio_to_irq(MX6Q_ARM2_CAP_TCH_INT),
768 I2C_BOARD_INFO("mxc_hdmi_i2c", 0x50),
771 I2C_BOARD_INFO("ov5640_mipi", 0x3c),
772 .platform_data = (void *)&ov5640_mipi_data,
776 static void imx6q_arm2_usbotg_vbus(bool on)
779 gpio_set_value(MX6Q_ARM2_USB_OTG_PWR, 1);
781 gpio_set_value(MX6Q_ARM2_USB_OTG_PWR, 0);
784 static void __init imx6q_arm2_init_usb(void)
788 imx_otg_base = MX6_IO_ADDRESS(MX6Q_USB_OTG_BASE_ADDR);
789 /* disable external charger detect,
790 * or it will affect signal quality at dp.
793 ret = gpio_request(MX6Q_ARM2_USB_OTG_PWR, "usb-pwr");
795 printk(KERN_ERR"failed to get GPIO MX6Q_ARM2_USB_OTG_PWR:"
799 gpio_direction_output(MX6Q_ARM2_USB_OTG_PWR, 0);
800 mxc_iomux_set_gpr_register(1, 13, 1, 1);
802 mx6_set_otghost_vbus_func(imx6q_arm2_usbotg_vbus);
805 #ifdef CONFIG_USB_EHCI_ARC_HSIC
811 static struct viv_gpu_platform_data imx6q_gpu_pdata __initdata = {
812 .reserved_mem_size = SZ_128M,
815 /* HW Initialization, if return 0, initialization is successful. */
816 static int mx6q_arm2_sata_init(struct device *dev, void __iomem *addr)
819 int ret = 0, iterations = 20;
822 /* Enable SATA PWR CTRL_0 of MAX7310 */
823 gpio_request(MX6Q_ARM2_MAX7310_1_BASE_ADDR, "SATA_PWR_EN");
824 gpio_direction_output(MX6Q_ARM2_MAX7310_1_BASE_ADDR, 1);
826 sata_clk = clk_get(dev, "imx_sata_clk");
827 if (IS_ERR(sata_clk)) {
828 dev_err(dev, "no sata clock.\n");
829 return PTR_ERR(sata_clk);
831 ret = clk_enable(sata_clk);
833 dev_err(dev, "can't enable sata clock.\n");
837 /* Set PHY Paremeters, two steps to configure the GPR13,
838 * one write for rest of parameters, mask of first write is 0x07FFFFFD,
839 * and the other one write for setting the mpll_clk_off_b
840 *.rx_eq_val_0(iomuxc_gpr13[26:24]),
841 *.los_lvl(iomuxc_gpr13[23:19]),
842 *.rx_dpll_mode_0(iomuxc_gpr13[18:16]),
843 *.sata_speed(iomuxc_gpr13[15]),
844 *.mpll_ss_en(iomuxc_gpr13[14]),
845 *.tx_atten_0(iomuxc_gpr13[13:11]),
846 *.tx_boost_0(iomuxc_gpr13[10:7]),
847 *.tx_lvl(iomuxc_gpr13[6:2]),
848 *.mpll_ck_off(iomuxc_gpr13[1]),
849 *.tx_edgerate_0(iomuxc_gpr13[0]),
851 tmpdata = readl(IOMUXC_GPR13);
852 writel(((tmpdata & ~0x07FFFFFD) | 0x0593A044), IOMUXC_GPR13);
854 /* enable SATA_PHY PLL */
855 tmpdata = readl(IOMUXC_GPR13);
856 writel(((tmpdata & ~0x2) | 0x2), IOMUXC_GPR13);
858 /* Get the AHB clock rate, and configure the TIMER1MS reg later */
859 clk = clk_get(NULL, "ahb");
861 dev_err(dev, "no ahb clock.\n");
863 goto release_sata_clk;
865 tmpdata = clk_get_rate(clk) / 1000;
868 sata_init(addr, tmpdata);
870 /* Release resources when there is no device on the port */
872 if ((readl(addr + PORT_SATA_SR) & 0xF) == 0)
877 if (iterations == 0) {
878 dev_info(dev, "NO sata disk.\n");
880 goto release_sata_clk;
882 } while (iterations-- > 0);
887 clk_disable(sata_clk);
890 /* Disable SATA PWR CTRL_0 of MAX7310 */
891 gpio_request(MX6Q_ARM2_MAX7310_1_BASE_ADDR, "SATA_PWR_EN");
892 gpio_direction_output(MX6Q_ARM2_MAX7310_1_BASE_ADDR, 0);
897 static void mx6q_arm2_sata_exit(struct device *dev)
899 clk_disable(sata_clk);
902 /* Disable SATA PWR CTRL_0 of MAX7310 */
903 gpio_request(MX6Q_ARM2_MAX7310_1_BASE_ADDR, "SATA_PWR_EN");
904 gpio_direction_output(MX6Q_ARM2_MAX7310_1_BASE_ADDR, 0);
908 static struct ahci_platform_data mx6q_arm2_sata_data = {
909 .init = mx6q_arm2_sata_init,
910 .exit = mx6q_arm2_sata_exit,
913 static struct imx_asrc_platform_data imx_asrc_data = {
918 static void mx6q_sabreauto_reset_mipi_dsi(void)
920 gpio_set_value(MX6Q_ARM2_DISP0_PWR, 1);
921 gpio_set_value(MX6Q_ARM2_DISP0_RESET, 1);
923 gpio_set_value(MX6Q_ARM2_DISP0_RESET, 0);
925 gpio_set_value(MX6Q_ARM2_DISP0_RESET, 1);
928 * it needs to delay 120ms minimum for reset complete
933 static struct mipi_dsi_platform_data mipi_dsi_pdata = {
936 .lcd_panel = "TRULY-WVGA",
937 .reset = mx6q_sabreauto_reset_mipi_dsi,
940 static struct ipuv3_fb_platform_data sabr_fb_data[] = {
943 .interface_pix_fmt = IPU_PIX_FMT_RGB666,
944 .mode_str = "LDB-XGA",
949 .interface_pix_fmt = IPU_PIX_FMT_RGB565,
950 .mode_str = "CLAA-WVGA",
955 .interface_pix_fmt = IPU_PIX_FMT_RGB666,
956 .mode_str = "LDB-XGA",
962 static void hdmi_init(int ipu_id, int disp_id)
964 int hdmi_mux_setting;
966 if ((ipu_id > 1) || (ipu_id < 0)) {
967 printk(KERN_ERR"Invalid IPU select for HDMI: %d. Set to 0\n",
972 if ((disp_id > 1) || (disp_id < 0)) {
973 printk(KERN_ERR"Invalid DI select for HDMI: %d. Set to 0\n",
978 /* Configure the connection between IPU1/2 and HDMI */
979 hdmi_mux_setting = 2*ipu_id + disp_id;
981 /* GPR3, bits 2-3 = HDMI_MUX_CTL */
982 mxc_iomux_set_gpr_register(3, 2, 2, hdmi_mux_setting);
985 static struct fsl_mxc_hdmi_platform_data hdmi_data = {
989 static struct fsl_mxc_hdmi_core_platform_data hdmi_core_data = {
994 static struct fsl_mxc_lcd_platform_data lcdif_data = {
997 .default_ifmt = IPU_PIX_FMT_RGB565,
1000 static struct fsl_mxc_ldb_platform_data ldb_data = {
1009 static struct imx_ipuv3_platform_data ipu_data[] = {
1012 .csi_clk[0] = "ccm_clk0",
1015 .csi_clk[0] = "ccm_clk0",
1019 static struct platform_pwm_backlight_data mx6_arm2_pwm_backlight_data = {
1021 .max_brightness = 255,
1022 .dft_brightness = 128,
1023 .pwm_period_ns = 50000,
1026 static struct gpio mx6q_flexcan_gpios[] = {
1027 { MX6Q_ARM2_CAN1_EN, GPIOF_OUT_INIT_LOW, "flexcan1-en" },
1028 { MX6Q_ARM2_CAN1_STBY, GPIOF_OUT_INIT_LOW, "flexcan1-stby" },
1029 { MX6Q_ARM2_CAN2_EN, GPIOF_OUT_INIT_LOW, "flexcan2-en" },
1032 static void mx6q_flexcan0_switch(int enable)
1035 gpio_set_value(MX6Q_ARM2_CAN1_EN, 1);
1036 gpio_set_value(MX6Q_ARM2_CAN1_STBY, 1);
1038 gpio_set_value(MX6Q_ARM2_CAN1_EN, 0);
1039 gpio_set_value(MX6Q_ARM2_CAN1_STBY, 0);
1043 static void mx6q_flexcan1_switch(int enable)
1046 gpio_set_value(MX6Q_ARM2_CAN2_EN, 1);
1047 gpio_set_value_cansleep(MX6Q_ARM2_CAN2_STBY, 1);
1049 gpio_set_value(MX6Q_ARM2_CAN2_EN, 0);
1050 gpio_set_value_cansleep(MX6Q_ARM2_CAN2_STBY, 0);
1054 static const struct flexcan_platform_data
1055 mx6q_arm2_flexcan_pdata[] __initconst = {
1057 .transceiver_switch = mx6q_flexcan0_switch,
1059 .transceiver_switch = mx6q_flexcan1_switch,
1063 static struct mipi_csi2_platform_data mipi_csi2_pdata = {
1068 .dphy_clk = "mipi_pllref_clk",
1069 .pixel_clk = "emi_clk",
1072 static void arm2_suspend_enter(void)
1074 /* suspend preparation */
1077 static void arm2_suspend_exit(void)
1081 static const struct pm_platform_data mx6q_arm2_pm_data __initconst = {
1083 .suspend_enter = arm2_suspend_enter,
1084 .suspend_exit = arm2_suspend_exit,
1087 static struct mxc_audio_platform_data sab_audio_data = {
1091 static struct platform_device sab_audio_device = {
1092 .name = "imx-cs42888",
1095 static struct imx_esai_platform_data sab_esai_pdata = {
1096 .flags = IMX_ESAI_NET,
1099 static struct regulator_consumer_supply arm2_vmmc_consumers[] = {
1100 REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx.1"),
1101 REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx.2"),
1102 REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx.3"),
1105 static struct regulator_init_data arm2_vmmc_init = {
1106 .num_consumer_supplies = ARRAY_SIZE(arm2_vmmc_consumers),
1107 .consumer_supplies = arm2_vmmc_consumers,
1110 static struct fixed_voltage_config arm2_vmmc_reg_config = {
1111 .supply_name = "vmmc",
1112 .microvolts = 3300000,
1114 .init_data = &arm2_vmmc_init,
1117 static struct platform_device arm2_vmmc_reg_devices = {
1118 .name = "reg-fixed-voltage",
1121 .platform_data = &arm2_vmmc_reg_config,
1125 #ifdef CONFIG_SND_SOC_CS42888
1127 static struct regulator_consumer_supply cs42888_arm2_consumer_va = {
1129 .dev_name = "0-0048",
1132 static struct regulator_consumer_supply cs42888_arm2_consumer_vd = {
1134 .dev_name = "0-0048",
1137 static struct regulator_consumer_supply cs42888_arm2_consumer_vls = {
1139 .dev_name = "0-0048",
1142 static struct regulator_consumer_supply cs42888_arm2_consumer_vlc = {
1144 .dev_name = "0-0048",
1147 static struct regulator_init_data cs42888_arm2_va_reg_initdata = {
1148 .num_consumer_supplies = 1,
1149 .consumer_supplies = &cs42888_arm2_consumer_va,
1152 static struct regulator_init_data cs42888_arm2_vd_reg_initdata = {
1153 .num_consumer_supplies = 1,
1154 .consumer_supplies = &cs42888_arm2_consumer_vd,
1157 static struct regulator_init_data cs42888_arm2_vls_reg_initdata = {
1158 .num_consumer_supplies = 1,
1159 .consumer_supplies = &cs42888_arm2_consumer_vls,
1162 static struct regulator_init_data cs42888_arm2_vlc_reg_initdata = {
1163 .num_consumer_supplies = 1,
1164 .consumer_supplies = &cs42888_arm2_consumer_vlc,
1167 static struct fixed_voltage_config cs42888_arm2_va_reg_config = {
1168 .supply_name = "VA",
1169 .microvolts = 2800000,
1171 .init_data = &cs42888_arm2_va_reg_initdata,
1174 static struct fixed_voltage_config cs42888_arm2_vd_reg_config = {
1175 .supply_name = "VD",
1176 .microvolts = 2800000,
1178 .init_data = &cs42888_arm2_vd_reg_initdata,
1181 static struct fixed_voltage_config cs42888_arm2_vls_reg_config = {
1182 .supply_name = "VLS",
1183 .microvolts = 2800000,
1185 .init_data = &cs42888_arm2_vls_reg_initdata,
1188 static struct fixed_voltage_config cs42888_arm2_vlc_reg_config = {
1189 .supply_name = "VLC",
1190 .microvolts = 2800000,
1192 .init_data = &cs42888_arm2_vlc_reg_initdata,
1195 static struct platform_device cs42888_arm2_va_reg_devices = {
1196 .name = "reg-fixed-voltage",
1199 .platform_data = &cs42888_arm2_va_reg_config,
1203 static struct platform_device cs42888_arm2_vd_reg_devices = {
1204 .name = "reg-fixed-voltage",
1207 .platform_data = &cs42888_arm2_vd_reg_config,
1211 static struct platform_device cs42888_arm2_vls_reg_devices = {
1212 .name = "reg-fixed-voltage",
1215 .platform_data = &cs42888_arm2_vls_reg_config,
1219 static struct platform_device cs42888_arm2_vlc_reg_devices = {
1220 .name = "reg-fixed-voltage",
1223 .platform_data = &cs42888_arm2_vlc_reg_config,
1227 #endif /* CONFIG_SND_SOC_CS42888 */
1229 #ifdef CONFIG_SND_SOC_SGTL5000
1231 static struct regulator_consumer_supply sgtl5000_arm2_consumer_vdda = {
1233 .dev_name = "0-000a",
1236 static struct regulator_consumer_supply sgtl5000_arm2_consumer_vddio = {
1238 .dev_name = "0-000a",
1241 static struct regulator_consumer_supply sgtl5000_arm2_consumer_vddd = {
1243 .dev_name = "0-000a",
1246 static struct regulator_init_data sgtl5000_arm2_vdda_reg_initdata = {
1247 .num_consumer_supplies = 1,
1248 .consumer_supplies = &sgtl5000_arm2_consumer_vdda,
1251 static struct regulator_init_data sgtl5000_arm2_vddio_reg_initdata = {
1252 .num_consumer_supplies = 1,
1253 .consumer_supplies = &sgtl5000_arm2_consumer_vddio,
1256 static struct regulator_init_data sgtl5000_arm2_vddd_reg_initdata = {
1257 .num_consumer_supplies = 1,
1258 .consumer_supplies = &sgtl5000_arm2_consumer_vddd,
1261 static struct fixed_voltage_config sgtl5000_arm2_vdda_reg_config = {
1262 .supply_name = "VDDA",
1263 .microvolts = 1800000,
1265 .init_data = &sgtl5000_arm2_vdda_reg_initdata,
1268 static struct fixed_voltage_config sgtl5000_arm2_vddio_reg_config = {
1269 .supply_name = "VDDIO",
1270 .microvolts = 3300000,
1272 .init_data = &sgtl5000_arm2_vddio_reg_initdata,
1275 static struct fixed_voltage_config sgtl5000_arm2_vddd_reg_config = {
1276 .supply_name = "VDDD",
1279 .init_data = &sgtl5000_arm2_vddd_reg_initdata,
1282 static struct platform_device sgtl5000_arm2_vdda_reg_devices = {
1283 .name = "reg-fixed-voltage",
1286 .platform_data = &sgtl5000_arm2_vdda_reg_config,
1290 static struct platform_device sgtl5000_arm2_vddio_reg_devices = {
1291 .name = "reg-fixed-voltage",
1294 .platform_data = &sgtl5000_arm2_vddio_reg_config,
1298 static struct platform_device sgtl5000_arm2_vddd_reg_devices = {
1299 .name = "reg-fixed-voltage",
1302 .platform_data = &sgtl5000_arm2_vddd_reg_config,
1306 #endif /* CONFIG_SND_SOC_SGTL5000 */
1308 static int __init imx6q_init_audio(void)
1310 struct clk *pll3_pfd, *esai_clk;
1311 mxc_register_device(&sab_audio_device, &sab_audio_data);
1312 imx6q_add_imx_esai(0, &sab_esai_pdata);
1314 esai_clk = clk_get(NULL, "esai_clk");
1315 if (IS_ERR(esai_clk))
1316 return PTR_ERR(esai_clk);
1318 pll3_pfd = clk_get(NULL, "pll3_pfd_508M");
1319 if (IS_ERR(pll3_pfd))
1320 return PTR_ERR(pll3_pfd);
1322 clk_set_parent(esai_clk, pll3_pfd);
1323 clk_set_rate(esai_clk, 101647058);
1325 #ifdef CONFIG_SND_SOC_SGTL5000
1326 platform_device_register(&sgtl5000_arm2_vdda_reg_devices);
1327 platform_device_register(&sgtl5000_arm2_vddio_reg_devices);
1328 platform_device_register(&sgtl5000_arm2_vddd_reg_devices);
1331 #ifdef CONFIG_SND_SOC_CS42888
1332 platform_device_register(&cs42888_arm2_va_reg_devices);
1333 platform_device_register(&cs42888_arm2_vd_reg_devices);
1334 platform_device_register(&cs42888_arm2_vls_reg_devices);
1335 platform_device_register(&cs42888_arm2_vlc_reg_devices);
1340 static int __init early_use_esai_record(char *p)
1346 early_param("esai_record", early_use_esai_record);
1348 static struct mxc_dvfs_platform_data arm2_dvfscore_data = {
1349 .reg_id = "cpu_vddgp",
1350 .clk1_id = "cpu_clk",
1351 .clk2_id = "gpc_dvfs_clk",
1352 .gpc_cntr_offset = MXC_GPC_CNTR_OFFSET,
1353 .ccm_cdcr_offset = MXC_CCM_CDCR_OFFSET,
1354 .ccm_cacrr_offset = MXC_CCM_CACRR_OFFSET,
1355 .ccm_cdhipr_offset = MXC_CCM_CDHIPR_OFFSET,
1356 .prediv_mask = 0x1F800,
1357 .prediv_offset = 11,
1359 .div3ck_mask = 0xE0000000,
1360 .div3ck_offset = 29,
1371 static int mx6_arm2_set_cpu_voltage(u32 cpu_volt)
1375 if (cpu_regulator == NULL)
1376 cpu_regulator = regulator_get(NULL, gp_reg_id);
1378 if (!IS_ERR(cpu_regulator))
1379 ret = regulator_set_voltage(cpu_regulator,
1380 cpu_volt, cpu_volt);
1384 static void __init fixup_mxc_board(struct machine_desc *desc, struct tag *tags,
1385 char **cmdline, struct meminfo *mi)
1387 set_cpu_voltage = mx6_arm2_set_cpu_voltage;
1390 static int __init early_enable_spdif(char *p)
1396 early_param("spdif", early_enable_spdif);
1398 static int __init early_enable_can(char *p)
1404 early_param("flexcan", early_enable_can);
1406 static int spdif_clk_set_rate(struct clk *clk, unsigned long rate)
1408 unsigned long rate_actual;
1409 rate_actual = clk_round_rate(clk, rate);
1410 clk_set_rate(clk, rate_actual);
1414 static struct mxc_spdif_platform_data mxc_spdif_data = {
1415 .spdif_tx = 1, /* enable tx */
1416 .spdif_rx = 1, /* enable rx */
1418 * spdif0_clk will be 454.7MHz divided by ccm dividers.
1420 * 44.1KHz: 454.7MHz / 7 (ccm) / 23 (spdif) = 44,128 Hz ~ 0.06% error
1421 * 48KHz: 454.7MHz / 4 (ccm) / 37 (spdif) = 48,004 Hz ~ 0.01% error
1422 * 32KHz: 454.7MHz / 6 (ccm) / 37 (spdif) = 32,003 Hz ~ 0.01% error
1424 .spdif_clk_44100 = 1, /* tx clk from spdif0_clk_root */
1425 .spdif_clk_48000 = 1, /* tx clk from spdif0_clk_root */
1426 .spdif_div_44100 = 23,
1427 .spdif_div_48000 = 37,
1428 .spdif_div_32000 = 37,
1429 .spdif_rx_clk = 0, /* rx clk from spdif stream */
1430 .spdif_clk_set_rate = spdif_clk_set_rate,
1431 .spdif_clk = NULL, /* spdif bus clk */
1435 * Board specific initialization.
1437 static void __init mx6_board_init(void)
1442 mxc_iomux_v3_setup_multiple_pads(mx6q_arm2_pads,
1443 ARRAY_SIZE(mx6q_arm2_pads));
1446 mxc_iomux_v3_setup_multiple_pads(mx6q_arm2_esai_record_pads,
1447 ARRAY_SIZE(mx6q_arm2_esai_record_pads));
1450 * S/PDIF in and i2c3 are mutually exclusive because both
1452 * S/PDIF out and can1 stby are mutually exclusive because both
1456 mxc_iomux_v3_setup_multiple_pads(mx6q_arm2_spdif_pads,
1457 ARRAY_SIZE(mx6q_arm2_spdif_pads));
1459 mxc_iomux_v3_setup_multiple_pads(mx6q_arm2_i2c3_pads,
1460 ARRAY_SIZE(mx6q_arm2_i2c3_pads));
1462 mxc_iomux_v3_setup_multiple_pads(mx6q_arm2_can_pads,
1463 ARRAY_SIZE(mx6q_arm2_can_pads));
1466 gp_reg_id = arm2_dvfscore_data.reg_id;
1467 mx6q_arm2_init_uart();
1468 imx6q_add_mipi_csi2(&mipi_csi2_pdata);
1469 imx6q_add_mxc_hdmi_core(&hdmi_core_data);
1471 imx6q_add_ipuv3(0, &ipu_data[0]);
1472 imx6q_add_ipuv3(1, &ipu_data[1]);
1474 for (i = 0; i < ARRAY_SIZE(sabr_fb_data); i++)
1475 imx6q_add_ipuv3fb(i, &sabr_fb_data[i]);
1477 imx6q_add_mipi_dsi(&mipi_dsi_pdata);
1478 imx6q_add_lcdif(&lcdif_data);
1479 imx6q_add_ldb(&ldb_data);
1480 imx6q_add_v4l2_output(0);
1481 imx6q_add_v4l2_capture(0);
1483 imx6q_add_imx_snvs_rtc();
1485 imx6q_add_imx_i2c(0, &mx6q_arm2_i2c0_data);
1486 imx6q_add_imx_i2c(1, &mx6q_arm2_i2c_data);
1487 i2c_register_board_info(0, mxc_i2c0_board_info,
1488 ARRAY_SIZE(mxc_i2c0_board_info));
1489 i2c_register_board_info(1, mxc_i2c1_board_info,
1490 ARRAY_SIZE(mxc_i2c1_board_info));
1492 imx6q_add_imx_i2c(2, &mx6q_arm2_i2c_data);
1493 i2c_register_board_info(2, mxc_i2c2_board_info,
1494 ARRAY_SIZE(mxc_i2c2_board_info));
1498 imx6q_add_ecspi(0, &mx6q_arm2_spi_data);
1501 imx6q_add_mxc_hdmi(&hdmi_data);
1503 imx6q_add_anatop_thermal_imx(1, &mx6q_arm2_anatop_thermal_data);
1506 imx6_init_fec(fec_data);
1508 imx6q_add_pm_imx(0, &mx6q_arm2_pm_data);
1509 imx6q_add_sdhci_usdhc_imx(3, &mx6q_arm2_sd4_data);
1510 imx6q_add_sdhci_usdhc_imx(2, &mx6q_arm2_sd3_data);
1511 imx_add_viv_gpu(&imx6_gpu_data, &imx6q_gpu_pdata);
1512 imx6q_arm2_init_usb();
1513 imx6q_add_ahci(0, &mx6q_arm2_sata_data);
1516 platform_device_register(&arm2_vmmc_reg_devices);
1517 imx_asrc_data.asrc_core_clk = clk_get(NULL, "asrc_clk");
1518 imx_asrc_data.asrc_audio_clk = clk_get(NULL, "asrc_serial_clk");
1519 imx6q_add_asrc(&imx_asrc_data);
1522 gpio_request(MX6Q_ARM2_DISP0_DET_INT, "disp0-detect");
1523 gpio_direction_input(MX6Q_ARM2_DISP0_DET_INT);
1525 /* DISP0 Reset - Assert for i2c disabled mode */
1526 gpio_request(MX6Q_ARM2_DISP0_RESET, "disp0-reset");
1527 gpio_direction_output(MX6Q_ARM2_DISP0_RESET, 0);
1529 /* DISP0 I2C enable */
1530 gpio_request(MX6Q_ARM2_DISP0_I2C_EN, "disp0-i2c");
1531 gpio_direction_output(MX6Q_ARM2_DISP0_I2C_EN, 0);
1533 gpio_request(MX6Q_ARM2_DISP0_PWR, "disp0-pwr");
1534 gpio_direction_output(MX6Q_ARM2_DISP0_PWR, 1);
1536 gpio_request(MX6Q_ARM2_LDB_BACKLIGHT, "ldb-backlight");
1537 gpio_direction_output(MX6Q_ARM2_LDB_BACKLIGHT, 1);
1540 imx6q_add_imx2_wdt(0, NULL);
1542 imx6q_add_gpmi(&mx6q_gpmi_nfc_platform_data);
1544 imx6q_add_dvfs_core(&arm2_dvfscore_data);
1546 imx6q_add_mxc_pwm(0);
1547 imx6q_add_mxc_pwm_backlight(0, &mx6_arm2_pwm_backlight_data);
1550 mxc_spdif_data.spdif_core_clk = clk_get_sys("mxc_spdif.0", NULL);
1551 clk_put(mxc_spdif_data.spdif_core_clk);
1552 imx6q_add_spdif(&mxc_spdif_data);
1553 imx6q_add_spdif_dai();
1554 imx6q_add_spdif_audio_device();
1555 } else if (flexcan_en) {
1556 ret = gpio_request_array(mx6q_flexcan_gpios,
1557 ARRAY_SIZE(mx6q_flexcan_gpios));
1559 pr_err("failed to request flexcan-gpios: %d\n", ret);
1561 imx6q_add_flexcan0(&mx6q_arm2_flexcan_pdata[0]);
1562 imx6q_add_flexcan1(&mx6q_arm2_flexcan_pdata[1]);
1566 imx6q_add_hdmi_soc();
1567 imx6q_add_hdmi_soc_dai();
1568 imx6q_add_perfmon(0);
1569 imx6q_add_perfmon(1);
1570 imx6q_add_perfmon(2);
1573 extern void __iomem *twd_base;
1574 static void __init mx6_timer_init(void)
1576 struct clk *uart_clk;
1577 #ifdef CONFIG_LOCAL_TIMERS
1578 twd_base = ioremap(LOCAL_TWD_ADDR, SZ_256);
1581 mx6_clocks_init(32768, 24000000, 0, 0);
1583 uart_clk = clk_get_sys("imx-uart.0", NULL);
1584 early_console_setup(UART4_BASE_ADDR, uart_clk);
1587 static struct sys_timer mxc_timer = {
1588 .init = mx6_timer_init,
1591 static void __init mx6q_reserve(void)
1595 if (imx6q_gpu_pdata.reserved_mem_size) {
1596 phys = memblock_alloc_base(imx6q_gpu_pdata.reserved_mem_size,
1598 memblock_free(phys, imx6q_gpu_pdata.reserved_mem_size);
1599 memblock_remove(phys, imx6q_gpu_pdata.reserved_mem_size);
1600 imx6q_gpu_pdata.reserved_mem_base = phys;
1605 * initialize __mach_desc_MX6Q_ARM2 data structure.
1607 MACHINE_START(MX6Q_ARM2, "Freescale i.MX 6Quad Armadillo2 Board")
1608 /* Maintainer: Freescale Semiconductor, Inc. */
1609 .boot_params = MX6_PHYS_OFFSET + 0x100,
1610 .fixup = fixup_mxc_board,
1611 .map_io = mx6_map_io,
1612 .init_irq = mx6_init_irq,
1613 .init_machine = mx6_board_init,
1614 .timer = &mxc_timer,
1615 .reserve = mx6q_reserve,