arch/arm/mach-mx6/board-mx6q_arm2.c

   1 /*
   2  * Copyright (C) 2011-2012 Freescale Semiconductor, Inc. All Rights Reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13
  14  * You should have received a copy of the GNU General Public License along
  15  * with this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  17  */
  18
  19 #include <linux/types.h>
  20 #include <linux/sched.h>
  21 #include <linux/delay.h>
  22 #include <linux/pm.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/irq.h>
  25 #include <linux/init.h>
  26 #include <linux/input.h>
  27 #include <linux/nodemask.h>
  28 #include <linux/clk.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/fsl_devices.h>
  31 #include <linux/smsc911x.h>
  32 #include <linux/spi/spi.h>
  33 #include <linux/spi/flash.h>
  34 #include <linux/i2c.h>
  35 #include <linux/i2c/pca953x.h>
  36 #include <linux/ata.h>
  37 #include <linux/mtd/mtd.h>
  38 #include <linux/mtd/map.h>
  39 #include <linux/mtd/partitions.h>
  40 #include <linux/pmic_external.h>
  41 #include <linux/pmic_status.h>
  42 #include <linux/ipu.h>
  43 #include <linux/mxcfb.h>
  44 #include <linux/pwm_backlight.h>
  45 #include <linux/fec.h>
  46 #include <linux/memblock.h>
  47 #include <linux/gpio.h>
  48 #include <linux/etherdevice.h>
  49 #include <linux/regulator/anatop-regulator.h>
  50 #include <linux/regulator/consumer.h>
  51 #include <linux/regulator/machine.h>
  52 #include <linux/regulator/fixed.h>
  53 #include <linux/mfd/max17135.h>
  54 #include <sound/pcm.h>
  55
  56 #include <mach/common.h>
  57 #include <mach/hardware.h>
  58 #include <mach/mxc_dvfs.h>
  59 #include <mach/memory.h>
  60 #include <mach/imx-uart.h>
  61 #include <mach/viv_gpu.h>
  62 #include <mach/ahci_sata.h>
  63 #include <mach/ipu-v3.h>
  64 #include <mach/mxc_hdmi.h>
  65 #include <mach/mxc_asrc.h>
  66 #include <mach/mipi_dsi.h>
  67 #include <mach/mipi_csi2.h>
  68
  69 #include <asm/irq.h>
  70 #include <asm/setup.h>
  71 #include <asm/mach-types.h>
  72 #include <asm/mach/arch.h>
  73 #include <asm/mach/time.h>
  74
  75 #include "usb.h"
  76 #include "devices-imx6q.h"
  77 #include "crm_regs.h"
  78 #include "cpu_op-mx6.h"
  79 #include "board-mx6q_arm2.h"
  80 #include "board-mx6dl_arm2.h"
  81
  82 /* GPIO PIN, sort by PORT/BIT */
  83 #define MX6_ARM2_LDB_BACKLIGHT          IMX_GPIO_NR(1, 9)
  84 #define MX6_ARM2_ECSPI1_CS0             IMX_GPIO_NR(2, 30)
  85 #define MX6_ARM2_ECSPI1_CS1             IMX_GPIO_NR(3, 19)
  86 #define MX6_ARM2_USB_OTG_PWR            IMX_GPIO_NR(3, 22)
  87 #define MX6_ARM2_DISP0_PWR              IMX_GPIO_NR(3, 24)
  88 #define MX6_ARM2_DISP0_I2C_EN           IMX_GPIO_NR(3, 28)
  89 #define MX6_ARM2_CAP_TCH_INT            IMX_GPIO_NR(3, 31)
  90 #define MX6_ARM2_DISP0_DET_INT          IMX_GPIO_NR(3, 31)
  91 #define MX6_ARM2_CSI0_RST               IMX_GPIO_NR(4, 5)
  92 #define MX6_ARM2_DISP0_RESET            IMX_GPIO_NR(5, 0)
  93 #define MX6_ARM2_CSI0_PWN               IMX_GPIO_NR(5, 23)
  94 #define MX6_ARM2_CAN2_EN                IMX_GPIO_NR(5, 24)
  95 #define MX6_ARM2_CSI0_RST_TVIN          IMX_GPIO_NR(5, 25)
  96 #define MX6_ARM2_SD3_CD                 IMX_GPIO_NR(6, 11)
  97 #define MX6_ARM2_SD3_WP                 IMX_GPIO_NR(6, 14)
  98 #define MX6_ARM2_CAN1_STBY              IMX_GPIO_NR(7, 12)
  99 #define MX6_ARM2_CAN1_EN                IMX_GPIO_NR(7, 13)
 100 #define MX6_ARM2_MAX7310_1_BASE_ADDR    IMX_GPIO_NR(8, 0)
 101 #define MX6_ARM2_MAX7310_2_BASE_ADDR    IMX_GPIO_NR(8, 8)
 102 #define MX6DL_ARM2_EPDC_SDDO_0          IMX_GPIO_NR(2, 22)
 103 #define MX6DL_ARM2_EPDC_SDDO_1          IMX_GPIO_NR(3, 10)
 104 #define MX6DL_ARM2_EPDC_SDDO_2          IMX_GPIO_NR(3, 12)
 105 #define MX6DL_ARM2_EPDC_SDDO_3          IMX_GPIO_NR(3, 11)
 106 #define MX6DL_ARM2_EPDC_SDDO_4          IMX_GPIO_NR(2, 27)
 107 #define MX6DL_ARM2_EPDC_SDDO_5          IMX_GPIO_NR(2, 30)
 108 #define MX6DL_ARM2_EPDC_SDDO_6          IMX_GPIO_NR(2, 23)
 109 #define MX6DL_ARM2_EPDC_SDDO_7          IMX_GPIO_NR(2, 26)
 110 #define MX6DL_ARM2_EPDC_SDDO_8          IMX_GPIO_NR(2, 24)
 111 #define MX6DL_ARM2_EPDC_SDDO_9          IMX_GPIO_NR(3, 15)
 112 #define MX6DL_ARM2_EPDC_SDDO_10         IMX_GPIO_NR(3, 16)
 113 #define MX6DL_ARM2_EPDC_SDDO_11         IMX_GPIO_NR(3, 23)
 114 #define MX6DL_ARM2_EPDC_SDDO_12         IMX_GPIO_NR(3, 19)
 115 #define MX6DL_ARM2_EPDC_SDDO_13         IMX_GPIO_NR(3, 13)
 116 #define MX6DL_ARM2_EPDC_SDDO_14         IMX_GPIO_NR(3, 14)
 117 #define MX6DL_ARM2_EPDC_SDDO_15         IMX_GPIO_NR(5, 2)
 118 #define MX6DL_ARM2_EPDC_GDCLK           IMX_GPIO_NR(2, 17)
 119 #define MX6DL_ARM2_EPDC_GDSP            IMX_GPIO_NR(2, 16)
 120 #define MX6DL_ARM2_EPDC_GDOE            IMX_GPIO_NR(6, 6)
 121 #define MX6DL_ARM2_EPDC_GDRL            IMX_GPIO_NR(5, 4)
 122 #define MX6DL_ARM2_EPDC_SDCLK           IMX_GPIO_NR(3, 31)
 123 #define MX6DL_ARM2_EPDC_SDOEZ           IMX_GPIO_NR(3, 30)
 124 #define MX6DL_ARM2_EPDC_SDOED           IMX_GPIO_NR(3, 26)
 125 #define MX6DL_ARM2_EPDC_SDOE            IMX_GPIO_NR(3, 27)
 126 #define MX6DL_ARM2_EPDC_SDLE            IMX_GPIO_NR(3, 1)
 127 #define MX6DL_ARM2_EPDC_SDCLKN          IMX_GPIO_NR(3, 0)
 128 #define MX6DL_ARM2_EPDC_SDSHR           IMX_GPIO_NR(2, 29)
 129 #define MX6DL_ARM2_EPDC_PWRCOM          IMX_GPIO_NR(2, 28)
 130 #define MX6DL_ARM2_EPDC_PWRSTAT         IMX_GPIO_NR(2, 21)
 131 #define MX6DL_ARM2_EPDC_PWRCTRL0        IMX_GPIO_NR(2, 20)
 132 #define MX6DL_ARM2_EPDC_PWRCTRL1        IMX_GPIO_NR(2, 19)
 133 #define MX6DL_ARM2_EPDC_PWRCTRL2        IMX_GPIO_NR(2, 18)
 134 #define MX6DL_ARM2_EPDC_PWRCTRL3        IMX_GPIO_NR(3, 28)
 135 #define MX6DL_ARM2_EPDC_BDR0            IMX_GPIO_NR(3, 2)
 136 #define MX6DL_ARM2_EPDC_BDR1            IMX_GPIO_NR(3, 3)
 137 #define MX6DL_ARM2_EPDC_SDCE0           IMX_GPIO_NR(3, 4)
 138 #define MX6DL_ARM2_EPDC_SDCE1           IMX_GPIO_NR(3, 5)
 139 #define MX6DL_ARM2_EPDC_SDCE2           IMX_GPIO_NR(3, 6)
 140 #define MX6DL_ARM2_EPDC_SDCE3           IMX_GPIO_NR(3, 7)
 141 #define MX6DL_ARM2_EPDC_SDCE4           IMX_GPIO_NR(3, 8)
 142 #define MX6DL_ARM2_EPDC_SDCE5           IMX_GPIO_NR(3, 9)
 143 #define MX6DL_ARM2_EPDC_PMIC_WAKE       IMX_GPIO_NR(2, 31)
 144 #define MX6DL_ARM2_EPDC_PMIC_INT        IMX_GPIO_NR(2, 25)
 145 #define MX6DL_ARM2_EPDC_VCOM            IMX_GPIO_NR(3, 17)
 146
 147 #define MX6_ARM2_IO_EXP_GPIO1(x)        (MX6_ARM2_MAX7310_1_BASE_ADDR + (x))
 148 #define MX6_ARM2_IO_EXP_GPIO2(x)        (MX6_ARM2_MAX7310_2_BASE_ADDR + (x))
 149
 150 #define MX6_ARM2_CAN2_STBY              MX6_ARM2_IO_EXP_GPIO2(1)
 151
 152
 153 #define BMCR_PDOWN                      0x0800 /* PHY Powerdown */
 154
 155 void __init early_console_setup(unsigned long base, struct clk *clk);
 156 static struct clk *sata_clk;
 157 static int esai_record;
 158 static int sgtl5000_en;
 159 static int spdif_en;
 160 static int flexcan_en;
 161 static int disable_mipi_dsi;
 162
 163 extern struct regulator *(*get_cpu_regulator)(void);
 164 extern void (*put_cpu_regulator)(void);
 165 extern char *gp_reg_id;
 166 extern int epdc_enabled;
 167 extern void mx6_cpu_regulator_init(void);
 168 static int max17135_regulator_init(struct max17135 *max17135);
 169
 170 enum sd_pad_mode {
 171         SD_PAD_MODE_LOW_SPEED,
 172         SD_PAD_MODE_MED_SPEED,
 173         SD_PAD_MODE_HIGH_SPEED,
 174 };
 175
 176 static int plt_sd3_pad_change(int clock)
 177 {
 178         static enum sd_pad_mode pad_mode = SD_PAD_MODE_LOW_SPEED;
 179
 180         iomux_v3_cfg_t *sd3_pads_200mhz = NULL;
 181         iomux_v3_cfg_t *sd3_pads_100mhz = NULL;
 182         iomux_v3_cfg_t *sd3_pads_50mhz = NULL;
 183
 184         u32 sd3_pads_200mhz_cnt;
 185         u32 sd3_pads_100mhz_cnt;
 186         u32 sd3_pads_50mhz_cnt;
 187
 188         if (cpu_is_mx6q()) {
 189                 sd3_pads_200mhz = mx6q_sd3_200mhz;
 190                 sd3_pads_100mhz = mx6q_sd3_100mhz;
 191                 sd3_pads_50mhz = mx6q_sd3_50mhz;
 192
 193                 sd3_pads_200mhz_cnt = ARRAY_SIZE(mx6q_sd3_200mhz);
 194                 sd3_pads_100mhz_cnt = ARRAY_SIZE(mx6q_sd3_100mhz);
 195                 sd3_pads_50mhz_cnt = ARRAY_SIZE(mx6q_sd3_50mhz);
 196         } else if (cpu_is_mx6dl()) {
 197                 sd3_pads_200mhz = mx6dl_sd3_200mhz;
 198                 sd3_pads_100mhz = mx6dl_sd3_100mhz;
 199                 sd3_pads_50mhz = mx6dl_sd3_50mhz;
 200
 201                 sd3_pads_200mhz_cnt = ARRAY_SIZE(mx6dl_sd3_200mhz);
 202                 sd3_pads_100mhz_cnt = ARRAY_SIZE(mx6dl_sd3_100mhz);
 203                 sd3_pads_50mhz_cnt = ARRAY_SIZE(mx6dl_sd3_50mhz);
 204         }
 205
 206         if (clock > 100000000) {
 207                 if (pad_mode == SD_PAD_MODE_HIGH_SPEED)
 208                         return 0;
 209                 BUG_ON(!sd3_pads_200mhz);
 210                 pad_mode = SD_PAD_MODE_HIGH_SPEED;
 211                 return mxc_iomux_v3_setup_multiple_pads(sd3_pads_200mhz,
 212                                                         sd3_pads_200mhz_cnt);
 213         } else if (clock > 52000000) {
 214                 if (pad_mode == SD_PAD_MODE_MED_SPEED)
 215                         return 0;
 216                 BUG_ON(!sd3_pads_100mhz);
 217                 pad_mode = SD_PAD_MODE_MED_SPEED;
 218                 return mxc_iomux_v3_setup_multiple_pads(sd3_pads_100mhz,
 219                                                         sd3_pads_100mhz_cnt);
 220         } else {
 221                 if (pad_mode == SD_PAD_MODE_LOW_SPEED)
 222                         return 0;
 223                 BUG_ON(!sd3_pads_50mhz);
 224                 pad_mode = SD_PAD_MODE_LOW_SPEED;
 225                 return mxc_iomux_v3_setup_multiple_pads(sd3_pads_50mhz,
 226                                                         sd3_pads_50mhz_cnt);
 227         }
 228 }
 229
 230 static int plt_sd4_pad_change(int clock)
 231 {
 232         static enum sd_pad_mode pad_mode = SD_PAD_MODE_LOW_SPEED;
 233
 234         iomux_v3_cfg_t *sd4_pads_200mhz = NULL;
 235         iomux_v3_cfg_t *sd4_pads_100mhz = NULL;
 236         iomux_v3_cfg_t *sd4_pads_50mhz = NULL;
 237
 238         u32 sd4_pads_200mhz_cnt;
 239         u32 sd4_pads_100mhz_cnt;
 240         u32 sd4_pads_50mhz_cnt;
 241
 242         if (cpu_is_mx6q()) {
 243                 sd4_pads_200mhz = mx6q_sd4_200mhz;
 244                 sd4_pads_100mhz = mx6q_sd4_100mhz;
 245                 sd4_pads_50mhz = mx6q_sd4_50mhz;
 246
 247                 sd4_pads_200mhz_cnt = ARRAY_SIZE(mx6q_sd4_200mhz);
 248                 sd4_pads_100mhz_cnt = ARRAY_SIZE(mx6q_sd4_100mhz);
 249                 sd4_pads_50mhz_cnt = ARRAY_SIZE(mx6q_sd4_50mhz);
 250         } else if (cpu_is_mx6dl()) {
 251                 sd4_pads_200mhz = mx6dl_sd4_200mhz;
 252                 sd4_pads_100mhz = mx6dl_sd4_100mhz;
 253                 sd4_pads_50mhz = mx6dl_sd4_50mhz;
 254
 255                 sd4_pads_200mhz_cnt = ARRAY_SIZE(mx6dl_sd4_200mhz);
 256                 sd4_pads_100mhz_cnt = ARRAY_SIZE(mx6dl_sd4_100mhz);
 257                 sd4_pads_50mhz_cnt = ARRAY_SIZE(mx6dl_sd4_50mhz);
 258         }
 259
 260         if (clock > 100000000) {
 261                 if (pad_mode == SD_PAD_MODE_HIGH_SPEED)
 262                         return 0;
 263
 264                 pad_mode = SD_PAD_MODE_HIGH_SPEED;
 265                 return mxc_iomux_v3_setup_multiple_pads(sd4_pads_200mhz,
 266                                                         sd4_pads_200mhz_cnt);
 267         } else if (clock > 52000000) {
 268                 if (pad_mode == SD_PAD_MODE_MED_SPEED)
 269                         return 0;
 270
 271                 pad_mode = SD_PAD_MODE_MED_SPEED;
 272                 return mxc_iomux_v3_setup_multiple_pads(sd4_pads_100mhz,
 273                                                         sd4_pads_100mhz_cnt);
 274         } else {
 275                 if (pad_mode == SD_PAD_MODE_LOW_SPEED)
 276                         return 0;
 277
 278                 pad_mode = SD_PAD_MODE_LOW_SPEED;
 279                 return mxc_iomux_v3_setup_multiple_pads(sd4_pads_50mhz,
 280                                                         sd4_pads_50mhz_cnt);
 281         }
 282 }
 283
 284 static const struct esdhc_platform_data mx6_arm2_sd3_data __initconst = {
 285         .cd_gpio                = MX6_ARM2_SD3_CD,
 286         .wp_gpio                = MX6_ARM2_SD3_WP,
 287         .support_18v            = 1,
 288         .support_8bit           = 1,
 289         .keep_power_at_suspend  = 1,
 290         .delay_line             = 0,
 291         .platform_pad_change    = plt_sd3_pad_change,
 292 };
 293
 294 /* No card detect signal for SD4 on ARM2 board*/
 295 static const struct esdhc_platform_data mx6_arm2_sd4_data __initconst = {
 296         .always_present         = 1,
 297         .support_8bit           = 1,
 298         .keep_power_at_suspend  = 1,
 299         .platform_pad_change    = plt_sd4_pad_change,
 300 };
 301
 302 static int __init gpmi_nand_platform_init(void)
 303 {
 304         iomux_v3_cfg_t *nand_pads = NULL;
 305         u32 nand_pads_cnt;
 306
 307         if (cpu_is_mx6q()) {
 308                 nand_pads = mx6q_gpmi_nand;
 309                 nand_pads_cnt = ARRAY_SIZE(mx6dl_gpmi_nand);
 310         } else if (cpu_is_mx6dl()) {
 311                 nand_pads = mx6dl_gpmi_nand;
 312                 nand_pads_cnt = ARRAY_SIZE(mx6dl_gpmi_nand);
 313
 314         }
 315         BUG_ON(!nand_pads);
 316         return mxc_iomux_v3_setup_multiple_pads(nand_pads, nand_pads_cnt);
 317 }
 318
 319 static const struct gpmi_nand_platform_data
 320 mx6_gpmi_nand_platform_data __initconst = {
 321         .platform_init           = gpmi_nand_platform_init,
 322         .min_prop_delay_in_ns    = 5,
 323         .max_prop_delay_in_ns    = 9,
 324         .max_chip_count          = 1,
 325         .enable_bbt              = 1,
 326 };
 327
 328 static const struct anatop_thermal_platform_data
 329         mx6_arm2_anatop_thermal_data __initconst = {
 330         .name = "anatop_thermal",
 331 };
 332
 333 static const struct imxuart_platform_data mx6_arm2_uart1_data __initconst = {
 334         .flags      = IMXUART_HAVE_RTSCTS | IMXUART_USE_DCEDTE | IMXUART_SDMA,
 335         .dma_req_rx = MX6Q_DMA_REQ_UART2_RX,
 336         .dma_req_tx = MX6Q_DMA_REQ_UART2_TX,
 337 };
 338
 339 static inline void mx6_arm2_init_uart(void)
 340 {
 341         imx6q_add_imx_uart(3, NULL);
 342         imx6q_add_imx_uart(1, &mx6_arm2_uart1_data);
 343 }
 344
 345 static int mx6_arm2_fec_phy_init(struct phy_device *phydev)
 346 {
 347         unsigned short val;
 348
 349         /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
 350         phy_write(phydev, 0xd, 0x7);
 351         phy_write(phydev, 0xe, 0x8016);
 352         phy_write(phydev, 0xd, 0x4007);
 353         val = phy_read(phydev, 0xe);
 354
 355         val &= 0xffe3;
 356         val |= 0x18;
 357         phy_write(phydev, 0xe, val);
 358
 359         /* introduce tx clock delay */
 360         phy_write(phydev, 0x1d, 0x5);
 361         val = phy_read(phydev, 0x1e);
 362         val |= 0x0100;
 363         phy_write(phydev, 0x1e, val);
 364
 365         /*check phy power*/
 366         val = phy_read(phydev, 0x0);
 367         if (val & BMCR_PDOWN)
 368                 phy_write(phydev, 0x0, (val & ~BMCR_PDOWN));
 369         return 0;
 370 }
 371
 372 static int mx6_arm2_fec_power_hibernate(struct phy_device *phydev)
 373 {
 374         unsigned short val;
 375
 376         /*set AR8031 debug reg 0xb to hibernate power*/
 377         phy_write(phydev, 0x1d, 0xb);
 378         val = phy_read(phydev, 0x1e);
 379
 380         val |= 0x8000;
 381         phy_write(phydev, 0x1e, val);
 382
 383         return 0;
 384 }
 385
 386 static struct fec_platform_data fec_data __initdata = {
 387         .init                   = mx6_arm2_fec_phy_init,
 388         .power_hibernate        = mx6_arm2_fec_power_hibernate,
 389         .phy                    = PHY_INTERFACE_MODE_RGMII,
 390 };
 391
 392 static int mx6_arm2_spi_cs[] = {
 393         MX6_ARM2_ECSPI1_CS0,
 394         MX6_ARM2_ECSPI1_CS1,
 395 };
 396
 397 static const struct spi_imx_master mx6_arm2_spi_data __initconst = {
 398         .chipselect     = mx6_arm2_spi_cs,
 399         .num_chipselect = ARRAY_SIZE(mx6_arm2_spi_cs),
 400 };
 401
 402 #if defined(CONFIG_MTD_M25P80) || defined(CONFIG_MTD_M25P80_MODULE)
 403 static struct mtd_partition m25p32_partitions[] = {
 404         {
 405                 .name   = "bootloader",
 406                 .offset = 0,
 407                 .size   = 0x00040000,
 408         }, {
 409                 .name   = "kernel",
 410                 .offset = MTDPART_OFS_APPEND,
 411                 .size   = MTDPART_SIZ_FULL,
 412         },
 413 };
 414
 415 static struct flash_platform_data m25p32_spi_flash_data = {
 416         .name           = "m25p32",
 417         .parts          = m25p32_partitions,
 418         .nr_parts       = ARRAY_SIZE(m25p32_partitions),
 419         .type           = "m25p32",
 420 };
 421 #endif
 422
 423 static struct spi_board_info m25p32_spi0_board_info[] __initdata = {
 424 #if defined(CONFIG_MTD_M25P80)
 425         {
 426         /* The modalias must be the same as spi device driver name */
 427         .modalias       = "m25p80",
 428         .max_speed_hz   = 20000000,
 429         .bus_num        = 0,
 430         .chip_select    = 1,
 431         .platform_data  = &m25p32_spi_flash_data,
 432         },
 433 #endif
 434 };
 435
 436 static void spi_device_init(void)
 437 {
 438         spi_register_board_info(m25p32_spi0_board_info,
 439                                 ARRAY_SIZE(m25p32_spi0_board_info));
 440 }
 441
 442 static int max7310_1_setup(struct i2c_client *client,
 443         unsigned gpio_base, unsigned ngpio,
 444         void *context)
 445 {
 446         int max7310_gpio_value[] = { 0, 1, 0, 1, 0, 0, 0, 0 };
 447
 448         int n;
 449
 450          for (n = 0; n < ARRAY_SIZE(max7310_gpio_value); ++n) {
 451                 gpio_request(gpio_base + n, "MAX7310 1 GPIO Expander");
 452                 if (max7310_gpio_value[n] < 0)
 453                         gpio_direction_input(gpio_base + n);
 454                 else
 455                         gpio_direction_output(gpio_base + n,
 456                                                 max7310_gpio_value[n]);
 457                 gpio_export(gpio_base + n, 0);
 458         }
 459
 460         return 0;
 461 }
 462
 463 static struct pca953x_platform_data max7310_platdata = {
 464         .gpio_base      = MX6_ARM2_MAX7310_1_BASE_ADDR,
 465         .invert         = 0,
 466         .setup          = max7310_1_setup,
 467 };
 468
 469 static int max7310_u48_setup(struct i2c_client *client,
 470         unsigned gpio_base, unsigned ngpio,
 471         void *context)
 472 {
 473         int max7310_gpio_value[] = { 1, 1, 1, 1, 0, 1, 0, 0 };
 474
 475         int n;
 476
 477          for (n = 0; n < ARRAY_SIZE(max7310_gpio_value); ++n) {
 478                 gpio_request(gpio_base + n, "MAX7310 U48 GPIO Expander");
 479                 if (max7310_gpio_value[n] < 0)
 480                         gpio_direction_input(gpio_base + n);
 481                 else
 482                         gpio_direction_output(gpio_base + n,
 483                                                 max7310_gpio_value[n]);
 484                 gpio_export(gpio_base + n, 0);
 485         }
 486
 487         return 0;
 488 }
 489
 490 static struct pca953x_platform_data max7310_u48_platdata = {
 491         .gpio_base      = MX6_ARM2_MAX7310_2_BASE_ADDR,
 492         .invert         = 0,
 493         .setup          = max7310_u48_setup,
 494 };
 495
 496 static void ddc_dvi_init(void)
 497 {
 498         /* enable DVI I2C */
 499         gpio_set_value(MX6_ARM2_DISP0_I2C_EN, 1);
 500
 501         /* DISP0 Detect */
 502         gpio_request(MX6_ARM2_DISP0_DET_INT, "disp0-detect");
 503         gpio_direction_input(MX6_ARM2_DISP0_DET_INT);
 504 }
 505
 506 static int ddc_dvi_update(void)
 507 {
 508         /* DVI cable state */
 509         if (gpio_get_value(MX6_ARM2_DISP0_DET_INT) == 1)
 510                 return 1;
 511         return 0;
 512 }
 513
 514 static struct fsl_mxc_dvi_platform_data sabr_ddc_dvi_data = {
 515         .ipu_id         = 0,
 516         .disp_id        = 0,
 517         .init           = ddc_dvi_init,
 518         .update         = ddc_dvi_update,
 519 };
 520
 521 static void mx6_csi0_io_init(void)
 522 {
 523         if (0 == sgtl5000_en) {
 524                 iomux_v3_cfg_t *sensor_pads = NULL;
 525                 u32 sensor_pads_cnt;
 526
 527                 if (cpu_is_mx6q()) {
 528                         sensor_pads = mx6q_arm2_csi0_sensor_pads;
 529                         sensor_pads_cnt = \
 530                                 ARRAY_SIZE(mx6q_arm2_csi0_sensor_pads);
 531                 } else if (cpu_is_mx6dl()) {
 532                         sensor_pads = mx6dl_arm2_csi0_sensor_pads;
 533                         sensor_pads_cnt = \
 534                                 ARRAY_SIZE(mx6dl_arm2_csi0_sensor_pads);
 535                 }
 536
 537                 BUG_ON(!sensor_pads);
 538                 mxc_iomux_v3_setup_multiple_pads(sensor_pads, sensor_pads_cnt);
 539         }
 540         /* Camera reset */
 541         gpio_request(MX6_ARM2_CSI0_RST, "cam-reset");
 542         gpio_direction_output(MX6_ARM2_CSI0_RST, 1);
 543
 544         /* Camera power down */
 545         gpio_request(MX6_ARM2_CSI0_PWN, "cam-pwdn");
 546         gpio_direction_output(MX6_ARM2_CSI0_PWN, 1);
 547         msleep(1);
 548         gpio_set_value(MX6_ARM2_CSI0_PWN, 0);
 549
 550         /* For MX6Q:
 551          * GPR1 bit19 and bit20 meaning:
 552          * Bit19:       0 - Enable mipi to IPU1 CSI0
 553          *                      virtual channel is fixed to 0
 554          *              1 - Enable parallel interface to IPU1 CSI0
 555          * Bit20:       0 - Enable mipi to IPU2 CSI1
 556          *                      virtual channel is fixed to 3
 557          *              1 - Enable parallel interface to IPU2 CSI1
 558          * IPU1 CSI1 directly connect to mipi csi2,
 559          *      virtual channel is fixed to 1
 560          * IPU2 CSI0 directly connect to mipi csi2,
 561          *      virtual channel is fixed to 2
 562          *
 563          * For MX6DL:
 564          * GPR1 bit 21 and GPR13 bit 0-5, RM has detail information
 565          */
 566         if (cpu_is_mx6q())
 567                 mxc_iomux_set_gpr_register(1, 19, 1, 1);
 568         else if (cpu_is_mx6dl())
 569                 mxc_iomux_set_gpr_register(13, 0, 3, 4);
 570 }
 571
 572 static struct fsl_mxc_camera_platform_data camera_data = {
 573         .analog_regulator       = "DA9052_LDO7",
 574         .core_regulator         = "DA9052_LDO9",
 575         .mclk                   = 24000000,
 576         .csi                    = 0,
 577         .io_init                = mx6_csi0_io_init,
 578 };
 579
 580 static void mx6_csi0_tvin_io_init(void)
 581 {
 582         if (0 == sgtl5000_en) {
 583                 iomux_v3_cfg_t *tvin_pads = NULL;
 584                 u32 tvin_pads_cnt;
 585
 586                 if (cpu_is_mx6q()) {
 587                         tvin_pads = mx6q_arm2_csi0_tvin_pads;
 588                         tvin_pads_cnt = \
 589                                 ARRAY_SIZE(mx6q_arm2_csi0_tvin_pads);
 590                 } else if (cpu_is_mx6dl()) {
 591                         tvin_pads = mx6dl_arm2_csi0_tvin_pads;
 592                         tvin_pads_cnt = \
 593                                 ARRAY_SIZE(mx6dl_arm2_csi0_tvin_pads);
 594                 }
 595
 596                 BUG_ON(!tvin_pads);
 597                 mxc_iomux_v3_setup_multiple_pads(tvin_pads, tvin_pads_cnt);
 598         }
 599         /* Tvin reset */
 600         gpio_request(MX6_ARM2_CSI0_RST_TVIN, "tvin-reset");
 601         gpio_direction_output(MX6_ARM2_CSI0_RST_TVIN, 1);
 602
 603         /* Tvin power down */
 604         gpio_request(MX6_ARM2_CSI0_PWN, "cam-pwdn");
 605         gpio_direction_output(MX6_ARM2_CSI0_PWN, 0);
 606         msleep(1);
 607         gpio_set_value(MX6_ARM2_CSI0_PWN, 1);
 608
 609         if (cpu_is_mx6q())
 610                 mxc_iomux_set_gpr_register(1, 19, 1, 1);
 611         else if (cpu_is_mx6dl())
 612                 mxc_iomux_set_gpr_register(13, 0, 3, 4);
 613 }
 614
 615 static struct fsl_mxc_tvin_platform_data tvin_data = {
 616         .io_init = mx6_csi0_tvin_io_init,
 617         .cvbs = false,
 618 };
 619
 620 static void mx6_mipi_sensor_io_init(void)
 621 {
 622         iomux_v3_cfg_t *mipi_sensor_pads = NULL;
 623         u32 mipi_sensor_pads_cnt;
 624
 625         if (cpu_is_mx6q()) {
 626                 mipi_sensor_pads = mx6q_arm2_mipi_sensor_pads;
 627                 mipi_sensor_pads_cnt = ARRAY_SIZE(mx6q_arm2_mipi_sensor_pads);
 628         } else if (cpu_is_mx6dl()) {
 629                 mipi_sensor_pads = mx6dl_arm2_mipi_sensor_pads;
 630                 mipi_sensor_pads_cnt = ARRAY_SIZE(mx6dl_arm2_mipi_sensor_pads);
 631
 632         }
 633         BUG_ON(!mipi_sensor_pads);
 634         mxc_iomux_v3_setup_multiple_pads(mipi_sensor_pads,
 635                                         mipi_sensor_pads_cnt);
 636
 637         if (cpu_is_mx6q())
 638                 mxc_iomux_set_gpr_register(1, 19, 1, 0);
 639         if (cpu_is_mx6dl())
 640                 mxc_iomux_set_gpr_register(13, 0, 3, 0);
 641 }
 642
 643 static struct fsl_mxc_camera_platform_data ov5640_mipi_data = {
 644         .mclk           = 24000000,
 645         .csi            = 0,
 646         .io_init        = mx6_mipi_sensor_io_init,
 647 };
 648
 649 static struct mxc_audio_codec_platform_data cs42888_data = {
 650         .rates = (SNDRV_PCM_RATE_44100 |
 651                         SNDRV_PCM_RATE_88200 |
 652                         SNDRV_PCM_RATE_176400),
 653 };
 654
 655 #define mV_to_uV(mV) (mV * 1000)
 656 #define uV_to_mV(uV) (uV / 1000)
 657 #define V_to_uV(V) (mV_to_uV(V * 1000))
 658 #define uV_to_V(uV) (uV_to_mV(uV) / 1000)
 659
 660 static struct regulator_consumer_supply display_consumers[] = {
 661         {
 662                 /* MAX17135 */
 663                 .supply = "DISPLAY",
 664         },
 665 };
 666
 667 static struct regulator_consumer_supply vcom_consumers[] = {
 668         {
 669                 /* MAX17135 */
 670                 .supply = "VCOM",
 671         },
 672 };
 673
 674 static struct regulator_consumer_supply v3p3_consumers[] = {
 675         {
 676                 /* MAX17135 */
 677                 .supply = "V3P3",
 678         },
 679 };
 680
 681 static struct regulator_init_data max17135_init_data[] = {
 682         {
 683                 .constraints = {
 684                         .name = "DISPLAY",
 685                         .valid_ops_mask =  REGULATOR_CHANGE_STATUS,
 686                 },
 687                 .num_consumer_supplies = ARRAY_SIZE(display_consumers),
 688                 .consumer_supplies = display_consumers,
 689         }, {
 690                 .constraints = {
 691                         .name = "GVDD",
 692                         .min_uV = V_to_uV(20),
 693                         .max_uV = V_to_uV(20),
 694                 },
 695         }, {
 696                 .constraints = {
 697                         .name = "GVEE",
 698                         .min_uV = V_to_uV(-22),
 699                         .max_uV = V_to_uV(-22),
 700                 },
 701         }, {
 702                 .constraints = {
 703                         .name = "HVINN",
 704                         .min_uV = V_to_uV(-22),
 705                         .max_uV = V_to_uV(-22),
 706                 },
 707         }, {
 708                 .constraints = {
 709                         .name = "HVINP",
 710                         .min_uV = V_to_uV(20),
 711                         .max_uV = V_to_uV(20),
 712                 },
 713         }, {
 714                 .constraints = {
 715                         .name = "VCOM",
 716                         .min_uV = mV_to_uV(-4325),
 717                         .max_uV = mV_to_uV(-500),
 718                         .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
 719                         REGULATOR_CHANGE_STATUS,
 720                 },
 721                 .num_consumer_supplies = ARRAY_SIZE(vcom_consumers),
 722                 .consumer_supplies = vcom_consumers,
 723         }, {
 724                 .constraints = {
 725                         .name = "VNEG",
 726                         .min_uV = V_to_uV(-15),
 727                         .max_uV = V_to_uV(-15),
 728                 },
 729         }, {
 730                 .constraints = {
 731                         .name = "VPOS",
 732                         .min_uV = V_to_uV(15),
 733                         .max_uV = V_to_uV(15),
 734                 },
 735         }, {
 736                 .constraints = {
 737                         .name = "V3P3",
 738                         .valid_ops_mask =  REGULATOR_CHANGE_STATUS,
 739                 },
 740                 .num_consumer_supplies = ARRAY_SIZE(v3p3_consumers),
 741                 .consumer_supplies = v3p3_consumers,
 742         },
 743 };
 744
 745 static struct platform_device max17135_sensor_device = {
 746         .name = "max17135_sensor",
 747         .id = 0,
 748 };
 749
 750 static struct max17135_platform_data max17135_pdata __initdata = {
 751         .vneg_pwrup = 1,
 752         .gvee_pwrup = 1,
 753         .vpos_pwrup = 2,
 754         .gvdd_pwrup = 1,
 755         .gvdd_pwrdn = 1,
 756         .vpos_pwrdn = 2,
 757         .gvee_pwrdn = 1,
 758         .vneg_pwrdn = 1,
 759         .gpio_pmic_pwrgood = MX6DL_ARM2_EPDC_PWRSTAT,
 760         .gpio_pmic_vcom_ctrl = MX6DL_ARM2_EPDC_VCOM,
 761         .gpio_pmic_wakeup = MX6DL_ARM2_EPDC_PMIC_WAKE,
 762         .gpio_pmic_v3p3 = MX6DL_ARM2_EPDC_PWRCTRL0,
 763         .gpio_pmic_intr = MX6DL_ARM2_EPDC_PMIC_INT,
 764         .regulator_init = max17135_init_data,
 765         .init = max17135_regulator_init,
 766 };
 767
 768 static int __init max17135_regulator_init(struct max17135 *max17135)
 769 {
 770         struct max17135_platform_data *pdata = &max17135_pdata;
 771         int i, ret;
 772
 773         if (!epdc_enabled) {
 774                 printk(KERN_DEBUG
 775                         "max17135_regulator_init abort: EPDC not enabled\n");
 776                 return 0;
 777         }
 778
 779         max17135->gvee_pwrup = pdata->gvee_pwrup;
 780         max17135->vneg_pwrup = pdata->vneg_pwrup;
 781         max17135->vpos_pwrup = pdata->vpos_pwrup;
 782         max17135->gvdd_pwrup = pdata->gvdd_pwrup;
 783         max17135->gvdd_pwrdn = pdata->gvdd_pwrdn;
 784         max17135->vpos_pwrdn = pdata->vpos_pwrdn;
 785         max17135->vneg_pwrdn = pdata->vneg_pwrdn;
 786         max17135->gvee_pwrdn = pdata->gvee_pwrdn;
 787
 788         max17135->max_wait = pdata->vpos_pwrup + pdata->vneg_pwrup +
 789                 pdata->gvdd_pwrup + pdata->gvee_pwrup;
 790
 791         max17135->gpio_pmic_pwrgood = pdata->gpio_pmic_pwrgood;
 792         max17135->gpio_pmic_vcom_ctrl = pdata->gpio_pmic_vcom_ctrl;
 793         max17135->gpio_pmic_wakeup = pdata->gpio_pmic_wakeup;
 794         max17135->gpio_pmic_v3p3 = pdata->gpio_pmic_v3p3;
 795         max17135->gpio_pmic_intr = pdata->gpio_pmic_intr;
 796
 797         gpio_request(max17135->gpio_pmic_wakeup, "epdc-pmic-wake");
 798         gpio_direction_output(max17135->gpio_pmic_wakeup, 0);
 799
 800         gpio_request(max17135->gpio_pmic_vcom_ctrl, "epdc-vcom");
 801         gpio_direction_output(max17135->gpio_pmic_vcom_ctrl, 0);
 802
 803         gpio_request(max17135->gpio_pmic_v3p3, "epdc-v3p3");
 804         gpio_direction_output(max17135->gpio_pmic_v3p3, 0);
 805
 806         gpio_request(max17135->gpio_pmic_intr, "epdc-pmic-int");
 807         gpio_direction_input(max17135->gpio_pmic_intr);
 808
 809         gpio_request(max17135->gpio_pmic_pwrgood, "epdc-pwrstat");
 810         gpio_direction_input(max17135->gpio_pmic_pwrgood);
 811
 812         max17135->vcom_setup = false;
 813         max17135->init_done = false;
 814
 815         for (i = 0; i < MAX17135_NUM_REGULATORS; i++) {
 816                 ret = max17135_register_regulator(max17135, i,
 817                         &pdata->regulator_init[i]);
 818                 if (ret != 0) {
 819                         printk(KERN_ERR"max17135 regulator init failed: %d\n",
 820                                 ret);
 821                         return ret;
 822                 }
 823         }
 824
 825         regulator_has_full_constraints();
 826
 827         return 0;
 828 }
 829
 830 static int sii902x_get_pins(void)
 831 {
 832         /* Sii902x HDMI controller */
 833         gpio_request(MX6_ARM2_DISP0_RESET, "disp0-reset");
 834         gpio_direction_output(MX6_ARM2_DISP0_RESET, 0);
 835         gpio_request(MX6_ARM2_DISP0_DET_INT, "disp0-detect");
 836         gpio_direction_input(MX6_ARM2_DISP0_DET_INT);
 837         return 1;
 838 }
 839
 840 static void sii902x_put_pins(void)
 841 {
 842         gpio_free(MX6_ARM2_DISP0_RESET);
 843         gpio_free(MX6_ARM2_DISP0_DET_INT);
 844 }
 845
 846 static void sii902x_hdmi_reset(void)
 847 {
 848        gpio_set_value(MX6_ARM2_DISP0_RESET, 0);
 849        msleep(10);
 850        gpio_set_value(MX6_ARM2_DISP0_RESET, 1);
 851        msleep(10);
 852 }
 853
 854 static struct fsl_mxc_lcd_platform_data sii902x_hdmi_data = {
 855         .ipu_id = 0,
 856         .disp_id = 0,
 857         .reset = sii902x_hdmi_reset,
 858         .get_pins = sii902x_get_pins,
 859         .put_pins = sii902x_put_pins,
 860 };
 861
 862 static struct i2c_board_info mxc_i2c0_board_info[] __initdata = {
 863         {
 864                 I2C_BOARD_INFO("cs42888", 0x48),
 865                 .platform_data = (void *)&cs42888_data,
 866         }, {
 867                 I2C_BOARD_INFO("ov5640", 0x3c),
 868                 .platform_data = (void *)&camera_data,
 869         }, {
 870                 I2C_BOARD_INFO("adv7180", 0x21),
 871                 .platform_data = (void *)&tvin_data,
 872         },
 873 };
 874
 875 static struct imxi2c_platform_data mx6_arm2_i2c0_data = {
 876         .bitrate = 100000,
 877 };
 878
 879 static struct imxi2c_platform_data mx6_arm2_i2c1_data = {
 880         .bitrate = 100000,
 881 };
 882
 883 static struct imxi2c_platform_data mx6_arm2_i2c2_data = {
 884         .bitrate = 400000,
 885 };
 886
 887 static struct i2c_board_info mxc_i2c2_board_info[] __initdata = {
 888         {
 889                 I2C_BOARD_INFO("max17135", 0x48),
 890                 .platform_data = &max17135_pdata,
 891         }, {
 892                 I2C_BOARD_INFO("max7310", 0x1F),
 893                 .platform_data = &max7310_platdata,
 894         }, {
 895                 I2C_BOARD_INFO("max7310", 0x1B),
 896                 .platform_data = &max7310_u48_platdata,
 897         }, {
 898                 I2C_BOARD_INFO("mxc_dvi", 0x50),
 899                 .platform_data = &sabr_ddc_dvi_data,
 900                 .irq = gpio_to_irq(MX6_ARM2_DISP0_DET_INT),
 901         }, {
 902                 I2C_BOARD_INFO("egalax_ts", 0x4),
 903                 .irq = gpio_to_irq(MX6_ARM2_CAP_TCH_INT),
 904         }, {
 905                 I2C_BOARD_INFO("sii902x", 0x39),
 906                 .platform_data = &sii902x_hdmi_data,
 907                 .irq = gpio_to_irq(MX6_ARM2_DISP0_DET_INT),
 908         },
 909 };
 910
 911 static struct i2c_board_info mxc_i2c1_board_info[] __initdata = {
 912         {
 913                 I2C_BOARD_INFO("egalax_ts", 0x4),
 914                 .irq = gpio_to_irq(MX6_ARM2_CAP_TCH_INT),
 915         }, {
 916                 I2C_BOARD_INFO("mxc_hdmi_i2c", 0x50),
 917         }, {
 918                 I2C_BOARD_INFO("ov5640_mipi", 0x3c),
 919                 .platform_data = (void *)&ov5640_mipi_data,
 920         }, {
 921                 I2C_BOARD_INFO("sgtl5000", 0x0a),
 922         },
 923 };
 924
 925 static int epdc_get_pins(void)
 926 {
 927         int ret = 0;
 928
 929         /* Claim GPIOs for EPDC pins - used during power up/down */
 930         ret |= gpio_request(MX6DL_ARM2_EPDC_SDDO_0, "epdc_d0");
 931         ret |= gpio_request(MX6DL_ARM2_EPDC_SDDO_1, "epdc_d1");
 932         ret |= gpio_request(MX6DL_ARM2_EPDC_SDDO_2, "epdc_d2");
 933         ret |= gpio_request(MX6DL_ARM2_EPDC_SDDO_3, "epdc_d3");
 934         ret |= gpio_request(MX6DL_ARM2_EPDC_SDDO_4, "epdc_d4");
 935         ret |= gpio_request(MX6DL_ARM2_EPDC_SDDO_5, "epdc_d5");
 936         ret |= gpio_request(MX6DL_ARM2_EPDC_SDDO_6, "epdc_d6");
 937         ret |= gpio_request(MX6DL_ARM2_EPDC_SDDO_7, "epdc_d7");
 938         ret |= gpio_request(MX6DL_ARM2_EPDC_GDCLK, "epdc_gdclk");
 939         ret |= gpio_request(MX6DL_ARM2_EPDC_GDSP, "epdc_gdsp");
 940         ret |= gpio_request(MX6DL_ARM2_EPDC_GDOE, "epdc_gdoe");
 941         ret |= gpio_request(MX6DL_ARM2_EPDC_GDRL, "epdc_gdrl");
 942         ret |= gpio_request(MX6DL_ARM2_EPDC_SDCLK, "epdc_sdclk");
 943         ret |= gpio_request(MX6DL_ARM2_EPDC_SDOE, "epdc_sdoe");
 944         ret |= gpio_request(MX6DL_ARM2_EPDC_SDLE, "epdc_sdle");
 945         ret |= gpio_request(MX6DL_ARM2_EPDC_SDSHR, "epdc_sdshr");
 946         ret |= gpio_request(MX6DL_ARM2_EPDC_BDR0, "epdc_bdr0");
 947         ret |= gpio_request(MX6DL_ARM2_EPDC_SDCE0, "epdc_sdce0");
 948         ret |= gpio_request(MX6DL_ARM2_EPDC_SDCE1, "epdc_sdce1");
 949         ret |= gpio_request(MX6DL_ARM2_EPDC_SDCE2, "epdc_sdce2");
 950
 951         return ret;
 952 }
 953
 954 static void epdc_put_pins(void)
 955 {
 956         gpio_free(MX6DL_ARM2_EPDC_SDDO_0);
 957         gpio_free(MX6DL_ARM2_EPDC_SDDO_1);
 958         gpio_free(MX6DL_ARM2_EPDC_SDDO_2);
 959         gpio_free(MX6DL_ARM2_EPDC_SDDO_3);
 960         gpio_free(MX6DL_ARM2_EPDC_SDDO_4);
 961         gpio_free(MX6DL_ARM2_EPDC_SDDO_5);
 962         gpio_free(MX6DL_ARM2_EPDC_SDDO_6);
 963         gpio_free(MX6DL_ARM2_EPDC_SDDO_7);
 964         gpio_free(MX6DL_ARM2_EPDC_GDCLK);
 965         gpio_free(MX6DL_ARM2_EPDC_GDSP);
 966         gpio_free(MX6DL_ARM2_EPDC_GDOE);
 967         gpio_free(MX6DL_ARM2_EPDC_GDRL);
 968         gpio_free(MX6DL_ARM2_EPDC_SDCLK);
 969         gpio_free(MX6DL_ARM2_EPDC_SDOE);
 970         gpio_free(MX6DL_ARM2_EPDC_SDLE);
 971         gpio_free(MX6DL_ARM2_EPDC_SDSHR);
 972         gpio_free(MX6DL_ARM2_EPDC_BDR0);
 973         gpio_free(MX6DL_ARM2_EPDC_SDCE0);
 974         gpio_free(MX6DL_ARM2_EPDC_SDCE1);
 975         gpio_free(MX6DL_ARM2_EPDC_SDCE2);
 976 }
 977
 978 static iomux_v3_cfg_t mx6dl_epdc_pads_enabled[] = {
 979         MX6DL_PAD_EIM_A16__EPDC_SDDO_0,
 980         MX6DL_PAD_EIM_DA10__EPDC_SDDO_1,
 981         MX6DL_PAD_EIM_DA12__EPDC_SDDO_2,
 982         MX6DL_PAD_EIM_DA11__EPDC_SDDO_3,
 983         MX6DL_PAD_EIM_LBA__EPDC_SDDO_4,
 984         MX6DL_PAD_EIM_EB2__EPDC_SDDO_5,
 985         MX6DL_PAD_EIM_CS0__EPDC_SDDO_6,
 986         MX6DL_PAD_EIM_RW__EPDC_SDDO_7,
 987         MX6DL_PAD_EIM_CS1__EPDC_SDDO_8,
 988         MX6DL_PAD_EIM_DA15__EPDC_SDDO_9,
 989         MX6DL_PAD_EIM_D16__EPDC_SDDO_10,
 990         MX6DL_PAD_EIM_D23__EPDC_SDDO_11,
 991         MX6DL_PAD_EIM_D19__EPDC_SDDO_12,
 992         MX6DL_PAD_EIM_DA13__EPDC_SDDO_13,
 993         MX6DL_PAD_EIM_DA14__EPDC_SDDO_14,
 994         MX6DL_PAD_EIM_A25__EPDC_SDDO_15,
 995         MX6DL_PAD_EIM_A21__EPDC_GDCLK,
 996         MX6DL_PAD_EIM_A22__EPDC_GDSP,
 997         MX6DL_PAD_EIM_A23__EPDC_GDOE,
 998         MX6DL_PAD_EIM_A24__EPDC_GDRL,
 999         MX6DL_PAD_EIM_D31__EPDC_SDCLK,
1000         MX6DL_PAD_EIM_D27__EPDC_SDOE,
1001         MX6DL_PAD_EIM_DA1__EPDC_SDLE,
1002         MX6DL_PAD_EIM_EB1__EPDC_SDSHR,
1003         MX6DL_PAD_EIM_DA2__EPDC_BDR_0,
1004         MX6DL_PAD_EIM_DA4__EPDC_SDCE_0,
1005         MX6DL_PAD_EIM_DA5__EPDC_SDCE_1,
1006         MX6DL_PAD_EIM_DA6__EPDC_SDCE_2,
1007 };
1008
1009 static iomux_v3_cfg_t mx6dl_epdc_pads_disabled[] = {
1010         MX6DL_PAD_EIM_A16__GPIO_2_22,
1011         MX6DL_PAD_EIM_DA10__GPIO_3_10,
1012         MX6DL_PAD_EIM_DA12__GPIO_3_12,
1013         MX6DL_PAD_EIM_DA11__GPIO_3_11,
1014         MX6DL_PAD_EIM_LBA__GPIO_2_27,
1015         MX6DL_PAD_EIM_EB2__GPIO_2_30,
1016         MX6DL_PAD_EIM_CS0__GPIO_2_23,
1017         MX6DL_PAD_EIM_RW__GPIO_2_26,
1018         MX6DL_PAD_EIM_CS1__GPIO_2_24,
1019         MX6DL_PAD_EIM_DA15__GPIO_3_15,
1020         MX6DL_PAD_EIM_D16__GPIO_3_16,
1021         MX6DL_PAD_EIM_D23__GPIO_3_23,
1022         MX6DL_PAD_EIM_D19__GPIO_3_19,
1023         MX6DL_PAD_EIM_DA13__GPIO_3_13,
1024         MX6DL_PAD_EIM_DA14__GPIO_3_14,
1025         MX6DL_PAD_EIM_A25__GPIO_5_2,
1026         MX6DL_PAD_EIM_A21__GPIO_2_17,
1027         MX6DL_PAD_EIM_A22__GPIO_2_16,
1028         MX6DL_PAD_EIM_A23__GPIO_6_6,
1029         MX6DL_PAD_EIM_A24__GPIO_5_4,
1030         MX6DL_PAD_EIM_D31__GPIO_3_31,
1031         MX6DL_PAD_EIM_D27__GPIO_3_27,
1032         MX6DL_PAD_EIM_DA1__GPIO_3_1,
1033         MX6DL_PAD_EIM_EB1__GPIO_2_29,
1034         MX6DL_PAD_EIM_DA2__GPIO_3_2,
1035         MX6DL_PAD_EIM_DA4__GPIO_3_4,
1036         MX6DL_PAD_EIM_DA5__GPIO_3_5,
1037         MX6DL_PAD_EIM_DA6__GPIO_3_6,
1038 };
1039 static void epdc_enable_pins(void)
1040 {
1041         /* Configure MUX settings to enable EPDC use */
1042         mxc_iomux_v3_setup_multiple_pads(mx6dl_epdc_pads_enabled, \
1043                                 ARRAY_SIZE(mx6dl_epdc_pads_enabled));
1044
1045         gpio_direction_input(MX6DL_ARM2_EPDC_SDDO_0);
1046         gpio_direction_input(MX6DL_ARM2_EPDC_SDDO_1);
1047         gpio_direction_input(MX6DL_ARM2_EPDC_SDDO_2);
1048         gpio_direction_input(MX6DL_ARM2_EPDC_SDDO_3);
1049         gpio_direction_input(MX6DL_ARM2_EPDC_SDDO_4);
1050         gpio_direction_input(MX6DL_ARM2_EPDC_SDDO_5);
1051         gpio_direction_input(MX6DL_ARM2_EPDC_SDDO_6);
1052         gpio_direction_input(MX6DL_ARM2_EPDC_SDDO_7);
1053         gpio_direction_input(MX6DL_ARM2_EPDC_GDCLK);
1054         gpio_direction_input(MX6DL_ARM2_EPDC_GDSP);
1055         gpio_direction_input(MX6DL_ARM2_EPDC_GDOE);
1056         gpio_direction_input(MX6DL_ARM2_EPDC_GDRL);
1057         gpio_direction_input(MX6DL_ARM2_EPDC_SDCLK);
1058         gpio_direction_input(MX6DL_ARM2_EPDC_SDOE);
1059         gpio_direction_input(MX6DL_ARM2_EPDC_SDLE);
1060         gpio_direction_input(MX6DL_ARM2_EPDC_SDSHR);
1061         gpio_direction_input(MX6DL_ARM2_EPDC_BDR0);
1062         gpio_direction_input(MX6DL_ARM2_EPDC_SDCE0);
1063         gpio_direction_input(MX6DL_ARM2_EPDC_SDCE1);
1064         gpio_direction_input(MX6DL_ARM2_EPDC_SDCE2);
1065 }
1066
1067 static void epdc_disable_pins(void)
1068 {
1069         /* Configure MUX settings for EPDC pins to
1070          * GPIO and drive to 0. */
1071         mxc_iomux_v3_setup_multiple_pads(mx6dl_epdc_pads_disabled, \
1072                                 ARRAY_SIZE(mx6dl_epdc_pads_disabled));
1073
1074         gpio_direction_output(MX6DL_ARM2_EPDC_SDDO_0, 0);
1075         gpio_direction_output(MX6DL_ARM2_EPDC_SDDO_1, 0);
1076         gpio_direction_output(MX6DL_ARM2_EPDC_SDDO_2, 0);
1077         gpio_direction_output(MX6DL_ARM2_EPDC_SDDO_3, 0);
1078         gpio_direction_output(MX6DL_ARM2_EPDC_SDDO_4, 0);
1079         gpio_direction_output(MX6DL_ARM2_EPDC_SDDO_5, 0);
1080         gpio_direction_output(MX6DL_ARM2_EPDC_SDDO_6, 0);
1081         gpio_direction_output(MX6DL_ARM2_EPDC_SDDO_7, 0);
1082         gpio_direction_output(MX6DL_ARM2_EPDC_GDCLK, 0);
1083         gpio_direction_output(MX6DL_ARM2_EPDC_GDSP, 0);
1084         gpio_direction_output(MX6DL_ARM2_EPDC_GDOE, 0);
1085         gpio_direction_output(MX6DL_ARM2_EPDC_GDRL, 0);
1086         gpio_direction_output(MX6DL_ARM2_EPDC_SDCLK, 0);
1087         gpio_direction_output(MX6DL_ARM2_EPDC_SDOE, 0);
1088         gpio_direction_output(MX6DL_ARM2_EPDC_SDLE, 0);
1089         gpio_direction_output(MX6DL_ARM2_EPDC_SDSHR, 0);
1090         gpio_direction_output(MX6DL_ARM2_EPDC_BDR0, 0);
1091         gpio_direction_output(MX6DL_ARM2_EPDC_SDCE0, 0);
1092         gpio_direction_output(MX6DL_ARM2_EPDC_SDCE1, 0);
1093         gpio_direction_output(MX6DL_ARM2_EPDC_SDCE2, 0);
1094 }
1095
1096 static struct fb_videomode e60_v110_mode = {
1097         .name = "E60_V110",
1098         .refresh = 50,
1099         .xres = 800,
1100         .yres = 600,
1101         .pixclock = 18604700,
1102         .left_margin = 8,
1103         .right_margin = 178,
1104         .upper_margin = 4,
1105         .lower_margin = 10,
1106         .hsync_len = 20,
1107         .vsync_len = 4,
1108         .sync = 0,
1109         .vmode = FB_VMODE_NONINTERLACED,
1110         .flag = 0,
1111 };
1112 static struct fb_videomode e60_v220_mode = {
1113         .name = "E60_V220",
1114         .refresh = 85,
1115         .xres = 800,
1116         .yres = 600,
1117         .pixclock = 30000000,
1118         .left_margin = 8,
1119         .right_margin = 164,
1120         .upper_margin = 4,
1121         .lower_margin = 8,
1122         .hsync_len = 4,
1123         .vsync_len = 1,
1124         .sync = 0,
1125         .vmode = FB_VMODE_NONINTERLACED,
1126         .flag = 0,
1127         .refresh = 85,
1128         .xres = 800,
1129         .yres = 600,
1130 };
1131 static struct fb_videomode e060scm_mode = {
1132         .name = "E060SCM",
1133         .refresh = 85,
1134         .xres = 800,
1135         .yres = 600,
1136         .pixclock = 26666667,
1137         .left_margin = 8,
1138         .right_margin = 100,
1139         .upper_margin = 4,
1140         .lower_margin = 8,
1141         .hsync_len = 4,
1142         .vsync_len = 1,
1143         .sync = 0,
1144         .vmode = FB_VMODE_NONINTERLACED,
1145         .flag = 0,
1146 };
1147 static struct fb_videomode e97_v110_mode = {
1148         .name = "E97_V110",
1149         .refresh = 50,
1150         .xres = 1200,
1151         .yres = 825,
1152         .pixclock = 32000000,
1153         .left_margin = 12,
1154         .right_margin = 128,
1155         .upper_margin = 4,
1156         .lower_margin = 10,
1157         .hsync_len = 20,
1158         .vsync_len = 4,
1159         .sync = 0,
1160         .vmode = FB_VMODE_NONINTERLACED,
1161         .flag = 0,
1162 };
1163
1164 static struct imx_epdc_fb_mode panel_modes[] = {
1165         {
1166                 &e60_v110_mode,
1167                 4,      /* vscan_holdoff */
1168                 10,     /* sdoed_width */
1169                 20,     /* sdoed_delay */
1170                 10,     /* sdoez_width */
1171                 20,     /* sdoez_delay */
1172                 428,    /* gdclk_hp_offs */
1173                 20,     /* gdsp_offs */
1174                 0,      /* gdoe_offs */
1175                 1,      /* gdclk_offs */
1176                 1,      /* num_ce */
1177         },
1178         {
1179                 &e60_v220_mode,
1180                 4,      /* vscan_holdoff */
1181                 10,     /* sdoed_width */
1182                 20,     /* sdoed_delay */
1183                 10,     /* sdoez_width */
1184                 20,     /* sdoez_delay */
1185                 465,    /* gdclk_hp_offs */
1186                 20,     /* gdsp_offs */
1187                 0,      /* gdoe_offs */
1188                 9,      /* gdclk_offs */
1189                 1,      /* num_ce */
1190         },
1191         {
1192                 &e060scm_mode,
1193                 4,      /* vscan_holdoff */
1194                 10,     /* sdoed_width */
1195                 20,     /* sdoed_delay */
1196                 10,     /* sdoez_width */
1197                 20,     /* sdoez_delay */
1198                 419,    /* gdclk_hp_offs */
1199                 20,     /* gdsp_offs */
1200                 0,      /* gdoe_offs */
1201                 5,      /* gdclk_offs */
1202                 1,      /* num_ce */
1203         },
1204         {
1205                 &e97_v110_mode,
1206                 8,      /* vscan_holdoff */
1207                 10,     /* sdoed_width */
1208                 20,     /* sdoed_delay */
1209                 10,     /* sdoez_width */
1210                 20,     /* sdoez_delay */
1211                 632,    /* gdclk_hp_offs */
1212                 20,     /* gdsp_offs */
1213                 0,      /* gdoe_offs */
1214                 1,      /* gdclk_offs */
1215                 3,      /* num_ce */
1216         }
1217 };
1218
1219 static struct imx_epdc_fb_platform_data epdc_data = {
1220         .epdc_mode = panel_modes,
1221         .num_modes = ARRAY_SIZE(panel_modes),
1222         .get_pins = epdc_get_pins,
1223         .put_pins = epdc_put_pins,
1224         .enable_pins = epdc_enable_pins,
1225         .disable_pins = epdc_disable_pins,
1226 };
1227
1228 static void imx6_arm2_usbotg_vbus(bool on)
1229 {
1230         if (on)
1231                 gpio_set_value(MX6_ARM2_USB_OTG_PWR, 1);
1232         else
1233                 gpio_set_value(MX6_ARM2_USB_OTG_PWR, 0);
1234 }
1235
1236 static void __init mx6_arm2_init_usb(void)
1237 {
1238         int ret = 0;
1239
1240         imx_otg_base = MX6_IO_ADDRESS(MX6Q_USB_OTG_BASE_ADDR);
1241
1242         /* disable external charger detect,
1243          * or it will affect signal quality at dp.
1244          */
1245
1246         ret = gpio_request(MX6_ARM2_USB_OTG_PWR, "usb-pwr");
1247         if (ret) {
1248                 pr_err("failed to get GPIO MX6_ARM2_USB_OTG_PWR:%d\n", ret);
1249                 return;
1250         }
1251         gpio_direction_output(MX6_ARM2_USB_OTG_PWR, 0);
1252         mxc_iomux_set_gpr_register(1, 13, 1, 1);
1253
1254         mx6_set_otghost_vbus_func(imx6_arm2_usbotg_vbus);
1255         mx6_usb_dr_init();
1256         mx6_usb_h1_init();
1257 #ifdef CONFIG_USB_EHCI_ARC_HSIC
1258         mx6_usb_h2_init();
1259         mx6_usb_h3_init();
1260 #endif
1261 }
1262
1263 static struct viv_gpu_platform_data imx6_gpu_pdata __initdata = {
1264         .reserved_mem_size = SZ_128M,
1265 };
1266
1267 /* HW Initialization, if return 0, initialization is successful. */
1268 static int mx6_arm2_sata_init(struct device *dev, void __iomem *addr)
1269 {
1270         u32 tmpdata;
1271         int ret = 0;
1272         struct clk *clk;
1273
1274         /* Enable SATA PWR CTRL_0 of MAX7310 */
1275         gpio_request(MX6_ARM2_MAX7310_1_BASE_ADDR, "SATA_PWR_EN");
1276         gpio_direction_output(MX6_ARM2_MAX7310_1_BASE_ADDR, 1);
1277
1278         sata_clk = clk_get(dev, "imx_sata_clk");
1279         if (IS_ERR(sata_clk)) {
1280                 dev_err(dev, "no sata clock.\n");
1281                 return PTR_ERR(sata_clk);
1282         }
1283         ret = clk_enable(sata_clk);
1284         if (ret) {
1285                 dev_err(dev, "can't enable sata clock.\n");
1286                 goto put_sata_clk;
1287         }
1288
1289         /* Set PHY Paremeters, two steps to configure the GPR13,
1290          * one write for rest of parameters, mask of first write is 0x07FFFFFD,
1291          * and the other one write for setting the mpll_clk_off_b
1292          *.rx_eq_val_0(iomuxc_gpr13[26:24]),
1293          *.los_lvl(iomuxc_gpr13[23:19]),
1294          *.rx_dpll_mode_0(iomuxc_gpr13[18:16]),
1295          *.sata_speed(iomuxc_gpr13[15]),
1296          *.mpll_ss_en(iomuxc_gpr13[14]),
1297          *.tx_atten_0(iomuxc_gpr13[13:11]),
1298          *.tx_boost_0(iomuxc_gpr13[10:7]),
1299          *.tx_lvl(iomuxc_gpr13[6:2]),
1300          *.mpll_ck_off(iomuxc_gpr13[1]),
1301          *.tx_edgerate_0(iomuxc_gpr13[0]),
1302          */
1303         tmpdata = readl(IOMUXC_GPR13);
1304         writel(((tmpdata & ~0x07FFFFFD) | 0x0593A044), IOMUXC_GPR13);
1305
1306         /* enable SATA_PHY PLL */
1307         tmpdata = readl(IOMUXC_GPR13);
1308         writel(((tmpdata & ~0x2) | 0x2), IOMUXC_GPR13);
1309
1310         /* Get the AHB clock rate, and configure the TIMER1MS reg later */
1311         clk = clk_get(NULL, "ahb");
1312         if (IS_ERR(clk)) {
1313                 dev_err(dev, "no ahb clock.\n");
1314                 ret = PTR_ERR(clk);
1315                 goto release_sata_clk;
1316         }
1317         tmpdata = clk_get_rate(clk) / 1000;
1318         clk_put(clk);
1319
1320         ret = sata_init(addr, tmpdata);
1321         if (ret == 0)
1322                 return ret;
1323
1324 release_sata_clk:
1325         clk_disable(sata_clk);
1326 put_sata_clk:
1327         clk_put(sata_clk);
1328         /* Disable SATA PWR CTRL_0 of MAX7310 */
1329         gpio_request(MX6_ARM2_MAX7310_1_BASE_ADDR, "SATA_PWR_EN");
1330         gpio_direction_output(MX6_ARM2_MAX7310_1_BASE_ADDR, 0);
1331
1332         return ret;
1333 }
1334
1335 static void mx6_arm2_sata_exit(struct device *dev)
1336 {
1337         clk_disable(sata_clk);
1338         clk_put(sata_clk);
1339
1340         /* Disable SATA PWR CTRL_0 of MAX7310 */
1341         gpio_request(MX6_ARM2_MAX7310_1_BASE_ADDR, "SATA_PWR_EN");
1342         gpio_direction_output(MX6_ARM2_MAX7310_1_BASE_ADDR, 0);
1343
1344 }
1345
1346 static struct ahci_platform_data mx6_arm2_sata_data = {
1347         .init   = mx6_arm2_sata_init,
1348         .exit   = mx6_arm2_sata_exit,
1349 };
1350
1351 static struct imx_asrc_platform_data imx_asrc_data = {
1352         .channel_bits   = 4,
1353         .clk_map_ver    = 2,
1354 };
1355
1356 static void mx6_arm2_reset_mipi_dsi(void)
1357 {
1358         gpio_set_value(MX6_ARM2_DISP0_PWR, 1);
1359         gpio_set_value(MX6_ARM2_DISP0_RESET, 1);
1360         udelay(10);
1361         gpio_set_value(MX6_ARM2_DISP0_RESET, 0);
1362         udelay(50);
1363         gpio_set_value(MX6_ARM2_DISP0_RESET, 1);
1364
1365         /*
1366          * it needs to delay 120ms minimum for reset complete
1367          */
1368         msleep(120);
1369 }
1370
1371 static struct mipi_dsi_platform_data mipi_dsi_pdata = {
1372         .ipu_id         = 1,
1373         .disp_id        = 1,
1374         .lcd_panel      = "TRULY-WVGA",
1375         .reset          = mx6_arm2_reset_mipi_dsi,
1376 };
1377
1378 static struct ipuv3_fb_platform_data sabr_fb_data[] = {
1379         { /*fb0*/
1380         .disp_dev               = "ldb",
1381         .interface_pix_fmt      = IPU_PIX_FMT_RGB666,
1382         .mode_str               = "LDB-XGA",
1383         .default_bpp            = 16,
1384         .int_clk                = false,
1385         }, {
1386         .disp_dev               = "mipi_dsi",
1387         .interface_pix_fmt      = IPU_PIX_FMT_RGB24,
1388         .mode_str               = "TRULY-WVGA",
1389         .default_bpp            = 24,
1390         .int_clk                = false,
1391         }, {
1392         .disp_dev               = "ldb",
1393         .interface_pix_fmt      = IPU_PIX_FMT_RGB666,
1394         .mode_str               = "LDB-XGA",
1395         .default_bpp            = 16,
1396         .int_clk                = false,
1397         }, {
1398         .disp_dev               = "lcd",
1399         .interface_pix_fmt      = IPU_PIX_FMT_RGB565,
1400         .mode_str               = "CLAA-WVGA",
1401         .default_bpp            = 16,
1402         .int_clk                = false,
1403         }
1404 };
1405
1406 static void hdmi_init(int ipu_id, int disp_id)
1407 {
1408         int hdmi_mux_setting;
1409         int max_ipu_id = cpu_is_mx6q() ? 1 : 0;
1410
1411         if ((ipu_id > max_ipu_id) || (ipu_id < 0)) {
1412                 pr_err("Invalid IPU select for HDMI: %d. Set to 0\n", ipu_id);
1413                 ipu_id = 0;
1414         }
1415
1416         if ((disp_id > 1) || (disp_id < 0)) {
1417                 pr_err("Invalid DI select for HDMI: %d. Set to 0\n", disp_id);
1418                 disp_id = 0;
1419         }
1420
1421         /* Configure the connection between IPU1/2 and HDMI */
1422         hdmi_mux_setting = 2 * ipu_id + disp_id;
1423
1424         /* GPR3, bits 2-3 = HDMI_MUX_CTL */
1425         mxc_iomux_set_gpr_register(3, 2, 2, hdmi_mux_setting);
1426 }
1427
1428 static struct fsl_mxc_hdmi_platform_data hdmi_data = {
1429         .init           = hdmi_init,
1430 };
1431
1432 static struct fsl_mxc_hdmi_core_platform_data hdmi_core_data = {
1433         .ipu_id         = 0,
1434         .disp_id        = 0,
1435 };
1436
1437 static struct fsl_mxc_lcd_platform_data lcdif_data = {
1438         .ipu_id         = 0,
1439         .disp_id        = 0,
1440         .default_ifmt   = IPU_PIX_FMT_RGB565,
1441 };
1442
1443 static struct fsl_mxc_ldb_platform_data ldb_data = {
1444         .ipu_id         = 1,
1445         .disp_id        = 0,
1446         .ext_ref        = 1,
1447         .mode           = LDB_SEP0,
1448         .sec_ipu_id     = 0,
1449         .sec_disp_id    = 1,
1450 };
1451
1452 static struct imx_ipuv3_platform_data ipu_data[] = {
1453         {
1454         .rev            = 4,
1455         .csi_clk[0]     = "clko_clk",
1456         }, {
1457         .rev            = 4,
1458         .csi_clk[0]     = "clko_clk",
1459         },
1460 };
1461
1462 static struct platform_pwm_backlight_data mx6_arm2_pwm_backlight_data = {
1463         .pwm_id         = 0,
1464         .max_brightness = 255,
1465         .dft_brightness = 128,
1466         .pwm_period_ns  = 50000,
1467 };
1468
1469 static struct gpio mx6_flexcan_gpios[] = {
1470         { MX6_ARM2_CAN1_EN, GPIOF_OUT_INIT_LOW, "flexcan1-en" },
1471         { MX6_ARM2_CAN1_STBY, GPIOF_OUT_INIT_LOW, "flexcan1-stby" },
1472         { MX6_ARM2_CAN2_EN, GPIOF_OUT_INIT_LOW, "flexcan2-en" },
1473 };
1474
1475 static void mx6_flexcan0_switch(int enable)
1476 {
1477         if (enable) {
1478                 gpio_set_value(MX6_ARM2_CAN1_EN, 1);
1479                 gpio_set_value(MX6_ARM2_CAN1_STBY, 1);
1480         } else {
1481                 gpio_set_value(MX6_ARM2_CAN1_EN, 0);
1482                 gpio_set_value(MX6_ARM2_CAN1_STBY, 0);
1483         }
1484 }
1485
1486 static void mx6_flexcan1_switch(int enable)
1487 {
1488         if (enable) {
1489                 gpio_set_value(MX6_ARM2_CAN2_EN, 1);
1490                 gpio_set_value_cansleep(MX6_ARM2_CAN2_STBY, 1);
1491         } else {
1492                 gpio_set_value(MX6_ARM2_CAN2_EN, 0);
1493                 gpio_set_value_cansleep(MX6_ARM2_CAN2_STBY, 0);
1494         }
1495 }
1496
1497 static const struct flexcan_platform_data
1498                 mx6_arm2_flexcan_pdata[] __initconst = {
1499         {
1500                 .transceiver_switch = mx6_flexcan0_switch,
1501         }, {
1502                 .transceiver_switch = mx6_flexcan1_switch,
1503         }
1504 };
1505
1506 static struct mipi_csi2_platform_data mipi_csi2_pdata = {
1507         .ipu_id         = 0,
1508         .csi_id         = 0,
1509         .v_channel      = 0,
1510         .lanes          = 2,
1511         .dphy_clk       = "mipi_pllref_clk",
1512         .pixel_clk      = "emi_clk",
1513 };
1514
1515 static void arm2_suspend_enter(void)
1516 {
1517         /* suspend preparation */
1518 }
1519
1520 static void arm2_suspend_exit(void)
1521 {
1522         /* resmue resore */
1523 }
1524 static const struct pm_platform_data mx6_arm2_pm_data __initconst = {
1525         .name           = "imx_pm",
1526         .suspend_enter  = arm2_suspend_enter,
1527         .suspend_exit   = arm2_suspend_exit,
1528 };
1529
1530 static struct mxc_audio_platform_data sab_audio_data = {
1531         .sysclk = 16934400,
1532 };
1533
1534 static struct platform_device sab_audio_device = {
1535         .name   = "imx-cs42888",
1536 };
1537
1538 static struct imx_esai_platform_data sab_esai_pdata = {
1539         .flags  = IMX_ESAI_NET,
1540 };
1541
1542 static struct regulator_consumer_supply arm2_vmmc_consumers[] = {
1543         REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx.1"),
1544         REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx.2"),
1545         REGULATOR_SUPPLY("vmmc", "sdhci-esdhc-imx.3"),
1546 };
1547
1548 static struct regulator_init_data arm2_vmmc_init = {
1549         .num_consumer_supplies = ARRAY_SIZE(arm2_vmmc_consumers),
1550         .consumer_supplies = arm2_vmmc_consumers,
1551 };
1552
1553 static struct fixed_voltage_config arm2_vmmc_reg_config = {
1554         .supply_name    = "vmmc",
1555         .microvolts     = 3300000,
1556         .gpio           = -1,
1557         .init_data      = &arm2_vmmc_init,
1558 };
1559
1560 static struct platform_device arm2_vmmc_reg_devices = {
1561         .name           = "reg-fixed-voltage",
1562         .id             = 0,
1563         .dev            = {
1564                 .platform_data = &arm2_vmmc_reg_config,
1565         },
1566 };
1567
1568 #ifdef CONFIG_SND_SOC_CS42888
1569
1570 static struct regulator_consumer_supply cs42888_arm2_consumer_va = {
1571         .supply         = "VA",
1572         .dev_name       = "0-0048",
1573 };
1574
1575 static struct regulator_consumer_supply cs42888_arm2_consumer_vd = {
1576         .supply         = "VD",
1577         .dev_name       = "0-0048",
1578 };
1579
1580 static struct regulator_consumer_supply cs42888_arm2_consumer_vls = {
1581         .supply         = "VLS",
1582         .dev_name       = "0-0048",
1583 };
1584
1585 static struct regulator_consumer_supply cs42888_arm2_consumer_vlc = {
1586         .supply         = "VLC",
1587         .dev_name       = "0-0048",
1588 };
1589
1590 static struct regulator_init_data cs42888_arm2_va_reg_initdata = {
1591         .num_consumer_supplies  = 1,
1592         .consumer_supplies      = &cs42888_arm2_consumer_va,
1593 };
1594
1595 static struct regulator_init_data cs42888_arm2_vd_reg_initdata = {
1596         .num_consumer_supplies  = 1,
1597         .consumer_supplies      = &cs42888_arm2_consumer_vd,
1598 };
1599
1600 static struct regulator_init_data cs42888_arm2_vls_reg_initdata = {
1601         .num_consumer_supplies  = 1,
1602         .consumer_supplies      = &cs42888_arm2_consumer_vls,
1603 };
1604
1605 static struct regulator_init_data cs42888_arm2_vlc_reg_initdata = {
1606         .num_consumer_supplies  = 1,
1607         .consumer_supplies      = &cs42888_arm2_consumer_vlc,
1608 };
1609
1610 static struct fixed_voltage_config cs42888_arm2_va_reg_config = {
1611         .supply_name            = "VA",
1612         .microvolts             = 2800000,
1613         .gpio                   = -1,
1614         .init_data              = &cs42888_arm2_va_reg_initdata,
1615 };
1616
1617 static struct fixed_voltage_config cs42888_arm2_vd_reg_config = {
1618         .supply_name            = "VD",
1619         .microvolts             = 2800000,
1620         .gpio                   = -1,
1621         .init_data              = &cs42888_arm2_vd_reg_initdata,
1622 };
1623
1624 static struct fixed_voltage_config cs42888_arm2_vls_reg_config = {
1625         .supply_name            = "VLS",
1626         .microvolts             = 2800000,
1627         .gpio                   = -1,
1628         .init_data              = &cs42888_arm2_vls_reg_initdata,
1629 };
1630
1631 static struct fixed_voltage_config cs42888_arm2_vlc_reg_config = {
1632         .supply_name            = "VLC",
1633         .microvolts             = 2800000,
1634         .gpio                   = -1,
1635         .init_data              = &cs42888_arm2_vlc_reg_initdata,
1636 };
1637
1638 static struct platform_device cs42888_arm2_va_reg_devices = {
1639         .name   = "reg-fixed-voltage",
1640         .id     = 3,
1641         .dev    = {
1642                 .platform_data = &cs42888_arm2_va_reg_config,
1643         },
1644 };
1645
1646 static struct platform_device cs42888_arm2_vd_reg_devices = {
1647         .name   = "reg-fixed-voltage",
1648         .id     = 4,
1649         .dev    = {
1650                 .platform_data = &cs42888_arm2_vd_reg_config,
1651         },
1652 };
1653
1654 static struct platform_device cs42888_arm2_vls_reg_devices = {
1655         .name   = "reg-fixed-voltage",
1656         .id     = 5,
1657         .dev    = {
1658                 .platform_data = &cs42888_arm2_vls_reg_config,
1659         },
1660 };
1661
1662 static struct platform_device cs42888_arm2_vlc_reg_devices = {
1663         .name   = "reg-fixed-voltage",
1664         .id     = 6,
1665         .dev    = {
1666                 .platform_data = &cs42888_arm2_vlc_reg_config,
1667         },
1668 };
1669
1670 #endif /* CONFIG_SND_SOC_CS42888 */
1671
1672 #ifdef CONFIG_SND_SOC_SGTL5000
1673
1674 static struct regulator_consumer_supply sgtl5000_arm2_consumer_vdda = {
1675         .supply         = "VDDA",
1676         .dev_name       = "1-000a",
1677 };
1678
1679 static struct regulator_consumer_supply sgtl5000_arm2_consumer_vddio = {
1680         .supply         = "VDDIO",
1681         .dev_name       = "1-000a",
1682 };
1683
1684 static struct regulator_consumer_supply sgtl5000_arm2_consumer_vddd = {
1685         .supply         = "VDDD",
1686         .dev_name       = "1-000a",
1687 };
1688
1689 static struct regulator_init_data sgtl5000_arm2_vdda_reg_initdata = {
1690         .num_consumer_supplies  = 1,
1691         .consumer_supplies      = &sgtl5000_arm2_consumer_vdda,
1692 };
1693
1694 static struct regulator_init_data sgtl5000_arm2_vddio_reg_initdata = {
1695         .num_consumer_supplies  = 1,
1696         .consumer_supplies      = &sgtl5000_arm2_consumer_vddio,
1697 };
1698
1699 static struct regulator_init_data sgtl5000_arm2_vddd_reg_initdata = {
1700         .num_consumer_supplies  = 1,
1701         .consumer_supplies      = &sgtl5000_arm2_consumer_vddd,
1702 };
1703
1704 static struct fixed_voltage_config sgtl5000_arm2_vdda_reg_config = {
1705         .supply_name            = "VDDA",
1706         .microvolts             = 1800000,
1707         .gpio                   = -1,
1708         .init_data              = &sgtl5000_arm2_vdda_reg_initdata,
1709 };
1710
1711 static struct fixed_voltage_config sgtl5000_arm2_vddio_reg_config = {
1712         .supply_name            = "VDDIO",
1713         .microvolts             = 3300000,
1714         .gpio                   = -1,
1715         .init_data              = &sgtl5000_arm2_vddio_reg_initdata,
1716 };
1717
1718 static struct fixed_voltage_config sgtl5000_arm2_vddd_reg_config = {
1719         .supply_name            = "VDDD",
1720         .microvolts             = 0,
1721         .gpio                   = -1,
1722         .init_data              = &sgtl5000_arm2_vddd_reg_initdata,
1723 };
1724
1725 static struct platform_device sgtl5000_arm2_vdda_reg_devices = {
1726         .name   = "reg-fixed-voltage",
1727         .id     = 7,
1728         .dev    = {
1729                 .platform_data = &sgtl5000_arm2_vdda_reg_config,
1730         },
1731 };
1732
1733 static struct platform_device sgtl5000_arm2_vddio_reg_devices = {
1734         .name   = "reg-fixed-voltage",
1735         .id     = 8,
1736         .dev    = {
1737                 .platform_data = &sgtl5000_arm2_vddio_reg_config,
1738         },
1739 };
1740
1741 static struct platform_device sgtl5000_arm2_vddd_reg_devices = {
1742         .name   = "reg-fixed-voltage",
1743         .id     = 9,
1744         .dev    = {
1745                 .platform_data = &sgtl5000_arm2_vddd_reg_config,
1746         },
1747 };
1748
1749 #endif /* CONFIG_SND_SOC_SGTL5000 */
1750
1751 static struct mxc_audio_platform_data mx6_arm2_audio_data;
1752
1753 static int mx6_arm2_sgtl5000_init(void)
1754 {
1755
1756         mx6_arm2_audio_data.sysclk = 12000000;
1757
1758         return 0;
1759 }
1760
1761 static struct imx_ssi_platform_data mx6_arm2_ssi_pdata = {
1762         .flags = IMX_SSI_DMA | IMX_SSI_SYN,
1763 };
1764
1765 static struct mxc_audio_platform_data mx6_arm2_audio_data = {
1766         .ssi_num = 1,
1767         .src_port = 2,
1768         .ext_port = 3,
1769         .init = mx6_arm2_sgtl5000_init,
1770         .hp_gpio = -1,
1771 };
1772
1773 static struct platform_device mx6_arm2_audio_device = {
1774         .name = "imx-sgtl5000",
1775 };
1776
1777 static int __init mx6_arm2_init_audio(void)
1778 {
1779         struct clk *pll3_pfd, *esai_clk;
1780         mxc_register_device(&sab_audio_device, &sab_audio_data);
1781         imx6q_add_imx_esai(0, &sab_esai_pdata);
1782
1783         esai_clk = clk_get(NULL, "esai_clk");
1784         if (IS_ERR(esai_clk))
1785                 return PTR_ERR(esai_clk);
1786
1787         pll3_pfd = clk_get(NULL, "pll3_pfd_508M");
1788         if (IS_ERR(pll3_pfd))
1789                 return PTR_ERR(pll3_pfd);
1790
1791         clk_set_parent(esai_clk, pll3_pfd);
1792         clk_set_rate(esai_clk, 101647058);
1793
1794 #ifdef CONFIG_SND_SOC_CS42888
1795         platform_device_register(&cs42888_arm2_va_reg_devices);
1796         platform_device_register(&cs42888_arm2_vd_reg_devices);
1797         platform_device_register(&cs42888_arm2_vls_reg_devices);
1798         platform_device_register(&cs42888_arm2_vlc_reg_devices);
1799 #endif
1800
1801         if (sgtl5000_en) {
1802                 /* SSI audio init part */
1803                 mxc_register_device(&mx6_arm2_audio_device,
1804                                 &mx6_arm2_audio_data);
1805                 imx6q_add_imx_ssi(1, &mx6_arm2_ssi_pdata);
1806
1807                 /*
1808                  * AUDMUX3 and CSI0_Camera use the same pin
1809                  * MX6x_PAD_CSI0_DAT5
1810                  */
1811                 if (cpu_is_mx6q()) {
1812                         mxc_iomux_v3_setup_multiple_pads(mx6q_arm2_audmux_pads,
1813                                         ARRAY_SIZE(mx6q_arm2_audmux_pads));
1814                 } else if (cpu_is_mx6dl()) {
1815                         mxc_iomux_v3_setup_multiple_pads(mx6dl_arm2_audmux_pads,
1816                                         ARRAY_SIZE(mx6dl_arm2_audmux_pads));
1817                 }
1818
1819 #ifdef CONFIG_SND_SOC_SGTL5000
1820         platform_device_register(&sgtl5000_arm2_vdda_reg_devices);
1821         platform_device_register(&sgtl5000_arm2_vddio_reg_devices);
1822         platform_device_register(&sgtl5000_arm2_vddd_reg_devices);
1823 #endif
1824         }
1825
1826         return 0;
1827 }
1828
1829 static int __init early_use_esai_record(char *p)
1830 {
1831         esai_record = 1;
1832         return 0;
1833 }
1834
1835 early_param("esai_record", early_use_esai_record);
1836
1837 static struct mxc_mlb_platform_data mx6_arm2_mlb150_data = {
1838         .reg_nvcc               = NULL,
1839         .mlb_clk                = "mlb150_clk",
1840         .mlb_pll_clk            = "pll6",
1841 };
1842
1843 static struct mxc_dvfs_platform_data arm2_dvfscore_data = {
1844         .reg_id                 = "cpu_vddgp",
1845         .clk1_id                = "cpu_clk",
1846         .clk2_id                = "gpc_dvfs_clk",
1847         .gpc_cntr_offset        = MXC_GPC_CNTR_OFFSET,
1848         .ccm_cdcr_offset        = MXC_CCM_CDCR_OFFSET,
1849         .ccm_cacrr_offset       = MXC_CCM_CACRR_OFFSET,
1850         .ccm_cdhipr_offset      = MXC_CCM_CDHIPR_OFFSET,
1851         .prediv_mask            = 0x1F800,
1852         .prediv_offset          = 11,
1853         .prediv_val             = 3,
1854         .div3ck_mask            = 0xE0000000,
1855         .div3ck_offset          = 29,
1856         .div3ck_val             = 2,
1857         .emac_val               = 0x08,
1858         .upthr_val              = 25,
1859         .dnthr_val              = 9,
1860         .pncthr_val             = 33,
1861         .upcnt_val              = 10,
1862         .dncnt_val              = 10,
1863         .delay_time             = 80,
1864 };
1865
1866 static void __init mx6_arm2_fixup(struct machine_desc *desc, struct tag *tags,
1867                                    char **cmdline, struct meminfo *mi)
1868 {
1869 }
1870
1871 static int __init early_enable_sgtl5000(char *p)
1872 {
1873         sgtl5000_en = 1;
1874         return 0;
1875 }
1876
1877 early_param("sgtl5000", early_enable_sgtl5000);
1878
1879 static int __init early_enable_spdif(char *p)
1880 {
1881         spdif_en = 1;
1882         return 0;
1883 }
1884
1885 early_param("spdif", early_enable_spdif);
1886
1887 static int __init early_enable_can(char *p)
1888 {
1889         flexcan_en = 1;
1890         return 0;
1891 }
1892
1893 early_param("flexcan", early_enable_can);
1894
1895 static int spdif_clk_set_rate(struct clk *clk, unsigned long rate)
1896 {
1897         unsigned long rate_actual;
1898         rate_actual = clk_round_rate(clk, rate);
1899         clk_set_rate(clk, rate_actual);
1900         return 0;
1901 }
1902
1903 static struct mxc_spdif_platform_data mxc_spdif_data = {
1904         .spdif_tx               = 1,            /* enable tx */
1905         .spdif_rx               = 1,            /* enable rx */
1906         /*
1907          * spdif0_clk will be 454.7MHz divided by ccm dividers.
1908          *
1909          * 44.1KHz: 454.7MHz / 7 (ccm) / 23 (spdif) = 44,128 Hz ~ 0.06% error
1910          * 48KHz:   454.7MHz / 4 (ccm) / 37 (spdif) = 48,004 Hz ~ 0.01% error
1911          * 32KHz:   454.7MHz / 6 (ccm) / 37 (spdif) = 32,003 Hz ~ 0.01% error
1912          */
1913         .spdif_clk_44100        = 1,    /* tx clk from spdif0_clk_root */
1914         .spdif_clk_48000        = 1,    /* tx clk from spdif0_clk_root */
1915         .spdif_div_44100        = 23,
1916         .spdif_div_48000        = 37,
1917         .spdif_div_32000        = 37,
1918         .spdif_rx_clk           = 0,    /* rx clk from spdif stream */
1919         .spdif_clk_set_rate     = spdif_clk_set_rate,
1920         .spdif_clk              = NULL, /* spdif bus clk */
1921 };
1922
1923 static int __init early_disable_mipi_dsi(char *p)
1924 {
1925         /*enable on board HDMI*/
1926         /*mulplex pin with mipi disp0_reset we should disable mipi reset*/
1927         disable_mipi_dsi = 1;
1928         return 0;
1929 }
1930
1931 early_param("disable_mipi_dsi", early_disable_mipi_dsi);
1932
1933 /*!
1934  * Board specific initialization.
1935  */
1936 static void __init mx6_arm2_init(void)
1937 {
1938         int i;
1939         int ret;
1940
1941         iomux_v3_cfg_t *common_pads = NULL;
1942         iomux_v3_cfg_t *esai_rec_pads = NULL;
1943         iomux_v3_cfg_t *spdif_pads = NULL;
1944         iomux_v3_cfg_t *flexcan_pads = NULL;
1945         iomux_v3_cfg_t *i2c3_pads = NULL;
1946
1947         int common_pads_cnt;
1948         int esai_rec_pads_cnt;
1949         int spdif_pads_cnt;
1950         int flexcan_pads_cnt;
1951         int i2c3_pads_cnt;
1952
1953
1954         /*
1955          * common pads: pads are non-shared with others on this board
1956          * feature_pds: pads are shared with others on this board
1957          */
1958
1959         if (cpu_is_mx6q()) {
1960                 common_pads = mx6q_arm2_pads;
1961                 esai_rec_pads = mx6q_arm2_esai_record_pads;
1962                 spdif_pads = mx6q_arm2_spdif_pads;
1963                 flexcan_pads = mx6q_arm2_can_pads;
1964                 i2c3_pads = mx6q_arm2_i2c3_pads;
1965
1966                 common_pads_cnt = ARRAY_SIZE(mx6q_arm2_pads);
1967                 esai_rec_pads_cnt = ARRAY_SIZE(mx6q_arm2_esai_record_pads);
1968                 spdif_pads_cnt =  ARRAY_SIZE(mx6q_arm2_spdif_pads);
1969                 flexcan_pads_cnt = ARRAY_SIZE(mx6q_arm2_can_pads);
1970                 i2c3_pads_cnt = ARRAY_SIZE(mx6q_arm2_i2c3_pads);
1971         } else if (cpu_is_mx6dl()) {
1972                 common_pads = mx6dl_arm2_pads;
1973                 esai_rec_pads = mx6dl_arm2_esai_record_pads;
1974                 spdif_pads = mx6dl_arm2_spdif_pads;
1975                 flexcan_pads = mx6dl_arm2_can_pads;
1976                 i2c3_pads = mx6dl_arm2_i2c3_pads;
1977
1978                 common_pads_cnt = ARRAY_SIZE(mx6dl_arm2_pads);
1979                 esai_rec_pads_cnt = ARRAY_SIZE(mx6dl_arm2_esai_record_pads);
1980                 spdif_pads_cnt =  ARRAY_SIZE(mx6dl_arm2_spdif_pads);
1981                 flexcan_pads_cnt = ARRAY_SIZE(mx6dl_arm2_can_pads);
1982                 i2c3_pads_cnt = ARRAY_SIZE(mx6dl_arm2_i2c3_pads);
1983         }
1984
1985         BUG_ON(!common_pads);
1986         mxc_iomux_v3_setup_multiple_pads(common_pads, common_pads_cnt);
1987
1988         if (esai_record) {
1989                 BUG_ON(!esai_rec_pads);
1990                 mxc_iomux_v3_setup_multiple_pads(esai_rec_pads,
1991                                                 esai_rec_pads_cnt);
1992         }
1993
1994         /*
1995          * IEEE-1588 ts_clk, S/PDIF in and i2c3 are mutually exclusive
1996          * because all of them use GPIO_16.
1997          * S/PDIF out and can1 stby are mutually exclusive because both
1998          * use GPIO_17.
1999          */
2000 #ifndef CONFIG_FEC_1588
2001         if (spdif_en) {
2002                 BUG_ON(!spdif_pads);
2003                 mxc_iomux_v3_setup_multiple_pads(spdif_pads, spdif_pads_cnt);
2004         } else {
2005                 BUG_ON(!i2c3_pads);
2006                 mxc_iomux_v3_setup_multiple_pads(i2c3_pads, i2c3_pads_cnt);
2007         }
2008 #else
2009         /* Set GPIO_16 input for IEEE-1588 ts_clk and RMII reference clock
2010          * For MX6 GPR1 bit21 meaning:
2011          * Bit21:       0 - GPIO_16 pad output
2012          *              1 - GPIO_16 pad input
2013          */
2014         mxc_iomux_set_gpr_register(1, 21, 1, 1);
2015 #endif
2016
2017         if (!spdif_en && flexcan_en) {
2018                 BUG_ON(!flexcan_pads);
2019                 mxc_iomux_v3_setup_multiple_pads(flexcan_pads,
2020                                                 flexcan_pads_cnt);
2021         }
2022
2023         /*
2024          * the following is the common devices support on the shared ARM2 boards
2025          * Since i.MX6DQ/DL share the same memory/Register layout, we don't
2026          * need to diff the i.MX6DQ or i.MX6DL here. We can simply use the
2027          * mx6q_add_features() for the shared devices. For which only exist
2028          * on each indivual SOC, we can use cpu_is_mx6q/6dl() to diff it.
2029          */
2030
2031         gp_reg_id = arm2_dvfscore_data.reg_id;
2032         mx6_arm2_init_uart();
2033         imx6q_add_mipi_csi2(&mipi_csi2_pdata);
2034         imx6q_add_mxc_hdmi_core(&hdmi_core_data);
2035
2036         imx6q_add_ipuv3(0, &ipu_data[0]);
2037         if (cpu_is_mx6q())
2038                 imx6q_add_ipuv3(1, &ipu_data[1]);
2039
2040         if (cpu_is_mx6dl()) {
2041                 mipi_dsi_pdata.ipu_id = 0;
2042                 mipi_dsi_pdata.disp_id = 1;
2043                 ldb_data.ipu_id = 0;
2044                 ldb_data.disp_id = 0;
2045                 for (i = 0; i < ARRAY_SIZE(sabr_fb_data) / 2; i++)
2046                         imx6q_add_ipuv3fb(i, &sabr_fb_data[i]);
2047         } else {
2048                 for (i = 0; i < ARRAY_SIZE(sabr_fb_data); i++)
2049                         imx6q_add_ipuv3fb(i, &sabr_fb_data[i]);
2050         }
2051
2052         if (!disable_mipi_dsi)
2053                 imx6q_add_mipi_dsi(&mipi_dsi_pdata);
2054         imx6q_add_lcdif(&lcdif_data);
2055         imx6q_add_ldb(&ldb_data);
2056         imx6q_add_v4l2_output(0);
2057         imx6q_add_v4l2_capture(0);
2058
2059         imx6q_add_imx_snvs_rtc();
2060
2061         imx6q_add_imx_i2c(0, &mx6_arm2_i2c0_data);
2062         imx6q_add_imx_i2c(1, &mx6_arm2_i2c1_data);
2063         i2c_register_board_info(0, mxc_i2c0_board_info,
2064                         ARRAY_SIZE(mxc_i2c0_board_info));
2065         i2c_register_board_info(1, mxc_i2c1_board_info,
2066                         ARRAY_SIZE(mxc_i2c1_board_info));
2067         if (!spdif_en) {
2068                 if (disable_mipi_dsi)
2069                         mx6_arm2_i2c2_data.bitrate = 100000;
2070                 imx6q_add_imx_i2c(2, &mx6_arm2_i2c2_data);
2071                 i2c_register_board_info(2, mxc_i2c2_board_info,
2072                                 ARRAY_SIZE(mxc_i2c2_board_info));
2073         }
2074
2075         /* SPI */
2076         imx6q_add_ecspi(0, &mx6_arm2_spi_data);
2077         spi_device_init();
2078
2079         imx6q_add_mxc_hdmi(&hdmi_data);
2080
2081         imx6q_add_anatop_thermal_imx(1, &mx6_arm2_anatop_thermal_data);
2082
2083         if (!esai_record)
2084                 imx6_init_fec(fec_data);
2085
2086         imx6q_add_pm_imx(0, &mx6_arm2_pm_data);
2087         imx6q_add_sdhci_usdhc_imx(3, &mx6_arm2_sd4_data);
2088         imx6q_add_sdhci_usdhc_imx(2, &mx6_arm2_sd3_data);
2089         imx_add_viv_gpu(&imx6_gpu_data, &imx6_gpu_pdata);
2090         if (cpu_is_mx6q())
2091                 imx6q_add_ahci(0, &mx6_arm2_sata_data);
2092         imx6q_add_vpu();
2093         mx6_arm2_init_usb();
2094         mx6_arm2_init_audio();
2095         platform_device_register(&arm2_vmmc_reg_devices);
2096         mx6_cpu_regulator_init();
2097
2098         imx_asrc_data.asrc_core_clk = clk_get(NULL, "asrc_clk");
2099         imx_asrc_data.asrc_audio_clk = clk_get(NULL, "asrc_serial_clk");
2100         imx6q_add_asrc(&imx_asrc_data);
2101
2102         /* DISP0 Reset - Assert for i2c disabled mode */
2103         gpio_request(MX6_ARM2_DISP0_RESET, "disp0-reset");
2104         gpio_direction_output(MX6_ARM2_DISP0_RESET, 0);
2105
2106         /* DISP0 I2C enable */
2107         if (!disable_mipi_dsi) {
2108                 gpio_request(MX6_ARM2_DISP0_I2C_EN, "disp0-i2c");
2109                 gpio_direction_output(MX6_ARM2_DISP0_I2C_EN, 0);
2110         }
2111         gpio_request(MX6_ARM2_DISP0_PWR, "disp0-pwr");
2112         gpio_direction_output(MX6_ARM2_DISP0_PWR, 1);
2113
2114         gpio_request(MX6_ARM2_LDB_BACKLIGHT, "ldb-backlight");
2115         gpio_direction_output(MX6_ARM2_LDB_BACKLIGHT, 1);
2116         imx6q_add_otp();
2117         imx6q_add_viim();
2118         imx6q_add_imx2_wdt(0, NULL);
2119         imx6q_add_dma();
2120         imx6q_add_gpmi(&mx6_gpmi_nand_platform_data);
2121
2122         imx6q_add_dvfs_core(&arm2_dvfscore_data);
2123
2124         imx6q_add_mxc_pwm(0);
2125         imx6q_add_mxc_pwm_backlight(0, &mx6_arm2_pwm_backlight_data);
2126
2127         if (spdif_en) {
2128                 mxc_spdif_data.spdif_core_clk = clk_get_sys("mxc_spdif.0", NULL);
2129                 clk_put(mxc_spdif_data.spdif_core_clk);
2130                 imx6q_add_spdif(&mxc_spdif_data);
2131                 imx6q_add_spdif_dai();
2132                 imx6q_add_spdif_audio_device();
2133         } else if (flexcan_en) {
2134                 ret = gpio_request_array(mx6_flexcan_gpios,
2135                                 ARRAY_SIZE(mx6_flexcan_gpios));
2136                 if (ret) {
2137                         pr_err("failed to request flexcan-gpios: %d\n", ret);
2138                 } else {
2139                         imx6q_add_flexcan0(&mx6_arm2_flexcan_pdata[0]);
2140                         imx6q_add_flexcan1(&mx6_arm2_flexcan_pdata[1]);
2141                 }
2142         }
2143
2144         imx6q_add_hdmi_soc();
2145         imx6q_add_hdmi_soc_dai();
2146         imx6q_add_perfmon(0);
2147         imx6q_add_perfmon(1);
2148         imx6q_add_perfmon(2);
2149         imx6q_add_mlb150(&mx6_arm2_mlb150_data);
2150
2151         if (cpu_is_mx6dl() && epdc_enabled) {
2152                 imx6dl_add_imx_pxp();
2153                 imx6dl_add_imx_pxp_client();
2154                 mxc_register_device(&max17135_sensor_device, NULL);
2155                 imx6dl_add_imx_epdc(&epdc_data);
2156         }
2157 }
2158
2159 extern void __iomem *twd_base;
2160 static void __init mx6_timer_init(void)
2161 {
2162         struct clk *uart_clk;
2163 #ifdef CONFIG_LOCAL_TIMERS
2164         twd_base = ioremap(LOCAL_TWD_ADDR, SZ_256);
2165         BUG_ON(!twd_base);
2166 #endif
2167         mx6_clocks_init(32768, 24000000, 0, 0);
2168
2169         uart_clk = clk_get_sys("imx-uart.0", NULL);
2170         early_console_setup(UART4_BASE_ADDR, uart_clk);
2171 }
2172
2173 static struct sys_timer mxc_timer = {
2174         .init   = mx6_timer_init,
2175 };
2176
2177 static void __init mx6_arm2_reserve(void)
2178 {
2179         phys_addr_t phys;
2180
2181         if (imx6_gpu_pdata.reserved_mem_size) {
2182                 phys = memblock_alloc_base(
2183                         imx6_gpu_pdata.reserved_mem_size, SZ_4K, SZ_2G);
2184                 memblock_free(phys, imx6_gpu_pdata.reserved_mem_size);
2185                 memblock_remove(phys, imx6_gpu_pdata.reserved_mem_size);
2186                 imx6_gpu_pdata.reserved_mem_base = phys;
2187         }
2188 }
2189
2190 MACHINE_START(MX6Q_ARM2, "Freescale i.MX 6Quad/Solo/DualLite Armadillo2 Board")
2191         .boot_params    = MX6_PHYS_OFFSET + 0x100,
2192         .fixup          = mx6_arm2_fixup,
2193         .map_io         = mx6_map_io,
2194         .init_irq       = mx6_init_irq,
2195         .init_machine   = mx6_arm2_init,
2196         .timer          = &mxc_timer,
2197         .reserve        = mx6_arm2_reserve,
2198 MACHINE_END