2 * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
20 #include <linux/types.h>
21 #include <linux/sched.h>
22 #include <linux/delay.h>
24 #include <linux/interrupt.h>
25 #include <linux/irq.h>
26 #include <linux/init.h>
27 #include <linux/input.h>
28 #include <linux/nodemask.h>
29 #include <linux/clk.h>
30 #include <linux/platform_device.h>
31 #include <linux/fsl_devices.h>
32 #include <linux/smsc911x.h>
33 #include <linux/spi/spi.h>
34 #include <linux/i2c.h>
35 #include <linux/i2c/pca953x.h>
36 #include <linux/ata.h>
37 #include <linux/mtd/mtd.h>
38 #include <linux/mtd/map.h>
39 #include <linux/mtd/partitions.h>
40 #include <linux/regulator/consumer.h>
41 #include <linux/pmic_external.h>
42 #include <linux/pmic_status.h>
43 #include <linux/ipu.h>
44 #include <linux/mxcfb.h>
45 #include <linux/pwm_backlight.h>
46 #include <linux/fec.h>
47 #include <linux/memblock.h>
48 #include <mach/common.h>
49 #include <mach/hardware.h>
51 #include <asm/setup.h>
52 #include <asm/mach-types.h>
53 #include <asm/mach/arch.h>
54 #include <asm/mach/time.h>
55 #include <asm/mach/flash.h>
56 #include <mach/memory.h>
57 #include <mach/iomux-mx6q.h>
58 #include <mach/imx-uart.h>
59 #include <mach/viv_gpu.h>
60 #include <mach/ahci_sata.h>
61 #include <mach/ipu-v3.h>
62 #include <linux/gpio.h>
63 #include <linux/etherdevice.h>
66 #include "devices-imx6q.h"
69 #define MX6Q_SABREAUTO_LDB_BACKLIGHT IMX_GPIO_NR(1, 9)
70 #define MX6Q_SABREAUTO_ECSPI1_CS0 IMX_GPIO_NR(2, 30)
71 #define MX6Q_SABREAUTO_ECSPI1_CS1 IMX_GPIO_NR(3, 19)
72 #define MX6Q_SABREAUTO_DISP0_PWR IMX_GPIO_NR(3, 24)
73 #define MX6Q_SABREAUTO_DISP0_I2C_EN IMX_GPIO_NR(3, 28)
74 #define MX6Q_SABREAUTO_DISP0_DET_INT IMX_GPIO_NR(3, 31)
75 #define MX6Q_SABREAUTO_DISP0_RESET IMX_GPIO_NR(5, 0)
76 #define MX6Q_SABREAUTO_SD3_CD IMX_GPIO_NR(6, 11)
77 #define MX6Q_SABREAUTO_SD3_WP IMX_GPIO_NR(6, 14)
78 #define MX6Q_SABREAUTO_USB_OTG_PWR IMX_GPIO_NR(3, 22)
79 #define MX6Q_SABREAUTO_MAX7310_1_BASE_ADDR IMX_GPIO_NR(8, 0)
80 #define MX6Q_SABREAUTO_MAX7310_2_BASE_ADDR IMX_GPIO_NR(8, 8)
81 #define MX6Q_SABREAUTO_CAP_TCH_INT IMX_GPIO_NR(3, 31)
83 void __init early_console_setup(unsigned long base, struct clk *clk);
84 static struct clk *sata_clk;
86 static iomux_v3_cfg_t mx6q_sabreauto_pads[] = {
89 MX6Q_PAD_KEY_COL0__UART4_TXD,
90 MX6Q_PAD_KEY_ROW0__UART4_RXD,
93 MX6Q_PAD_KEY_COL1__ENET_MDIO,
94 MX6Q_PAD_KEY_COL2__ENET_MDC,
95 MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC,
96 MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0,
97 MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1,
98 MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2,
99 MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3,
100 MX6Q_PAD_RGMII_TX_CTL__ENET_RGMII_TX_CTL,
101 MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK,
102 MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC,
103 MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0,
104 MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1,
105 MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2,
106 MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3,
107 MX6Q_PAD_RGMII_RX_CTL__ENET_RGMII_RX_CTL,
108 MX6Q_PAD_GPIO_0__CCM_CLKO,
109 MX6Q_PAD_GPIO_3__CCM_CLKO2,
112 MX6Q_PAD_SD1_CLK__USDHC1_CLK,
113 MX6Q_PAD_SD1_CMD__USDHC1_CMD,
114 MX6Q_PAD_SD1_DAT0__USDHC1_DAT0,
115 MX6Q_PAD_SD1_DAT1__USDHC1_DAT1,
116 MX6Q_PAD_SD1_DAT2__USDHC1_DAT2,
117 MX6Q_PAD_SD1_DAT3__USDHC1_DAT3,
119 MX6Q_PAD_SD2_CLK__USDHC2_CLK,
120 MX6Q_PAD_SD2_CMD__USDHC2_CMD,
121 MX6Q_PAD_SD2_DAT0__USDHC2_DAT0,
122 MX6Q_PAD_SD2_DAT1__USDHC2_DAT1,
123 MX6Q_PAD_SD2_DAT2__USDHC2_DAT2,
124 MX6Q_PAD_SD2_DAT3__USDHC2_DAT3,
126 MX6Q_PAD_SD3_CLK__USDHC3_CLK,
127 MX6Q_PAD_SD3_CMD__USDHC3_CMD,
128 MX6Q_PAD_SD3_DAT0__USDHC3_DAT0,
129 MX6Q_PAD_SD3_DAT1__USDHC3_DAT1,
130 MX6Q_PAD_SD3_DAT2__USDHC3_DAT2,
131 MX6Q_PAD_SD3_DAT3__USDHC3_DAT3,
132 MX6Q_PAD_SD3_DAT4__USDHC3_DAT4,
133 MX6Q_PAD_SD3_DAT5__USDHC3_DAT5,
134 MX6Q_PAD_SD3_DAT6__USDHC3_DAT6,
135 MX6Q_PAD_SD3_DAT7__USDHC3_DAT7,
136 MX6Q_PAD_SD3_RST__USDHC3_RST,
138 MX6Q_PAD_GPIO_18__USDHC3_VSELECT,
139 /* SD3_CD and SD3_WP */
140 MX6Q_PAD_NANDF_CS0__GPIO_6_11,
141 MX6Q_PAD_NANDF_CS1__GPIO_6_14,
143 MX6Q_PAD_SD4_CLK__USDHC4_CLK,
144 MX6Q_PAD_SD4_CMD__USDHC4_CMD,
145 MX6Q_PAD_SD4_DAT0__USDHC4_DAT0,
146 MX6Q_PAD_SD4_DAT1__USDHC4_DAT1,
147 MX6Q_PAD_SD4_DAT2__USDHC4_DAT2,
148 MX6Q_PAD_SD4_DAT3__USDHC4_DAT3,
149 MX6Q_PAD_SD4_DAT4__USDHC4_DAT4,
150 MX6Q_PAD_SD4_DAT5__USDHC4_DAT5,
151 MX6Q_PAD_SD4_DAT6__USDHC4_DAT6,
152 MX6Q_PAD_SD4_DAT7__USDHC4_DAT7,
153 MX6Q_PAD_NANDF_ALE__USDHC4_RST,
155 MX6Q_PAD_EIM_D16__ECSPI1_SCLK,
156 MX6Q_PAD_EIM_D17__ECSPI1_MISO,
157 MX6Q_PAD_EIM_D18__ECSPI1_MOSI,
160 MX6Q_PAD_ENET_RXD0__ESAI1_HCKT,
161 /* MX6Q_PAD_ENET_RX_ER__ESAI1_HCKR,
162 MX6Q_PAD_ENET_MDIO__ESAI1_SCKR,
163 MX6Q_PAD_ENET_REF_CLK__ESAI1_FSR, */
164 MX6Q_PAD_ENET_CRS_DV__ESAI1_SCKT,
165 MX6Q_PAD_ENET_RXD1__ESAI1_FST,
166 /* MX6Q_PAD_ENET_TX_EN__ESAI1_TX3_RX2,
167 MX6Q_PAD_ENET_TXD1__ESAI1_TX2_RX3,
168 MX6Q_PAD_ENET_TXD0__ESAI1_TX4_RX1,
169 MX6Q_PAD_ENET_MDC__ESAI1_TX5_RX0, */
170 MX6Q_PAD_NANDF_CS2__ESAI1_TX0,
171 MX6Q_PAD_NANDF_CS3__ESAI1_TX1,
172 /* MX53_PAD_PATA_DATA4__GPIO2_4, */
175 MX6Q_PAD_CSI0_DAT8__I2C1_SDA,
176 MX6Q_PAD_CSI0_DAT9__I2C1_SCL,
179 MX6Q_PAD_KEY_COL3__I2C2_SCL,
180 MX6Q_PAD_KEY_ROW3__I2C2_SDA,
183 MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,
184 MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15,
185 MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2,
186 MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3,
187 MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0,
188 MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1,
189 MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2,
190 MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3,
191 MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4,
192 MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5,
193 MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6,
194 MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7,
195 MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8,
196 MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9,
197 MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10,
198 MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11,
199 MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12,
200 MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13,
201 MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14,
202 MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15,
203 MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16,
204 MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17,
205 MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18,
206 MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19,
207 MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20,
208 MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21,
209 MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22,
210 MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23,
212 MX6Q_PAD_EIM_D24__GPIO_3_24,
215 MX6Q_PAD_GPIO_9__GPIO_1_9,
217 /* DISP0 I2C ENABLE*/
218 MX6Q_PAD_EIM_D28__GPIO_3_28,
221 MX6Q_PAD_EIM_D31__GPIO_3_31,
224 MX6Q_PAD_EIM_WAIT__GPIO_5_0,
227 MX6Q_PAD_GPIO_5__I2C3_SCL,
228 MX6Q_PAD_GPIO_16__I2C3_SDA,
229 MX6Q_PAD_GPIO_1__USBOTG_ID,
231 static const struct esdhc_platform_data mx6q_sabreauto_sd3_data __initconst = {
232 .cd_gpio = MX6Q_SABREAUTO_SD3_CD,
233 .wp_gpio = MX6Q_SABREAUTO_SD3_WP,
237 /* No card detect signal for SD4 */
238 static const struct esdhc_platform_data mx6q_sabreauto_sd4_data __initconst = {
242 static const struct anatop_thermal_platform_data mx6q_sabreauto_anatop_thermal_data __initconst = {
243 .name = "anatop_thermal",
246 static inline void mx6q_sabreauto_init_uart(void)
248 imx6q_add_imx_uart(0, NULL);
249 imx6q_add_imx_uart(1, NULL);
250 imx6q_add_imx_uart(3, NULL);
253 static void __init fixup_mxc_board(struct machine_desc *desc, struct tag *tags,
254 char **cmdline, struct meminfo *mi)
258 static struct fec_platform_data fec_data __initdata = {
259 .phy = PHY_INTERFACE_MODE_RGMII,
262 static inline void imx6q_init_fec(void)
264 random_ether_addr(fec_data.mac);
265 imx6q_add_fec(&fec_data);
268 static int mx6q_sabreauto_spi_cs[] = {
269 MX6Q_SABREAUTO_ECSPI1_CS0,
270 MX6Q_SABREAUTO_ECSPI1_CS1,
273 static const struct spi_imx_master mx6q_sabreauto_spi_data __initconst = {
274 .chipselect = mx6q_sabreauto_spi_cs,
275 .num_chipselect = ARRAY_SIZE(mx6q_sabreauto_spi_cs),
278 static int max7310_1_setup(struct i2c_client *client,
279 unsigned gpio_base, unsigned ngpio,
282 int max7310_gpio_value[] = {
283 0, 1, 0, 1, 0, 0, 0, 0,
288 for (n = 0; n < ARRAY_SIZE(max7310_gpio_value); ++n) {
289 gpio_request(gpio_base + n, "MAX7310 1 GPIO Expander");
290 if (max7310_gpio_value[n] < 0)
291 gpio_direction_input(gpio_base + n);
293 gpio_direction_output(gpio_base + n,
294 max7310_gpio_value[n]);
295 gpio_export(gpio_base + n, 0);
301 static struct pca953x_platform_data max7310_platdata = {
302 .gpio_base = MX6Q_SABREAUTO_MAX7310_1_BASE_ADDR,
304 .setup = max7310_1_setup,
307 static int max7310_u48_setup(struct i2c_client *client,
308 unsigned gpio_base, unsigned ngpio,
311 int max7310_gpio_value[] = {
312 0, 1, 1, 1, 0, 0, 0, 0,
317 for (n = 0; n < ARRAY_SIZE(max7310_gpio_value); ++n) {
318 gpio_request(gpio_base + n, "MAX7310 U48 GPIO Expander");
319 if (max7310_gpio_value[n] < 0)
320 gpio_direction_input(gpio_base + n);
322 gpio_direction_output(gpio_base + n,
323 max7310_gpio_value[n]);
324 gpio_export(gpio_base + n, 0);
330 static struct pca953x_platform_data max7310_u48_platdata = {
331 .gpio_base = MX6Q_SABREAUTO_MAX7310_2_BASE_ADDR,
333 .setup = max7310_u48_setup,
336 static void ddc_dvi_init(void)
339 gpio_set_value(MX6Q_SABREAUTO_DISP0_I2C_EN, 1);
342 static int ddc_dvi_update(void)
344 /* DVI cable state */
345 if (gpio_get_value(MX6Q_SABREAUTO_DISP0_DET_INT) == 1)
351 static struct fsl_mxc_dvi_platform_data sabr_ddc_dvi_data = {
354 .init = ddc_dvi_init,
355 .update = ddc_dvi_update,
358 static struct i2c_board_info mxc_i2c0_board_info[] __initdata = {
360 I2C_BOARD_INFO("cs42888", 0x48),
364 static struct imxi2c_platform_data mx6q_sabreauto_i2c_data = {
368 static struct imxi2c_platform_data mx6q_sabreauto_i2c0_data = {
372 static struct i2c_board_info mxc_i2c2_board_info[] __initdata = {
374 I2C_BOARD_INFO("max7310", 0x1F),
375 .platform_data = &max7310_platdata,
378 I2C_BOARD_INFO("max7310", 0x1B),
379 .platform_data = &max7310_u48_platdata,
382 I2C_BOARD_INFO("mxc_dvi", 0x50),
383 .platform_data = &sabr_ddc_dvi_data,
384 .irq = gpio_to_irq(MX6Q_SABREAUTO_DISP0_DET_INT),
388 static int p1003_ts_hw_status(void)
390 return gpio_get_value(MX6Q_SABREAUTO_CAP_TCH_INT);
393 static struct p1003_ts_platform_data p1003_ts_data = {
394 .hw_status = p1003_ts_hw_status,
397 static struct i2c_board_info mxc_i2c1_board_info[] __initdata = {
399 I2C_BOARD_INFO("egalax_ts", 0x4),
400 .irq = gpio_to_irq(MX6Q_SABREAUTO_CAP_TCH_INT),
403 I2C_BOARD_INFO("p1003_fwv33", 0x41),
404 .irq = gpio_to_irq(MX6Q_SABREAUTO_CAP_TCH_INT),
405 .platform_data = &p1003_ts_data,
409 static void imx6q_sabreauto_usbotg_vbus(bool on)
412 gpio_set_value(MX6Q_SABREAUTO_USB_OTG_PWR, 1);
414 gpio_set_value(MX6Q_SABREAUTO_USB_OTG_PWR, 0);
417 static void __init imx6q_sabreauto_init_usb(void)
421 imx_otg_base = MX6_IO_ADDRESS(MX6Q_USB_OTG_BASE_ADDR);
422 /* disable external charger detect, or it will affect signal quality at dp */
424 ret = gpio_request(MX6Q_SABREAUTO_USB_OTG_PWR, "usb-pwr");
426 printk(KERN_ERR"failed to get GPIO MX6Q_SABREAUTO_USB_OTG_PWR: %d\n", ret);
429 gpio_direction_output(MX6Q_SABREAUTO_USB_OTG_PWR, 0);
430 mxc_iomux_set_gpr_register(1, 13, 1, 1);
432 mx6_set_otghost_vbus_func(imx6q_sabreauto_usbotg_vbus);
436 static struct viv_gpu_platform_data imx6q_gc2000_pdata __initdata = {
437 .reserved_mem_size = SZ_128M,
440 /* HW Initialization, if return 0, initialization is successful. */
441 static int mx6q_sabreauto_sata_init(struct device *dev, void __iomem *addr)
447 /* Enable SATA PWR CTRL_0 of MAX7310 */
448 gpio_request(MX6Q_SABREAUTO_MAX7310_1_BASE_ADDR, "SATA_PWR_EN");
449 gpio_direction_output(MX6Q_SABREAUTO_MAX7310_1_BASE_ADDR, 1);
451 sata_clk = clk_get(dev, "imx_sata_clk");
452 if (IS_ERR(sata_clk)) {
453 dev_err(dev, "no sata clock.\n");
454 return PTR_ERR(sata_clk);
456 ret = clk_enable(sata_clk);
458 dev_err(dev, "can't enable sata clock.\n");
462 /* Set PHY Paremeters, two steps to configure the GPR13,
463 * one write for rest of parameters, mask of first write is 0x07FFFFFD,
464 * and the other one write for setting the mpll_clk_off_b
465 *.rx_eq_val_0(iomuxc_gpr13[26:24]),
466 *.los_lvl(iomuxc_gpr13[23:19]),
467 *.rx_dpll_mode_0(iomuxc_gpr13[18:16]),
468 *.sata_speed(iomuxc_gpr13[15]),
469 *.mpll_ss_en(iomuxc_gpr13[14]),
470 *.tx_atten_0(iomuxc_gpr13[13:11]),
471 *.tx_boost_0(iomuxc_gpr13[10:7]),
472 *.tx_lvl(iomuxc_gpr13[6:2]),
473 *.mpll_ck_off(iomuxc_gpr13[1]),
474 *.tx_edgerate_0(iomuxc_gpr13[0]),
476 tmpdata = readl(IOMUXC_GPR13);
477 writel(((tmpdata & ~0x07FFFFFD) | 0x0593A044), IOMUXC_GPR13);
479 /* enable SATA_PHY PLL */
480 tmpdata = readl(IOMUXC_GPR13);
481 writel(((tmpdata & ~0x2) | 0x2), IOMUXC_GPR13);
483 /* Get the AHB clock rate, and configure the TIMER1MS reg later */
484 clk = clk_get(NULL, "ahb");
486 dev_err(dev, "no ahb clock.\n");
488 goto release_sata_clk;
490 tmpdata = clk_get_rate(clk) / 1000;
493 sata_init(addr, tmpdata);
498 clk_disable(sata_clk);
505 static void mx6q_sabreauto_sata_exit(struct device *dev)
507 clk_disable(sata_clk);
510 /* Disable SATA PWR CTRL_0 of MAX7310 */
511 gpio_request(MX6Q_SABREAUTO_MAX7310_1_BASE_ADDR, "SATA_PWR_EN");
512 gpio_direction_output(MX6Q_SABREAUTO_MAX7310_1_BASE_ADDR, 0);
516 static struct ahci_platform_data mx6q_sabreauto_sata_data = {
517 .init = mx6q_sabreauto_sata_init,
518 .exit = mx6q_sabreauto_sata_exit,
521 static struct ipuv3_fb_platform_data sabr_fb_data[] = {
524 .interface_pix_fmt = IPU_PIX_FMT_RGB565,
525 .mode_str = "CLAA-WVGA",
530 .interface_pix_fmt = IPU_PIX_FMT_RGB666,
531 .mode_str = "LDB-XGA",
537 static struct fsl_mxc_lcd_platform_data lcdif_data = {
540 .default_ifmt = IPU_PIX_FMT_RGB565,
543 static struct fsl_mxc_ldb_platform_data ldb_data = {
550 static struct imx_ipuv3_platform_data ipu_data[] = {
558 static void sabreauto_suspend_enter(void)
560 /* suspend preparation */
563 static void sabreauto_suspend_exit(void)
567 static const struct pm_platform_data mx6q_sabreauto_pm_data __initconst = {
569 .suspend_enter = sabreauto_suspend_enter,
570 .suspend_exit = sabreauto_suspend_exit,
573 static struct mxc_audio_platform_data sab_audio_data = {
577 static struct platform_device sab_audio_device = {
578 .name = "imx-cs42888",
581 static struct imx_esai_platform_data sab_esai_pdata = {
582 .flags = IMX_ESAI_NET,
585 static int imx6q_init_audio(void)
587 struct clk *pll3_pfd, *esai_clk;
588 mxc_register_device(&sab_audio_device, &sab_audio_data);
589 imx6q_add_imx_esai(0, &sab_esai_pdata);
591 esai_clk = clk_get(NULL, "esai_clk");
592 if (IS_ERR(esai_clk))
593 return PTR_ERR(esai_clk);
595 pll3_pfd = clk_get(NULL, "pll3_pfd_508M");
596 if (IS_ERR(pll3_pfd))
597 return PTR_ERR(pll3_pfd);
599 clk_set_parent(esai_clk, pll3_pfd);
600 clk_set_rate(esai_clk, 101647058);
603 * Board specific initialization.
605 static void __init mx6_board_init(void)
609 mxc_iomux_v3_setup_multiple_pads(mx6q_sabreauto_pads,
610 ARRAY_SIZE(mx6q_sabreauto_pads));
612 mx6q_sabreauto_init_uart();
614 imx6q_add_ipuv3(0, &ipu_data[0]);
615 imx6q_add_ipuv3(1, &ipu_data[1]);
617 for (i = 0; i < ARRAY_SIZE(sabr_fb_data); i++)
618 imx6q_add_ipuv3fb(i, &sabr_fb_data[i]);
620 imx6q_add_lcdif(&lcdif_data);
621 imx6q_add_ldb(&ldb_data);
622 imx6q_add_v4l2_output(0);
624 imx6q_add_imx_snvs_rtc();
626 imx6q_add_imx_i2c(0, &mx6q_sabreauto_i2c0_data);
627 imx6q_add_imx_i2c(1, &mx6q_sabreauto_i2c_data);
628 imx6q_add_imx_i2c(2, &mx6q_sabreauto_i2c_data);
629 i2c_register_board_info(0, mxc_i2c0_board_info,
630 ARRAY_SIZE(mxc_i2c0_board_info));
631 i2c_register_board_info(1, mxc_i2c1_board_info,
632 ARRAY_SIZE(mxc_i2c1_board_info));
633 i2c_register_board_info(2, mxc_i2c2_board_info,
634 ARRAY_SIZE(mxc_i2c2_board_info));
636 imx6q_add_anatop_thermal_imx(1, &mx6q_sabreauto_anatop_thermal_data);
639 imx6q_add_pm_imx(0, &mx6q_sabreauto_pm_data);
640 imx6q_add_sdhci_usdhc_imx(3, &mx6q_sabreauto_sd4_data);
641 imx6q_add_sdhci_usdhc_imx(2, &mx6q_sabreauto_sd3_data);
642 imx_add_viv_gpu("gc2000", &imx6_gc2000_data, &imx6q_gc2000_pdata);
643 imx_add_viv_gpu("gc355", &imx6_gc355_data, NULL);
644 imx_add_viv_gpu("gc320", &imx6_gc320_data, NULL);
645 imx6q_sabreauto_init_usb();
646 imx6q_add_ahci(0, &mx6q_sabreauto_sata_data);
651 gpio_request(MX6Q_SABREAUTO_DISP0_DET_INT, "disp0-detect");
652 gpio_direction_input(MX6Q_SABREAUTO_DISP0_DET_INT);
654 /* DISP0 Reset - Assert for i2c disabled mode */
655 gpio_request(MX6Q_SABREAUTO_DISP0_RESET, "disp0-reset");
656 gpio_direction_output(MX6Q_SABREAUTO_DISP0_RESET, 0);
658 /* DISP0 I2C enable */
659 gpio_request(MX6Q_SABREAUTO_DISP0_I2C_EN, "disp0-i2c");
660 gpio_direction_output(MX6Q_SABREAUTO_DISP0_I2C_EN, 0);
662 gpio_request(MX6Q_SABREAUTO_DISP0_PWR, "disp0-pwr");
663 gpio_direction_output(MX6Q_SABREAUTO_DISP0_PWR, 1);
665 gpio_request(MX6Q_SABREAUTO_LDB_BACKLIGHT, "ldb-backlight");
666 gpio_direction_output(MX6Q_SABREAUTO_LDB_BACKLIGHT, 1);
668 imx6q_add_imx2_wdt(0, NULL);
671 extern void __iomem *twd_base;
672 static void __init mx6_timer_init(void)
674 struct clk *uart_clk;
675 #ifdef CONFIG_LOCAL_TIMERS
676 twd_base = ioremap(LOCAL_TWD_ADDR, SZ_256);
679 mx6_clocks_init(32768, 24000000, 0, 0);
681 uart_clk = clk_get_sys("imx-uart.0", NULL);
682 early_console_setup(UART4_BASE_ADDR, uart_clk);
685 static struct sys_timer mxc_timer = {
686 .init = mx6_timer_init,
689 static void __init mx6q_reserve(void)
693 if (imx6q_gc2000_pdata.reserved_mem_size) {
694 phys = memblock_alloc_base(imx6q_gc2000_pdata.reserved_mem_size, SZ_4K, SZ_2G);
695 memblock_free(phys, imx6q_gc2000_pdata.reserved_mem_size);
696 memblock_remove(phys, imx6q_gc2000_pdata.reserved_mem_size);
697 imx6q_gc2000_pdata.reserved_mem_base = phys;
702 * initialize __mach_desc_MX6Q_SABREAUTO data structure.
704 MACHINE_START(MX6Q_SABREAUTO, "Freescale i.MX 6Quad SABRE Auto Board")
705 /* Maintainer: Freescale Semiconductor, Inc. */
706 .boot_params = MX6_PHYS_OFFSET + 0x100,
707 .fixup = fixup_mxc_board,
708 .map_io = mx6_map_io,
709 .init_irq = mx6_init_irq,
710 .init_machine = mx6_board_init,
712 .reserve = mx6q_reserve,