arch/arm/mach-mx6/board-mx6q_sabrelite.c

   1 /*
   2  * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13
  14  * You should have received a copy of the GNU General Public License along
  15  * with this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  17  */
  18
  19
  20 #include <linux/types.h>
  21 #include <linux/sched.h>
  22 #include <linux/delay.h>
  23 #include <linux/pm.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/irq.h>
  26 #include <linux/init.h>
  27 #include <linux/input.h>
  28 #include <linux/nodemask.h>
  29 #include <linux/clk.h>
  30 #include <linux/platform_device.h>
  31 #include <linux/fsl_devices.h>
  32 #include <linux/spi/spi.h>
  33 #include <linux/i2c.h>
  34 #include <linux/i2c/pca953x.h>
  35 #include <linux/ata.h>
  36 #include <linux/mtd/mtd.h>
  37 #include <linux/mtd/map.h>
  38 #include <linux/mtd/partitions.h>
  39 #include <linux/regulator/consumer.h>
  40 #include <linux/pmic_external.h>
  41 #include <linux/pmic_status.h>
  42 #include <linux/ipu.h>
  43 #include <linux/mxcfb.h>
  44 #include <linux/pwm_backlight.h>
  45 #include <linux/fec.h>
  46 #include <linux/memblock.h>
  47 #include <linux/gpio.h>
  48 #include <linux/etherdevice.h>
  49 #include <linux/regulator/machine.h>
  50 #include <linux/regulator/fixed.h>
  51
  52 #include <mach/common.h>
  53 #include <mach/hardware.h>
  54 #include <mach/mxc_dvfs.h>
  55 #include <mach/memory.h>
  56 #include <mach/iomux-mx6q.h>
  57 #include <mach/imx-uart.h>
  58 #include <mach/viv_gpu.h>
  59 #include <mach/ipu-v3.h>
  60 #include <mach/mxc_hdmi.h>
  61 #include <mach/mxc_asrc.h>
  62
  63 #include <asm/irq.h>
  64 #include <asm/setup.h>
  65 #include <asm/mach-types.h>
  66 #include <asm/mach/arch.h>
  67 #include <asm/mach/time.h>
  68 #include <asm/mach/flash.h>
  69
  70 #include "usb.h"
  71 #include "devices-imx6q.h"
  72 #include "crm_regs.h"
  73 #include "cpu_op-mx6.h"
  74 #define MX6Q_SABRELITE_SD3_CD           IMX_GPIO_NR(7, 0)
  75 #define MX6Q_SABRELITE_SD3_WP           IMX_GPIO_NR(7, 1)
  76 #define MX6Q_SABRELITE_SD4_CD           IMX_GPIO_NR(2, 6)
  77 #define MX6Q_SABRELITE_SD4_WP           IMX_GPIO_NR(2, 7)
  78 #define MX6Q_SABRELITE_ECSPI1_CS1       IMX_GPIO_NR(3, 19)
  79 #define MX6Q_SABRELITE_USB_OTG_PWR      IMX_GPIO_NR(3, 22)
  80 #define MX6Q_SABRELITE_CAP_TCH_INT1     IMX_GPIO_NR(1, 9)
  81 #define MX6Q_SABRELITE_USB_HUB_RESET    IMX_GPIO_NR(7, 12)
  82
  83 void __init early_console_setup(unsigned long base, struct clk *clk);
  84
  85 extern struct regulator *(*get_cpu_regulator)(void);
  86 extern void (*put_cpu_regulator)(void);
  87 extern int (*set_cpu_voltage)(u32 volt);
  88 extern int mx6_set_cpu_voltage(u32 cpu_volt);
  89
  90 static iomux_v3_cfg_t mx6q_sabrelite_pads[] = {
  91         /* AUDMUX */
  92         MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD,
  93         MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC,
  94         MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD,
  95         MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS,
  96
  97         /* CAN1  */
  98         MX6Q_PAD_KEY_ROW2__CAN1_RXCAN,
  99         MX6Q_PAD_KEY_COL2__CAN1_TXCAN,
 100         MX6Q_PAD_ENET_CRS_DV__GPIO_1_25,        /* STNDBY */
 101         MX6Q_PAD_ENET_RXD1__GPIO_1_26,          /* NERR */
 102         MX6Q_PAD_ENET_RXD0__GPIO_1_27,          /* Enable */
 103
 104         /* CCM  */
 105         MX6Q_PAD_GPIO_0__CCM_CLKO,              /* SGTL500 sys_mclk */
 106         MX6Q_PAD_GPIO_3__CCM_CLKO2,             /* J5 - Camera MCLK */
 107
 108         /* ECSPI1 */
 109         MX6Q_PAD_EIM_D17__ECSPI1_MISO,
 110         MX6Q_PAD_EIM_D18__ECSPI1_MOSI,
 111         MX6Q_PAD_EIM_D16__ECSPI1_SCLK,
 112
 113         /* ENET */
 114         MX6Q_PAD_ENET_MDIO__ENET_MDIO,
 115         MX6Q_PAD_ENET_MDC__ENET_MDC,
 116         MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC,
 117         MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0,
 118         MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1,
 119         MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2,
 120         MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3,
 121         MX6Q_PAD_RGMII_TX_CTL__ENET_RGMII_TX_CTL,
 122         MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK,
 123         MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC,
 124         MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0,
 125         MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1,
 126         MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2,
 127         MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3,
 128         MX6Q_PAD_RGMII_RX_CTL__ENET_RGMII_RX_CTL,
 129         MX6Q_PAD_ENET_TX_EN__GPIO_1_28,         /* Micrel RGMII Phy Interrupt */
 130         MX6Q_PAD_EIM_D23__GPIO_3_23,            /* RGMII reset */
 131
 132         /* GPIO1 */
 133         MX6Q_PAD_ENET_RX_ER__GPIO_1_24,         /* J9 - Microphone Detect */
 134
 135         /* GPIO2 */
 136         MX6Q_PAD_NANDF_D1__GPIO_2_1,    /* J14 - Menu Button */
 137         MX6Q_PAD_NANDF_D2__GPIO_2_2,    /* J14 - Back Button */
 138         MX6Q_PAD_NANDF_D3__GPIO_2_3,    /* J14 - Search Button */
 139         MX6Q_PAD_NANDF_D4__GPIO_2_4,    /* J14 - Home Button */
 140         MX6Q_PAD_EIM_A22__GPIO_2_16,    /* J12 - Boot Mode Select */
 141         MX6Q_PAD_EIM_A21__GPIO_2_17,    /* J12 - Boot Mode Select */
 142         MX6Q_PAD_EIM_A20__GPIO_2_18,    /* J12 - Boot Mode Select */
 143         MX6Q_PAD_EIM_A19__GPIO_2_19,    /* J12 - Boot Mode Select */
 144         MX6Q_PAD_EIM_A18__GPIO_2_20,    /* J12 - Boot Mode Select */
 145         MX6Q_PAD_EIM_A17__GPIO_2_21,    /* J12 - Boot Mode Select */
 146         MX6Q_PAD_EIM_A16__GPIO_2_22,    /* J12 - Boot Mode Select */
 147         MX6Q_PAD_EIM_RW__GPIO_2_26,     /* J12 - Boot Mode Select */
 148         MX6Q_PAD_EIM_LBA__GPIO_2_27,    /* J12 - Boot Mode Select */
 149         MX6Q_PAD_EIM_EB0__GPIO_2_28,    /* J12 - Boot Mode Select */
 150         MX6Q_PAD_EIM_EB1__GPIO_2_29,    /* J12 - Boot Mode Select */
 151         MX6Q_PAD_EIM_EB3__GPIO_2_31,    /* J12 - Boot Mode Select */
 152
 153         /* GPIO3 */
 154         MX6Q_PAD_EIM_DA0__GPIO_3_0,     /* J12 - Boot Mode Select */
 155         MX6Q_PAD_EIM_DA1__GPIO_3_1,     /* J12 - Boot Mode Select */
 156         MX6Q_PAD_EIM_DA2__GPIO_3_2,     /* J12 - Boot Mode Select */
 157         MX6Q_PAD_EIM_DA3__GPIO_3_3,     /* J12 - Boot Mode Select */
 158         MX6Q_PAD_EIM_DA4__GPIO_3_4,     /* J12 - Boot Mode Select */
 159         MX6Q_PAD_EIM_DA5__GPIO_3_5,     /* J12 - Boot Mode Select */
 160         MX6Q_PAD_EIM_DA6__GPIO_3_6,     /* J12 - Boot Mode Select */
 161         MX6Q_PAD_EIM_DA7__GPIO_3_7,     /* J12 - Boot Mode Select */
 162         MX6Q_PAD_EIM_DA8__GPIO_3_8,     /* J12 - Boot Mode Select */
 163         MX6Q_PAD_EIM_DA9__GPIO_3_9,     /* J12 - Boot Mode Select */
 164         MX6Q_PAD_EIM_DA10__GPIO_3_10,   /* J12 - Boot Mode Select */
 165         MX6Q_PAD_EIM_DA11__GPIO_3_11,   /* J12 - Boot Mode Select */
 166         MX6Q_PAD_EIM_DA12__GPIO_3_12,   /* J12 - Boot Mode Select */
 167         MX6Q_PAD_EIM_DA13__GPIO_3_13,   /* J12 - Boot Mode Select */
 168         MX6Q_PAD_EIM_DA14__GPIO_3_14,   /* J12 - Boot Mode Select */
 169         MX6Q_PAD_EIM_DA15__GPIO_3_15,   /* J12 - Boot Mode Select */
 170
 171         /* GPIO4 */
 172         MX6Q_PAD_GPIO_19__GPIO_4_5,     /* J14 - Volume Down */
 173
 174         /* GPIO5 */
 175         MX6Q_PAD_EIM_WAIT__GPIO_5_0,    /* J12 - Boot Mode Select */
 176         MX6Q_PAD_EIM_A24__GPIO_5_4,     /* J12 - Boot Mode Select */
 177
 178         /* GPIO6 */
 179         MX6Q_PAD_EIM_A23__GPIO_6_6,     /* J12 - Boot Mode Select */
 180
 181         /* GPIO7 */
 182         MX6Q_PAD_GPIO_17__GPIO_7_12,    /* USB Hub Reset */
 183         MX6Q_PAD_GPIO_18__GPIO_7_13,    /* J14 - Volume Up */
 184
 185         /* HDMI */
 186         MX6Q_PAD_EIM_EB2__HDMI_TX_DDC_SCL,
 187         MX6Q_PAD_EIM_D16__HDMI_TX_DDC_SDA,
 188         MX6Q_PAD_EIM_A25__HDMI_TX_CEC_LINE,
 189         MX6Q_PAD_SD1_DAT1__HDMI_TX_OPHYDTB_0,
 190         MX6Q_PAD_SD1_DAT0__HDMI_TX_OPHYDTB_1,
 191
 192         /* I2C1, SGTL5000 */
 193         MX6Q_PAD_EIM_D21__I2C1_SCL,     /* GPIO3[21] */
 194         MX6Q_PAD_EIM_D28__I2C1_SDA,     /* GPIO3[28] */
 195
 196         /* I2C2 Camera, MIPI */
 197         MX6Q_PAD_KEY_COL3__I2C2_SCL,    /* GPIO4[12] */
 198         MX6Q_PAD_KEY_ROW3__I2C2_SDA,    /* GPIO4[13] */
 199
 200         /* I2C3 */
 201         MX6Q_PAD_GPIO_5__I2C3_SCL,      /* GPIO1[5] - J7 - Display card */
 202         MX6Q_PAD_GPIO_16__I2C3_SDA,     /* GPIO7[11] - J15 - RGB connector */
 203
 204         /* IPU1 Camera */
 205         MX6Q_PAD_CSI0_DAT8__IPU1_CSI0_D_8,
 206         MX6Q_PAD_CSI0_DAT9__IPU1_CSI0_D_9,
 207         MX6Q_PAD_CSI0_DAT10__IPU1_CSI0_D_10,
 208         MX6Q_PAD_CSI0_DAT11__IPU1_CSI0_D_11,
 209         MX6Q_PAD_CSI0_DAT12__IPU1_CSI0_D_12,
 210         MX6Q_PAD_CSI0_DAT13__IPU1_CSI0_D_13,
 211         MX6Q_PAD_CSI0_DAT14__IPU1_CSI0_D_14,
 212         MX6Q_PAD_CSI0_DAT15__IPU1_CSI0_D_15,
 213         MX6Q_PAD_CSI0_DAT16__IPU1_CSI0_D_16,
 214         MX6Q_PAD_CSI0_DAT17__IPU1_CSI0_D_17,
 215         MX6Q_PAD_CSI0_DAT18__IPU1_CSI0_D_18,
 216         MX6Q_PAD_CSI0_DAT19__IPU1_CSI0_D_19,
 217         MX6Q_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN,
 218         MX6Q_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC,
 219         MX6Q_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK,
 220         MX6Q_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC,
 221         MX6Q_PAD_GPIO_6__GPIO_1_6,              /* J5 - Camera GP */
 222         MX6Q_PAD_GPIO_8__GPIO_1_8,              /* J5 - Camera Reset */
 223         MX6Q_PAD_SD1_DAT0__GPIO_1_16,           /* J5 - Camera GP */
 224         MX6Q_PAD_NANDF_D5__GPIO_2_5,            /* J16 - MIPI GP */
 225         MX6Q_PAD_NANDF_WP_B__GPIO_6_9,          /* J16 - MIPI GP */
 226
 227         /* DISPLAY */
 228         MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,
 229         MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15,             /* DE */
 230         MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2,               /* HSync */
 231         MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3,               /* VSync */
 232         MX6Q_PAD_DI0_PIN4__IPU1_DI0_PIN4,               /* Contrast */
 233         MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0,
 234         MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1,
 235         MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2,
 236         MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3,
 237         MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4,
 238         MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5,
 239         MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6,
 240         MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7,
 241         MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8,
 242         MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9,
 243         MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10,
 244         MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11,
 245         MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12,
 246         MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13,
 247         MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14,
 248         MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15,
 249         MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16,
 250         MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17,
 251         MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18,
 252         MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19,
 253         MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20,
 254         MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21,
 255         MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22,
 256         MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23,
 257         MX6Q_PAD_GPIO_7__GPIO_1_7,              /* J7 - Display Connector GP */
 258         MX6Q_PAD_GPIO_9__GPIO_1_9,              /* J7 - Display Connector GP */
 259         MX6Q_PAD_NANDF_D0__GPIO_2_0,            /* J6 - LVDS Display contrast */
 260
 261
 262         /* PWM1 */
 263         MX6Q_PAD_SD1_DAT3__PWM1_PWMO,           /* GPIO1[21] */
 264
 265         /* PWM2 */
 266         MX6Q_PAD_SD1_DAT2__PWM2_PWMO,           /* GPIO1[19] */
 267
 268         /* PWM3 */
 269         MX6Q_PAD_SD1_DAT1__PWM3_PWMO,           /* GPIO1[17] */
 270
 271         /* PWM4 */
 272         MX6Q_PAD_SD1_CMD__PWM4_PWMO,            /* GPIO1[18] */
 273
 274         /* UART1  */
 275         MX6Q_PAD_SD3_DAT7__UART1_TXD,
 276         MX6Q_PAD_SD3_DAT6__UART1_RXD,
 277
 278         /* UART2 for debug */
 279         MX6Q_PAD_EIM_D26__UART2_TXD,
 280         MX6Q_PAD_EIM_D27__UART2_RXD,
 281
 282         /* USBOTG ID pin */
 283         MX6Q_PAD_GPIO_1__USBOTG_ID,
 284
 285         /* USDHC3 */
 286         MX6Q_PAD_SD3_CLK__USDHC3_CLK_50MHZ,
 287         MX6Q_PAD_SD3_CMD__USDHC3_CMD_50MHZ,
 288         MX6Q_PAD_SD3_DAT0__USDHC3_DAT0_50MHZ,
 289         MX6Q_PAD_SD3_DAT1__USDHC3_DAT1_50MHZ,
 290         MX6Q_PAD_SD3_DAT2__USDHC3_DAT2_50MHZ,
 291         MX6Q_PAD_SD3_DAT3__USDHC3_DAT3_50MHZ,
 292         MX6Q_PAD_SD3_DAT5__GPIO_7_0,            /* J18 - SD3_CD */
 293         MX6Q_PAD_SD3_DAT4__GPIO_7_1,            /* J18 - SD3_WP */
 294
 295         /* USDHC4 */
 296         MX6Q_PAD_SD4_CLK__USDHC4_CLK_50MHZ,
 297         MX6Q_PAD_SD4_CMD__USDHC4_CMD_50MHZ,
 298         MX6Q_PAD_SD4_DAT0__USDHC4_DAT0_50MHZ,
 299         MX6Q_PAD_SD4_DAT1__USDHC4_DAT1_50MHZ,
 300         MX6Q_PAD_SD4_DAT2__USDHC4_DAT2_50MHZ,
 301         MX6Q_PAD_SD4_DAT3__USDHC4_DAT3_50MHZ,
 302         MX6Q_PAD_NANDF_D6__GPIO_2_6,            /* J20 - SD4_CD */
 303         MX6Q_PAD_NANDF_D7__GPIO_2_7,            /* SD4_WP */
 304 };
 305
 306 #define MX6Q_USDHC_PAD_SETTING(id, speed)       \
 307 mx6q_sd##id##_##speed##mhz[] = {                \
 308         MX6Q_PAD_SD##id##_CLK__USDHC##id##_CLK_##speed##MHZ,    \
 309         MX6Q_PAD_SD##id##_CMD__USDHC##id##_CMD_##speed##MHZ,    \
 310         MX6Q_PAD_SD##id##_DAT0__USDHC##id##_DAT0_##speed##MHZ,  \
 311         MX6Q_PAD_SD##id##_DAT1__USDHC##id##_DAT1_##speed##MHZ,  \
 312         MX6Q_PAD_SD##id##_DAT2__USDHC##id##_DAT2_##speed##MHZ,  \
 313         MX6Q_PAD_SD##id##_DAT3__USDHC##id##_DAT3_##speed##MHZ,  \
 314 }
 315
 316 static iomux_v3_cfg_t MX6Q_USDHC_PAD_SETTING(3, 50);
 317 static iomux_v3_cfg_t MX6Q_USDHC_PAD_SETTING(3, 100);
 318 static iomux_v3_cfg_t MX6Q_USDHC_PAD_SETTING(3, 200);
 319 static iomux_v3_cfg_t MX6Q_USDHC_PAD_SETTING(4, 50);
 320 static iomux_v3_cfg_t MX6Q_USDHC_PAD_SETTING(4, 100);
 321 static iomux_v3_cfg_t MX6Q_USDHC_PAD_SETTING(4, 200);
 322
 323 enum sd_pad_mode {
 324         SD_PAD_MODE_LOW_SPEED,
 325         SD_PAD_MODE_MED_SPEED,
 326         SD_PAD_MODE_HIGH_SPEED,
 327 };
 328
 329 static int plt_sd3_pad_change(int clock)
 330 {
 331         static enum sd_pad_mode pad_mode = SD_PAD_MODE_LOW_SPEED;
 332
 333         if (clock > 100000000) {
 334                 if (pad_mode == SD_PAD_MODE_HIGH_SPEED)
 335                         return 0;
 336
 337                 pad_mode = SD_PAD_MODE_HIGH_SPEED;
 338                 return mxc_iomux_v3_setup_multiple_pads(mx6q_sd3_200mhz,
 339                                         ARRAY_SIZE(mx6q_sd3_200mhz));
 340         } else if (clock > 52000000) {
 341                 if (pad_mode == SD_PAD_MODE_MED_SPEED)
 342                         return 0;
 343
 344                 pad_mode = SD_PAD_MODE_MED_SPEED;
 345                 return mxc_iomux_v3_setup_multiple_pads(mx6q_sd3_100mhz,
 346                                         ARRAY_SIZE(mx6q_sd3_100mhz));
 347         } else {
 348                 if (pad_mode == SD_PAD_MODE_LOW_SPEED)
 349                         return 0;
 350
 351                 pad_mode = SD_PAD_MODE_LOW_SPEED;
 352                 return mxc_iomux_v3_setup_multiple_pads(mx6q_sd3_50mhz,
 353                                         ARRAY_SIZE(mx6q_sd3_50mhz));
 354         }
 355 }
 356
 357 static int plt_sd4_pad_change(int clock)
 358 {
 359         static enum sd_pad_mode pad_mode = SD_PAD_MODE_LOW_SPEED;
 360
 361         if (clock > 100000000) {
 362                 if (pad_mode == SD_PAD_MODE_HIGH_SPEED)
 363                         return 0;
 364
 365                 pad_mode = SD_PAD_MODE_HIGH_SPEED;
 366                 return mxc_iomux_v3_setup_multiple_pads(mx6q_sd4_200mhz,
 367                                         ARRAY_SIZE(mx6q_sd4_200mhz));
 368         } else if (clock > 52000000) {
 369                 if (pad_mode == SD_PAD_MODE_MED_SPEED)
 370                         return 0;
 371
 372                 pad_mode = SD_PAD_MODE_MED_SPEED;
 373                 return mxc_iomux_v3_setup_multiple_pads(mx6q_sd4_100mhz,
 374                                         ARRAY_SIZE(mx6q_sd4_100mhz));
 375         } else {
 376                 if (pad_mode == SD_PAD_MODE_LOW_SPEED)
 377                         return 0;
 378
 379                 pad_mode = SD_PAD_MODE_LOW_SPEED;
 380                 return mxc_iomux_v3_setup_multiple_pads(mx6q_sd4_50mhz,
 381                                         ARRAY_SIZE(mx6q_sd4_50mhz));
 382         }
 383 }
 384
 385 static const struct esdhc_platform_data mx6q_sabrelite_sd3_data __initconst = {
 386         .cd_gpio = MX6Q_SABRELITE_SD3_CD,
 387         .wp_gpio = MX6Q_SABRELITE_SD3_WP,
 388         .platform_pad_change = plt_sd3_pad_change,
 389 };
 390
 391 static const struct esdhc_platform_data mx6q_sabrelite_sd4_data __initconst = {
 392         .cd_gpio = MX6Q_SABRELITE_SD4_CD,
 393         .wp_gpio = MX6Q_SABRELITE_SD4_WP,
 394         .platform_pad_change = plt_sd4_pad_change,
 395 };
 396
 397 static const struct anatop_thermal_platform_data
 398         mx6q_sabrelite_anatop_thermal_data __initconst = {
 399                 .name = "anatop_thermal",
 400 };
 401
 402 static inline void mx6q_sabrelite_init_uart(void)
 403 {
 404         imx6q_add_imx_uart(0, NULL);
 405         imx6q_add_imx_uart(1, NULL);
 406 }
 407
 408 static int mx6q_sabrelite_fec_phy_init(struct phy_device *phydev)
 409 {
 410         /* prefer master mode, 1000 Base-T capable */
 411         phy_write(phydev, 0x9, 0x0f00);
 412
 413         /* min rx data delay */
 414         phy_write(phydev, 0x0b, 0x8105);
 415         phy_write(phydev, 0x0c, 0x0000);
 416
 417         /* max rx/tx clock delay, min rx/tx control delay */
 418         phy_write(phydev, 0x0b, 0x8104);
 419         phy_write(phydev, 0x0c, 0xf0f0);
 420         phy_write(phydev, 0x0b, 0x104);
 421
 422         return 0;
 423 }
 424
 425 static struct fec_platform_data fec_data __initdata = {
 426         .init = mx6q_sabrelite_fec_phy_init,
 427         .phy = PHY_INTERFACE_MODE_RGMII,
 428 };
 429
 430 static inline void imx6q_init_fec(void)
 431 {
 432         random_ether_addr(fec_data.mac);
 433         imx6q_add_fec(&fec_data);
 434 }
 435
 436 static int mx6q_sabrelite_spi_cs[] = {
 437         MX6Q_SABRELITE_ECSPI1_CS1,
 438 };
 439
 440 static const struct spi_imx_master mx6q_sabrelite_spi_data __initconst = {
 441         .chipselect     = mx6q_sabrelite_spi_cs,
 442         .num_chipselect = ARRAY_SIZE(mx6q_sabrelite_spi_cs),
 443 };
 444
 445 static struct mxc_audio_platform_data mx6_sabrelite_audio_data;
 446
 447 static int mx6_sabrelite_sgtl5000_init(void)
 448 {
 449         struct clk *clko;
 450         struct clk *new_parent;
 451         int rate;
 452
 453         clko = clk_get(NULL, "clko_clk");
 454         if (IS_ERR(clko)) {
 455                 pr_err("can't get CLKO clock.\n");
 456                 return PTR_ERR(clko);
 457         }
 458         new_parent = clk_get(NULL, "ahb");
 459         if (!IS_ERR(new_parent)) {
 460                 clk_set_parent(clko, new_parent);
 461                 clk_put(new_parent);
 462         }
 463         rate = clk_round_rate(clko, 16000000);
 464         if (rate < 8000000 || rate > 27000000) {
 465                 pr_err("Error:SGTL5000 mclk freq %d out of range!\n", rate);
 466                 clk_put(clko);
 467                 return -1;
 468         }
 469
 470         mx6_sabrelite_audio_data.sysclk = rate;
 471         clk_set_rate(clko, rate);
 472         clk_enable(clko);
 473         return 0;
 474 }
 475
 476 static struct imx_ssi_platform_data mx6_sabrelite_ssi_pdata = {
 477         .flags = IMX_SSI_DMA | IMX_SSI_SYN,
 478 };
 479
 480 static struct mxc_audio_platform_data mx6_sabrelite_audio_data = {
 481         .ssi_num = 1,
 482         .src_port = 2,
 483         .ext_port = 4,
 484         .init = mx6_sabrelite_sgtl5000_init,
 485         .hp_gpio = -1,
 486 };
 487
 488 static struct platform_device mx6_sabrelite_audio_device = {
 489         .name = "imx-sgtl5000",
 490 };
 491
 492 static struct imxi2c_platform_data mx6q_sabrelite_i2c_data = {
 493         .bitrate = 100000,
 494 };
 495
 496 static struct i2c_board_info mxc_i2c0_board_info[] __initdata = {
 497         {
 498                 I2C_BOARD_INFO("sgtl5000", 0x0a),
 499         },
 500 };
 501
 502 static struct i2c_board_info mxc_i2c1_board_info[] __initdata = {
 503         {
 504                 I2C_BOARD_INFO("mxc_hdmi_i2c", 0x50),
 505         },
 506 };
 507
 508 static struct i2c_board_info mxc_i2c2_board_info[] __initdata = {
 509         {
 510                 I2C_BOARD_INFO("egalax_ts", 0x4),
 511                 .irq = gpio_to_irq(MX6Q_SABRELITE_CAP_TCH_INT1),
 512         },
 513 };
 514
 515 static void imx6q_sabrelite_usbotg_vbus(bool on)
 516 {
 517         if (on)
 518                 gpio_set_value(MX6Q_SABRELITE_USB_OTG_PWR, 1);
 519         else
 520                 gpio_set_value(MX6Q_SABRELITE_USB_OTG_PWR, 0);
 521 }
 522
 523 static void __init imx6q_sabrelite_init_usb(void)
 524 {
 525         int ret = 0;
 526
 527         imx_otg_base = MX6_IO_ADDRESS(MX6Q_USB_OTG_BASE_ADDR);
 528         /* disable external charger detect,
 529          * or it will affect signal quality at dp .
 530          */
 531         ret = gpio_request(MX6Q_SABRELITE_USB_OTG_PWR, "usb-pwr");
 532         if (ret) {
 533                 pr_err("failed to get GPIO MX6Q_SABRELITE_USB_OTG_PWR: %d\n",
 534                         ret);
 535                 return;
 536         }
 537         gpio_direction_output(MX6Q_SABRELITE_USB_OTG_PWR, 0);
 538         mxc_iomux_set_gpr_register(1, 13, 1, 1);
 539
 540         mx6_set_otghost_vbus_func(imx6q_sabrelite_usbotg_vbus);
 541         mx6_usb_dr_init();
 542         mx6_usb_h1_init();
 543 }
 544 static struct viv_gpu_platform_data imx6q_gpu_pdata __initdata = {
 545         .reserved_mem_size = SZ_128M,
 546 };
 547
 548 static struct ipuv3_fb_platform_data sabrelite_fb_data[] = {
 549         { /*fb0*/
 550         .disp_dev = "ldb",
 551         .interface_pix_fmt = IPU_PIX_FMT_RGB666,
 552         .mode_str = "LDB-XGA",
 553         .default_bpp = 16,
 554         .int_clk = false,
 555         }, {
 556         .disp_dev = "lcd",
 557         .interface_pix_fmt = IPU_PIX_FMT_RGB565,
 558         .mode_str = "CLAA-WVGA",
 559         .default_bpp = 16,
 560         .int_clk = false,
 561         }, {
 562         .disp_dev = "ldb",
 563         .interface_pix_fmt = IPU_PIX_FMT_RGB666,
 564         .mode_str = "LDB-SVGA",
 565         .default_bpp = 16,
 566         .int_clk = false,
 567         }, {
 568         .disp_dev = "ldb",
 569         .interface_pix_fmt = IPU_PIX_FMT_RGB666,
 570         .mode_str = "LDB-VGA",
 571         .default_bpp = 16,
 572         .int_clk = false,
 573         },
 574 };
 575
 576 static void hdmi_init(int ipu_id, int disp_id)
 577 {
 578         int hdmi_mux_setting;
 579
 580         if ((ipu_id > 1) || (ipu_id < 0)) {
 581                 pr_err("Invalid IPU select for HDMI: %d. Set to 0\n", ipu_id);
 582                 ipu_id = 0;
 583         }
 584
 585         if ((disp_id > 1) || (disp_id < 0)) {
 586                 pr_err("Invalid DI select for HDMI: %d. Set to 0\n", disp_id);
 587                 disp_id = 0;
 588         }
 589
 590         /* Configure the connection between IPU1/2 and HDMI */
 591         hdmi_mux_setting = 2*ipu_id + disp_id;
 592
 593         /* GPR3, bits 2-3 = HDMI_MUX_CTL */
 594         mxc_iomux_set_gpr_register(3, 2, 2, hdmi_mux_setting);
 595 }
 596
 597 static struct fsl_mxc_hdmi_platform_data hdmi_data = {
 598         .init = hdmi_init,
 599 };
 600
 601 static struct fsl_mxc_hdmi_core_platform_data hdmi_core_data = {
 602         .ipu_id = 0,
 603         .disp_id = 0,
 604 };
 605
 606 static struct fsl_mxc_lcd_platform_data lcdif_data = {
 607         .ipu_id = 0,
 608         .disp_id = 0,
 609         .default_ifmt = IPU_PIX_FMT_RGB565,
 610 };
 611
 612 static struct fsl_mxc_ldb_platform_data ldb_data = {
 613         .ipu_id = 1,
 614         .disp_id = 0,
 615         .ext_ref = 1,
 616         .mode = LDB_SEP0,
 617         .sec_ipu_id = 1,
 618         .sec_disp_id = 1,
 619 };
 620
 621 static struct imx_ipuv3_platform_data ipu_data[] = {
 622         {
 623         .rev = 4,
 624         }, {
 625         .rev = 4,
 626         },
 627 };
 628
 629 static void sabrelite_suspend_enter(void)
 630 {
 631         /* suspend preparation */
 632 }
 633
 634 static void sabrelite_suspend_exit(void)
 635 {
 636         /* resume restore */
 637 }
 638 static const struct pm_platform_data mx6q_sabrelite_pm_data __initconst = {
 639         .name = "imx_pm",
 640         .suspend_enter = sabrelite_suspend_enter,
 641         .suspend_exit = sabrelite_suspend_exit,
 642 };
 643
 644 #ifdef CONFIG_SND_SOC_SGTL5000
 645
 646 static struct regulator_consumer_supply sgtl5000_sabrelite_consumer_vdda = {
 647         .supply = "VDDA",
 648         .dev_name = "0-000a",
 649 };
 650
 651 static struct regulator_consumer_supply sgtl5000_sabrelite_consumer_vddio = {
 652         .supply = "VDDIO",
 653         .dev_name = "0-000a",
 654 };
 655
 656 static struct regulator_consumer_supply sgtl5000_sabrelite_consumer_vddd = {
 657         .supply = "VDDD",
 658         .dev_name = "0-000a",
 659 };
 660
 661 static struct regulator_init_data sgtl5000_sabrelite_vdda_reg_initdata = {
 662         .num_consumer_supplies = 1,
 663         .consumer_supplies = &sgtl5000_sabrelite_consumer_vdda,
 664 };
 665
 666 static struct regulator_init_data sgtl5000_sabrelite_vddio_reg_initdata = {
 667         .num_consumer_supplies = 1,
 668         .consumer_supplies = &sgtl5000_sabrelite_consumer_vddio,
 669 };
 670
 671 static struct regulator_init_data sgtl5000_sabrelite_vddd_reg_initdata = {
 672         .num_consumer_supplies = 1,
 673         .consumer_supplies = &sgtl5000_sabrelite_consumer_vddd,
 674 };
 675
 676 static struct fixed_voltage_config sgtl5000_sabrelite_vdda_reg_config = {
 677         .supply_name            = "VDDA",
 678         .microvolts             = 2500000,
 679         .gpio                   = -1,
 680         .init_data              = &sgtl5000_sabrelite_vdda_reg_initdata,
 681 };
 682
 683 static struct fixed_voltage_config sgtl5000_sabrelite_vddio_reg_config = {
 684         .supply_name            = "VDDIO",
 685         .microvolts             = 3300000,
 686         .gpio                   = -1,
 687         .init_data              = &sgtl5000_sabrelite_vddio_reg_initdata,
 688 };
 689
 690 static struct fixed_voltage_config sgtl5000_sabrelite_vddd_reg_config = {
 691         .supply_name            = "VDDD",
 692         .microvolts             = 0,
 693         .gpio                   = -1,
 694         .init_data              = &sgtl5000_sabrelite_vddd_reg_initdata,
 695 };
 696
 697 static struct platform_device sgtl5000_sabrelite_vdda_reg_devices = {
 698         .name   = "reg-fixed-voltage",
 699         .id     = 0,
 700         .dev    = {
 701                 .platform_data = &sgtl5000_sabrelite_vdda_reg_config,
 702         },
 703 };
 704
 705 static struct platform_device sgtl5000_sabrelite_vddio_reg_devices = {
 706         .name   = "reg-fixed-voltage",
 707         .id     = 1,
 708         .dev    = {
 709                 .platform_data = &sgtl5000_sabrelite_vddio_reg_config,
 710         },
 711 };
 712
 713 static struct platform_device sgtl5000_sabrelite_vddd_reg_devices = {
 714         .name   = "reg-fixed-voltage",
 715         .id     = 2,
 716         .dev    = {
 717                 .platform_data = &sgtl5000_sabrelite_vddd_reg_config,
 718         },
 719 };
 720
 721 #endif /* CONFIG_SND_SOC_SGTL5000 */
 722
 723 static int imx6q_init_audio(void)
 724 {
 725         mxc_register_device(&mx6_sabrelite_audio_device,
 726                             &mx6_sabrelite_audio_data);
 727         imx6q_add_imx_ssi(1, &mx6_sabrelite_ssi_pdata);
 728 #ifdef CONFIG_SND_SOC_SGTL5000
 729         platform_device_register(&sgtl5000_sabrelite_vdda_reg_devices);
 730         platform_device_register(&sgtl5000_sabrelite_vddio_reg_devices);
 731         platform_device_register(&sgtl5000_sabrelite_vddd_reg_devices);
 732 #endif
 733         return 0;
 734 }
 735
 736 static struct platform_pwm_backlight_data mx6_sabrelite_pwm_backlight_data = {
 737         .pwm_id = 3,
 738         .max_brightness = 255,
 739         .dft_brightness = 128,
 740         .pwm_period_ns = 50000,
 741 };
 742
 743 static struct mxc_dvfs_platform_data sabrelite_dvfscore_data = {
 744         .reg_id = "cpu_vddgp",
 745         .clk1_id = "cpu_clk",
 746         .clk2_id = "gpc_dvfs_clk",
 747         .gpc_cntr_offset = MXC_GPC_CNTR_OFFSET,
 748         .ccm_cdcr_offset = MXC_CCM_CDCR_OFFSET,
 749         .ccm_cacrr_offset = MXC_CCM_CACRR_OFFSET,
 750         .ccm_cdhipr_offset = MXC_CCM_CDHIPR_OFFSET,
 751         .prediv_mask = 0x1F800,
 752         .prediv_offset = 11,
 753         .prediv_val = 3,
 754         .div3ck_mask = 0xE0000000,
 755         .div3ck_offset = 29,
 756         .div3ck_val = 2,
 757         .emac_val = 0x08,
 758         .upthr_val = 25,
 759         .dnthr_val = 9,
 760         .pncthr_val = 33,
 761         .upcnt_val = 10,
 762         .dncnt_val = 10,
 763         .delay_time = 80,
 764 };
 765
 766 static int mx6_sabre_set_cpu_voltage(u32 cpu_volt)
 767 {
 768         return mx6_set_cpu_voltage(cpu_volt);
 769 }
 770
 771 static void __init fixup_mxc_board(struct machine_desc *desc, struct tag *tags,
 772                                    char **cmdline, struct meminfo *mi)
 773 {
 774         set_cpu_voltage = mx6_sabre_set_cpu_voltage;
 775 }
 776
 777 /*!
 778  * Board specific initialization.
 779  */
 780 static void __init mx6_sabrelite_board_init(void)
 781 {
 782         int i;
 783
 784         mxc_iomux_v3_setup_multiple_pads(mx6q_sabrelite_pads,
 785                                         ARRAY_SIZE(mx6q_sabrelite_pads));
 786
 787         mx6q_sabrelite_init_uart();
 788         imx6q_add_mxc_hdmi_core(&hdmi_core_data);
 789
 790         imx6q_add_ipuv3(0, &ipu_data[0]);
 791         imx6q_add_ipuv3(1, &ipu_data[1]);
 792
 793         for (i = 0; i < ARRAY_SIZE(sabrelite_fb_data); i++)
 794                 imx6q_add_ipuv3fb(i, &sabrelite_fb_data[i]);
 795
 796         imx6q_add_lcdif(&lcdif_data);
 797         imx6q_add_ldb(&ldb_data);
 798         imx6q_add_v4l2_output(0);
 799
 800         imx6q_add_imx_snvs_rtc();
 801
 802         imx6q_add_imx_i2c(0, &mx6q_sabrelite_i2c_data);
 803         imx6q_add_imx_i2c(1, &mx6q_sabrelite_i2c_data);
 804         imx6q_add_imx_i2c(2, &mx6q_sabrelite_i2c_data);
 805         i2c_register_board_info(0, mxc_i2c0_board_info,
 806                         ARRAY_SIZE(mxc_i2c0_board_info));
 807         i2c_register_board_info(1, mxc_i2c1_board_info,
 808                         ARRAY_SIZE(mxc_i2c1_board_info));
 809         i2c_register_board_info(2, mxc_i2c2_board_info,
 810                         ARRAY_SIZE(mxc_i2c2_board_info));
 811
 812         imx6q_add_mxc_hdmi(&hdmi_data);
 813
 814         imx6q_add_anatop_thermal_imx(1, &mx6q_sabrelite_anatop_thermal_data);
 815         imx6q_init_fec();
 816         imx6q_add_pm_imx(0, &mx6q_sabrelite_pm_data);
 817         imx6q_add_sdhci_usdhc_imx(3, &mx6q_sabrelite_sd4_data);
 818         imx6q_add_sdhci_usdhc_imx(2, &mx6q_sabrelite_sd3_data);
 819         imx_add_viv_gpu(&imx6_gpu_data, &imx6q_gpu_pdata);
 820         imx6q_sabrelite_init_usb();
 821         imx6q_add_vpu();
 822         imx6q_init_audio();
 823         /* release USB Hub reset */
 824         gpio_set_value(MX6Q_SABRELITE_USB_HUB_RESET, 1);
 825
 826         imx6q_add_mxc_pwm(0);
 827         imx6q_add_mxc_pwm(1);
 828         imx6q_add_mxc_pwm(2);
 829         imx6q_add_mxc_pwm(3);
 830         imx6q_add_mxc_pwm_backlight(3, &mx6_sabrelite_pwm_backlight_data);
 831
 832         imx6q_add_otp();
 833         imx6q_add_viim();
 834         imx6q_add_imx2_wdt(0, NULL);
 835         imx6q_add_dma();
 836
 837         imx6q_add_dvfs_core(&sabrelite_dvfscore_data);
 838 }
 839
 840 extern void __iomem *twd_base;
 841 static void __init mx6_sabrelite_timer_init(void)
 842 {
 843         struct clk *uart_clk;
 844 #ifdef CONFIG_LOCAL_TIMERS
 845         twd_base = ioremap(LOCAL_TWD_ADDR, SZ_256);
 846         BUG_ON(!twd_base);
 847 #endif
 848         mx6_clocks_init(32768, 24000000, 0, 0);
 849
 850         uart_clk = clk_get_sys("imx-uart.0", NULL);
 851         early_console_setup(UART2_BASE_ADDR, uart_clk);
 852 }
 853
 854 static struct sys_timer mx6_sabrelite_timer = {
 855         .init   = mx6_sabrelite_timer_init,
 856 };
 857
 858 static void __init mx6q_sabrelite_reserve(void)
 859 {
 860         phys_addr_t phys;
 861
 862         if (imx6q_gpu_pdata.reserved_mem_size) {
 863                 phys = memblock_alloc_base(imx6q_gpu_pdata.reserved_mem_size,
 864                                            SZ_4K, SZ_2G);
 865                 memblock_free(phys, imx6q_gpu_pdata.reserved_mem_size);
 866                 memblock_remove(phys, imx6q_gpu_pdata.reserved_mem_size);
 867                 imx6q_gpu_pdata.reserved_mem_base = phys;
 868         }
 869 }
 870
 871 /*
 872  * initialize __mach_desc_MX6Q_SABRELITE data structure.
 873  */
 874 MACHINE_START(MX6Q_SABRELITE, "Freescale i.MX 6Quad Sabre-Lite Board")
 875         /* Maintainer: Freescale Semiconductor, Inc. */
 876         .boot_params = MX6_PHYS_OFFSET + 0x100,
 877         .fixup = fixup_mxc_board,
 878         .map_io = mx6_map_io,
 879         .init_irq = mx6_init_irq,
 880         .init_machine = mx6_sabrelite_board_init,
 881         .timer = &mx6_sabrelite_timer,
 882         .reserve = mx6q_sabrelite_reserve,
 883 MACHINE_END