arch/arm/mach-mx6/clock.c

   1
   2 /*
   3  * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved.
   4  */
   5
   6 /*
   7  * The code contained herein is licensed under the GNU General Public
   8  * License. You may obtain a copy of the GNU General Public License
   9  * Version 2 or later at the following locations:
  10  *
  11  * http://www.opensource.org/licenses/gpl-license.html
  12  * http://www.gnu.org/copyleft/gpl.html
  13  */
  14
  15 #include <linux/kernel.h>
  16 #include <linux/init.h>
  17 #include <linux/types.h>
  18 #include <linux/time.h>
  19 #include <linux/hrtimer.h>
  20 #include <linux/mm.h>
  21 #include <linux/errno.h>
  22 #include <linux/delay.h>
  23 #include <linux/clk.h>
  24 #include <linux/io.h>
  25 #include <linux/clkdev.h>
  26 #include <linux/regulator/consumer.h>
  27 #include <asm/div64.h>
  28 #include <mach/hardware.h>
  29 #include <mach/common.h>
  30 #include <mach/clock.h>
  31 #include <mach/mxc_dvfs.h>
  32 #include "crm_regs.h"
  33 #include "cpu_op-mx6.h"
  34 #include "regs-anadig.h"
  35
  36 #ifdef CONFIG_CLK_DEBUG
  37 #define __INIT_CLK_DEBUG(n)     .name = #n,
  38 #else
  39 #define __INIT_CLK_DEBUG(n)
  40 #endif
  41
  42 extern u32 arm_max_freq;
  43 extern int mxc_jtag_enabled;
  44 extern struct regulator *cpu_regulator;
  45 extern struct cpu_op *(*get_cpu_op)(int *op);
  46 extern int lp_high_freq;
  47 extern int lp_med_freq;
  48 extern int mx6q_revision(void);
  49
  50 void __iomem *apll_base;
  51 static struct clk pll1_sys_main_clk;
  52 static struct clk pll2_528_bus_main_clk;
  53 static struct clk pll2_pfd_400M;
  54 static struct clk pll3_usb_otg_main_clk;
  55 static struct clk pll4_audio_main_clk;
  56 static struct clk pll5_video_main_clk;
  57 static struct clk pll6_mlb150_main_clk;
  58 static struct clk pll7_usb_host_main_clk;
  59 static struct clk pll8_enet_main_clk;
  60 static struct clk apbh_dma_clk;
  61 static struct clk openvg_axi_clk;
  62 static struct clk enfc_clk;
  63 static struct clk usdhc3_clk;
  64
  65 static struct cpu_op *cpu_op_tbl;
  66 static int cpu_op_nr;
  67
  68 #define SPIN_DELAY      1200000 /* in nanoseconds */
  69
  70 #define AUDIO_VIDEO_MIN_CLK_FREQ        650000000
  71 #define AUDIO_VIDEO_MAX_CLK_FREQ        1300000000
  72
  73 /* We need to check the exp status again after timer expiration,
  74  * as there might be interrupt coming between the first time exp
  75  * and the time reading, then the time reading may be several ms
  76  * after the exp checking due to the irq handle, so we need to
  77  * check it to make sure the exp return the right value after
  78  * timer expiration. */
  79 #define WAIT(exp, timeout) \
  80 ({ \
  81         struct timespec nstimeofday; \
  82         struct timespec curtime; \
  83         int result = 1; \
  84         getnstimeofday(&nstimeofday); \
  85         while (!(exp)) { \
  86                 getnstimeofday(&curtime); \
  87                 if ((curtime.tv_nsec - nstimeofday.tv_nsec) > (timeout)) { \
  88                         if (!(exp)) \
  89                                 result = 0; \
  90                         break; \
  91                 } \
  92         } \
  93         result; \
  94 })
  95
  96 /* External clock values passed-in by the board code */
  97 static unsigned long external_high_reference, external_low_reference;
  98 static unsigned long oscillator_reference, ckih2_reference;
  99 static unsigned long anaclk_1_reference, anaclk_2_reference;
 100
 101 /* For MX 6DL/S, Video PLL may be used by synchronous display devices,
 102  * such as HDMI or LVDS, and also by the EPDC.  If EPDC is in use,
 103  * it must use the Video PLL to achieve the clock frequencies it needs.
 104  * So if EPDC is in use, the "epdc" string should be added to kernel
 105  * parameters, in order to set the EPDC parent clock to the Video PLL.
 106  * This will have an impact on the behavior of HDMI and LVDS.
 107  */
 108 int epdc_enabled;
 109 static int __init epdc_setup(char *__unused)
 110 {
 111         epdc_enabled = 1;
 112         return 1;
 113 }
 114 __setup("epdc", epdc_setup);
 115
 116 static void __calc_pre_post_dividers(u32 max_podf, u32 div, u32 *pre, u32 *post)
 117 {
 118         u32 min_pre, temp_pre, old_err, err;
 119
 120         /* Some of the podfs are 3 bits while others are 6 bits.
 121           * Handle both cases here.
 122           */
 123         if (div >= 512 && (max_podf == 64)) {
 124                 /* For pre = 3bits and podf = 6 bits, max divider is 512. */
 125                 *pre = 8;
 126                 *post = 64;
 127         } else if (div >= 64 && (max_podf == 8)) {
 128                 /* For pre = 3bits and podf = 3 bits, max divider is 64. */
 129                 *pre = 8;
 130                 *post = 8;
 131         } else if (div >= 8) {
 132                 /* Find the minimum pre-divider for a max podf */
 133                 if (max_podf == 64)
 134                         min_pre = (div - 1) / (1 << 6) + 1;
 135                 else
 136                         min_pre = (div - 1) / (1 << 3) + 1;
 137                 old_err = 8;
 138                 /* Now loop through to find the max pre-divider. */
 139                 for (temp_pre = 8; temp_pre >= min_pre; temp_pre--) {
 140                         err = div % temp_pre;
 141                         if (err == 0) {
 142                                 *pre = temp_pre;
 143                                 break;
 144                         }
 145                         err = temp_pre - err;
 146                         if (err < old_err) {
 147                                 old_err = err;
 148                                 *pre = temp_pre;
 149                         }
 150                 }
 151                 *post = (div + *pre - 1) / *pre;
 152         } else if (div < 8) {
 153                 *pre = div;
 154                 *post = 1;
 155         }
 156 }
 157
 158 static int _clk_enable(struct clk *clk)
 159 {
 160         u32 reg;
 161         reg = __raw_readl(clk->enable_reg);
 162         reg |= MXC_CCM_CCGRx_CG_MASK << clk->enable_shift;
 163         __raw_writel(reg, clk->enable_reg);
 164
 165         if (clk->flags & AHB_HIGH_SET_POINT)
 166                 lp_high_freq++;
 167         else if (clk->flags & AHB_MED_SET_POINT)
 168                 lp_med_freq++;
 169
 170         return 0;
 171 }
 172
 173 static void _clk_disable(struct clk *clk)
 174 {
 175         u32 reg;
 176         reg = __raw_readl(clk->enable_reg);
 177         reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift);
 178         __raw_writel(reg, clk->enable_reg);
 179
 180         if (clk->flags & AHB_HIGH_SET_POINT)
 181                 lp_high_freq--;
 182         else if (clk->flags & AHB_MED_SET_POINT)
 183                 lp_med_freq--;
 184 }
 185
 186 static void _clk_disable_inwait(struct clk *clk)
 187 {
 188         u32 reg;
 189         reg = __raw_readl(clk->enable_reg);
 190         reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift);
 191         reg |= 1 << clk->enable_shift;
 192         __raw_writel(reg, clk->enable_reg);
 193 }
 194
 195 /*
 196  * For the 4-to-1 muxed input clock
 197  */
 198 static inline u32 _get_mux(struct clk *parent, struct clk *m0,
 199                            struct clk *m1, struct clk *m2, struct clk *m3)
 200 {
 201         if (parent == m0)
 202                 return 0;
 203         else if (parent == m1)
 204                 return 1;
 205         else if (parent == m2)
 206                 return 2;
 207         else if (parent == m3)
 208                 return 3;
 209         else
 210                 BUG();
 211
 212         return 0;
 213 }
 214
 215 static inline void __iomem *_get_pll_base(struct clk *pll)
 216 {
 217         if (pll == &pll1_sys_main_clk)
 218                 return PLL1_SYS_BASE_ADDR;
 219         else if (pll == &pll2_528_bus_main_clk)
 220                 return PLL2_528_BASE_ADDR;
 221         else if (pll == &pll3_usb_otg_main_clk)
 222                 return PLL3_480_USB1_BASE_ADDR;
 223         else if (pll == &pll4_audio_main_clk)
 224                 return PLL4_AUDIO_BASE_ADDR;
 225         else if (pll == &pll5_video_main_clk)
 226                 return PLL5_VIDEO_BASE_ADDR;
 227         else if (pll == &pll6_mlb150_main_clk)
 228                 return PLL6_MLB_BASE_ADDR;
 229         else if (pll == &pll7_usb_host_main_clk)
 230                 return PLL7_480_USB2_BASE_ADDR;
 231         else if (pll == &pll8_enet_main_clk)
 232                 return PLL8_ENET_BASE_ADDR;
 233         else
 234                 BUG();
 235         return NULL;
 236 }
 237
 238
 239 /*
 240  * For the 6-to-1 muxed input clock
 241  */
 242 static inline u32 _get_mux6(struct clk *parent, struct clk *m0, struct clk *m1,
 243                             struct clk *m2, struct clk *m3, struct clk *m4,
 244                             struct clk *m5)
 245 {
 246         if (parent == m0)
 247                 return 0;
 248         else if (parent == m1)
 249                 return 1;
 250         else if (parent == m2)
 251                 return 2;
 252         else if (parent == m3)
 253                 return 3;
 254         else if (parent == m4)
 255                 return 4;
 256         else if (parent == m5)
 257                 return 5;
 258         else
 259                 BUG();
 260
 261         return 0;
 262 }
 263 static unsigned long get_high_reference_clock_rate(struct clk *clk)
 264 {
 265         return external_high_reference;
 266 }
 267
 268 static unsigned long get_low_reference_clock_rate(struct clk *clk)
 269 {
 270         return external_low_reference;
 271 }
 272
 273 static unsigned long get_oscillator_reference_clock_rate(struct clk *clk)
 274 {
 275         return oscillator_reference;
 276 }
 277
 278 static unsigned long get_ckih2_reference_clock_rate(struct clk *clk)
 279 {
 280         return ckih2_reference;
 281 }
 282
 283 static unsigned long _clk_anaclk_1_get_rate(struct clk *clk)
 284 {
 285         return anaclk_1_reference;
 286 }
 287
 288 static int _clk_anaclk_1_set_rate(struct clk *clk, unsigned long rate)
 289 {
 290         anaclk_1_reference = rate;
 291         return 0;
 292 }
 293
 294 static unsigned long _clk_anaclk_2_get_rate(struct clk *clk)
 295 {
 296         return anaclk_2_reference;
 297 }
 298
 299 static int _clk_anaclk_2_set_rate(struct clk *clk, unsigned long rate)
 300 {
 301         anaclk_2_reference = rate;
 302         return 0;
 303 }
 304
 305 /* External high frequency clock */
 306 static struct clk ckih_clk = {
 307         __INIT_CLK_DEBUG(ckih_clk)
 308         .get_rate = get_high_reference_clock_rate,
 309 };
 310
 311 static struct clk ckih2_clk = {
 312         __INIT_CLK_DEBUG(ckih2_clk)
 313         .get_rate = get_ckih2_reference_clock_rate,
 314 };
 315
 316 static struct clk osc_clk = {
 317         __INIT_CLK_DEBUG(osc_clk)
 318         .get_rate = get_oscillator_reference_clock_rate,
 319 };
 320
 321 /* External low frequency (32kHz) clock */
 322 static struct clk ckil_clk = {
 323         __INIT_CLK_DEBUG(ckil_clk)
 324         .get_rate = get_low_reference_clock_rate,
 325 };
 326
 327 static struct clk anaclk_1 = {
 328         __INIT_CLK_DEBUG(anaclk_1)
 329         .get_rate = _clk_anaclk_1_get_rate,
 330         .set_rate = _clk_anaclk_1_set_rate,
 331 };
 332
 333 static struct clk anaclk_2 = {
 334         __INIT_CLK_DEBUG(anaclk_2)
 335         .get_rate = _clk_anaclk_2_get_rate,
 336         .set_rate = _clk_anaclk_2_set_rate,
 337 };
 338
 339 static unsigned long pfd_round_rate(struct clk *clk, unsigned long rate)
 340 {
 341         u32 frac;
 342         u64 tmp;
 343
 344         tmp = (u64)clk_get_rate(clk->parent) * 18;
 345         tmp += rate/2;
 346         do_div(tmp, rate);
 347         frac = tmp;
 348         frac = frac < 12 ? 12 : frac;
 349         frac = frac > 35 ? 35 : frac;
 350         tmp = (u64)clk_get_rate(clk->parent) * 18;
 351         do_div(tmp, frac);
 352         return tmp;
 353 }
 354
 355 static unsigned long pfd_get_rate(struct clk *clk)
 356 {
 357         u32 frac;
 358         u64 tmp;
 359         tmp = (u64)clk_get_rate(clk->parent) * 18;
 360
 361         if (apbh_dma_clk.usecount == 0)
 362                 apbh_dma_clk.enable(&apbh_dma_clk);
 363
 364         frac = (__raw_readl(clk->enable_reg) >> clk->enable_shift) &
 365                         ANADIG_PFD_FRAC_MASK;
 366
 367         do_div(tmp, frac);
 368
 369         return tmp;
 370 }
 371
 372 static int pfd_set_rate(struct clk *clk, unsigned long rate)
 373 {
 374         u32 frac;
 375         u64 tmp;
 376         tmp = (u64)clk_get_rate(clk->parent) * 18;
 377
 378         if (apbh_dma_clk.usecount == 0)
 379                 apbh_dma_clk.enable(&apbh_dma_clk);
 380
 381         /* Round up the divider so that we don't set a rate
 382           * higher than what is requested. */
 383         tmp += rate/2;
 384         do_div(tmp, rate);
 385         frac = tmp;
 386         frac = frac < 12 ? 12 : frac;
 387         frac = frac > 35 ? 35 : frac;
 388         /* clear clk frac bits */
 389         __raw_writel(ANADIG_PFD_FRAC_MASK << clk->enable_shift,
 390                         (int)clk->enable_reg + 8);
 391         /* set clk frac bits */
 392         __raw_writel(frac << clk->enable_shift,
 393                         (int)clk->enable_reg + 4);
 394
 395         if (apbh_dma_clk.usecount == 0)
 396                 apbh_dma_clk.disable(&apbh_dma_clk);
 397         return 0;
 398 }
 399
 400 static int _clk_pfd_enable(struct clk *clk)
 401 {
 402         if (apbh_dma_clk.usecount == 0)
 403                 apbh_dma_clk.enable(&apbh_dma_clk);
 404
 405         /* clear clk gate bit */
 406         __raw_writel((1 << (clk->enable_shift + 7)),
 407                         (int)clk->enable_reg + 8);
 408
 409         if (apbh_dma_clk.usecount == 0)
 410                 apbh_dma_clk.disable(&apbh_dma_clk);
 411
 412         return 0;
 413 }
 414
 415 static void _clk_pfd_disable(struct clk *clk)
 416 {
 417         if (apbh_dma_clk.usecount == 0)
 418                 apbh_dma_clk.enable(&apbh_dma_clk);
 419
 420         /* set clk gate bit */
 421         __raw_writel((1 << (clk->enable_shift + 7)),
 422                         (int)clk->enable_reg + 4);
 423
 424         if (apbh_dma_clk.usecount == 0)
 425                 apbh_dma_clk.disable(&apbh_dma_clk);
 426 }
 427
 428 static int _clk_pll_enable(struct clk *clk)
 429 {
 430         unsigned int reg;
 431         void __iomem *pllbase;
 432
 433         pllbase = _get_pll_base(clk);
 434
 435         reg = __raw_readl(pllbase);
 436         reg &= ~ANADIG_PLL_BYPASS;
 437         reg &= ~ANADIG_PLL_POWER_DOWN;
 438
 439         /* The 480MHz PLLs have the opposite definition for power bit. */
 440         if (clk == &pll3_usb_otg_main_clk || clk == &pll7_usb_host_main_clk)
 441                 reg |= ANADIG_PLL_POWER_DOWN;
 442
 443         __raw_writel(reg, pllbase);
 444
 445         /* It will power on pll3 */
 446         if (clk == &pll3_usb_otg_main_clk)
 447                 __raw_writel(BM_ANADIG_ANA_MISC2_CONTROL0, apll_base + HW_ANADIG_ANA_MISC2_CLR);
 448
 449         /* Wait for PLL to lock */
 450         if (!WAIT(__raw_readl(pllbase) & ANADIG_PLL_LOCK,
 451                                 SPIN_DELAY))
 452                 panic("pll enable failed\n");
 453
 454         /* Enable the PLL output now*/
 455         reg = __raw_readl(pllbase);
 456         reg |= ANADIG_PLL_ENABLE;
 457         __raw_writel(reg, pllbase);
 458
 459         return 0;
 460 }
 461
 462 static void _clk_pll_disable(struct clk *clk)
 463 {
 464         unsigned int reg;
 465         void __iomem *pllbase;
 466
 467         pllbase = _get_pll_base(clk);
 468
 469         reg = __raw_readl(pllbase);
 470         reg |= ANADIG_PLL_BYPASS;
 471         reg &= ~ANADIG_PLL_ENABLE;
 472
 473         __raw_writel(reg, pllbase);
 474
 475         /*
 476          * It will power off PLL3's power, it is the TO1.1 fix
 477          * Please see TKT064178 for detail.
 478          */
 479         if (clk == &pll3_usb_otg_main_clk)
 480                 __raw_writel(BM_ANADIG_ANA_MISC2_CONTROL0, apll_base + HW_ANADIG_ANA_MISC2_SET);
 481 }
 482
 483 static unsigned long  _clk_pll1_main_get_rate(struct clk *clk)
 484 {
 485         unsigned int div;
 486         unsigned long val;
 487
 488         div = __raw_readl(PLL1_SYS_BASE_ADDR) & ANADIG_PLL_SYS_DIV_SELECT_MASK;
 489         val = (clk_get_rate(clk->parent) * div) / 2;
 490         return val;
 491 }
 492
 493 static int _clk_pll1_main_set_rate(struct clk *clk, unsigned long rate)
 494 {
 495         unsigned int reg, div;
 496
 497         if (rate < AUDIO_VIDEO_MIN_CLK_FREQ || rate > AUDIO_VIDEO_MAX_CLK_FREQ)
 498                 return -EINVAL;
 499
 500         div = (rate * 2) / clk_get_rate(clk->parent);
 501
 502         /* Update div */
 503         reg = __raw_readl(PLL1_SYS_BASE_ADDR) & ~ANADIG_PLL_SYS_DIV_SELECT_MASK;
 504         reg |= div;
 505         __raw_writel(reg, PLL1_SYS_BASE_ADDR);
 506
 507         /* Wait for PLL1 to lock */
 508         if (!WAIT(__raw_readl(PLL1_SYS_BASE_ADDR) & ANADIG_PLL_LOCK,
 509                                 SPIN_DELAY))
 510                 panic("pll1 enable failed\n");
 511
 512         return 0;
 513 }
 514
 515 static struct clk pll1_sys_main_clk = {
 516         __INIT_CLK_DEBUG(pll1_sys_main_clk)
 517         .parent = &osc_clk,
 518         .get_rate = _clk_pll1_main_get_rate,
 519         .set_rate = _clk_pll1_main_set_rate,
 520         .enable = _clk_pll_enable,
 521         .disable = _clk_pll_disable,
 522 };
 523
 524 static int _clk_pll1_sw_set_parent(struct clk *clk, struct clk *parent)
 525 {
 526         u32 reg;
 527
 528         reg = __raw_readl(MXC_CCM_CCSR);
 529
 530         if (parent == &pll1_sys_main_clk) {
 531                 reg &= ~MXC_CCM_CCSR_PLL1_SW_CLK_SEL;
 532                 __raw_writel(reg, MXC_CCM_CCSR);
 533                 /* Set the step_clk parent to be lp_apm, to save power. */
 534                 reg = __raw_readl(MXC_CCM_CCSR);
 535                 reg = (reg & ~MXC_CCM_CCSR_STEP_SEL);
 536         } else {
 537                 /* Set STEP_CLK to be the parent*/
 538                 if (parent == &osc_clk) {
 539                         /* Set STEP_CLK to be sourced from LPAPM. */
 540                         reg = __raw_readl(MXC_CCM_CCSR);
 541                         reg = (reg & ~MXC_CCM_CCSR_STEP_SEL);
 542                         __raw_writel(reg, MXC_CCM_CCSR);
 543                 } else {
 544                         /* Set STEP_CLK to be sourced from PLL2-PDF (400MHz). */
 545                         reg = __raw_readl(MXC_CCM_CCSR);
 546                         reg |= MXC_CCM_CCSR_STEP_SEL;
 547                         __raw_writel(reg, MXC_CCM_CCSR);
 548
 549                 }
 550                 reg = __raw_readl(MXC_CCM_CCSR);
 551                 reg |= MXC_CCM_CCSR_PLL1_SW_CLK_SEL;
 552         }
 553         __raw_writel(reg, MXC_CCM_CCSR);
 554         return 0;
 555 }
 556
 557 static unsigned long _clk_pll1_sw_get_rate(struct clk *clk)
 558 {
 559         return clk_get_rate(clk->parent);
 560 }
 561
 562 static struct clk pll1_sw_clk = {
 563         __INIT_CLK_DEBUG(pll1_sw_clk)
 564         .parent = &pll1_sys_main_clk,
 565         .set_parent = _clk_pll1_sw_set_parent,
 566         .get_rate = _clk_pll1_sw_get_rate,
 567 };
 568
 569 static unsigned long _clk_pll2_main_get_rate(struct clk *clk)
 570 {
 571         unsigned int div;
 572         unsigned long val;
 573
 574         div = __raw_readl(PLL2_528_BASE_ADDR) & ANADIG_PLL_528_DIV_SELECT;
 575
 576         if (div == 1)
 577                 val = clk_get_rate(clk->parent) * 22;
 578
 579         else
 580                 val = clk_get_rate(clk->parent) * 20;
 581
 582         return val;
 583 }
 584
 585 static int _clk_pll2_main_set_rate(struct clk *clk, unsigned long rate)
 586 {
 587         unsigned int reg,  div;
 588
 589         if (rate == 528000000)
 590                 div = 1;
 591         else if (rate == 480000000)
 592                 div = 0;
 593         else
 594                 return -EINVAL;
 595
 596         reg = __raw_readl(PLL2_528_BASE_ADDR);
 597         reg &= ~ANADIG_PLL_528_DIV_SELECT;
 598         reg |= div;
 599         __raw_writel(reg, PLL2_528_BASE_ADDR);
 600
 601         return 0;
 602 }
 603
 604 static struct clk pll2_528_bus_main_clk = {
 605         __INIT_CLK_DEBUG(pll2_528_bus_main_clk)
 606         .parent = &osc_clk,
 607         .get_rate = _clk_pll2_main_get_rate,
 608         .set_rate = _clk_pll2_main_set_rate,
 609         .enable = _clk_pll_enable,
 610         .disable = _clk_pll_disable,
 611 };
 612
 613 static struct clk pll2_pfd_400M = {
 614         __INIT_CLK_DEBUG(pll2_pfd_400M)
 615         .parent = &pll2_528_bus_main_clk,
 616         .enable_reg = (void *)PFD_528_BASE_ADDR,
 617         .enable_shift = ANADIG_PFD2_FRAC_OFFSET,
 618         .enable = _clk_pfd_enable,
 619         .disable = _clk_pfd_disable,
 620         .get_rate = pfd_get_rate,
 621         .set_rate = pfd_set_rate,
 622         .get_rate = pfd_get_rate,
 623         .round_rate = pfd_round_rate,
 624 };
 625
 626 static struct clk pll2_pfd_352M = {
 627         __INIT_CLK_DEBUG(pll2_pfd_352M)
 628         .parent = &pll2_528_bus_main_clk,
 629         .enable_reg = (void *)PFD_528_BASE_ADDR,
 630         .enable_shift = ANADIG_PFD0_FRAC_OFFSET,
 631         .enable = _clk_pfd_enable,
 632         .disable = _clk_pfd_disable,
 633         .set_rate = pfd_set_rate,
 634         .get_rate = pfd_get_rate,
 635         .round_rate = pfd_round_rate,
 636 };
 637
 638 static struct clk pll2_pfd_594M = {
 639         __INIT_CLK_DEBUG(pll2_pfd_594M)
 640         .parent = &pll2_528_bus_main_clk,
 641         .enable_reg = (void *)PFD_528_BASE_ADDR,
 642         .enable_shift = ANADIG_PFD1_FRAC_OFFSET,
 643         .enable = _clk_pfd_enable,
 644         .disable = _clk_pfd_disable,
 645         .set_rate = pfd_set_rate,
 646         .get_rate = pfd_get_rate,
 647         .round_rate = pfd_round_rate,
 648 };
 649
 650 static unsigned long _clk_pll2_200M_get_rate(struct clk *clk)
 651 {
 652         return clk_get_rate(clk->parent) / 2;
 653 }
 654
 655 static struct clk pll2_200M = {
 656         __INIT_CLK_DEBUG(pll2_200M)
 657         .parent = &pll2_pfd_400M,
 658         .get_rate = _clk_pll2_200M_get_rate,
 659 };
 660
 661 static unsigned long _clk_pll3_usb_otg_get_rate(struct clk *clk)
 662 {
 663         unsigned int div;
 664         unsigned long val;
 665
 666         div = __raw_readl(PLL3_480_USB1_BASE_ADDR)
 667                 & ANADIG_PLL_480_DIV_SELECT_MASK;
 668
 669         if (div == 1)
 670                 val = clk_get_rate(clk->parent) * 22;
 671         else
 672                 val = clk_get_rate(clk->parent) * 20;
 673         return val;
 674 }
 675
 676 static int _clk_pll3_usb_otg_set_rate(struct clk *clk, unsigned long rate)
 677 {
 678         unsigned int reg,  div;
 679
 680         if (rate == 528000000)
 681                 div = 1;
 682         else if (rate == 480000000)
 683                 div = 0;
 684         else
 685                 return -EINVAL;
 686
 687         reg = __raw_readl(PLL3_480_USB1_BASE_ADDR);
 688         reg &= ~ANADIG_PLL_480_DIV_SELECT_MASK;
 689         reg |= div;
 690         __raw_writel(reg, PLL3_480_USB1_BASE_ADDR);
 691
 692         return 0;
 693 }
 694
 695
 696 /* same as pll3_main_clk. These two clocks should always be the same */
 697 static struct clk pll3_usb_otg_main_clk = {
 698         __INIT_CLK_DEBUG(pll3_usb_otg_main_clk)
 699         .parent = &osc_clk,
 700         .enable = _clk_pll_enable,
 701         .disable = _clk_pll_disable,
 702         .set_rate = _clk_pll3_usb_otg_set_rate,
 703         .get_rate = _clk_pll3_usb_otg_get_rate,
 704 };
 705
 706 /* for USB OTG */
 707 static struct clk usb_phy1_clk = {
 708         __INIT_CLK_DEBUG(usb_phy1_clk)
 709         .parent = &pll3_usb_otg_main_clk,
 710         .set_rate = _clk_pll3_usb_otg_set_rate,
 711         .get_rate = _clk_pll3_usb_otg_get_rate,
 712 };
 713
 714 /* For HSIC port 1 */
 715 static struct clk usb_phy3_clk = {
 716         __INIT_CLK_DEBUG(usb_phy3_clk)
 717         .parent = &pll3_usb_otg_main_clk,
 718         .set_rate = _clk_pll3_usb_otg_set_rate,
 719         .get_rate = _clk_pll3_usb_otg_get_rate,
 720 };
 721
 722 /* For HSIC port 2 */
 723 static struct clk usb_phy4_clk = {
 724         __INIT_CLK_DEBUG(usb_phy4_clk)
 725         .parent = &pll3_usb_otg_main_clk,
 726         .set_rate = _clk_pll3_usb_otg_set_rate,
 727         .get_rate = _clk_pll3_usb_otg_get_rate,
 728 };
 729
 730 static struct clk pll3_pfd_508M = {
 731         __INIT_CLK_DEBUG(pll3_pfd_508M)
 732         .parent = &pll3_usb_otg_main_clk,
 733         .enable_reg = (void *)PFD_480_BASE_ADDR,
 734         .enable_shift = ANADIG_PFD2_FRAC_OFFSET,
 735         .enable = _clk_pfd_enable,
 736         .disable = _clk_pfd_disable,
 737         .set_rate = pfd_set_rate,
 738         .get_rate = pfd_get_rate,
 739         .round_rate = pfd_round_rate,
 740 };
 741
 742 static struct clk pll3_pfd_454M = {
 743         __INIT_CLK_DEBUG(pll3_pfd_454M)
 744         .parent = &pll3_usb_otg_main_clk,
 745         .enable_reg = (void *)PFD_480_BASE_ADDR,
 746         .enable_shift = ANADIG_PFD3_FRAC_OFFSET,
 747         .enable = _clk_pfd_enable,
 748         .disable = _clk_pfd_disable,
 749         .set_rate = pfd_set_rate,
 750         .get_rate = pfd_get_rate,
 751         .round_rate = pfd_round_rate,
 752 };
 753
 754 static struct clk pll3_pfd_720M = {
 755         __INIT_CLK_DEBUG(pll3_pfd_720M)
 756         .parent = &pll3_usb_otg_main_clk,
 757         .enable_reg = (void *)PFD_480_BASE_ADDR,
 758         .enable_shift = ANADIG_PFD0_FRAC_OFFSET,
 759         .enable = _clk_pfd_enable,
 760         .disable = _clk_pfd_disable,
 761         .set_rate = pfd_set_rate,
 762         .get_rate = pfd_get_rate,
 763         .round_rate = pfd_round_rate,
 764 };
 765
 766 static struct clk pll3_pfd_540M = {
 767         __INIT_CLK_DEBUG(pll3_pfd_540M)
 768         .parent = &pll3_usb_otg_main_clk,
 769         .enable_reg = (void *)PFD_480_BASE_ADDR,
 770         .enable_shift = ANADIG_PFD1_FRAC_OFFSET,
 771         .enable = _clk_pfd_enable,
 772         .disable = _clk_pfd_disable,
 773         .set_rate = pfd_set_rate,
 774         .get_rate = pfd_get_rate,
 775         .round_rate = pfd_round_rate,
 776         .get_rate = pfd_get_rate,
 777 };
 778
 779 static unsigned long _clk_pll3_sw_get_rate(struct clk *clk)
 780 {
 781         return clk_get_rate(clk->parent);
 782 }
 783
 784 /* same as pll3_main_clk. These two clocks should always be the same */
 785 static struct clk pll3_sw_clk = {
 786         __INIT_CLK_DEBUG(pll3_sw_clk)
 787         .parent = &pll3_usb_otg_main_clk,
 788         .get_rate = _clk_pll3_sw_get_rate,
 789 };
 790
 791 static unsigned long _clk_pll3_120M_get_rate(struct clk *clk)
 792 {
 793         return clk_get_rate(clk->parent) / 4;
 794 }
 795
 796 static struct clk pll3_120M = {
 797         __INIT_CLK_DEBUG(pll3_120M)
 798         .parent = &pll3_sw_clk,
 799         .get_rate = _clk_pll3_120M_get_rate,
 800 };
 801
 802 static unsigned long _clk_pll3_80M_get_rate(struct clk *clk)
 803 {
 804         return clk_get_rate(clk->parent) / 6;
 805 }
 806
 807 static struct clk pll3_80M = {
 808         __INIT_CLK_DEBUG(pll3_80M)
 809         .parent = &pll3_sw_clk,
 810         .get_rate = _clk_pll3_80M_get_rate,
 811 };
 812
 813 static unsigned long _clk_pll3_60M_get_rate(struct clk *clk)
 814 {
 815         return clk_get_rate(clk->parent) / 8;
 816 }
 817
 818 static struct clk pll3_60M = {
 819         __INIT_CLK_DEBUG(pll3_60M)
 820         .parent = &pll3_sw_clk,
 821         .get_rate = _clk_pll3_60M_get_rate,
 822 };
 823
 824 static unsigned long  _clk_audio_video_get_rate(struct clk *clk)
 825 {
 826         unsigned int div, mfn, mfd;
 827         unsigned long rate;
 828         unsigned int parent_rate = clk_get_rate(clk->parent);
 829         void __iomem *pllbase;
 830         int rev = mx6q_revision();
 831         unsigned int test_div_sel, control3, post_div = 1;
 832
 833         if (clk == &pll4_audio_main_clk)
 834                 pllbase = PLL4_AUDIO_BASE_ADDR;
 835         else
 836                 pllbase = PLL5_VIDEO_BASE_ADDR;
 837
 838         if ((rev >= IMX_CHIP_REVISION_1_1) || cpu_is_mx6dl()) {
 839                 test_div_sel = (__raw_readl(pllbase)
 840                         & ANADIG_PLL_AV_TEST_DIV_SEL_MASK)
 841                         >> ANADIG_PLL_AV_TEST_DIV_SEL_OFFSET;
 842                 if (test_div_sel == 0)
 843                         post_div = 4;
 844                 else if (test_div_sel == 1)
 845                         post_div = 2;
 846
 847                 if (clk == &pll5_video_main_clk) {
 848                         control3 = (__raw_readl(ANA_MISC2_BASE_ADDR)
 849                                 & ANADIG_ANA_MISC2_CONTROL3_MASK)
 850                                 >> ANADIG_ANA_MISC2_CONTROL3_OFFSET;
 851                         if (control3 == 1)
 852                                 post_div *= 2;
 853                         else if (control3 == 3)
 854                                 post_div *= 4;
 855                 }
 856         }
 857
 858         div = __raw_readl(pllbase) & ANADIG_PLL_SYS_DIV_SELECT_MASK;
 859         mfn = __raw_readl(pllbase + PLL_NUM_DIV_OFFSET);
 860         mfd = __raw_readl(pllbase + PLL_DENOM_DIV_OFFSET);
 861
 862         rate = (parent_rate * div) + ((parent_rate / mfd) * mfn);
 863         rate = rate / post_div;
 864
 865         return rate;
 866 }
 867
 868 static int _clk_audio_video_set_rate(struct clk *clk, unsigned long rate)
 869 {
 870         unsigned int reg,  div;
 871         unsigned int mfn, mfd = 1000000;
 872         s64 temp64;
 873         unsigned int parent_rate = clk_get_rate(clk->parent);
 874         void __iomem *pllbase;
 875         unsigned long min_clk_rate, pre_div_rate;
 876         int rev = mx6q_revision();
 877         u32 test_div_sel = 2;
 878         u32 control3 = 0;
 879
 880         if ((rev < IMX_CHIP_REVISION_1_1) && !cpu_is_mx6dl())
 881                 min_clk_rate = AUDIO_VIDEO_MIN_CLK_FREQ;
 882         else if (clk == &pll4_audio_main_clk)
 883                 min_clk_rate = AUDIO_VIDEO_MIN_CLK_FREQ / 4;
 884         else
 885                 min_clk_rate = AUDIO_VIDEO_MIN_CLK_FREQ / 16;
 886
 887         if ((rate < min_clk_rate) || (rate > AUDIO_VIDEO_MAX_CLK_FREQ))
 888                 return -EINVAL;
 889
 890         if (clk == &pll4_audio_main_clk)
 891                 pllbase = PLL4_AUDIO_BASE_ADDR;
 892         else
 893                 pllbase = PLL5_VIDEO_BASE_ADDR;
 894
 895         pre_div_rate = rate;
 896         if ((rev >= IMX_CHIP_REVISION_1_1) || cpu_is_mx6dl()) {
 897                 while (pre_div_rate < AUDIO_VIDEO_MIN_CLK_FREQ) {
 898                         pre_div_rate *= 2;
 899                         /*
 900                          * test_div_sel field values:
 901                          * 2 -> Divide by 1
 902                          * 1 -> Divide by 2
 903                          * 0 -> Divide by 4
 904                          *
 905                          * control3 field values:
 906                          * 0 -> Divide by 1
 907                          * 1 -> Divide by 2
 908                          * 3 -> Divide by 4
 909                          */
 910                         if (test_div_sel != 0)
 911                                 test_div_sel--;
 912                         else {
 913                                 control3++;
 914                                 if (control3 == 2)
 915                                         control3++;
 916                         }
 917                 }
 918         }
 919
 920         div = pre_div_rate / parent_rate;
 921         temp64 = (u64) (pre_div_rate - (div * parent_rate));
 922         temp64 *= mfd;
 923         do_div(temp64, parent_rate);
 924         mfn = temp64;
 925
 926         reg = __raw_readl(pllbase)
 927                         & ~ANADIG_PLL_SYS_DIV_SELECT_MASK
 928                         & ~ANADIG_PLL_AV_TEST_DIV_SEL_MASK;
 929         reg |= div |
 930                 (test_div_sel << ANADIG_PLL_AV_TEST_DIV_SEL_OFFSET);
 931         __raw_writel(reg, pllbase);
 932         __raw_writel(mfn, pllbase + PLL_NUM_DIV_OFFSET);
 933         __raw_writel(mfd, pllbase + PLL_DENOM_DIV_OFFSET);
 934
 935         if (rev >= IMX_CHIP_REVISION_1_1) {
 936                 reg = __raw_readl(ANA_MISC2_BASE_ADDR)
 937                         & ~ANADIG_ANA_MISC2_CONTROL3_MASK;
 938                 reg |= control3 << ANADIG_ANA_MISC2_CONTROL3_OFFSET;
 939                 __raw_writel(reg, ANA_MISC2_BASE_ADDR);
 940         }
 941
 942         return 0;
 943 }
 944
 945 static unsigned long _clk_audio_video_round_rate(struct clk *clk,
 946                                                 unsigned long rate)
 947 {
 948         unsigned long min_clk_rate;
 949         unsigned int div, post_div = 1;
 950         unsigned int mfn, mfd = 1000000;
 951         s64 temp64;
 952         unsigned int parent_rate = clk_get_rate(clk->parent);
 953         unsigned long pre_div_rate;
 954         u32 test_div_sel = 2;
 955         u32 control3 = 0;
 956         unsigned long final_rate;
 957         int rev = mx6q_revision();
 958
 959         if ((rev < IMX_CHIP_REVISION_1_1) && !cpu_is_mx6dl())
 960                 min_clk_rate = AUDIO_VIDEO_MIN_CLK_FREQ;
 961         else if (clk == &pll4_audio_main_clk)
 962                 min_clk_rate = AUDIO_VIDEO_MIN_CLK_FREQ / 4;
 963         else
 964                 min_clk_rate = AUDIO_VIDEO_MIN_CLK_FREQ / 16;
 965
 966         if (rate < min_clk_rate)
 967                 return min_clk_rate;
 968
 969         if (rate > AUDIO_VIDEO_MAX_CLK_FREQ)
 970                 return AUDIO_VIDEO_MAX_CLK_FREQ;
 971
 972         pre_div_rate = rate;
 973         if ((rev >= IMX_CHIP_REVISION_1_1) || cpu_is_mx6dl()) {
 974                 while (pre_div_rate < AUDIO_VIDEO_MIN_CLK_FREQ) {
 975                         pre_div_rate *= 2;
 976                         post_div *= 2;
 977                         if (test_div_sel != 0)
 978                                 test_div_sel--;
 979                         else {
 980                                 control3++;
 981                                 if (control3 == 2)
 982                                         control3++;
 983                         }
 984                 }
 985         }
 986
 987         div = pre_div_rate / parent_rate;
 988         temp64 = (u64) (pre_div_rate - (div * parent_rate));
 989         temp64 *= mfd;
 990         do_div(temp64, parent_rate);
 991         mfn = temp64;
 992
 993         final_rate = (parent_rate * div) + ((parent_rate / mfd) * mfn);
 994         final_rate = final_rate / post_div;
 995
 996         return final_rate;
 997 }
 998
 999 static int _clk_audio_video_set_parent(struct clk *clk, struct clk *parent)
1000 {
1001         u32 reg;
1002         int mux;
1003         void __iomem *pllbase;
1004
1005         if (clk == &pll4_audio_main_clk)
1006                 pllbase = PLL4_AUDIO_BASE_ADDR;
1007         else
1008                 pllbase = PLL5_VIDEO_BASE_ADDR;
1009
1010         reg = __raw_readl(pllbase) & ~ANADIG_PLL_BYPASS_CLK_SRC_MASK;
1011         mux = _get_mux6(parent, &osc_clk, &anaclk_1, &anaclk_2,
1012                                 NULL, NULL, NULL);
1013         reg |= mux << ANADIG_PLL_BYPASS_CLK_SRC_OFFSET;
1014         __raw_writel(reg, pllbase);
1015
1016         /* Set anaclk_x as input */
1017         if (parent == &anaclk_1) {
1018                 reg = __raw_readl(ANADIG_MISC1_REG);
1019                 reg |= (ANATOP_LVDS_CLK1_IBEN_MASK &
1020                                 ~ANATOP_LVDS_CLK1_OBEN_MASK);
1021                 __raw_writel(reg, ANADIG_MISC1_REG);
1022         } else if (parent == &anaclk_2) {
1023                 reg = __raw_readl(ANADIG_MISC1_REG);
1024                 reg |= (ANATOP_LVDS_CLK2_IBEN_MASK &
1025                                 ~ANATOP_LVDS_CLK2_OBEN_MASK);
1026                 __raw_writel(reg, ANADIG_MISC1_REG);
1027         }
1028
1029         return 0;
1030 }
1031
1032 static struct clk pll4_audio_main_clk = {
1033         __INIT_CLK_DEBUG(pll4_audio_main_clk)
1034         .parent = &osc_clk,
1035         .enable = _clk_pll_enable,
1036         .disable = _clk_pll_disable,
1037         .set_rate = _clk_audio_video_set_rate,
1038         .get_rate = _clk_audio_video_get_rate,
1039         .round_rate = _clk_audio_video_round_rate,
1040         .set_parent = _clk_audio_video_set_parent,
1041 };
1042
1043 static struct clk pll5_video_main_clk = {
1044         __INIT_CLK_DEBUG(pll5_video_main_clk)
1045         .parent = &osc_clk,
1046         .enable = _clk_pll_enable,
1047         .disable = _clk_pll_disable,
1048         .set_rate = _clk_audio_video_set_rate,
1049         .get_rate = _clk_audio_video_get_rate,
1050         .round_rate = _clk_audio_video_round_rate,
1051         .set_parent = _clk_audio_video_set_parent,
1052 };
1053
1054 static int _clk_pll_mlb_main_enable(struct clk *clk)
1055 {
1056         unsigned int reg;
1057         void __iomem *pllbase;
1058
1059         pllbase = _get_pll_base(clk);
1060
1061         reg = __raw_readl(pllbase);
1062         reg &= ~ANADIG_PLL_BYPASS;
1063
1064         reg = 0x0da20000;
1065         __raw_writel(reg, pllbase);
1066
1067         /* Wait for PLL to lock */
1068         if (!WAIT(__raw_readl(pllbase) & ANADIG_PLL_LOCK,
1069                 SPIN_DELAY))
1070                 panic("pll enable failed\n");
1071
1072         return 0;
1073 }
1074
1075 static struct clk pll6_mlb150_main_clk = {
1076         __INIT_CLK_DEBUG(pll6_mlb150_main_clk)
1077         .parent = &osc_clk,
1078         .enable = _clk_pll_mlb_main_enable,
1079         .disable = _clk_pll_disable,
1080 };
1081
1082 static unsigned long _clk_pll7_usb_otg_get_rate(struct clk *clk)
1083 {
1084         unsigned int div;
1085         unsigned long val;
1086
1087         div = __raw_readl(PLL7_480_USB2_BASE_ADDR)
1088                 & ANADIG_PLL_480_DIV_SELECT_MASK;
1089
1090         if (div == 1)
1091                 val = clk_get_rate(clk->parent) * 22;
1092         else
1093                 val = clk_get_rate(clk->parent) * 20;
1094         return val;
1095 }
1096
1097 static int _clk_pll7_usb_otg_set_rate(struct clk *clk, unsigned long rate)
1098 {
1099         unsigned int reg,  div;
1100
1101         if (rate == 528000000)
1102                 div = 1;
1103         else if (rate == 480000000)
1104                 div = 0;
1105         else
1106                 return -EINVAL;
1107
1108         reg = __raw_readl(PLL7_480_USB2_BASE_ADDR);
1109         reg &= ~ANADIG_PLL_480_DIV_SELECT_MASK;
1110         reg |= div;
1111         __raw_writel(reg, PLL7_480_USB2_BASE_ADDR);
1112
1113         return 0;
1114 }
1115
1116 static struct clk pll7_usb_host_main_clk = {
1117         __INIT_CLK_DEBUG(pll7_usb_host_main_clk)
1118         .parent = &osc_clk,
1119         .enable = _clk_pll_enable,
1120         .disable = _clk_pll_disable,
1121         .set_rate = _clk_pll7_usb_otg_set_rate,
1122         .get_rate = _clk_pll7_usb_otg_get_rate,
1123
1124 };
1125
1126 static struct clk pll8_enet_main_clk = {
1127         __INIT_CLK_DEBUG(pll8_enet_main_clk)
1128         .parent = &osc_clk,
1129         .enable = _clk_pll_enable,
1130         .disable = _clk_pll_disable,
1131 };
1132
1133 static unsigned long _clk_arm_get_rate(struct clk *clk)
1134 {
1135         u32 cacrr, div;
1136
1137         cacrr = __raw_readl(MXC_CCM_CACRR);
1138         div = (cacrr & MXC_CCM_CACRR_ARM_PODF_MASK) + 1;
1139         return clk_get_rate(clk->parent) / div;
1140 }
1141
1142 static int _clk_arm_set_rate(struct clk *clk, unsigned long rate)
1143 {
1144         int i;
1145         u32 div;
1146         u32 parent_rate;
1147
1148
1149         for (i = 0; i < cpu_op_nr; i++) {
1150                 if (rate == cpu_op_tbl[i].cpu_rate)
1151                         break;
1152         }
1153         if (i >= cpu_op_nr)
1154                 return -EINVAL;
1155
1156         if (cpu_op_tbl[i].pll_rate != clk_get_rate(&pll1_sys_main_clk)) {
1157                 /* Change the PLL1 rate. */
1158                 if (pll2_pfd_400M.usecount != 0)
1159                         pll1_sw_clk.set_parent(&pll1_sw_clk, &pll2_pfd_400M);
1160                 else
1161                         pll1_sw_clk.set_parent(&pll1_sw_clk, &osc_clk);
1162                 pll1_sys_main_clk.set_rate(&pll1_sys_main_clk, cpu_op_tbl[i].pll_rate);
1163                 pll1_sw_clk.set_parent(&pll1_sw_clk, &pll1_sys_main_clk);
1164         }
1165
1166         parent_rate = clk_get_rate(clk->parent);
1167         div = parent_rate / rate;
1168
1169         if (div == 0)
1170                 div = 1;
1171
1172         if ((parent_rate / div) > rate)
1173                 div++;
1174
1175         if (div > 8)
1176                 return -1;
1177
1178         __raw_writel(div - 1, MXC_CCM_CACRR);
1179
1180         return 0;
1181 }
1182
1183 static struct clk cpu_clk = {
1184         __INIT_CLK_DEBUG(cpu_clk)
1185         .parent = &pll1_sw_clk,
1186         .set_rate = _clk_arm_set_rate,
1187         .get_rate = _clk_arm_get_rate,
1188 };
1189
1190 static unsigned long _clk_twd_get_rate(struct clk *clk)
1191 {
1192         return clk_get_rate(clk->parent) / 2;
1193 }
1194
1195 static struct clk twd_clk = {
1196         __INIT_CLK_DEBUG(twd_clk)
1197         .parent = &cpu_clk,
1198         .get_rate = _clk_twd_get_rate,
1199 };
1200
1201 static int _clk_periph_set_parent(struct clk *clk, struct clk *parent)
1202 {
1203         u32 reg;
1204         int mux;
1205
1206         mux = _get_mux6(parent, &pll2_528_bus_main_clk, &pll2_pfd_400M,
1207                 &pll2_pfd_352M, &pll2_200M, &pll3_sw_clk, &osc_clk);
1208
1209         if (mux <= 3) {
1210                 /* Set the pre_periph_clk multiplexer */
1211                 reg = __raw_readl(MXC_CCM_CBCMR);
1212                 reg &= ~MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK;
1213                 reg |= mux << MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET;
1214                 __raw_writel(reg, MXC_CCM_CBCMR);
1215
1216                 /* Set the periph_clk_sel multiplexer. */
1217                 reg = __raw_readl(MXC_CCM_CBCDR);
1218                 reg &= ~MXC_CCM_CBCDR_PERIPH_CLK_SEL;
1219                 __raw_writel(reg, MXC_CCM_CBCDR);
1220         } else {
1221                 reg = __raw_readl(MXC_CCM_CBCDR);
1222                 /* Set the periph_clk2_podf divider to divide by 1. */
1223                 reg &= ~MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK;
1224                 __raw_writel(reg, MXC_CCM_CBCDR);
1225
1226                 /* Set the periph_clk2_sel mux. */
1227                 reg = __raw_readl(MXC_CCM_CBCMR);
1228                 reg &= ~MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK;
1229                 reg |= ((mux - 4) << MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET);
1230                 __raw_writel(reg, MXC_CCM_CBCMR);
1231
1232                 while (__raw_readl(MXC_CCM_CDHIPR))
1233                         ;
1234
1235                 reg = __raw_readl(MXC_CCM_CBCDR);
1236                 /* Set periph_clk_sel to select periph_clk2. */
1237                 reg |= MXC_CCM_CBCDR_PERIPH_CLK_SEL;
1238                 __raw_writel(reg, MXC_CCM_CBCDR);
1239         }
1240
1241         if (!WAIT(!(__raw_readl(MXC_CCM_CDHIPR)
1242              & MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY), SPIN_DELAY))
1243                 panic("_clk_periph_set_parent failed\n");
1244
1245         return 0;
1246 }
1247
1248 static unsigned long _clk_periph_get_rate(struct clk *clk)
1249 {
1250         u32 div = 1;
1251         u32 reg;
1252         unsigned long val;
1253
1254         if ((clk->parent == &pll3_sw_clk) || (clk->parent == &osc_clk)) {
1255                 reg = __raw_readl(MXC_CCM_CBCDR)
1256                         & MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK;
1257                 div = (reg >> MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET) + 1;
1258         }
1259         val = clk_get_rate(clk->parent) / div;
1260         return val;
1261 }
1262
1263 static struct clk periph_clk = {
1264         __INIT_CLK_DEBUG(periph_clk)
1265         .parent = &pll2_528_bus_main_clk,
1266         .set_parent = _clk_periph_set_parent,
1267         .get_rate = _clk_periph_get_rate,
1268 };
1269
1270 static unsigned long _clk_axi_get_rate(struct clk *clk)
1271 {
1272         u32 div, reg;
1273         unsigned long val;
1274
1275         reg = __raw_readl(MXC_CCM_CBCDR) & MXC_CCM_CBCDR_AXI_PODF_MASK;
1276         div = (reg >> MXC_CCM_CBCDR_AXI_PODF_OFFSET);
1277
1278         val = clk_get_rate(clk->parent) / (div + 1);
1279         return val;
1280 }
1281
1282 static int _clk_axi_set_rate(struct clk *clk, unsigned long rate)
1283 {
1284         u32 reg, div;
1285         u32 parent_rate = clk_get_rate(clk->parent);
1286
1287         div = parent_rate / rate;
1288
1289         if (div == 0)
1290                 div++;
1291         if (((parent_rate / div) != rate) || (div > 8))
1292                 return -EINVAL;
1293
1294         reg = __raw_readl(MXC_CCM_CBCDR);
1295         reg &= ~MXC_CCM_CBCDR_AXI_PODF_MASK;
1296         reg |= (div - 1) << MXC_CCM_CBCDR_AXI_PODF_OFFSET;
1297         __raw_writel(reg, MXC_CCM_CBCDR);
1298
1299         if (!WAIT(!(__raw_readl(MXC_CCM_CDHIPR)
1300              & MXC_CCM_CDHIPR_AXI_PODF_BUSY), SPIN_DELAY))
1301                 panic("pll _clk_axi_a_set_rate failed\n");
1302
1303         return 0;
1304 }
1305
1306 static unsigned long _clk_axi_round_rate(struct clk *clk,
1307                                                 unsigned long rate)
1308 {
1309         u32 div;
1310         u32 parent_rate = clk_get_rate(clk->parent);
1311
1312         div = parent_rate / rate;
1313
1314         /* Make sure rate is not greater than the maximum
1315          * value for the clock.
1316          * Also prevent a div of 0.
1317          */
1318
1319         if (div > 8)
1320                 div = 8;
1321         else if (div == 0)
1322                 div++;
1323
1324         return parent_rate / div;
1325 }
1326
1327 static int _clk_axi_set_parent(struct clk *clk, struct clk *parent)
1328 {
1329         u32 reg;
1330         int mux;
1331
1332         mux = _get_mux6(parent, &periph_clk, &pll2_pfd_400M,
1333                                 &pll3_pfd_540M, NULL, NULL, NULL);
1334
1335         if (mux == 0) {
1336                 /* Set the AXI_SEL mux */
1337                 reg = __raw_readl(MXC_CCM_CBCDR) & ~MXC_CCM_CBCDR_AXI_SEL;
1338                 __raw_writel(reg, MXC_CCM_CBCDR);
1339         } else {
1340                 /* Set the AXI_ALT_SEL mux. */
1341                 reg = __raw_readl(MXC_CCM_CBCDR)
1342                         & ~MXC_CCM_CBCDR_AXI_ALT_SEL_MASK;
1343                 reg |= ((mux - 1) << MXC_CCM_CBCDR_AXI_ALT_SEL_OFFSET);
1344                 __raw_writel(reg, MXC_CCM_CBCDR);
1345
1346                 /* Set the AXI_SEL mux */
1347                 reg = __raw_readl(MXC_CCM_CBCDR) & ~MXC_CCM_CBCDR_AXI_SEL;
1348                 reg |= MXC_CCM_CBCDR_AXI_SEL;
1349                 __raw_writel(reg, MXC_CCM_CBCDR);
1350         }
1351         return 0;
1352 }
1353
1354 static struct clk axi_clk = {
1355         __INIT_CLK_DEBUG(axi_clk)
1356         .parent = &periph_clk,
1357         .set_parent = _clk_axi_set_parent,
1358         .set_rate = _clk_axi_set_rate,
1359         .get_rate = _clk_axi_get_rate,
1360         .round_rate = _clk_axi_round_rate,
1361 };
1362
1363 static unsigned long _clk_ahb_get_rate(struct clk *clk)
1364 {
1365         u32 reg, div;
1366
1367         reg = __raw_readl(MXC_CCM_CBCDR);
1368         div = ((reg & MXC_CCM_CBCDR_AHB_PODF_MASK) >>
1369                MXC_CCM_CBCDR_AHB_PODF_OFFSET) + 1;
1370
1371         return clk_get_rate(clk->parent) / div;
1372 }
1373
1374 static int _clk_ahb_set_rate(struct clk *clk, unsigned long rate)
1375 {
1376         u32 reg, div;
1377         u32 parent_rate = clk_get_rate(clk->parent);
1378
1379         div = parent_rate / rate;
1380         if (div == 0)
1381                 div++;
1382         if (((parent_rate / div) != rate) || (div > 8))
1383                 return -EINVAL;
1384
1385         reg = __raw_readl(MXC_CCM_CBCDR);
1386         reg &= ~MXC_CCM_CBCDR_AHB_PODF_MASK;
1387         reg |= (div - 1) << MXC_CCM_CBCDR_AHB_PODF_OFFSET;
1388         __raw_writel(reg, MXC_CCM_CBCDR);
1389
1390         if (!WAIT(!(__raw_readl(MXC_CCM_CDHIPR) & MXC_CCM_CDHIPR_AHB_PODF_BUSY),
1391                                 SPIN_DELAY))
1392                         panic("_clk_ahb_set_rate failed\n");
1393
1394         return 0;
1395 }
1396
1397 static unsigned long _clk_ahb_round_rate(struct clk *clk,
1398                                                 unsigned long rate)
1399 {
1400         u32 div;
1401         u32 parent_rate = clk_get_rate(clk->parent);
1402
1403         div = parent_rate / rate;
1404
1405         /* Make sure rate is not greater than the maximum value for the clock.
1406          * Also prevent a div of 0.
1407          */
1408         if (div == 0)
1409                 div++;
1410
1411         if (div > 8)
1412                 div = 8;
1413
1414         return parent_rate / div;
1415 }
1416
1417 static struct clk ahb_clk = {
1418         __INIT_CLK_DEBUG(ahb_clk)
1419         .parent = &periph_clk,
1420         .get_rate = _clk_ahb_get_rate,
1421         .set_rate = _clk_ahb_set_rate,
1422         .round_rate = _clk_ahb_round_rate,
1423 };
1424
1425 static unsigned long _clk_ipg_get_rate(struct clk *clk)
1426 {
1427         u32 reg, div;
1428
1429         reg = __raw_readl(MXC_CCM_CBCDR);
1430         div = ((reg & MXC_CCM_CBCDR_IPG_PODF_MASK) >>
1431                 MXC_CCM_CBCDR_IPG_PODF_OFFSET) + 1;
1432
1433         return clk_get_rate(clk->parent) / div;
1434 }
1435
1436
1437 static struct clk ipg_clk = {
1438         __INIT_CLK_DEBUG(ipg_clk)
1439         .parent = &ahb_clk,
1440         .get_rate = _clk_ipg_get_rate,
1441 };
1442
1443 static struct clk tzasc1_clk = {
1444         __INIT_CLK_DEBUG(tzasc1_clk)
1445         .id = 0,
1446         .parent = &ipg_clk,
1447         .enable_reg = MXC_CCM_CCGR2,
1448         .enable_shift = MXC_CCM_CCGRx_CG11_OFFSET,
1449         .enable = _clk_enable,
1450         .disable = _clk_disable_inwait,
1451 };
1452
1453 static struct clk tzasc2_clk = {
1454         __INIT_CLK_DEBUG(tzasc2_clk)
1455         .id = 0,
1456         .parent = &ipg_clk,
1457         .enable_reg = MXC_CCM_CCGR2,
1458         .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET,
1459         .enable = _clk_enable,
1460         .disable = _clk_disable_inwait,
1461 };
1462
1463 static struct clk mx6fast1_clk = {
1464         __INIT_CLK_DEBUG(mx6fast1_clk)
1465         .id = 0,
1466         .parent = &ahb_clk,
1467         .enable_reg = MXC_CCM_CCGR4,
1468         .enable_shift = MXC_CCM_CCGRx_CG4_OFFSET,
1469         .enable = _clk_enable,
1470         .disable = _clk_disable_inwait,
1471 };
1472
1473 static struct clk mx6per1_clk = {
1474         __INIT_CLK_DEBUG(mx6per1_clk)
1475         .id = 0,
1476         .parent = &ahb_clk,
1477         .secondary = &mx6fast1_clk,
1478         .enable_reg = MXC_CCM_CCGR4,
1479         .enable_shift = MXC_CCM_CCGRx_CG6_OFFSET,
1480         .enable = _clk_enable,
1481         .disable = _clk_disable_inwait,
1482 };
1483
1484 static struct clk mx6per2_clk = {
1485         __INIT_CLK_DEBUG(mx6per2_clk)
1486         .id = 0,
1487         .parent = &ahb_clk,
1488         .enable_reg = MXC_CCM_CCGR4,
1489         .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
1490         .enable = _clk_enable,
1491         .disable = _clk_disable_inwait,
1492 };
1493
1494 static unsigned long _clk_mmdc_ch0_axi_get_rate(struct clk *clk)
1495 {
1496         u32 reg, div;
1497
1498         reg = __raw_readl(MXC_CCM_CBCDR);
1499         div = ((reg & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
1500                         MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET) + 1;
1501
1502         return clk_get_rate(clk->parent) / div;
1503 }
1504
1505 static int _clk_mmdc_ch0_axi_set_rate(struct clk *clk, unsigned long rate)
1506 {
1507         u32 reg, div;
1508         u32 parent_rate = clk_get_rate(clk->parent);
1509
1510         div = parent_rate / rate;
1511         if (div == 0)
1512                 div++;
1513         if (((parent_rate / div) != rate) || (div > 8))
1514                 return -EINVAL;
1515
1516         reg = __raw_readl(MXC_CCM_CBCDR);
1517         reg &= ~MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK;
1518         reg |= (div - 1) << MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
1519         __raw_writel(reg, MXC_CCM_CBCDR);
1520
1521         if (!WAIT(!(__raw_readl(MXC_CCM_CDHIPR)
1522                 & MXC_CCM_CDHIPR_MMDC_CH0_PODF_BUSY),
1523                                 SPIN_DELAY))
1524                         panic("_clk_mmdc_ch0_axi_set_rate failed\n");
1525
1526         return 0;
1527 }
1528
1529 static unsigned long _clk_mmdc_ch0_axi_round_rate(struct clk *clk,
1530                                                 unsigned long rate)
1531 {
1532         u32 div;
1533         u32 parent_rate = clk_get_rate(clk->parent);
1534
1535         div = parent_rate / rate;
1536
1537         /* Make sure rate is not greater than the maximum value for the clock.
1538          * Also prevent a div of 0.
1539          */
1540         if (div == 0)
1541                 div++;
1542
1543         if (div > 8)
1544                 div = 8;
1545
1546         return parent_rate / div;
1547 }
1548
1549 static struct clk mmdc_ch0_axi_clk[] = {
1550         {
1551         __INIT_CLK_DEBUG(mmdc_ch0_axi_clk)
1552         .id = 0,
1553         .parent = &periph_clk,
1554         .enable = _clk_enable,
1555         .disable = _clk_disable_inwait,
1556         .enable_reg = MXC_CCM_CCGR3,
1557         .enable_shift = MXC_CCM_CCGRx_CG10_OFFSET,
1558         .secondary = &mmdc_ch0_axi_clk[1],
1559         .get_rate = _clk_mmdc_ch0_axi_get_rate,
1560         .set_rate = _clk_mmdc_ch0_axi_set_rate,
1561         .round_rate = _clk_mmdc_ch0_axi_round_rate,
1562         },
1563         {
1564         __INIT_CLK_DEBUG(mmdc_ch0_ipg_clk)
1565         .id = 0,
1566         .parent = &ipg_clk,
1567         .enable = _clk_enable,
1568         .disable = _clk_disable_inwait,
1569         .enable_reg = MXC_CCM_CCGR3,
1570         .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET,
1571         .secondary = &tzasc1_clk,
1572         },
1573 };
1574
1575 static unsigned long _clk_mmdc_ch1_axi_get_rate(struct clk *clk)
1576 {
1577         u32 reg, div;
1578
1579         reg = __raw_readl(MXC_CCM_CBCDR);
1580         div = ((reg & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) >>
1581                         MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET) + 1;
1582
1583         return clk_get_rate(clk->parent) / div;
1584 }
1585
1586 static int _clk_mmdc_ch1_axi_set_rate(struct clk *clk, unsigned long rate)
1587 {
1588         u32 reg, div;
1589         u32 parent_rate = clk_get_rate(clk->parent);
1590
1591         div = parent_rate / rate;
1592         if (div == 0)
1593                 div++;
1594         if (((parent_rate / div) != rate) || (div > 8))
1595                 return -EINVAL;
1596
1597         reg = __raw_readl(MXC_CCM_CBCDR);
1598         reg &= ~MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK;
1599         reg |= (div - 1) << MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
1600         __raw_writel(reg, MXC_CCM_CBCDR);
1601
1602         if (!WAIT(!(__raw_readl(MXC_CCM_CDHIPR)
1603                 & MXC_CCM_CDHIPR_MMDC_CH1_PODF_BUSY), SPIN_DELAY))
1604                         panic("_clk_mmdc_ch1_axi_set_rate failed\n");
1605
1606         return 0;
1607 }
1608
1609 static unsigned long _clk_mmdc_ch1_axi_round_rate(struct clk *clk,
1610                                                 unsigned long rate)
1611 {
1612         u32 div;
1613         u32 parent_rate = clk_get_rate(clk->parent);
1614
1615         div = parent_rate / rate;
1616
1617         /* Make sure rate is not greater than the maximum value for the clock.
1618          * Also prevent a div of 0.
1619          */
1620         if (div == 0)
1621                 div++;
1622
1623         if (div > 8)
1624                 div = 8;
1625
1626         return parent_rate / div;
1627 }
1628
1629 static struct clk mmdc_ch1_axi_clk[] = {
1630         {
1631         __INIT_CLK_DEBUG(mmdc_ch1_axi_clk)
1632         .id = 0,
1633         .parent = &pll2_pfd_400M,
1634         .enable = _clk_enable,
1635         .disable = _clk_disable,
1636         .enable_reg = MXC_CCM_CCGR3,
1637         .enable_shift = MXC_CCM_CCGRx_CG11_OFFSET,
1638         .secondary = &mmdc_ch1_axi_clk[1],
1639         .get_rate = _clk_mmdc_ch1_axi_get_rate,
1640         .set_rate = _clk_mmdc_ch1_axi_set_rate,
1641         .round_rate = _clk_mmdc_ch1_axi_round_rate,
1642         },
1643         {
1644         .id = 1,
1645         __INIT_CLK_DEBUG(mmdc_ch1_ipg_clk)
1646         .parent = &ipg_clk,
1647         .enable = _clk_enable,
1648         .disable = _clk_disable,
1649         .enable_reg = MXC_CCM_CCGR3,
1650         .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
1651         .secondary = &tzasc2_clk,
1652         },
1653 };
1654
1655 static struct clk ocram_clk = {
1656         __INIT_CLK_DEBUG(ocram_clk)
1657         .id = 0,
1658         .parent = &ahb_clk,
1659         .enable_reg = MXC_CCM_CCGR3,
1660         .enable_shift = MXC_CCM_CCGRx_CG14_OFFSET,
1661         .enable = _clk_enable,
1662         .disable = _clk_disable_inwait,
1663 };
1664
1665 static unsigned long _clk_ipg_perclk_get_rate(struct clk *clk)
1666 {
1667         u32 reg, div;
1668
1669         reg = __raw_readl(MXC_CCM_CSCMR1);
1670         div = ((reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK) >>
1671                         MXC_CCM_CSCMR1_PERCLK_PODF_OFFSET) + 1;
1672
1673         return clk_get_rate(clk->parent) / div;
1674 }
1675
1676 static int _clk_ipg_perclk_set_rate(struct clk *clk, unsigned long rate)
1677 {
1678         u32 reg, div;
1679         u32 parent_rate = clk_get_rate(clk->parent);
1680
1681         div = parent_rate / rate;
1682         if (div == 0)
1683                 div++;
1684         if (((parent_rate / div) != rate) || (div > 64))
1685                 return -EINVAL;
1686
1687         reg = __raw_readl(MXC_CCM_CSCMR1);
1688         reg &= ~MXC_CCM_CSCMR1_PERCLK_PODF_MASK;
1689         reg |= (div - 1) << MXC_CCM_CSCMR1_PERCLK_PODF_OFFSET;
1690         __raw_writel(reg, MXC_CCM_CSCMR1);
1691
1692         return 0;
1693 }
1694
1695
1696 static unsigned long _clk_ipg_perclk_round_rate(struct clk *clk,
1697                                                 unsigned long rate)
1698 {
1699         u32 div;
1700         u32 parent_rate = clk_get_rate(clk->parent);
1701
1702         div = parent_rate / rate;
1703
1704         /* Make sure rate is not greater than the maximum value for the clock.
1705          * Also prevent a div of 0.
1706          */
1707         if (div == 0)
1708                 div++;
1709
1710         if (div > 64)
1711                 div = 64;
1712
1713         return parent_rate / div;
1714 }
1715
1716 static struct clk ipg_perclk = {
1717         __INIT_CLK_DEBUG(ipg_perclk)
1718         .parent = &ipg_clk,
1719         .get_rate = _clk_ipg_perclk_get_rate,
1720         .set_rate = _clk_ipg_perclk_set_rate,
1721         .round_rate = _clk_ipg_perclk_round_rate,
1722 };
1723
1724 static struct clk spba_clk = {
1725         __INIT_CLK_DEBUG(spba_clk)
1726         .parent = &ipg_clk,
1727         .enable_reg = MXC_CCM_CCGR5,
1728         .enable_shift = MXC_CCM_CCGRx_CG6_OFFSET,
1729         .enable = _clk_enable,
1730         .disable = _clk_disable,
1731 };
1732
1733 static struct clk sdma_clk[] = {
1734         {
1735          __INIT_CLK_DEBUG(sdma_clk)
1736          .parent = &ahb_clk,
1737          .enable_reg = MXC_CCM_CCGR5,
1738          .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET,
1739          .enable = _clk_enable,
1740          .disable = _clk_disable,
1741          .secondary = &sdma_clk[1],
1742         },
1743         {
1744          .parent = &mx6per1_clk,
1745 #ifdef CONFIG_SDMA_IRAM
1746          .secondary = &ocram_clk,
1747 #else
1748         .secondary = &mmdc_ch0_axi_clk[0],
1749 #endif
1750         },
1751 };
1752
1753 static int _clk_gpu2d_axi_set_parent(struct clk *clk, struct clk *parent)
1754 {
1755         u32 reg = __raw_readl(MXC_CCM_CBCMR) & ~MXC_CCM_CBCMR_GPU2D_AXI_CLK_SEL;
1756
1757         if (parent == &ahb_clk)
1758                 reg |= MXC_CCM_CBCMR_GPU2D_AXI_CLK_SEL;
1759
1760         __raw_writel(reg, MXC_CCM_CBCMR);
1761
1762         return 0;
1763 }
1764
1765 static struct clk gpu2d_axi_clk = {
1766         __INIT_CLK_DEBUG(gpu2d_axi_clk)
1767         .parent = &axi_clk,
1768         .set_parent = _clk_gpu2d_axi_set_parent,
1769 };
1770
1771 static int _clk_gpu3d_axi_set_parent(struct clk *clk, struct clk *parent)
1772 {
1773         u32 reg = __raw_readl(MXC_CCM_CBCMR) & ~MXC_CCM_CBCMR_GPU3D_AXI_CLK_SEL;
1774
1775         if (parent == &ahb_clk)
1776                 reg |= MXC_CCM_CBCMR_GPU3D_AXI_CLK_SEL;
1777
1778         __raw_writel(reg, MXC_CCM_CBCMR);
1779
1780         return 0;
1781 }
1782
1783 static struct clk gpu3d_axi_clk = {
1784         __INIT_CLK_DEBUG(gpu3d_axi_clk)
1785         .parent = &axi_clk,
1786         .secondary = &mmdc_ch0_axi_clk[0],
1787         .set_parent = _clk_gpu3d_axi_set_parent,
1788 };
1789
1790 static int _clk_pcie_axi_set_parent(struct clk *clk, struct clk *parent)
1791 {
1792         u32 reg = __raw_readl(MXC_CCM_CBCMR) & ~MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL;
1793
1794         if (parent == &ahb_clk)
1795                 reg |= MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL;
1796
1797         __raw_writel(reg, MXC_CCM_CBCMR);
1798
1799         return 0;
1800 }
1801
1802 static struct clk pcie_axi_clk = {
1803         __INIT_CLK_DEBUG(pcie_axi_clk)
1804         .parent = &axi_clk,
1805         .set_parent = _clk_pcie_axi_set_parent,
1806 };
1807
1808 static int _clk_vdo_axi_set_parent(struct clk *clk, struct clk *parent)
1809 {
1810         u32 reg = __raw_readl(MXC_CCM_CBCMR) & ~MXC_CCM_CBCMR_VDOAXI_CLK_SEL;
1811
1812         if (parent == &ahb_clk)
1813                 reg |= MXC_CCM_CBCMR_VDOAXI_CLK_SEL;
1814
1815         __raw_writel(reg, MXC_CCM_CBCMR);
1816
1817         return 0;
1818 }
1819
1820 static struct clk vdo_axi_clk = {
1821         __INIT_CLK_DEBUG(vdo_axi_clk)
1822         .parent = &axi_clk,
1823         .enable_reg = MXC_CCM_CCGR6,
1824         .enable_shift = MXC_CCM_CCGRx_CG6_OFFSET,
1825         .enable = _clk_enable,
1826         .disable = _clk_disable,
1827         .set_parent = _clk_vdo_axi_set_parent,
1828 };
1829
1830 static struct clk vdoa_clk = {
1831         __INIT_CLK_DEBUG(vdoa_clk)
1832         .id = 0,
1833         .parent = &axi_clk,
1834         .secondary = &mx6fast1_clk,
1835         .enable_reg = MXC_CCM_CCGR2,
1836         .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
1837         .enable = _clk_enable,
1838         .disable = _clk_disable,
1839 };
1840
1841 static unsigned long _clk_gpt_get_rate(struct clk *clk)
1842 {
1843         unsigned long rate;
1844
1845         if (mx6q_revision() == IMX_CHIP_REVISION_1_0)
1846                 return clk_get_rate(clk->parent);
1847
1848         rate = mx6_timer_rate();
1849         if (!rate)
1850                 return clk_get_rate(clk->parent);
1851
1852         return rate;
1853 }
1854
1855 static struct clk gpt_clk[] = {
1856         {
1857         __INIT_CLK_DEBUG(gpt_clk)
1858          .parent = &osc_clk,
1859          .id = 0,
1860          .enable_reg = MXC_CCM_CCGR1,
1861          .enable_shift = MXC_CCM_CCGRx_CG10_OFFSET,
1862          .enable = _clk_enable,
1863          .disable = _clk_disable,
1864          .get_rate = _clk_gpt_get_rate,
1865          .secondary = &gpt_clk[1],
1866          },
1867         {
1868         __INIT_CLK_DEBUG(gpt_serial_clk)
1869          .id = 0,
1870          .enable_reg = MXC_CCM_CCGR1,
1871          .enable_shift = MXC_CCM_CCGRx_CG11_OFFSET,
1872          .enable = _clk_enable,
1873          .disable = _clk_disable,
1874          },
1875 };
1876
1877 static unsigned long _clk_iim_get_rate(struct clk *clk)
1878 {
1879         return clk_get_rate(clk->parent);
1880 }
1881
1882 static struct clk iim_clk = {
1883         __INIT_CLK_DEBUG(iim_clk)
1884         .parent = &ipg_clk,
1885         .enable = _clk_enable,
1886         .enable_reg = MXC_CCM_CCGR2,
1887         .enable_shift = MXC_CCM_CCGRx_CG6_OFFSET,
1888         .disable = _clk_disable,
1889         .get_rate = _clk_iim_get_rate,
1890 };
1891
1892 static struct clk i2c_clk[] = {
1893         {
1894         __INIT_CLK_DEBUG(i2c_clk_0)
1895          .id = 0,
1896          .parent = &ipg_perclk,
1897          .enable_reg = MXC_CCM_CCGR2,
1898          .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET,
1899          .enable = _clk_enable,
1900          .disable = _clk_disable,
1901          },
1902         {
1903         __INIT_CLK_DEBUG(i2c_clk_1)
1904          .id = 1,
1905          .parent = &ipg_perclk,
1906          .enable_reg = MXC_CCM_CCGR2,
1907          .enable_shift = MXC_CCM_CCGRx_CG4_OFFSET,
1908          .enable = _clk_enable,
1909          .disable = _clk_disable,
1910          },
1911         {
1912         __INIT_CLK_DEBUG(i2c_clk_2)
1913          .id = 2,
1914          .parent = &ipg_perclk,
1915          .enable_reg = MXC_CCM_CCGR2,
1916          .enable_shift = MXC_CCM_CCGRx_CG5_OFFSET,
1917          .enable = _clk_enable,
1918          .disable = _clk_disable,
1919          },
1920 };
1921
1922 static int _clk_vpu_axi_set_parent(struct clk *clk, struct clk *parent)
1923 {
1924         int mux;
1925         u32 reg = __raw_readl(MXC_CCM_CBCMR)
1926                 & ~MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK;
1927
1928         mux = _get_mux6(parent, &axi_clk, &pll2_pfd_400M,
1929                 &pll2_pfd_352M, NULL, NULL, NULL);
1930
1931         reg |= (mux << MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET);
1932
1933         __raw_writel(reg, MXC_CCM_CBCMR);
1934
1935         return 0;
1936 }
1937
1938 static unsigned long _clk_vpu_axi_get_rate(struct clk *clk)
1939 {
1940         u32 reg, div;
1941
1942         reg = __raw_readl(MXC_CCM_CSCDR1);
1943         div = ((reg & MXC_CCM_CSCDR1_VPU_AXI_PODF_MASK) >>
1944                         MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET) + 1;
1945
1946         return clk_get_rate(clk->parent) / div;
1947 }
1948
1949 static int _clk_vpu_axi_set_rate(struct clk *clk, unsigned long rate)
1950 {
1951         u32 reg, div;
1952         u32 parent_rate = clk_get_rate(clk->parent);
1953
1954         div = parent_rate / rate;
1955         if (div == 0)
1956                 div++;
1957         if (((parent_rate / div) != rate) || (div > 8))
1958                 return -EINVAL;
1959
1960         reg = __raw_readl(MXC_CCM_CSCDR1);
1961         reg &= ~MXC_CCM_CSCDR1_VPU_AXI_PODF_MASK;
1962         reg |= (div - 1) << MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET;
1963         __raw_writel(reg, MXC_CCM_CSCDR1);
1964
1965         return 0;
1966 }
1967
1968 static unsigned long _clk_vpu_axi_round_rate(struct clk *clk,
1969                                                 unsigned long rate)
1970 {
1971         u32 div;
1972         u32 parent_rate = clk_get_rate(clk->parent);
1973
1974         div = parent_rate / rate;
1975
1976         /* Make sure rate is not greater than the maximum value for the clock.
1977          * Also prevent a div of 0.
1978          */
1979         if (div == 0)
1980                 div++;
1981
1982         if (div > 8)
1983                 div = 8;
1984
1985         return parent_rate / div;
1986 }
1987
1988 static struct clk vpu_clk[] = {
1989         {
1990         __INIT_CLK_DEBUG(vpu_clk)
1991         .parent = &axi_clk,
1992         .enable_reg = MXC_CCM_CCGR6,
1993         .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
1994         .enable = _clk_enable,
1995         .disable = _clk_disable,
1996         .set_parent = _clk_vpu_axi_set_parent,
1997         .round_rate = _clk_vpu_axi_round_rate,
1998         .set_rate = _clk_vpu_axi_set_rate,
1999         .get_rate = _clk_vpu_axi_get_rate,
2000         .secondary = &vpu_clk[1],
2001         },
2002         {
2003         .parent =  &mmdc_ch0_axi_clk[0],
2004         .secondary = &vpu_clk[2],
2005         },
2006         {
2007         .parent =  &mx6fast1_clk,
2008         .secondary = &ocram_clk,
2009         },
2010
2011 };
2012
2013 static int _clk_ipu1_set_parent(struct clk *clk, struct clk *parent)
2014 {
2015         int mux;
2016         u32 reg = __raw_readl(MXC_CCM_CSCDR3)
2017                 & ~MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_MASK;
2018
2019         mux = _get_mux6(parent, &mmdc_ch0_axi_clk[0],
2020                 &pll2_pfd_400M, &pll3_120M, &pll3_pfd_540M, NULL, NULL);
2021
2022         reg |= (mux << MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_OFFSET);
2023
2024         __raw_writel(reg, MXC_CCM_CSCDR3);
2025
2026         return 0;
2027 }
2028
2029 static unsigned long _clk_ipu1_get_rate(struct clk *clk)
2030 {
2031         u32 reg, div;
2032
2033         reg = __raw_readl(MXC_CCM_CSCDR3);
2034         div = ((reg & MXC_CCM_CSCDR3_IPU1_HSP_PODF_MASK) >>
2035                         MXC_CCM_CSCDR3_IPU1_HSP_PODF_OFFSET) + 1;
2036
2037         return clk_get_rate(clk->parent) / div;
2038 }
2039
2040 static int _clk_ipu1_set_rate(struct clk *clk, unsigned long rate)
2041 {
2042         u32 reg, div;
2043         u32 parent_rate = clk_get_rate(clk->parent);
2044
2045         div = parent_rate / rate;
2046         if (div == 0)
2047                 div++;
2048         if (((parent_rate / div) != rate) || (div > 8))
2049                 return -EINVAL;
2050
2051         reg = __raw_readl(MXC_CCM_CSCDR3);
2052         reg &= ~MXC_CCM_CSCDR3_IPU1_HSP_PODF_MASK;
2053         reg |= (div - 1) << MXC_CCM_CSCDR3_IPU1_HSP_PODF_OFFSET;
2054         __raw_writel(reg, MXC_CCM_CSCDR3);
2055
2056         return 0;
2057 }
2058
2059 static unsigned long _clk_ipu_round_rate(struct clk *clk,
2060                                                 unsigned long rate)
2061 {
2062         u32 div;
2063         u32 parent_rate = clk_get_rate(clk->parent);
2064
2065         div = parent_rate / rate;
2066
2067         /* Make sure rate is not greater than the maximum value for the clock.
2068          * Also prevent a div of 0.
2069          */
2070         if (div == 0)
2071                 div++;
2072
2073         if (div > 8)
2074                 div = 8;
2075
2076         return parent_rate / div;
2077 }
2078
2079 static struct clk ipu1_clk = {
2080         __INIT_CLK_DEBUG(ipu1_clk)
2081         .parent = &mmdc_ch0_axi_clk[0],
2082         .secondary = &mmdc_ch0_axi_clk[0],
2083         .enable_reg = MXC_CCM_CCGR3,
2084         .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET,
2085         .enable = _clk_enable,
2086         .disable = _clk_disable,
2087         .set_parent = _clk_ipu1_set_parent,
2088         .round_rate = _clk_ipu_round_rate,
2089         .set_rate = _clk_ipu1_set_rate,
2090         .get_rate = _clk_ipu1_get_rate,
2091         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
2092 };
2093
2094 static int _clk_ipu2_set_parent(struct clk *clk, struct clk *parent)
2095 {
2096         int mux;
2097         u32 reg = __raw_readl(MXC_CCM_CSCDR3)
2098                 & ~MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_MASK;
2099
2100         mux = _get_mux6(parent, &mmdc_ch0_axi_clk[0],
2101                 &pll2_pfd_400M, &pll3_120M, &pll3_pfd_540M, NULL, NULL);
2102
2103         reg |= (mux << MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_OFFSET);
2104
2105         __raw_writel(reg, MXC_CCM_CSCDR3);
2106
2107         return 0;
2108 }
2109
2110 static unsigned long _clk_ipu2_get_rate(struct clk *clk)
2111 {
2112         u32 reg, div;
2113
2114         reg = __raw_readl(MXC_CCM_CSCDR3);
2115         div = ((reg & MXC_CCM_CSCDR3_IPU2_HSP_PODF_MASK) >>
2116                         MXC_CCM_CSCDR3_IPU2_HSP_PODF_OFFSET) + 1;
2117
2118         return clk_get_rate(clk->parent) / div;
2119 }
2120
2121 static int _clk_ipu2_set_rate(struct clk *clk, unsigned long rate)
2122 {
2123         u32 reg, div;
2124         u32 parent_rate = clk_get_rate(clk->parent);
2125
2126         div = parent_rate / rate;
2127         if (div == 0)
2128                 div++;
2129         if (((parent_rate / div) != rate) || (div > 8))
2130                 return -EINVAL;
2131
2132         reg = __raw_readl(MXC_CCM_CSCDR3);
2133         reg &= ~MXC_CCM_CSCDR3_IPU2_HSP_PODF_MASK;
2134         reg |= (div - 1) << MXC_CCM_CSCDR3_IPU2_HSP_PODF_OFFSET;
2135         __raw_writel(reg, MXC_CCM_CSCDR3);
2136
2137         return 0;
2138 }
2139
2140 static struct clk ipu2_clk = {
2141         __INIT_CLK_DEBUG(ipu2_clk)
2142         .parent = &mmdc_ch0_axi_clk[0],
2143         .secondary = &mmdc_ch0_axi_clk[0],
2144         .enable_reg = MXC_CCM_CCGR3,
2145         .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET,
2146         .enable = _clk_enable,
2147         .disable = _clk_disable,
2148         .set_parent = _clk_ipu2_set_parent,
2149         .round_rate = _clk_ipu_round_rate,
2150         .set_rate = _clk_ipu2_set_rate,
2151         .get_rate = _clk_ipu2_get_rate,
2152         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
2153 };
2154
2155 static struct clk usdhc_dep_clk = {
2156         .parent = &mmdc_ch0_axi_clk[0],
2157         .secondary = &mx6per1_clk,
2158         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
2159         };
2160
2161 static unsigned long _clk_usdhc_round_rate(struct clk *clk,
2162                                                 unsigned long rate)
2163 {
2164         u32 div;
2165         u32 parent_rate = clk_get_rate(clk->parent);
2166
2167         div = parent_rate / rate;
2168
2169         /* Make sure rate is not greater than the maximum value for the clock.
2170          * Also prevent a div of 0.
2171          */
2172         if (div == 0)
2173                 div++;
2174
2175         if (div > 8)
2176                 div = 8;
2177
2178         return parent_rate / div;
2179 }
2180
2181 static int _clk_usdhc1_set_parent(struct clk *clk, struct clk *parent)
2182 {
2183         u32 reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_USDHC1_CLK_SEL;
2184
2185         if (parent == &pll2_pfd_352M)
2186                 reg |= (MXC_CCM_CSCMR1_USDHC1_CLK_SEL);
2187
2188         __raw_writel(reg, MXC_CCM_CSCMR1);
2189
2190         return 0;
2191 }
2192
2193 static unsigned long _clk_usdhc1_get_rate(struct clk *clk)
2194 {
2195         u32 reg, div;
2196
2197         reg = __raw_readl(MXC_CCM_CSCDR1);
2198         div = ((reg & MXC_CCM_CSCDR1_USDHC1_PODF_MASK) >>
2199                         MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET) + 1;
2200
2201         return clk_get_rate(clk->parent) / div;
2202 }
2203
2204 static int _clk_usdhc1_set_rate(struct clk *clk, unsigned long rate)
2205 {
2206         u32 reg, div;
2207         u32 parent_rate = clk_get_rate(clk->parent);
2208
2209         div = parent_rate / rate;
2210         if (div == 0)
2211                 div++;
2212         if (((parent_rate / div) != rate) || (div > 8))
2213                 return -EINVAL;
2214
2215         reg = __raw_readl(MXC_CCM_CSCDR1);
2216         reg &= ~MXC_CCM_CSCDR1_USDHC1_PODF_MASK;
2217         reg |= (div - 1) << MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET;
2218         __raw_writel(reg, MXC_CCM_CSCDR1);
2219
2220         return 0;
2221 }
2222
2223 static struct clk usdhc1_clk = {
2224         __INIT_CLK_DEBUG(usdhc1_clk)
2225         .id = 0,
2226         .parent = &pll2_pfd_400M,
2227         .secondary = &usdhc_dep_clk,
2228         .enable_reg = MXC_CCM_CCGR6,
2229         .enable_shift = MXC_CCM_CCGRx_CG1_OFFSET,
2230         .enable = _clk_enable,
2231         .disable = _clk_disable,
2232         .set_parent = _clk_usdhc1_set_parent,
2233         .round_rate = _clk_usdhc_round_rate,
2234         .set_rate = _clk_usdhc1_set_rate,
2235         .get_rate = _clk_usdhc1_get_rate,
2236         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
2237 };
2238
2239 static int _clk_usdhc2_set_parent(struct clk *clk, struct clk *parent)
2240 {
2241         u32 reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_USDHC2_CLK_SEL;
2242
2243         if (parent == &pll2_pfd_352M)
2244                 reg |= (MXC_CCM_CSCMR1_USDHC2_CLK_SEL);
2245
2246         __raw_writel(reg, MXC_CCM_CSCMR1);
2247
2248         return 0;
2249 }
2250
2251 static unsigned long _clk_usdhc2_get_rate(struct clk *clk)
2252 {
2253         u32 reg, div;
2254
2255         reg = __raw_readl(MXC_CCM_CSCDR1);
2256         div = ((reg & MXC_CCM_CSCDR1_USDHC2_PODF_MASK) >>
2257                         MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET) + 1;
2258
2259         return clk_get_rate(clk->parent) / div;
2260 }
2261
2262 static int _clk_usdhc2_set_rate(struct clk *clk, unsigned long rate)
2263 {
2264         u32 reg, div;
2265         u32 parent_rate = clk_get_rate(clk->parent);
2266
2267         div = parent_rate / rate;
2268         if (div == 0)
2269                 div++;
2270         if (((parent_rate / div) != rate) || (div > 8))
2271                 return -EINVAL;
2272
2273         reg = __raw_readl(MXC_CCM_CSCDR1);
2274         reg &= ~MXC_CCM_CSCDR1_USDHC2_PODF_MASK;
2275         reg |= (div - 1) << MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET;
2276         __raw_writel(reg, MXC_CCM_CSCDR1);
2277
2278         return 0;
2279 }
2280
2281 static struct clk usdhc2_clk = {
2282         __INIT_CLK_DEBUG(usdhc2_clk)
2283         .id = 1,
2284         .parent = &pll2_pfd_400M,
2285         .secondary = &usdhc_dep_clk,
2286         .enable_reg = MXC_CCM_CCGR6,
2287         .enable_shift = MXC_CCM_CCGRx_CG2_OFFSET,
2288         .enable = _clk_enable,
2289         .disable = _clk_disable,
2290         .set_parent = _clk_usdhc2_set_parent,
2291         .round_rate = _clk_usdhc_round_rate,
2292         .set_rate = _clk_usdhc2_set_rate,
2293         .get_rate = _clk_usdhc2_get_rate,
2294         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
2295 };
2296
2297 static int _clk_usdhc3_set_parent(struct clk *clk, struct clk *parent)
2298 {
2299         u32 reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_USDHC3_CLK_SEL;
2300
2301         if (parent == &pll2_pfd_352M)
2302                 reg |= (MXC_CCM_CSCMR1_USDHC3_CLK_SEL);
2303
2304         __raw_writel(reg, MXC_CCM_CSCMR1);
2305
2306         return 0;
2307 }
2308
2309 static unsigned long _clk_usdhc3_get_rate(struct clk *clk)
2310 {
2311         u32 reg, div;
2312
2313         reg = __raw_readl(MXC_CCM_CSCDR1);
2314         div = ((reg & MXC_CCM_CSCDR1_USDHC3_PODF_MASK) >>
2315                         MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET) + 1;
2316
2317         return clk_get_rate(clk->parent) / div;
2318 }
2319
2320 static int _clk_usdhc3_set_rate(struct clk *clk, unsigned long rate)
2321 {
2322         u32 reg, div;
2323         u32 parent_rate = clk_get_rate(clk->parent);
2324
2325         div = parent_rate / rate;
2326         if (div == 0)
2327                 div++;
2328         if (((parent_rate / div) != rate) || (div > 8))
2329                 return -EINVAL;
2330
2331         reg = __raw_readl(MXC_CCM_CSCDR1);
2332         reg &= ~MXC_CCM_CSCDR1_USDHC3_PODF_MASK;
2333         reg |= (div - 1) << MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET;
2334         __raw_writel(reg, MXC_CCM_CSCDR1);
2335
2336         return 0;
2337 }
2338
2339
2340 static struct clk usdhc3_clk = {
2341         __INIT_CLK_DEBUG(usdhc3_clk)
2342         .id = 2,
2343         .parent = &pll2_pfd_400M,
2344         .secondary = &usdhc_dep_clk,
2345         .enable_reg = MXC_CCM_CCGR6,
2346         .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET,
2347         .enable = _clk_enable,
2348         .disable = _clk_disable,
2349         .set_parent = _clk_usdhc3_set_parent,
2350         .round_rate = _clk_usdhc_round_rate,
2351         .set_rate = _clk_usdhc3_set_rate,
2352         .get_rate = _clk_usdhc3_get_rate,
2353         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
2354 };
2355
2356 static int _clk_usdhc4_set_parent(struct clk *clk, struct clk *parent)
2357 {
2358         u32 reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_USDHC4_CLK_SEL;
2359
2360         if (parent == &pll2_pfd_352M)
2361                 reg |= (MXC_CCM_CSCMR1_USDHC4_CLK_SEL);
2362
2363         __raw_writel(reg, MXC_CCM_CSCMR1);
2364
2365         return 0;
2366 }
2367
2368 static unsigned long _clk_usdhc4_get_rate(struct clk *clk)
2369 {
2370         u32 reg, div;
2371
2372         reg = __raw_readl(MXC_CCM_CSCDR1);
2373         div = ((reg & MXC_CCM_CSCDR1_USDHC4_PODF_MASK) >>
2374                         MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET) + 1;
2375
2376         return clk_get_rate(clk->parent) / div;
2377 }
2378
2379 static int _clk_usdhc4_set_rate(struct clk *clk, unsigned long rate)
2380 {
2381         u32 reg, div;
2382         u32 parent_rate = clk_get_rate(clk->parent);
2383
2384         div = parent_rate / rate;
2385         if (div == 0)
2386                 div++;
2387         if (((parent_rate / div) != rate) || (div > 8))
2388                 return -EINVAL;
2389
2390         reg = __raw_readl(MXC_CCM_CSCDR1);
2391         reg &= ~MXC_CCM_CSCDR1_USDHC4_PODF_MASK;
2392         reg |= (div - 1) << MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET;
2393         __raw_writel(reg, MXC_CCM_CSCDR1);
2394
2395         return 0;
2396 }
2397
2398
2399 static struct clk usdhc4_clk = {
2400         __INIT_CLK_DEBUG(usdhc4_clk)
2401         .id = 3,
2402         .parent = &pll2_pfd_400M,
2403         .secondary = &usdhc_dep_clk,
2404         .enable_reg = MXC_CCM_CCGR6,
2405         .enable_shift = MXC_CCM_CCGRx_CG4_OFFSET,
2406         .enable = _clk_enable,
2407         .disable = _clk_disable,
2408         .set_parent = _clk_usdhc4_set_parent,
2409         .round_rate = _clk_usdhc_round_rate,
2410         .set_rate = _clk_usdhc4_set_rate,
2411         .get_rate = _clk_usdhc4_get_rate,
2412         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
2413 };
2414
2415 static unsigned long _clk_ssi_round_rate(struct clk *clk,
2416                                                 unsigned long rate)
2417 {
2418         u32 pre, post;
2419         u32 parent_rate = clk_get_rate(clk->parent);
2420         u32 div = parent_rate / rate;
2421
2422         if (parent_rate % rate)
2423                 div++;
2424
2425         __calc_pre_post_dividers(1 << 6, div, &pre, &post);
2426
2427         return parent_rate / (pre * post);
2428 }
2429
2430 static unsigned long _clk_ssi1_get_rate(struct clk *clk)
2431 {
2432         u32 reg, prediv, podf;
2433
2434         reg = __raw_readl(MXC_CCM_CS1CDR);
2435
2436         prediv = ((reg & MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK)
2437                 >> MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET) + 1;
2438         podf = ((reg & MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK)
2439                 >> MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET) + 1;
2440
2441         return clk_get_rate(clk->parent) / (prediv * podf);
2442 }
2443
2444 static int _clk_ssi1_set_rate(struct clk *clk, unsigned long rate)
2445 {
2446         u32 reg, div, pre, post;
2447         u32 parent_rate = clk_get_rate(clk->parent);
2448
2449         div = parent_rate / rate;
2450         if (div == 0)
2451                 div++;
2452         if (((parent_rate / div) != rate) || div > 512)
2453                 return -EINVAL;
2454
2455         __calc_pre_post_dividers(1 << 6, div, &pre, &post);
2456
2457         reg = __raw_readl(MXC_CCM_CS1CDR);
2458         reg &= ~(MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK |
2459                  MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK);
2460         reg |= (post - 1) << MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET;
2461         reg |= (pre - 1) << MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET;
2462
2463         __raw_writel(reg, MXC_CCM_CS1CDR);
2464
2465         return 0;
2466 }
2467
2468
2469 static int _clk_ssi1_set_parent(struct clk *clk, struct clk *parent)
2470 {
2471         u32 reg, mux;
2472
2473         reg = __raw_readl(MXC_CCM_CSCMR1)
2474                 & ~MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK;
2475
2476         mux = _get_mux6(parent, &pll3_pfd_508M, &pll3_pfd_454M,
2477                         &pll4_audio_main_clk, NULL, NULL, NULL);
2478         reg |= (mux << MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET);
2479
2480         __raw_writel(reg, MXC_CCM_CSCMR1);
2481
2482         return 0;
2483 }
2484
2485 static struct clk ssi1_clk = {
2486         __INIT_CLK_DEBUG(ssi1_clk)
2487         .parent = &pll3_pfd_508M,
2488         .enable_reg = MXC_CCM_CCGR5,
2489         .enable_shift = MXC_CCM_CCGRx_CG9_OFFSET,
2490         .enable = _clk_enable,
2491         .disable = _clk_disable,
2492         .set_parent = _clk_ssi1_set_parent,
2493         .set_rate = _clk_ssi1_set_rate,
2494         .round_rate = _clk_ssi_round_rate,
2495         .get_rate = _clk_ssi1_get_rate,
2496 #ifdef CONFIG_SND_MXC_SOC_IRAM
2497          .secondary = &ocram_clk,
2498 #else
2499          .secondary = &mmdc_ch0_axi_clk[0],
2500 #endif
2501 };
2502
2503 static unsigned long _clk_ssi2_get_rate(struct clk *clk)
2504 {
2505         u32 reg, prediv, podf;
2506
2507         reg = __raw_readl(MXC_CCM_CS2CDR);
2508
2509         prediv = ((reg & MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK)
2510                 >> MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET) + 1;
2511         podf = ((reg & MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK)
2512                 >> MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET) + 1;
2513
2514         return clk_get_rate(clk->parent) / (prediv * podf);
2515 }
2516
2517 static int _clk_ssi2_set_rate(struct clk *clk, unsigned long rate)
2518 {
2519         u32 reg, div, pre, post;
2520         u32 parent_rate = clk_get_rate(clk->parent);
2521
2522         div = parent_rate / rate;
2523         if (div == 0)
2524                 div++;
2525         if (((parent_rate / div) != rate) || div > 512)
2526                 return -EINVAL;
2527
2528         __calc_pre_post_dividers(1 << 6, div, &pre, &post);
2529
2530         reg = __raw_readl(MXC_CCM_CS2CDR);
2531         reg &= ~(MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK |
2532                  MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK);
2533         reg |= (post - 1) << MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET;
2534         reg |= (pre - 1) << MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET;
2535
2536         __raw_writel(reg, MXC_CCM_CS2CDR);
2537
2538         return 0;
2539 }
2540
2541
2542 static int _clk_ssi2_set_parent(struct clk *clk, struct clk *parent)
2543 {
2544         u32 reg, mux;
2545
2546         reg = __raw_readl(MXC_CCM_CSCMR1)
2547                 & ~MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK;
2548
2549         mux = _get_mux6(parent, &pll3_pfd_508M, &pll3_pfd_454M,
2550                         &pll4_audio_main_clk, NULL, NULL, NULL);
2551         reg |= (mux << MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET);
2552
2553         __raw_writel(reg, MXC_CCM_CSCMR1);
2554
2555         return 0;
2556 }
2557
2558 static struct clk ssi2_clk = {
2559         __INIT_CLK_DEBUG(ssi2_clk)
2560         .parent = &pll3_pfd_508M,
2561         .enable_reg = MXC_CCM_CCGR5,
2562         .enable_shift = MXC_CCM_CCGRx_CG10_OFFSET,
2563         .enable = _clk_enable,
2564         .disable = _clk_disable,
2565         .set_parent = _clk_ssi2_set_parent,
2566         .set_rate = _clk_ssi2_set_rate,
2567         .round_rate = _clk_ssi_round_rate,
2568         .get_rate = _clk_ssi2_get_rate,
2569 #ifdef CONFIG_SND_MXC_SOC_IRAM
2570          .secondary = &ocram_clk,
2571 #else
2572          .secondary = &mmdc_ch0_axi_clk[0],
2573 #endif
2574 };
2575
2576 static unsigned long _clk_ssi3_get_rate(struct clk *clk)
2577 {
2578         u32 reg, prediv, podf;
2579
2580         reg = __raw_readl(MXC_CCM_CS1CDR);
2581
2582         prediv = ((reg & MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK)
2583                 >> MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET) + 1;
2584         podf = ((reg & MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK)
2585                 >> MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET) + 1;
2586
2587         return clk_get_rate(clk->parent) / (prediv * podf);
2588 }
2589
2590 static int _clk_ssi3_set_rate(struct clk *clk, unsigned long rate)
2591 {
2592         u32 reg, div, pre, post;
2593         u32 parent_rate = clk_get_rate(clk->parent);
2594
2595         div = parent_rate / rate;
2596         if (div == 0)
2597                 div++;
2598         if (((parent_rate / div) != rate) || div > 512)
2599                 return -EINVAL;
2600
2601         __calc_pre_post_dividers(1 << 6, div, &pre, &post);
2602
2603         reg = __raw_readl(MXC_CCM_CS1CDR);
2604         reg &= ~(MXC_CCM_CS1CDR_SSI3_CLK_PODF_MASK|
2605                  MXC_CCM_CS1CDR_SSI3_CLK_PRED_MASK);
2606         reg |= (post - 1) << MXC_CCM_CS1CDR_SSI3_CLK_PODF_OFFSET;
2607         reg |= (pre - 1) << MXC_CCM_CS1CDR_SSI3_CLK_PRED_OFFSET;
2608
2609         __raw_writel(reg, MXC_CCM_CS1CDR);
2610
2611         return 0;
2612 }
2613
2614
2615 static int _clk_ssi3_set_parent(struct clk *clk, struct clk *parent)
2616 {
2617         u32 reg, mux;
2618
2619         reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_SSI3_CLK_SEL_MASK;
2620
2621         mux = _get_mux6(parent, &pll3_pfd_508M, &pll3_pfd_454M,
2622                                 &pll4_audio_main_clk, NULL, NULL, NULL);
2623         reg |= (mux << MXC_CCM_CSCMR1_SSI3_CLK_SEL_OFFSET);
2624
2625         __raw_writel(reg, MXC_CCM_CSCMR1);
2626
2627         return 0;
2628 }
2629
2630 static struct clk ssi3_clk = {
2631         __INIT_CLK_DEBUG(ssi3_clk)
2632         .parent = &pll3_pfd_508M,
2633         .enable_reg = MXC_CCM_CCGR5,
2634         .enable_shift = MXC_CCM_CCGRx_CG11_OFFSET,
2635         .enable = _clk_enable,
2636         .disable = _clk_disable,
2637         .set_parent = _clk_ssi3_set_parent,
2638         .set_rate = _clk_ssi3_set_rate,
2639         .round_rate = _clk_ssi_round_rate,
2640         .get_rate = _clk_ssi3_get_rate,
2641 #ifdef CONFIG_SND_MXC_SOC_IRAM
2642          .secondary = &ocram_clk,
2643 #else
2644          .secondary = &mmdc_ch0_axi_clk[0],
2645 #endif
2646 };
2647
2648 static unsigned long _clk_ldb_di_round_rate(struct clk *clk,
2649                                                 unsigned long rate)
2650 {
2651         u32 parent_rate = clk_get_rate(clk->parent);
2652
2653         if (rate * 7 <= parent_rate + parent_rate/20)
2654                 return parent_rate / 7;
2655         else
2656                 return 2 * parent_rate / 7;
2657 }
2658
2659 static unsigned long _clk_ldb_di0_get_rate(struct clk *clk)
2660 {
2661         u32 div;
2662
2663         div = __raw_readl(MXC_CCM_CSCMR2) &
2664                 MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
2665
2666         if (div)
2667                 return clk_get_rate(clk->parent) / 7;
2668
2669         return (2 * clk_get_rate(clk->parent)) / 7;
2670 }
2671
2672 static int _clk_ldb_di0_set_rate(struct clk *clk, unsigned long rate)
2673 {
2674         u32 reg, div = 0;
2675         u32 parent_rate = clk_get_rate(clk->parent);
2676
2677         if (rate * 7 <= parent_rate + parent_rate/20) {
2678                 div = 7;
2679                 rate = parent_rate / 7;
2680         } else
2681                 rate = 2 * parent_rate / 7;
2682
2683         reg = __raw_readl(MXC_CCM_CSCMR2);
2684         if (div == 7)
2685                 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
2686         else
2687                 reg &= ~MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
2688
2689         __raw_writel(reg, MXC_CCM_CSCMR2);
2690
2691         return 0;
2692 }
2693
2694 static int _clk_ldb_di0_set_parent(struct clk *clk, struct clk *parent)
2695 {
2696         u32 reg, mux;
2697
2698         reg = __raw_readl(MXC_CCM_CS2CDR)
2699                 & ~MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK;
2700
2701         mux = _get_mux6(parent, &pll5_video_main_clk,
2702                 &pll2_pfd_352M, &pll2_pfd_400M, &pll3_pfd_540M,
2703                 &pll3_usb_otg_main_clk, NULL);
2704         reg |= (mux << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET);
2705
2706         __raw_writel(reg, MXC_CCM_CS2CDR);
2707
2708         return 0;
2709 }
2710
2711 static struct clk ldb_di0_clk = {
2712          __INIT_CLK_DEBUG(ldb_di0_clk)
2713         .id = 0,
2714         .parent = &pll3_pfd_540M,
2715         .enable_reg = MXC_CCM_CCGR3,
2716         .enable_shift = MXC_CCM_CCGRx_CG6_OFFSET,
2717         .enable = _clk_enable,
2718         .disable = _clk_disable,
2719         .set_parent = _clk_ldb_di0_set_parent,
2720         .set_rate = _clk_ldb_di0_set_rate,
2721         .round_rate = _clk_ldb_di_round_rate,
2722         .get_rate = _clk_ldb_di0_get_rate,
2723         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
2724 };
2725
2726 static unsigned long _clk_ldb_di1_get_rate(struct clk *clk)
2727 {
2728         u32 div;
2729
2730         div = __raw_readl(MXC_CCM_CSCMR2) &
2731                 MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
2732
2733         if (div)
2734                 return clk_get_rate(clk->parent) / 7;
2735
2736         return (2 * clk_get_rate(clk->parent)) / 7;
2737 }
2738
2739 static int _clk_ldb_di1_set_rate(struct clk *clk, unsigned long rate)
2740 {
2741         u32 reg, div = 0;
2742         u32 parent_rate = clk_get_rate(clk->parent);
2743
2744         if (rate * 7 <= parent_rate + parent_rate/20) {
2745                 div = 7;
2746                 rate = parent_rate / 7;
2747         } else
2748                 rate = 2 * parent_rate / 7;
2749
2750         reg = __raw_readl(MXC_CCM_CSCMR2);
2751         if (div == 7)
2752                 reg |= MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
2753         else
2754                 reg &= ~MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
2755
2756         __raw_writel(reg, MXC_CCM_CSCMR2);
2757
2758         return 0;
2759 }
2760
2761 static int _clk_ldb_di1_set_parent(struct clk *clk, struct clk *parent)
2762 {
2763         u32 reg, mux;
2764
2765         reg = __raw_readl(MXC_CCM_CS2CDR)
2766                 & ~MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK;
2767
2768         mux = _get_mux6(parent, &pll5_video_main_clk,
2769                 &pll2_pfd_352M, &pll2_pfd_400M, &pll3_pfd_540M,
2770                 &pll3_usb_otg_main_clk, NULL);
2771         reg |= (mux << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
2772
2773         __raw_writel(reg, MXC_CCM_CS2CDR);
2774
2775         return 0;
2776 }
2777
2778 static struct clk ldb_di1_clk = {
2779          __INIT_CLK_DEBUG(ldb_di1_clk)
2780         .id = 0,
2781         .parent = &pll3_pfd_540M,
2782         .enable_reg = MXC_CCM_CCGR3,
2783         .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
2784         .enable = _clk_enable,
2785         .disable = _clk_disable,
2786         .set_parent = _clk_ldb_di1_set_parent,
2787         .set_rate = _clk_ldb_di1_set_rate,
2788         .round_rate = _clk_ldb_di_round_rate,
2789         .get_rate = _clk_ldb_di1_get_rate,
2790         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
2791 };
2792
2793
2794 static unsigned long _clk_ipu_di_round_rate(struct clk *clk,
2795                                                 unsigned long rate)
2796 {
2797         u32 div;
2798         u32 parent_rate = clk_get_rate(clk->parent);
2799
2800         if ((clk->parent == &ldb_di0_clk) ||
2801                 (clk->parent == &ldb_di1_clk))
2802                 return parent_rate;
2803
2804         div = parent_rate / rate;
2805         /* Round to closest divisor */
2806         if ((parent_rate % rate) > (rate / 2))
2807                 div++;
2808
2809         /* Make sure rate is not greater than the maximum value for the clock.
2810          * Also prevent a div of 0.
2811          */
2812         if (div == 0)
2813                 div++;
2814
2815         if (div > 8)
2816                 div = 8;
2817
2818         return parent_rate / div;
2819 }
2820
2821 static unsigned long _clk_ipu1_di0_get_rate(struct clk *clk)
2822 {
2823         u32 reg, div;
2824
2825         if ((clk->parent == &ldb_di0_clk) ||
2826                 (clk->parent == &ldb_di1_clk))
2827                 return clk_get_rate(clk->parent);
2828
2829         reg = __raw_readl(MXC_CCM_CHSCCDR);
2830
2831         div = ((reg & MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK) >>
2832                          MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET) + 1;
2833
2834         return clk_get_rate(clk->parent) / div;
2835 }
2836
2837 static int _clk_ipu1_di0_set_rate(struct clk *clk, unsigned long rate)
2838 {
2839         u32 reg, div;
2840         u32 parent_rate = clk_get_rate(clk->parent);
2841
2842         if ((clk->parent == &ldb_di0_clk) ||
2843                 (clk->parent == &ldb_di1_clk)) {
2844                 if (parent_rate == rate)
2845                         return 0;
2846                 else
2847                         return -EINVAL;
2848         }
2849
2850         div = parent_rate / rate;
2851         if (div == 0)
2852                 div++;
2853         if (((parent_rate / div) != rate) || (div > 8))
2854                 return -EINVAL;
2855
2856         reg = __raw_readl(MXC_CCM_CHSCCDR);
2857         reg &= ~MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK;
2858         reg |= (div - 1) << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET;
2859         __raw_writel(reg, MXC_CCM_CHSCCDR);
2860
2861         return 0;
2862 }
2863
2864
2865 static int _clk_ipu1_di0_set_parent(struct clk *clk, struct clk *parent)
2866 {
2867         u32 reg, mux;
2868
2869         if (parent == &ldb_di0_clk)
2870                 mux = 0x3;
2871         else if (parent == &ldb_di1_clk)
2872                 mux = 0x4;
2873         else {
2874                 reg = __raw_readl(MXC_CCM_CHSCCDR)
2875                         & ~MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK;
2876
2877                 mux = _get_mux6(parent, &mmdc_ch0_axi_clk[0],
2878                                 &pll3_usb_otg_main_clk, &pll5_video_main_clk,
2879                                 &pll2_pfd_352M, &pll2_pfd_400M, &pll3_pfd_540M);
2880                 reg |= (mux << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
2881
2882                 __raw_writel(reg, MXC_CCM_CHSCCDR);
2883
2884                 /* Derive clock from divided pre-muxed ipu1_di0 clock.*/
2885                 mux = 0;
2886         }
2887
2888         reg = __raw_readl(MXC_CCM_CHSCCDR)
2889                 & ~MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK;
2890         __raw_writel(reg | (mux << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET),
2891                 MXC_CCM_CHSCCDR);
2892
2893         return 0;
2894 }
2895
2896 static unsigned long _clk_ipu1_di1_get_rate(struct clk *clk)
2897 {
2898         u32 reg, div;
2899
2900         if ((clk->parent == &ldb_di0_clk) ||
2901                 (clk->parent == &ldb_di1_clk))
2902                 return clk_get_rate(clk->parent);
2903
2904         reg = __raw_readl(MXC_CCM_CHSCCDR);
2905
2906         div = ((reg & MXC_CCM_CHSCCDR_IPU1_DI1_PODF_MASK)
2907                         >> MXC_CCM_CHSCCDR_IPU1_DI1_PODF_OFFSET) + 1;
2908
2909         return clk_get_rate(clk->parent) / div;
2910 }
2911
2912 static int _clk_ipu1_di1_set_rate(struct clk *clk, unsigned long rate)
2913 {
2914         u32 reg, div;
2915         u32 parent_rate = clk_get_rate(clk->parent);
2916
2917         if ((clk->parent == &ldb_di0_clk) ||
2918                 (clk->parent == &ldb_di1_clk)) {
2919                 if (parent_rate == rate)
2920                         return 0;
2921                 else
2922                         return -EINVAL;
2923         }
2924
2925         div = parent_rate / rate;
2926         if (div == 0)
2927                 div++;
2928         if (((parent_rate / div) != rate) || (div > 8))
2929                 return -EINVAL;
2930
2931         reg = __raw_readl(MXC_CCM_CHSCCDR);
2932         reg &= ~MXC_CCM_CHSCCDR_IPU1_DI1_PODF_MASK;
2933         reg |= (div - 1) << MXC_CCM_CHSCCDR_IPU1_DI1_PODF_OFFSET;
2934         __raw_writel(reg, MXC_CCM_CHSCCDR);
2935
2936         return 0;
2937 }
2938
2939
2940 static int _clk_ipu1_di1_set_parent(struct clk *clk, struct clk *parent)
2941 {
2942         u32 reg, mux;
2943
2944         if (parent == &ldb_di0_clk)
2945                 mux = 0x3;
2946         else if (parent == &ldb_di1_clk)
2947                 mux = 0x4;
2948         else {
2949                 reg = __raw_readl(MXC_CCM_CHSCCDR)
2950                         & ~MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_MASK;
2951
2952                 mux = _get_mux6(parent, &mmdc_ch0_axi_clk[0],
2953                                 &pll3_usb_otg_main_clk, &pll5_video_main_clk,
2954                                 &pll2_pfd_352M, &pll2_pfd_400M, &pll3_pfd_540M);
2955                 reg |= (mux << MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_OFFSET);
2956
2957                 __raw_writel(reg, MXC_CCM_CHSCCDR);
2958
2959                 /* Derive clock from divided pre-muxed ipu1_di0 clock.*/
2960                 mux = 0;
2961         }
2962         reg = __raw_readl(MXC_CCM_CHSCCDR)
2963                 & ~MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_MASK;
2964         __raw_writel(reg | (mux << MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET),
2965                 MXC_CCM_CHSCCDR);
2966
2967         return 0;
2968 }
2969
2970 static struct clk ipu1_di_clk[] = {
2971         {
2972          __INIT_CLK_DEBUG(ipu1_di_clk_0)
2973         .id = 0,
2974         .parent = &pll5_video_main_clk,
2975         .enable_reg = MXC_CCM_CCGR3,
2976         .enable_shift = MXC_CCM_CCGRx_CG1_OFFSET,
2977         .enable = _clk_enable,
2978         .disable = _clk_disable,
2979         .set_parent = _clk_ipu1_di0_set_parent,
2980         .set_rate = _clk_ipu1_di0_set_rate,
2981         .round_rate = _clk_ipu_di_round_rate,
2982         .get_rate = _clk_ipu1_di0_get_rate,
2983         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
2984         },
2985         {
2986          __INIT_CLK_DEBUG(ipu1_di_clk_1)
2987         .id = 1,
2988         .parent = &pll5_video_main_clk,
2989         .enable_reg = MXC_CCM_CCGR3,
2990         .enable_shift = MXC_CCM_CCGRx_CG2_OFFSET,
2991         .enable = _clk_enable,
2992         .disable = _clk_disable,
2993         .set_parent = _clk_ipu1_di1_set_parent,
2994         .set_rate = _clk_ipu1_di1_set_rate,
2995         .round_rate = _clk_ipu_di_round_rate,
2996         .get_rate = _clk_ipu1_di1_get_rate,
2997         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
2998         },
2999 };
3000
3001 static unsigned long _clk_ipu2_di0_get_rate(struct clk *clk)
3002 {
3003         u32 reg, div;
3004
3005         if ((clk->parent == &ldb_di0_clk) ||
3006                 (clk->parent == &ldb_di1_clk))
3007                 return clk_get_rate(clk->parent);
3008
3009         reg = __raw_readl(MXC_CCM_CSCDR2);
3010
3011         div = ((reg & MXC_CCM_CSCDR2_IPU2_DI0_PODF_MASK) >>
3012                         MXC_CCM_CSCDR2_IPU2_DI0_PODF_OFFSET) + 1;
3013
3014         return clk_get_rate(clk->parent) / div;
3015 }
3016
3017 static int _clk_ipu2_di0_set_rate(struct clk *clk, unsigned long rate)
3018 {
3019         u32 reg, div;
3020         u32 parent_rate = clk_get_rate(clk->parent);
3021
3022         if ((clk->parent == &ldb_di0_clk) ||
3023                 (clk->parent == &ldb_di1_clk)) {
3024                 if (parent_rate == rate)
3025                         return 0;
3026                 else
3027                         return -EINVAL;
3028         }
3029
3030         div = parent_rate / rate;
3031         if (div == 0)
3032                 div++;
3033         if (((parent_rate / div) != rate) || (div > 8))
3034                 return -EINVAL;
3035
3036         reg = __raw_readl(MXC_CCM_CSCDR2);
3037         reg &= ~MXC_CCM_CSCDR2_IPU2_DI0_PODF_MASK;
3038         reg |= (div - 1) << MXC_CCM_CSCDR2_IPU2_DI0_PODF_OFFSET;
3039         __raw_writel(reg, MXC_CCM_CSCDR2);
3040
3041         return 0;
3042 }
3043
3044 static int _clk_ipu2_di0_set_parent(struct clk *clk, struct clk *parent)
3045 {
3046         u32 reg, mux;
3047
3048         if (parent == &ldb_di0_clk)
3049                 mux = 0x3;
3050         else if (parent == &ldb_di1_clk)
3051                 mux = 0x4;
3052         else {
3053                 reg = __raw_readl(MXC_CCM_CSCDR2)
3054                         & ~MXC_CCM_CSCDR2_IPU2_DI0_PRE_CLK_SEL_MASK;
3055
3056                 mux = _get_mux6(parent, &mmdc_ch0_axi_clk[0],
3057                                 &pll3_usb_otg_main_clk, &pll5_video_main_clk,
3058                                 &pll2_pfd_352M, &pll2_pfd_400M, &pll3_pfd_540M);
3059                 reg |= (mux << MXC_CCM_CSCDR2_IPU2_DI0_PRE_CLK_SEL_OFFSET);
3060
3061                 __raw_writel(reg, MXC_CCM_CSCDR2);
3062
3063                 /* Derive clock from divided pre-muxed ipu2_di0 clock.*/
3064                 mux = 0;
3065         }
3066         reg = __raw_readl(MXC_CCM_CSCDR2)
3067                 & ~MXC_CCM_CSCDR2_IPU2_DI0_CLK_SEL_MASK;
3068         __raw_writel(reg | (mux << MXC_CCM_CSCDR2_IPU2_DI0_CLK_SEL_OFFSET),
3069                 MXC_CCM_CSCDR2);
3070
3071         return 0;
3072 }
3073
3074 static unsigned long _clk_ipu2_di1_get_rate(struct clk *clk)
3075 {
3076         u32 reg, div;
3077
3078         if ((clk->parent == &ldb_di0_clk) ||
3079                 (clk->parent == &ldb_di1_clk))
3080                 return clk_get_rate(clk->parent);
3081
3082         reg = __raw_readl(MXC_CCM_CSCDR2);
3083
3084         div = ((reg & MXC_CCM_CSCDR2_IPU2_DI1_PODF_MASK)
3085                 >> MXC_CCM_CSCDR2_IPU2_DI1_PODF_OFFSET) + 1;
3086
3087         return clk_get_rate(clk->parent) / div;
3088 }
3089
3090 static int _clk_ipu2_di1_set_rate(struct clk *clk, unsigned long rate)
3091 {
3092         u32 reg, div;
3093         u32 parent_rate = clk_get_rate(clk->parent);
3094
3095         if ((clk->parent == &ldb_di0_clk) ||
3096                 (clk->parent == &ldb_di1_clk)) {
3097                 if (parent_rate == rate)
3098                         return 0;
3099                 else
3100                         return -EINVAL;
3101         }
3102
3103         div = parent_rate / rate;
3104         if (div == 0)
3105                 div++;
3106         if (((parent_rate / div) != rate) || (div > 8))
3107                 return -EINVAL;
3108
3109         reg = __raw_readl(MXC_CCM_CSCDR2);
3110         reg &= ~MXC_CCM_CSCDR2_IPU2_DI1_PODF_MASK;
3111         reg |= (div - 1) << MXC_CCM_CSCDR2_IPU2_DI1_PODF_OFFSET;
3112         __raw_writel(reg, MXC_CCM_CSCDR2);
3113
3114         return 0;
3115 }
3116
3117 static int _clk_ipu2_di1_set_parent(struct clk *clk, struct clk *parent)
3118 {
3119         u32 reg, mux;
3120
3121         if (parent == &ldb_di0_clk)
3122                 mux = 0x3;
3123         else if (parent == &ldb_di1_clk)
3124                 mux = 0x4;
3125         else {
3126                 reg = __raw_readl(MXC_CCM_CSCDR2)
3127                         & ~MXC_CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_MASK;
3128
3129                 mux = _get_mux6(parent, &mmdc_ch0_axi_clk[0],
3130                                 &pll3_usb_otg_main_clk, &pll5_video_main_clk,
3131                                 &pll2_pfd_352M, &pll2_pfd_400M, &pll3_pfd_540M);
3132                 reg |= (mux << MXC_CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_OFFSET);
3133
3134                 __raw_writel(reg, MXC_CCM_CSCDR2);
3135
3136                 /* Derive clock from divided pre-muxed ipu1_di0 clock.*/
3137                 mux = 0;
3138         }
3139         reg = __raw_readl(MXC_CCM_CSCDR2)
3140                 & ~MXC_CCM_CSCDR2_IPU2_DI1_CLK_SEL_MASK;
3141         __raw_writel(reg | (mux << MXC_CCM_CSCDR2_IPU2_DI1_CLK_SEL_OFFSET),
3142                 MXC_CCM_CSCDR2);
3143
3144         return 0;
3145 }
3146
3147 static struct clk ipu2_di_clk[] = {
3148         {
3149          __INIT_CLK_DEBUG(ipu2_di_clk_0)
3150         .id = 0,
3151         .parent = &pll5_video_main_clk,
3152         .enable_reg = MXC_CCM_CCGR3,
3153         .enable_shift = MXC_CCM_CCGRx_CG4_OFFSET,
3154         .enable = _clk_enable,
3155         .disable = _clk_disable,
3156         .set_parent = _clk_ipu2_di0_set_parent,
3157         .set_rate = _clk_ipu2_di0_set_rate,
3158         .round_rate = _clk_ipu_di_round_rate,
3159         .get_rate = _clk_ipu2_di0_get_rate,
3160         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
3161         },
3162         {
3163          __INIT_CLK_DEBUG(ipu2_di_clk_1)
3164         .id = 1,
3165         .parent = &pll5_video_main_clk,
3166         .enable_reg = MXC_CCM_CCGR3,
3167         .enable_shift = MXC_CCM_CCGRx_CG5_OFFSET,
3168         .enable = _clk_enable,
3169         .disable = _clk_disable,
3170         .set_parent = _clk_ipu2_di1_set_parent,
3171         .set_rate = _clk_ipu2_di1_set_rate,
3172         .round_rate = _clk_ipu_di_round_rate,
3173         .get_rate = _clk_ipu2_di1_get_rate,
3174         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
3175         },
3176 };
3177
3178 static unsigned long _clk_can_root_round_rate(struct clk *clk,
3179                                                 unsigned long rate)
3180 {
3181         u32 div;
3182         u32 parent_rate = clk_get_rate(clk->parent);
3183
3184         div = parent_rate / rate;
3185
3186         /* Make sure rate is not greater than the maximum value for the clock.
3187          * Also prevent a div of 0.
3188          */
3189         if (div == 0)
3190                 div++;
3191
3192         if (div > 64)
3193                 div = 64;
3194
3195         return parent_rate / div;
3196 }
3197
3198 static int _clk_can_root_set_rate(struct clk *clk, unsigned long rate)
3199 {
3200         u32 reg, div;
3201         u32 parent_rate = clk_get_rate(clk->parent);
3202
3203         div = parent_rate / rate;
3204         if (div == 0)
3205                 div++;
3206         if (((parent_rate / div) != rate) || (div > 64))
3207                 return -EINVAL;
3208
3209         reg = __raw_readl(MXC_CCM_CSCMR2) & MXC_CCM_CSCMR2_CAN_CLK_PODF_MASK;
3210         reg |= ((div - 1) << MXC_CCM_CSCMR2_CAN_CLK_PODF_OFFSET);
3211
3212         __raw_writel(reg, MXC_CCM_CSCMR2);
3213
3214         return 0;
3215 }
3216
3217 static unsigned long _clk_can_root_get_rate(struct clk *clk)
3218 {
3219         u32 reg, div;
3220         unsigned long val;
3221
3222         reg = __raw_readl(MXC_CCM_CSCMR2) & MXC_CCM_CSCMR2_CAN_CLK_PODF_MASK;
3223         div = (reg >> MXC_CCM_CSCMR2_CAN_CLK_PODF_OFFSET) + 1;
3224         val = clk_get_rate(clk->parent) / div;
3225
3226         return val;
3227 }
3228
3229 static struct clk can_clk_root = {
3230          __INIT_CLK_DEBUG(can_clk_root)
3231         .parent = &pll3_60M,
3232         .set_rate = _clk_can_root_set_rate,
3233         .get_rate = _clk_can_root_get_rate,
3234         .round_rate = _clk_can_root_round_rate,
3235 };
3236
3237 static struct clk can2_clk[] = {
3238         {
3239          __INIT_CLK_DEBUG(can2_module_clk)
3240         .id = 0,
3241         .parent = &can_clk_root,
3242         .enable_reg = MXC_CCM_CCGR0,
3243         .enable_shift = MXC_CCM_CCGRx_CG9_OFFSET,
3244         .enable = _clk_enable,
3245         .disable = _clk_disable,
3246         .secondary = &can2_clk[1],
3247         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
3248         },
3249         {
3250          __INIT_CLK_DEBUG(can2_serial_clk)
3251         .id = 1,
3252         .parent = &can_clk_root,
3253         .enable_reg = MXC_CCM_CCGR0,
3254         .enable_shift = MXC_CCM_CCGRx_CG10_OFFSET,
3255         .enable = _clk_enable,
3256         .disable = _clk_disable,
3257         },
3258 };
3259
3260
3261 static struct clk can1_clk[] = {
3262         {
3263          __INIT_CLK_DEBUG(can1_module_clk)
3264         .id = 0,
3265         .parent = &can_clk_root,
3266         .enable_reg = MXC_CCM_CCGR0,
3267         .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
3268         .enable = _clk_enable,
3269         .disable = _clk_disable,
3270         .secondary = &can1_clk[1],
3271         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
3272         },
3273         {
3274          __INIT_CLK_DEBUG(can1_serial_clk)
3275         .id = 1,
3276         .parent = &can_clk_root,
3277         .enable_reg = MXC_CCM_CCGR0,
3278         .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET,
3279         .enable = _clk_enable,
3280         .disable = _clk_disable,
3281         },
3282 };
3283
3284 static unsigned long _clk_spdif_round_rate(struct clk *clk,
3285                                                 unsigned long rate)
3286 {
3287         u32 pre, post;
3288         u32 parent_rate = clk_get_rate(clk->parent);
3289         u32 div = parent_rate / rate;
3290
3291         if (parent_rate % rate)
3292                 div++;
3293
3294         __calc_pre_post_dividers(1 << 3, div, &pre, &post);
3295
3296         return parent_rate / (pre * post);
3297 }
3298
3299 static int _clk_spdif0_set_parent(struct clk *clk, struct clk *parent)
3300 {
3301         u32 reg, mux;
3302
3303         reg = __raw_readl(MXC_CCM_CDCDR)
3304                 & ~MXC_CCM_CDCDR_SPDIF0_CLK_SEL_MASK;
3305
3306         mux = _get_mux6(parent, &pll4_audio_main_clk,
3307                 &pll3_pfd_508M, &pll3_pfd_454M,
3308                 &pll3_sw_clk, NULL, NULL);
3309         reg |= mux << MXC_CCM_CDCDR_SPDIF0_CLK_SEL_OFFSET;
3310
3311         __raw_writel(reg, MXC_CCM_CDCDR);
3312
3313         return 0;
3314 }
3315
3316 static unsigned long _clk_spdif0_get_rate(struct clk *clk)
3317 {
3318         u32 reg, pred, podf;
3319
3320         reg = __raw_readl(MXC_CCM_CDCDR);
3321
3322         pred = ((reg & MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK)
3323                 >> MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET) + 1;
3324         podf = ((reg & MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK)
3325                 >> MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET) + 1;
3326
3327         return clk_get_rate(clk->parent) / (pred * podf);
3328 }
3329
3330 static int _clk_spdif0_set_rate(struct clk *clk, unsigned long rate)
3331 {
3332         u32 reg, div, pre, post;
3333         u32 parent_rate = clk_get_rate(clk->parent);
3334
3335         div = parent_rate / rate;
3336         if (div == 0)
3337                 div++;
3338         if (((parent_rate / div) != rate) || div > 64)
3339                 return -EINVAL;
3340
3341         __calc_pre_post_dividers(1 << 3, div, &pre, &post);
3342
3343         reg = __raw_readl(MXC_CCM_CDCDR);
3344         reg &= ~(MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK|
3345                  MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK);
3346         reg |= (post - 1) << MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET;
3347         reg |= (pre - 1) << MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET;
3348
3349         __raw_writel(reg, MXC_CCM_CDCDR);
3350
3351         return 0;
3352 }
3353
3354 static struct clk spdif0_clk[] = {
3355         {
3356         __INIT_CLK_DEBUG(spdif0_clk_0)
3357         .id = 0,
3358         .parent = &pll3_sw_clk,
3359          .enable = _clk_enable,
3360          .enable_reg = MXC_CCM_CCGR5,
3361          .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
3362          .disable = _clk_disable,
3363          .secondary = &spdif0_clk[1],
3364          .set_rate = _clk_spdif0_set_rate,
3365          .get_rate = _clk_spdif0_get_rate,
3366          .set_parent = _clk_spdif0_set_parent,
3367          .round_rate = _clk_spdif_round_rate,
3368         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
3369         },
3370         {
3371         __INIT_CLK_DEBUG(spdif0_clk_1)
3372          .id = 1,
3373          .parent = &ipg_clk,
3374          .secondary = &spba_clk,
3375          },
3376 };
3377
3378 static unsigned long _clk_esai_round_rate(struct clk *clk,
3379                                                 unsigned long rate)
3380 {
3381         u32 pre, post;
3382         u32 parent_rate = clk_get_rate(clk->parent);
3383         u32 div = parent_rate / rate;
3384
3385         if (parent_rate % rate)
3386                 div++;
3387
3388         __calc_pre_post_dividers(1 << 3, div, &pre, &post);
3389
3390         return parent_rate / (pre * post);
3391 }
3392
3393 static int _clk_esai_set_parent(struct clk *clk, struct clk *parent)
3394 {
3395         u32 reg, mux;
3396
3397         reg = __raw_readl(MXC_CCM_CSCMR2) & ~MXC_CCM_CSCMR2_ESAI_CLK_SEL_MASK;
3398
3399         mux = _get_mux6(parent, &pll4_audio_main_clk, &pll3_pfd_508M,
3400                         &pll3_pfd_454M, &pll3_sw_clk, NULL, NULL);
3401         reg |= mux << MXC_CCM_CSCMR2_ESAI_CLK_SEL_OFFSET;
3402
3403         __raw_writel(reg, MXC_CCM_CSCMR2);
3404
3405         return 0;
3406 }
3407
3408 static unsigned long _clk_esai_get_rate(struct clk *clk)
3409 {
3410         u32 reg, pred, podf;
3411
3412         reg = __raw_readl(MXC_CCM_CS1CDR);
3413
3414         pred = ((reg & MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK)
3415                 >> MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET) + 1;
3416         podf = ((reg & MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK)
3417                 >> MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET) + 1;
3418
3419         return clk_get_rate(clk->parent) / (pred * podf);
3420 }
3421
3422 static int _clk_esai_set_rate(struct clk *clk, unsigned long rate)
3423 {
3424         u32 reg, div, pre, post;
3425         u32 parent_rate = clk_get_rate(clk->parent);
3426
3427         div = parent_rate / rate;
3428         if (div == 0)
3429                 div++;
3430         if (((parent_rate / div) != rate) || div > 64)
3431                 return -EINVAL;
3432
3433         __calc_pre_post_dividers(1 << 3, div, &pre, &post);
3434
3435         reg = __raw_readl(MXC_CCM_CS1CDR);
3436         reg &= ~(MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK|
3437                  MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK);
3438         reg |= (post - 1) << MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET;
3439         reg |= (pre - 1) << MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET;
3440
3441         __raw_writel(reg, MXC_CCM_CS1CDR);
3442
3443         return 0;
3444 }
3445
3446 static struct clk esai_clk = {
3447         __INIT_CLK_DEBUG(esai_clk)
3448          .id = 0,
3449          .parent = &pll3_sw_clk,
3450          .secondary = &spba_clk,
3451          .enable_reg = MXC_CCM_CCGR1,
3452          .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET,
3453          .enable = _clk_enable,
3454          .disable = _clk_disable,
3455          .set_rate = _clk_esai_set_rate,
3456          .get_rate = _clk_esai_get_rate,
3457          .set_parent = _clk_esai_set_parent,
3458          .round_rate = _clk_esai_round_rate,
3459 };
3460
3461 static int _clk_enet_enable(struct clk *clk)
3462 {
3463         unsigned int reg;
3464
3465         /* Enable ENET ref clock */
3466         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
3467         reg &= ~ANADIG_PLL_BYPASS;
3468         reg |= ANADIG_PLL_ENABLE;
3469         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
3470
3471         _clk_enable(clk);
3472         return 0;
3473 }
3474
3475 static void _clk_enet_disable(struct clk *clk)
3476 {
3477         unsigned int reg;
3478
3479         _clk_disable(clk);
3480
3481         /* Enable ENET ref clock */
3482         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
3483         reg |= ANADIG_PLL_BYPASS;
3484         reg &= ~ANADIG_PLL_ENABLE;
3485         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
3486 }
3487
3488 static int _clk_enet_set_rate(struct clk *clk, unsigned long rate)
3489 {
3490         unsigned int reg, div = 1;
3491
3492         switch (rate) {
3493         case 25000000:
3494                 div = 0;
3495                 break;
3496         case 50000000:
3497                 div = 1;
3498                 break;
3499         case 100000000:
3500                 div = 2;
3501                 break;
3502         case 125000000:
3503                 div = 3;
3504                 break;
3505         default:
3506                 return -EINVAL;
3507         }
3508         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
3509         reg &= ~ANADIG_PLL_ENET_DIV_SELECT_MASK;
3510         reg |= (div << ANADIG_PLL_ENET_DIV_SELECT_OFFSET);
3511         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
3512
3513         return 0;
3514 }
3515
3516 static unsigned long _clk_enet_get_rate(struct clk *clk)
3517 {
3518         unsigned int div;
3519
3520         div = (__raw_readl(PLL8_ENET_BASE_ADDR))
3521                 & ANADIG_PLL_ENET_DIV_SELECT_MASK;
3522
3523         switch (div) {
3524         case 0:
3525                 div = 20;
3526                 break;
3527         case 1:
3528                 div = 10;
3529                 break;
3530         case 3:
3531                 div = 5;
3532                 break;
3533         case 4:
3534                 div = 4;
3535                 break;
3536         }
3537
3538         return 500000000 / div;
3539 }
3540
3541 static struct clk enet_clk[] = {
3542         {
3543         __INIT_CLK_DEBUG(enet_clk)
3544          .id = 0,
3545          .parent = &pll8_enet_main_clk,
3546          .enable_reg = MXC_CCM_CCGR1,
3547          .enable_shift = MXC_CCM_CCGRx_CG5_OFFSET,
3548          .enable = _clk_enet_enable,
3549          .disable = _clk_enet_disable,
3550          .set_rate = _clk_enet_set_rate,
3551          .get_rate = _clk_enet_get_rate,
3552         .secondary = &enet_clk[1],
3553         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
3554         },
3555         {
3556         .parent = &mmdc_ch0_axi_clk[0],
3557         .secondary = &mx6per1_clk,
3558         },
3559 };
3560
3561 static struct clk ecspi_clk[] = {
3562         {
3563         __INIT_CLK_DEBUG(ecspi0_clk)
3564         .id = 0,
3565         .parent = &pll3_60M,
3566         .secondary = &spba_clk,
3567         .enable_reg = MXC_CCM_CCGR1,
3568         .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET,
3569         .enable = _clk_enable,
3570         .disable = _clk_disable,
3571         },
3572         {
3573         __INIT_CLK_DEBUG(ecspi1_clk)
3574         .id = 1,
3575         .parent = &pll3_60M,
3576         .secondary = &spba_clk,
3577         .enable_reg = MXC_CCM_CCGR1,
3578         .enable_shift = MXC_CCM_CCGRx_CG1_OFFSET,
3579         .enable = _clk_enable,
3580         .disable = _clk_disable,
3581         },
3582         {
3583         __INIT_CLK_DEBUG(ecspi2_clk)
3584         .id = 2,
3585         .parent = &pll3_60M,
3586         .secondary = &spba_clk,
3587         .enable_reg = MXC_CCM_CCGR1,
3588         .enable_shift = MXC_CCM_CCGRx_CG2_OFFSET,
3589         .enable = _clk_enable,
3590         .disable = _clk_disable,
3591         },
3592         {
3593         __INIT_CLK_DEBUG(ecspi3_clk)
3594         .id = 3,
3595         .parent = &pll3_60M,
3596         .secondary = &spba_clk,
3597         .enable_reg = MXC_CCM_CCGR1,
3598         .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET,
3599         .enable = _clk_enable,
3600         .disable = _clk_disable,
3601         },
3602         {
3603         __INIT_CLK_DEBUG(ecspi4_clk)
3604         .id = 4,
3605         .parent = &pll3_60M,
3606         .secondary = &spba_clk,
3607         .enable_reg = MXC_CCM_CCGR1,
3608         .enable_shift = MXC_CCM_CCGRx_CG4_OFFSET,
3609         .enable = _clk_enable,
3610         .disable = _clk_disable,
3611         },
3612 };
3613
3614 static unsigned long _clk_emi_slow_round_rate(struct clk *clk,
3615                                                 unsigned long rate)
3616 {
3617         u32 div;
3618         u32 parent_rate = clk_get_rate(clk->parent);
3619
3620         div = parent_rate / rate;
3621
3622         /* Make sure rate is not greater than the maximum value for the clock.
3623          * Also prevent a div of 0.
3624          */
3625         if (div == 0)
3626                 div++;
3627
3628         if (div > 8)
3629                 div = 8;
3630
3631         return parent_rate / div;
3632 }
3633
3634 static int _clk_emi_slow_set_parent(struct clk *clk, struct clk *parent)
3635 {
3636         int mux;
3637         u32 reg = __raw_readl(MXC_CCM_CSCMR1)
3638                 & ~MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK;
3639
3640         mux = _get_mux6(parent, &axi_clk, &pll3_usb_otg_main_clk,
3641                                 &pll2_pfd_400M, &pll2_pfd_352M, NULL, NULL);
3642         reg |= (mux << MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET);
3643         __raw_writel(reg, MXC_CCM_CSCMR1);
3644
3645         return 0;
3646 }
3647
3648 static unsigned long _clk_emi_slow_get_rate(struct clk *clk)
3649 {
3650         u32 reg, div;
3651
3652         reg = __raw_readl(MXC_CCM_CSCMR1);
3653         div = ((reg & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK) >>
3654                         MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET) + 1;
3655
3656         return clk_get_rate(clk->parent) / div;
3657 }
3658
3659 static int _clk_emi_slow_set_rate(struct clk *clk, unsigned long rate)
3660 {
3661         u32 reg, div;
3662         u32 parent_rate = clk_get_rate(clk->parent);
3663
3664         div = parent_rate / rate;
3665         if (div == 0)
3666                 div++;
3667         if (((parent_rate / div) != rate) || (div > 8))
3668                 return -EINVAL;
3669
3670         reg = __raw_readl(MXC_CCM_CSCMR1);
3671         reg &= ~MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK;
3672         reg |= (div - 1) << MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET;
3673         __raw_writel(reg, MXC_CCM_CSCMR1);
3674
3675         return 0;
3676 }
3677
3678 static struct clk emi_slow_clk = {
3679         __INIT_CLK_DEBUG(emi_slow_clk)
3680          .id = 0,
3681          .parent = &axi_clk,
3682          .enable_reg = MXC_CCM_CCGR6,
3683          .enable_shift = MXC_CCM_CCGRx_CG5_OFFSET,
3684          .enable = _clk_enable,
3685          .disable = _clk_disable,
3686          .set_rate = _clk_emi_slow_set_rate,
3687          .get_rate = _clk_emi_slow_get_rate,
3688          .round_rate = _clk_emi_slow_round_rate,
3689          .set_parent = _clk_emi_slow_set_parent,
3690 };
3691
3692 static unsigned long _clk_emi_round_rate(struct clk *clk,
3693                                                 unsigned long rate)
3694 {
3695         u32 div;
3696         u32 parent_rate = clk_get_rate(clk->parent);
3697
3698         div = parent_rate / rate;
3699
3700         /* Make sure rate is not greater than the maximum value for the clock.
3701          * Also prevent a div of 0.
3702          */
3703         if (div == 0)
3704                 div++;
3705
3706         if (div > 8)
3707                 div = 8;
3708
3709         return parent_rate / div;
3710 }
3711
3712 static int _clk_emi_set_parent(struct clk *clk, struct clk *parent)
3713 {
3714         int mux;
3715         u32 reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_ACLK_EMI_MASK;
3716
3717         mux = _get_mux6(parent, &axi_clk, &pll3_usb_otg_main_clk,
3718                         &pll2_pfd_400M, &pll2_pfd_352M, NULL, NULL);
3719         reg |= (mux << MXC_CCM_CSCMR1_ACLK_EMI_OFFSET);
3720         __raw_writel(reg, MXC_CCM_CSCMR1);
3721
3722         return 0;
3723 }
3724
3725 static unsigned long _clk_emi_get_rate(struct clk *clk)
3726 {
3727         u32 reg, div;
3728
3729         reg = __raw_readl(MXC_CCM_CSCMR1);
3730         div = ((reg & MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK) >>
3731                         MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET) + 1;
3732
3733         return clk_get_rate(clk->parent) / div;
3734 }
3735
3736 static int _clk_emi_set_rate(struct clk *clk, unsigned long rate)
3737 {
3738         u32 reg, div;
3739         u32 parent_rate = clk_get_rate(clk->parent);
3740
3741         div = parent_rate / rate;
3742         if (div == 0)
3743                 div++;
3744         if (((parent_rate / div) != rate) || (div > 8))
3745                 return -EINVAL;
3746
3747         reg = __raw_readl(MXC_CCM_CSCMR1);
3748         reg &= ~MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK;
3749         reg |= (div - 1) << MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET;
3750         __raw_writel(reg, MXC_CCM_CSCMR1);
3751
3752         return 0;
3753 }
3754
3755 static struct clk emi_clk = {
3756         __INIT_CLK_DEBUG(emi_clk)
3757          .id = 0,
3758          .parent = &axi_clk,
3759          .set_rate = _clk_emi_set_rate,
3760          .get_rate = _clk_emi_get_rate,
3761          .round_rate = _clk_emi_round_rate,
3762          .set_parent = _clk_emi_set_parent,
3763 };
3764
3765 static unsigned long _clk_enfc_round_rate(struct clk *clk,
3766                                                 unsigned long rate)
3767 {
3768         u32 pre, post;
3769         u32 parent_rate = clk_get_rate(clk->parent);
3770         u32 div = parent_rate / rate;
3771
3772         if (parent_rate % rate)
3773                 div++;
3774
3775         __calc_pre_post_dividers(1 << 6, div, &pre, &post);
3776
3777         return parent_rate / (pre * post);
3778 }
3779
3780 static int _clk_enfc_set_parent(struct clk *clk, struct clk *parent)
3781 {
3782         u32 reg, mux;
3783
3784         reg = __raw_readl(MXC_CCM_CS2CDR)
3785                 & ~MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK;
3786
3787         mux = _get_mux6(parent, &pll2_pfd_352M,
3788                 &pll2_528_bus_main_clk, &pll3_usb_otg_main_clk,
3789                 &pll2_pfd_400M, NULL, NULL);
3790         reg |= mux << MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET;
3791
3792         __raw_writel(reg, MXC_CCM_CS2CDR);
3793
3794         return 0;
3795 }
3796
3797 static unsigned long _clk_enfc_get_rate(struct clk *clk)
3798 {
3799         u32 reg, pred, podf;
3800
3801         reg = __raw_readl(MXC_CCM_CS2CDR);
3802
3803         pred = ((reg & MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK)
3804                 >> MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET) + 1;
3805         podf = ((reg & MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK)
3806                 >> MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET) + 1;
3807
3808         return clk_get_rate(clk->parent) / (pred * podf);
3809 }
3810
3811 static int _clk_enfc_set_rate(struct clk *clk, unsigned long rate)
3812 {
3813         u32 reg, div, pre, post;
3814         u32 parent_rate = clk_get_rate(clk->parent);
3815
3816         div = parent_rate / rate;
3817         if (div == 0)
3818                 div++;
3819         if (((parent_rate / div) != rate) || div > 512)
3820                 return -EINVAL;
3821
3822         __calc_pre_post_dividers(1 << 6, div, &pre, &post);
3823
3824         reg = __raw_readl(MXC_CCM_CS2CDR);
3825         reg &= ~(MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK|
3826                  MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK);
3827         reg |= (post - 1) << MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET;
3828         reg |= (pre - 1) << MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET;
3829
3830         __raw_writel(reg, MXC_CCM_CS2CDR);
3831
3832         return 0;
3833 }
3834
3835 static struct clk enfc_clk = {
3836         __INIT_CLK_DEBUG(enfc_clk)
3837          .id = 0,
3838          .parent = &pll2_pfd_352M,
3839          .enable_reg = MXC_CCM_CCGR2,
3840          .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
3841          .enable = _clk_enable,
3842          .disable = _clk_disable,
3843          .set_rate = _clk_enfc_set_rate,
3844          .get_rate = _clk_enfc_get_rate,
3845          .round_rate = _clk_enfc_round_rate,
3846          .set_parent = _clk_enfc_set_parent,
3847 };
3848
3849 static unsigned long _clk_uart_round_rate(struct clk *clk,
3850                                                 unsigned long rate)
3851 {
3852         u32 div;
3853         u32 parent_rate = clk_get_rate(clk->parent);
3854
3855         div = parent_rate / rate;
3856
3857         /* Make sure rate is not greater than the maximum value for the clock.
3858          * Also prevent a div of 0.
3859          */
3860         if (div == 0)
3861                 div++;
3862
3863         if (div > 64)
3864                 div = 64;
3865
3866         return parent_rate / div;
3867 }
3868
3869 static int _clk_uart_set_rate(struct clk *clk, unsigned long rate)
3870 {
3871         u32 reg, div;
3872         u32 parent_rate = clk_get_rate(clk->parent);
3873
3874         div = parent_rate / rate;
3875         if (div == 0)
3876                 div++;
3877         if (((parent_rate / div) != rate) || (div > 64))
3878                 return -EINVAL;
3879
3880         reg = __raw_readl(MXC_CCM_CSCDR1) & MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
3881         reg |= ((div - 1) << MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET);
3882
3883         __raw_writel(reg, MXC_CCM_CSCDR1);
3884
3885         return 0;
3886 }
3887
3888 static unsigned long _clk_uart_get_rate(struct clk *clk)
3889 {
3890         u32 reg, div;
3891         unsigned long val;
3892
3893         reg = __raw_readl(MXC_CCM_CSCDR1) & MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
3894         div = (reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET) + 1;
3895         val = clk_get_rate(clk->parent) / div;
3896
3897         return val;
3898 }
3899
3900 static struct clk uart_clk[] = {
3901         {
3902         __INIT_CLK_DEBUG(uart_clk)
3903          .id = 0,
3904          .parent = &pll3_80M,
3905          .enable_reg = MXC_CCM_CCGR5,
3906          .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET,
3907          .enable = _clk_enable,
3908          .disable = _clk_disable,
3909          .secondary = &uart_clk[1],
3910          .set_rate = _clk_uart_set_rate,
3911          .get_rate = _clk_uart_get_rate,
3912          .round_rate = _clk_uart_round_rate,
3913         },
3914         {
3915         __INIT_CLK_DEBUG(uart_serial_clk)
3916          .id = 1,
3917          .enable_reg = MXC_CCM_CCGR5,
3918          .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
3919          .enable = _clk_enable,
3920          .disable = _clk_disable,
3921         },
3922 };
3923
3924 static unsigned long _clk_hsi_tx_round_rate(struct clk *clk,
3925                                                 unsigned long rate)
3926 {
3927         u32 div;
3928         u32 parent_rate = clk_get_rate(clk->parent);
3929
3930         div = parent_rate / rate;
3931
3932         /* Make sure rate is not greater than the maximum value for the clock.
3933          * Also prevent a div of 0.
3934          */
3935         if (div == 0)
3936                 div++;
3937
3938         if (div > 8)
3939                 div = 8;
3940
3941         return parent_rate / div;
3942 }
3943
3944 static int _clk_hsi_tx_set_parent(struct clk *clk, struct clk *parent)
3945 {
3946         u32 reg = __raw_readl(MXC_CCM_CDCDR) & ~MXC_CCM_CDCDR_HSI_TX_CLK_SEL;
3947
3948         if (parent == &pll2_pfd_400M)
3949                 reg |= (MXC_CCM_CDCDR_HSI_TX_CLK_SEL);
3950
3951         __raw_writel(reg, MXC_CCM_CDCDR);
3952
3953         return 0;
3954 }
3955
3956 static unsigned long _clk_hsi_tx_get_rate(struct clk *clk)
3957 {
3958         u32 reg, div;
3959
3960         reg = __raw_readl(MXC_CCM_CDCDR);
3961         div = ((reg & MXC_CCM_CDCDR_HSI_TX_PODF_MASK) >>
3962                         MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET) + 1;
3963
3964         return clk_get_rate(clk->parent) / div;
3965 }
3966
3967 static int _clk_hsi_tx_set_rate(struct clk *clk, unsigned long rate)
3968 {
3969         u32 reg, div;
3970         u32 parent_rate = clk_get_rate(clk->parent);
3971
3972         div = parent_rate / rate;
3973         if (div == 0)
3974                 div++;
3975         if (((parent_rate / div) != rate) || (div > 8))
3976                 return -EINVAL;
3977
3978         reg = __raw_readl(MXC_CCM_CDCDR);
3979         reg &= ~MXC_CCM_CDCDR_HSI_TX_PODF_MASK;
3980         reg |= (div - 1) << MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET;
3981         __raw_writel(reg, MXC_CCM_CDCDR);
3982
3983         return 0;
3984 }
3985
3986 static struct clk hsi_tx_clk[] = {
3987         {
3988          __INIT_CLK_DEBUG(hsi_tx_clk)
3989         .id = 0,
3990          .parent = &pll2_pfd_400M,
3991         .enable_reg = MXC_CCM_CCGR3,
3992         .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET,
3993         .enable = _clk_enable,
3994         .disable = _clk_disable,
3995         .set_parent = _clk_hsi_tx_set_parent,
3996         .round_rate = _clk_hsi_tx_round_rate,
3997         .set_rate = _clk_hsi_tx_set_rate,
3998         .get_rate = _clk_hsi_tx_get_rate,
3999          .secondary = &hsi_tx_clk[1],
4000         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
4001         },
4002         {
4003         .parent = &mx6per1_clk,
4004         .secondary = &mx6per2_clk,
4005          },
4006 };
4007
4008 static struct clk mipi_pllref_clk = {
4009          __INIT_CLK_DEBUG(mipi_pllref_clk)
4010         .id = 0,
4011         .parent = &pll3_pfd_540M,
4012         .enable_reg = MXC_CCM_CCGR3,
4013         .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET,
4014         .enable = _clk_enable,
4015         .disable = _clk_disable,
4016 };
4017
4018 static struct clk hdmi_clk[] = {
4019         {
4020          __INIT_CLK_DEBUG(hdmi_isfr_clk)
4021         .id = 0,
4022         .parent = &pll3_pfd_540M,
4023         .enable_reg = MXC_CCM_CCGR2,
4024         .enable_shift = MXC_CCM_CCGRx_CG2_OFFSET,
4025         .enable = _clk_enable,
4026         .disable = _clk_disable,
4027         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
4028         },
4029         {
4030          __INIT_CLK_DEBUG(hdmi_iahb_clk)
4031         .id = 1,
4032          .parent = &ahb_clk,
4033         .enable_reg = MXC_CCM_CCGR2,
4034         .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET,
4035         .enable = _clk_enable,
4036         .disable = _clk_disable,
4037         },
4038 };
4039
4040 static struct clk caam_clk[] = {
4041         {
4042          __INIT_CLK_DEBUG(caam_mem_clk)
4043         .id = 0,
4044         .enable_reg = MXC_CCM_CCGR0,
4045         .enable_shift = MXC_CCM_CCGRx_CG4_OFFSET,
4046         .enable = _clk_enable,
4047         .disable = _clk_disable,
4048         .secondary = &caam_clk[1],
4049         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
4050         },
4051         {
4052          __INIT_CLK_DEBUG(caam_aclk_clk)
4053         .id = 1,
4054         .enable_reg = MXC_CCM_CCGR0,
4055         .enable_shift = MXC_CCM_CCGRx_CG5_OFFSET,
4056         .enable = _clk_enable,
4057         .disable = _clk_disable,
4058         .secondary = &caam_clk[2],
4059         },
4060         {
4061          __INIT_CLK_DEBUG(caam_ipg_clk)
4062         .id = 2,
4063         .enable_reg = MXC_CCM_CCGR0,
4064         .enable_shift = MXC_CCM_CCGRx_CG4_OFFSET,
4065         .enable = _clk_enable,
4066         .disable = _clk_disable,
4067         .parent = &mmdc_ch0_axi_clk[0],
4068         .secondary = &mx6per1_clk,
4069         },
4070 };
4071
4072 static int _clk_asrc_serial_set_parent(struct clk *clk, struct clk *parent)
4073 {
4074         u32 reg, mux;
4075
4076         reg = __raw_readl(MXC_CCM_CDCDR) & ~MXC_CCM_CDCDR_SPDIF1_CLK_SEL_MASK;
4077
4078         mux = _get_mux6(parent, &pll4_audio_main_clk, &pll3_pfd_508M,
4079                         &pll3_pfd_454M, &pll3_sw_clk, NULL, NULL);
4080         reg |= mux << MXC_CCM_CDCDR_SPDIF1_CLK_SEL_OFFSET;
4081
4082         __raw_writel(reg, MXC_CCM_CDCDR);
4083
4084         return 0;
4085 }
4086
4087 static unsigned long _clk_asrc_serial_get_rate(struct clk *clk)
4088 {
4089         u32 reg, pred, podf;
4090
4091         reg = __raw_readl(MXC_CCM_CDCDR);
4092
4093         pred = ((reg & MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK)
4094                 >> MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET) + 1;
4095         podf = ((reg & MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK)
4096                 >> MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET) + 1;
4097
4098         return clk_get_rate(clk->parent) / (pred * podf);
4099 }
4100
4101 static int _clk_asrc_serial_set_rate(struct clk *clk, unsigned long rate)
4102 {
4103         u32 reg, div, pre, post;
4104         u32 parent_rate = clk_get_rate(clk->parent);
4105
4106         div = parent_rate / rate;
4107         if (div == 0)
4108                 div++;
4109         if (((parent_rate / div) != rate) || div > 64)
4110                 return -EINVAL;
4111
4112         __calc_pre_post_dividers(1 << 3, div, &pre, &post);
4113
4114         reg = __raw_readl(MXC_CCM_CDCDR);
4115         reg &= ~(MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK|
4116                  MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK);
4117         reg |= (post - 1) << MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET;
4118         reg |= (pre - 1) << MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET;
4119
4120         __raw_writel(reg, MXC_CCM_CDCDR);
4121
4122         return 0;
4123 }
4124
4125 static unsigned long _clk_asrc_serial_round_rate(struct clk *clk,
4126                                                 unsigned long rate)
4127 {
4128         u32 pre, post;
4129         u32 parent_rate = clk_get_rate(clk->parent);
4130         u32 div = parent_rate / rate;
4131
4132         if (parent_rate % rate)
4133                 div++;
4134
4135         __calc_pre_post_dividers(1 << 3, div, &pre, &post);
4136
4137         return parent_rate / (pre * post);
4138 }
4139
4140 static struct clk asrc_clk[] = {
4141         {
4142         __INIT_CLK_DEBUG(asrc_clk)
4143         .id = 0,
4144         .parent = &pll4_audio_main_clk,
4145         .enable_reg = MXC_CCM_CCGR0,
4146         .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET,
4147         .enable = _clk_enable,
4148         .disable = _clk_disable,
4149         .secondary = &spba_clk,
4150         },
4151         {
4152         /*In the MX6 spec, asrc_serial_clk is listed as SPDIF1 clk
4153          * This clock can never be gated and does  not have any
4154          * CCGR bits associated with it.
4155          */
4156         __INIT_CLK_DEBUG(asrc_serial_clk)
4157         .id = 1,
4158         .parent = &pll3_sw_clk,
4159          .set_rate = _clk_asrc_serial_set_rate,
4160          .get_rate = _clk_asrc_serial_get_rate,
4161          .set_parent = _clk_asrc_serial_set_parent,
4162          .round_rate = _clk_asrc_serial_round_rate,
4163         },
4164 };
4165
4166 static struct clk apbh_dma_clk = {
4167         __INIT_CLK_DEBUG(apbh_dma_clk)
4168         .parent = &usdhc3_clk,
4169         .secondary = &mx6per1_clk,
4170         .enable = _clk_enable,
4171         .disable = _clk_disable_inwait,
4172         .enable_reg = MXC_CCM_CCGR0,
4173         .enable_shift = MXC_CCM_CCGRx_CG2_OFFSET,
4174 };
4175
4176 static struct clk aips_tz2_clk = {
4177         __INIT_CLK_DEBUG(aips_tz2_clk)
4178         .parent = &ahb_clk,
4179         .enable_reg = MXC_CCM_CCGR0,
4180         .enable_shift = MXC_CCM_CCGRx_CG1_OFFSET,
4181         .enable = _clk_enable,
4182         .disable = _clk_disable_inwait,
4183 };
4184
4185 static struct clk aips_tz1_clk = {
4186         __INIT_CLK_DEBUG(aips_tz1_clk)
4187         .parent = &ahb_clk,
4188         .enable_reg = MXC_CCM_CCGR0,
4189         .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET,
4190         .enable = _clk_enable,
4191         .disable = _clk_disable_inwait,
4192 };
4193
4194
4195 static struct clk openvg_axi_clk = {
4196         __INIT_CLK_DEBUG(openvg_axi_clk)
4197         .parent = &gpu2d_axi_clk,
4198         .enable = _clk_enable,
4199         .enable_reg = MXC_CCM_CCGR3,
4200         .enable_shift = MXC_CCM_CCGRx_CG15_OFFSET,
4201         .disable = _clk_disable,
4202         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
4203 };
4204
4205 static unsigned long _clk_gpu3d_core_round_rate(struct clk *clk,
4206                                                 unsigned long rate)
4207 {
4208         u32 div;
4209         u32 parent_rate = clk_get_rate(clk->parent);
4210
4211         div = parent_rate / rate;
4212
4213         /* Make sure rate is not greater than the maximum value for the clock.
4214          * Also prevent a div of 0.
4215          */
4216         if (div == 0)
4217                 div++;
4218
4219         if (div > 8)
4220                 div = 8;
4221
4222         return parent_rate / div;
4223 }
4224
4225 static int _clk_gpu3d_core_set_parent(struct clk *clk, struct clk *parent)
4226 {
4227         int mux;
4228         u32 reg = __raw_readl(MXC_CCM_CBCMR)
4229                 & ~MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK;
4230
4231         mux = _get_mux6(parent, &mmdc_ch0_axi_clk[0],
4232                 &pll3_usb_otg_main_clk,
4233                 &pll2_pfd_594M, &pll2_pfd_400M, NULL, NULL);
4234         reg |= (mux << MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET);
4235         __raw_writel(reg, MXC_CCM_CBCMR);
4236
4237         return 0;
4238 }
4239
4240 static unsigned long _clk_gpu3d_core_get_rate(struct clk *clk)
4241 {
4242         u32 reg, div;
4243
4244         reg = __raw_readl(MXC_CCM_CBCMR);
4245         div = ((reg & MXC_CCM_CBCMR_GPU3D_CORE_PODF_MASK) >>
4246                         MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET) + 1;
4247
4248         return clk_get_rate(clk->parent) / div;
4249 }
4250
4251 static int _clk_gpu3d_core_set_rate(struct clk *clk, unsigned long rate)
4252 {
4253         u32 reg, div;
4254         u32 parent_rate = clk_get_rate(clk->parent);
4255
4256         div = parent_rate / rate;
4257         if (div == 0)
4258                 div++;
4259         if (div > 8)
4260                 div = 8;
4261
4262         reg = __raw_readl(MXC_CCM_CBCMR);
4263         reg &= ~MXC_CCM_CBCMR_GPU3D_CORE_PODF_MASK;
4264         reg |= (div - 1) << MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET;
4265         __raw_writel(reg, MXC_CCM_CBCMR);
4266
4267         return 0;
4268 }
4269
4270 static struct clk gpu3d_core_clk[] = {
4271         {
4272         __INIT_CLK_DEBUG(gpu3d_core_clk)
4273         .parent = &pll2_pfd_594M,
4274         .enable = _clk_enable,
4275         .enable_reg = MXC_CCM_CCGR1,
4276         .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
4277         .disable = _clk_disable,
4278         .set_parent = _clk_gpu3d_core_set_parent,
4279         .set_rate = _clk_gpu3d_core_set_rate,
4280         .get_rate = _clk_gpu3d_core_get_rate,
4281         .round_rate = _clk_gpu3d_core_round_rate,
4282         .secondary = &gpu3d_core_clk[1],
4283         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
4284         },
4285         {
4286         .parent = &gpu3d_axi_clk,
4287         .secondary = &mx6fast1_clk,
4288         },
4289 };
4290
4291 static unsigned long _clk_gpu2d_core_round_rate(struct clk *clk,
4292                                                 unsigned long rate)
4293 {
4294         u32 div;
4295         u32 parent_rate = clk_get_rate(clk->parent);
4296
4297         div = parent_rate / rate;
4298
4299         /* Make sure rate is not greater than the maximum value for the clock.
4300          * Also prevent a div of 0.
4301          */
4302         if (div == 0)
4303                 div++;
4304
4305         if (div > 8)
4306                 div = 8;
4307
4308         return parent_rate / div;
4309 }
4310
4311 static int _clk_gpu2d_core_set_parent(struct clk *clk, struct clk *parent)
4312 {
4313         int mux;
4314         u32 reg = __raw_readl(MXC_CCM_CBCMR) &
4315                                 ~MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK;
4316
4317         /*on mx6dl, 2d core clock sources from 3d shader core clock*/
4318         if (!cpu_is_mx6dl()) {
4319                 mux = _get_mux6(parent, &axi_clk, &pll3_usb_otg_main_clk,
4320                         &pll2_pfd_352M, &pll2_pfd_400M, NULL, NULL);
4321                 reg |= (mux << MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET);
4322                 __raw_writel(reg, MXC_CCM_CBCMR);
4323         }
4324
4325         return 0;
4326 }
4327
4328 static unsigned long _clk_gpu2d_core_get_rate(struct clk *clk)
4329 {
4330         u32 reg, div = 1;
4331
4332         reg = __raw_readl(MXC_CCM_CBCMR);
4333         if (cpu_is_mx6q())
4334                 div = ((reg & MXC_CCM_CBCMR_GPU2D_CORE_PODF_MASK) >>
4335                                 MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET) + 1;
4336         else if (cpu_is_mx6dl())
4337                 /* on i.mx6dl, gpu2d_core_clk source from gpu3d_shader_clk */
4338                 return clk_get_rate(clk->parent);
4339
4340         return clk_get_rate(clk->parent) / div;
4341 }
4342
4343 static int _clk_gpu2d_core_set_rate(struct clk *clk, unsigned long rate)
4344 {
4345         u32 reg, div;
4346         u32 parent_rate = clk_get_rate(clk->parent);
4347
4348         div = parent_rate / rate;
4349         if (div == 0)
4350                 div++;
4351         if (((parent_rate / div) != rate) || (div > 8))
4352                 return -EINVAL;
4353
4354         reg = __raw_readl(MXC_CCM_CBCMR);
4355         reg &= ~MXC_CCM_CBCMR_GPU2D_CORE_PODF_MASK;
4356         reg |= (div - 1) << MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET;
4357         __raw_writel(reg, MXC_CCM_CBCMR);
4358
4359         return 0;
4360 }
4361 static struct clk gpu2d_core_clk[] = {
4362         {
4363         __INIT_CLK_DEBUG(gpu2d_core_clk)
4364         .parent = &pll2_pfd_352M,
4365         .enable = _clk_enable,
4366         .enable_reg = MXC_CCM_CCGR1,
4367         .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET,
4368         .disable = _clk_disable,
4369         .set_parent = _clk_gpu2d_core_set_parent,
4370         .set_rate = _clk_gpu2d_core_set_rate,
4371         .get_rate = _clk_gpu2d_core_get_rate,
4372         .round_rate = _clk_gpu2d_core_round_rate,
4373         .secondary = &mx6fast1_clk,
4374         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
4375         },
4376 };
4377
4378 static unsigned long _clk_gpu3d_shader_round_rate(struct clk *clk,
4379                                                 unsigned long rate)
4380 {
4381         u32 div;
4382         u32 parent_rate = clk_get_rate(clk->parent);
4383
4384         div = parent_rate / rate;
4385
4386         /* Make sure rate is not greater than the maximum value for the clock.
4387          * Also prevent a div of 0.
4388          */
4389         if (div == 0)
4390                 div++;
4391
4392         if (div > 8)
4393                 div = 8;
4394
4395         return parent_rate / div;
4396 }
4397
4398 static int _clk_gpu3d_shader_set_parent(struct clk *clk, struct clk *parent)
4399 {
4400         int mux;
4401         u32 reg = __raw_readl(MXC_CCM_CBCMR)
4402                 & ~MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_MASK;
4403
4404         mux = _get_mux6(parent, &mmdc_ch0_axi_clk[0],
4405                 &pll3_usb_otg_main_clk,
4406                 &pll2_pfd_594M, &pll3_pfd_720M, NULL, NULL);
4407         reg |= (mux << MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET);
4408         __raw_writel(reg, MXC_CCM_CBCMR);
4409
4410         return 0;
4411 }
4412
4413 static unsigned long _clk_gpu3d_shader_get_rate(struct clk *clk)
4414 {
4415         u32 reg, div;
4416
4417         reg = __raw_readl(MXC_CCM_CBCMR);
4418         div = ((reg & MXC_CCM_CBCMR_GPU3D_SHADER_PODF_MASK) >>
4419                         MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET) + 1;
4420
4421         return clk_get_rate(clk->parent) / div;
4422 }
4423
4424 static int _clk_gpu3d_shader_set_rate(struct clk *clk, unsigned long rate)
4425 {
4426         u32 reg, div;
4427         u32 parent_rate = clk_get_rate(clk->parent);
4428
4429         div = parent_rate / rate;
4430         if (div == 0)
4431                 div++;
4432         if (div > 8)
4433                 div = 8;
4434
4435         reg = __raw_readl(MXC_CCM_CBCMR);
4436         reg &= ~MXC_CCM_CBCMR_GPU3D_SHADER_PODF_MASK;
4437         reg |= (div - 1) << MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET;
4438         __raw_writel(reg, MXC_CCM_CBCMR);
4439
4440         return 0;
4441 }
4442
4443
4444 static struct clk gpu3d_shader_clk = {
4445         __INIT_CLK_DEBUG(gpu3d_shader_clk)
4446         .parent = &pll3_pfd_720M,
4447         .secondary = &mmdc_ch0_axi_clk[0],
4448         .enable = _clk_enable,
4449         .enable_reg = MXC_CCM_CCGR1,
4450         .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
4451         .disable = _clk_disable,
4452         .set_parent = _clk_gpu3d_shader_set_parent,
4453         .set_rate = _clk_gpu3d_shader_set_rate,
4454         .get_rate = _clk_gpu3d_shader_get_rate,
4455         .round_rate = _clk_gpu3d_shader_round_rate,
4456         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
4457 };
4458
4459 /* set the parent by the ipcg table */
4460 static struct clk gpmi_nand_clk[] = {
4461         {       /* gpmi_io_clk */
4462         __INIT_CLK_DEBUG(gpmi_io_clk)
4463         .parent = &enfc_clk,
4464         .secondary = &gpmi_nand_clk[1],
4465         .enable = _clk_enable,
4466         .enable_reg = MXC_CCM_CCGR4,
4467         .enable_shift = MXC_CCM_CCGRx_CG14_OFFSET,
4468         .disable = _clk_disable,
4469         },
4470         {       /* gpmi_apb_clk */
4471         __INIT_CLK_DEBUG(gpmi_apb_clk)
4472         .parent = &usdhc3_clk,
4473         .secondary = &gpmi_nand_clk[2],
4474         .enable = _clk_enable,
4475         .enable_reg = MXC_CCM_CCGR4,
4476         .enable_shift = MXC_CCM_CCGRx_CG15_OFFSET,
4477         .disable = _clk_disable,
4478         },
4479         {       /* bch_clk */
4480         __INIT_CLK_DEBUG(gpmi_bch_clk)
4481         .parent = &usdhc4_clk,
4482         .secondary = &gpmi_nand_clk[3],
4483         .enable = _clk_enable,
4484         .enable_reg = MXC_CCM_CCGR4,
4485         .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
4486         .disable = _clk_disable,
4487         },
4488         {       /* bch_apb_clk */
4489         __INIT_CLK_DEBUG(gpmi_bch_apb_clk)
4490         .parent = &usdhc3_clk,
4491         .secondary = &gpmi_nand_clk[4],
4492         .enable = _clk_enable,
4493         .enable_reg = MXC_CCM_CCGR4,
4494         .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET,
4495         .disable = _clk_disable,
4496         },
4497         {       /* bch relative clk */
4498         __INIT_CLK_DEBUG(pl301_mx6qperl_bch)
4499         .parent = &mx6per1_clk,
4500         .secondary = &mmdc_ch0_axi_clk[0],
4501         },
4502 };
4503
4504 static struct clk pwm_clk[] = {
4505         {
4506         __INIT_CLK_DEBUG(pwm_clk_0)
4507          .parent = &ipg_perclk,
4508          .id = 0,
4509          .enable_reg = MXC_CCM_CCGR4,
4510          .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET,
4511          .enable = _clk_enable,
4512          .disable = _clk_disable,
4513          },
4514         {
4515         __INIT_CLK_DEBUG(pwm_clk_1)
4516          .parent = &ipg_perclk,
4517          .id = 1,
4518          .enable_reg = MXC_CCM_CCGR4,
4519          .enable_shift = MXC_CCM_CCGRx_CG9_OFFSET,
4520          .enable = _clk_enable,
4521          .disable = _clk_disable,
4522          },
4523         {
4524         __INIT_CLK_DEBUG(pwm_clk_2)
4525          .parent = &ipg_perclk,
4526          .id = 2,
4527          .enable_reg = MXC_CCM_CCGR4,
4528          .enable_shift = MXC_CCM_CCGRx_CG10_OFFSET,
4529          .enable = _clk_enable,
4530          .disable = _clk_disable,
4531          },
4532         {
4533         __INIT_CLK_DEBUG(pwm_clk_3)
4534          .parent = &ipg_perclk,
4535          .id = 3,
4536          .enable_reg = MXC_CCM_CCGR4,
4537          .enable_shift = MXC_CCM_CCGRx_CG11_OFFSET,
4538          .enable = _clk_enable,
4539          .disable = _clk_disable,
4540          },
4541 };
4542
4543 static int _clk_pcie_enable(struct clk *clk)
4544 {
4545         unsigned int reg;
4546
4547         /* Clear Power Down and Enable PLLs */
4548         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
4549         reg &= ~ANADIG_PLL_ENET_POWER_DOWN;
4550         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
4551
4552         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
4553         reg |= ANADIG_PLL_ENET_EN;
4554         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
4555
4556         /* Waiting for the PLL is locked */
4557         if (!WAIT(ANADIG_PLL_ENET_LOCK & __raw_readl(PLL8_ENET_BASE_ADDR),
4558                                 SPIN_DELAY))
4559                 panic("pll8 lock failed\n");
4560
4561         /* Disable the bypass */
4562         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
4563         reg &= ~ANADIG_PLL_ENET_BYPASS;
4564         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
4565
4566         /*
4567          * Enable SATA ref clock.
4568          * PCIe needs both sides to have the same source of refernce clock,
4569          * The SATA reference clock is taken out on clk out
4570          */
4571         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
4572         reg |= ANADIG_PLL_ENET_EN_SATA;
4573         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
4574
4575         /* Activate LVDS CLK1 (the MiniPCIe slot clock input) */
4576         reg = __raw_readl(ANADIG_MISC1_REG);
4577         reg &= ~ANATOP_LVDS_CLK1_IBEN_MASK;
4578         __raw_writel(reg, ANADIG_MISC1_REG);
4579
4580         reg = __raw_readl(ANADIG_MISC1_REG);
4581         reg |= ANATOP_LVDS_CLK1_SRC_SATA;
4582         __raw_writel(reg, ANADIG_MISC1_REG);
4583
4584         reg = __raw_readl(ANADIG_MISC1_REG);
4585         reg |= ANATOP_LVDS_CLK1_OBEN_MASK;
4586         __raw_writel(reg, ANADIG_MISC1_REG);
4587
4588         /* Enable PCIE ref clock */
4589         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
4590         reg |= ANADIG_PLL_ENET_EN_PCIE;
4591         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
4592
4593         _clk_enable(clk);
4594
4595         return 0;
4596 }
4597
4598 static void _clk_pcie_disable(struct clk *clk)
4599 {
4600         unsigned int reg;
4601
4602         _clk_disable(clk);
4603
4604         /* Disable SATA ref clock */
4605         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
4606         reg &= ~ANADIG_PLL_ENET_EN_PCIE;
4607         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
4608 }
4609
4610 static struct clk pcie_clk[] = {
4611         {
4612         __INIT_CLK_DEBUG(pcie_clk)
4613         .parent = &pcie_axi_clk,
4614         .enable = _clk_pcie_enable,
4615         .disable = _clk_pcie_disable,
4616         .enable_reg = MXC_CCM_CCGR4,
4617         .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET,
4618         .secondary = &pcie_clk[1],
4619         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
4620         },
4621         {
4622         .parent = &mmdc_ch0_axi_clk[0],
4623         .secondary = &mx6fast1_clk,
4624         },
4625 };
4626
4627 static int _clk_sata_enable(struct clk *clk)
4628 {
4629         unsigned int reg;
4630
4631         /* Clear Power Down and Enable PLLs */
4632         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
4633         reg &= ~ANADIG_PLL_ENET_POWER_DOWN;
4634         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
4635
4636         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
4637         reg |= ANADIG_PLL_ENET_EN;
4638         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
4639
4640         /* Waiting for the PLL is locked */
4641         if (!WAIT(ANADIG_PLL_ENET_LOCK & __raw_readl(PLL8_ENET_BASE_ADDR),
4642                                 SPIN_DELAY))
4643                 panic("pll8 lock failed\n");
4644
4645         /* Disable the bypass */
4646         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
4647         reg &= ~ANADIG_PLL_ENET_BYPASS;
4648         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
4649
4650         /* Enable SATA ref clock */
4651         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
4652         reg |= ANADIG_PLL_ENET_EN_SATA;
4653         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
4654
4655         _clk_enable(clk);
4656
4657         return 0;
4658 }
4659
4660 static void _clk_sata_disable(struct clk *clk)
4661 {
4662         unsigned int reg;
4663
4664         _clk_disable(clk);
4665
4666         /* Disable SATA ref clock */
4667         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
4668         reg &= ~ANADIG_PLL_ENET_EN_SATA;
4669         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
4670 }
4671
4672 static struct clk sata_clk[] = {
4673         {
4674         __INIT_CLK_DEBUG(sata_clk)
4675         .parent = &ipg_clk,
4676         .enable = _clk_sata_enable,
4677         .enable_reg = MXC_CCM_CCGR5,
4678         .enable_shift = MXC_CCM_CCGRx_CG2_OFFSET,
4679         .disable = _clk_sata_disable,
4680         .secondary = &sata_clk[1],
4681         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
4682         },
4683         {
4684         .parent = &mmdc_ch0_axi_clk[0],
4685         .secondary = &mx6per1_clk,
4686         }
4687 };
4688
4689 static struct clk usboh3_clk[] = {
4690         {
4691         __INIT_CLK_DEBUG(usboh3_clk)
4692         .parent = &ahb_clk,
4693         .enable = _clk_enable,
4694         .enable_reg = MXC_CCM_CCGR6,
4695         .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET,
4696         .disable = _clk_disable,
4697         .secondary = &usboh3_clk[1],
4698         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
4699         },
4700         {
4701         .parent = &mmdc_ch0_axi_clk[0],
4702         .secondary = &mx6per1_clk,
4703         },
4704 };
4705
4706 static struct clk mlb150_clk = {
4707         __INIT_CLK_DEBUG(mlb150_clk)
4708         .id = 0,
4709         .parent = &ipg_clk,
4710         .enable_reg = MXC_CCM_CCGR3,
4711         .enable_shift = MXC_CCM_CCGRx_CG9_OFFSET,
4712         .enable = _clk_enable,
4713         .disable = _clk_disable,
4714 };
4715
4716 static int _clk_enable1(struct clk *clk)
4717 {
4718         u32 reg;
4719         reg = __raw_readl(clk->enable_reg);
4720         reg |= 1 << clk->enable_shift;
4721         __raw_writel(reg, clk->enable_reg);
4722
4723         return 0;
4724 }
4725
4726 static void _clk_disable1(struct clk *clk)
4727 {
4728         u32 reg;
4729         reg = __raw_readl(clk->enable_reg);
4730         reg &= ~(1 << clk->enable_shift);
4731         __raw_writel(reg, clk->enable_reg);
4732 }
4733
4734 static int _clk_clko_set_parent(struct clk *clk, struct clk *parent)
4735 {
4736         u32 sel, reg;
4737
4738         if (parent == &pll3_usb_otg_main_clk)
4739                 sel = 0;
4740         else if (parent == &pll2_528_bus_main_clk)
4741                 sel = 1;
4742         else if (parent == &pll1_sys_main_clk)
4743                 sel = 2;
4744         else if (parent == &pll5_video_main_clk)
4745                 sel = 3;
4746         else if (parent == &axi_clk)
4747                 sel = 5;
4748         else if (parent == &enfc_clk)
4749                 sel = 6;
4750         else if (parent == &ipu1_di_clk[0])
4751                 sel = 7;
4752         else if (parent == &ipu1_di_clk[1])
4753                 sel = 8;
4754         else if (parent == &ipu2_di_clk[0])
4755                 sel = 9;
4756         else if (parent == &ipu2_di_clk[1])
4757                 sel = 10;
4758         else if (parent == &ahb_clk)
4759                 sel = 11;
4760         else if (parent == &ipg_clk)
4761                 sel = 12;
4762         else if (parent == &ipg_perclk)
4763                 sel = 13;
4764         else if (parent == &ckil_clk)
4765                 sel = 14;
4766         else if (parent == &pll4_audio_main_clk)
4767                 sel = 15;
4768         else
4769                 return -EINVAL;
4770
4771         reg = __raw_readl(MXC_CCM_CCOSR);
4772         reg &= ~MXC_CCM_CCOSR_CKOL_SEL_MASK;
4773         reg |= sel << MXC_CCM_CCOSR_CKOL_SEL_OFFSET;
4774         __raw_writel(reg, MXC_CCM_CCOSR);
4775         return 0;
4776 }
4777
4778 static unsigned long _clk_clko_get_rate(struct clk *clk)
4779 {
4780         u32 reg = __raw_readl(MXC_CCM_CCOSR);
4781         u32 div = ((reg & MXC_CCM_CCOSR_CKOL_DIV_MASK) >>
4782                         MXC_CCM_CCOSR_CKOL_DIV_OFFSET) + 1;
4783         return clk_get_rate(clk->parent) / div;
4784 }
4785
4786 static int _clk_clko_set_rate(struct clk *clk, unsigned long rate)
4787 {
4788         u32 reg;
4789         u32 parent_rate = clk_get_rate(clk->parent);
4790         u32 div = parent_rate / rate;
4791
4792         if (div == 0)
4793                 div++;
4794         if (((parent_rate / div) != rate) || (div > 8))
4795                 return -EINVAL;
4796
4797         reg = __raw_readl(MXC_CCM_CCOSR);
4798         reg &= ~MXC_CCM_CCOSR_CKOL_DIV_MASK;
4799         reg |= (div - 1) << MXC_CCM_CCOSR_CKOL_DIV_OFFSET;
4800         __raw_writel(reg, MXC_CCM_CCOSR);
4801         return 0;
4802 }
4803
4804 static unsigned long _clk_clko_round_rate(struct clk *clk,
4805                                                 unsigned long rate)
4806 {
4807         u32 parent_rate = clk_get_rate(clk->parent);
4808         u32 div = parent_rate / rate;
4809
4810         /* Make sure rate is not greater than the maximum value for the clock.
4811          * Also prevent a div of 0.
4812          */
4813         if (div == 0)
4814                 div++;
4815         if (div > 8)
4816                 div = 8;
4817         return parent_rate / div;
4818 }
4819
4820 static int _clk_clko2_set_parent(struct clk *clk, struct clk *parent)
4821 {
4822         u32 sel, reg;
4823
4824         if (parent == &mmdc_ch0_axi_clk[0])
4825                 sel = 0;
4826         else if (parent == &mmdc_ch1_axi_clk[0])
4827                 sel = 1;
4828         else if (parent == &usdhc4_clk)
4829                 sel = 2;
4830         else if (parent == &usdhc1_clk)
4831                 sel = 3;
4832         else if (parent == &gpu2d_axi_clk)
4833                 sel = 4;
4834         else if (parent == &ecspi_clk[0])
4835                 sel = 6;
4836         else if (parent == &gpu3d_axi_clk)
4837                 sel = 7;
4838         else if (parent == &usdhc3_clk)
4839                 sel = 8;
4840         else if (parent == &pcie_clk[0])
4841                 sel = 9;
4842         else if (parent == &ipu1_clk)
4843                 sel = 11;
4844         else if (parent == &ipu2_clk)
4845                 sel = 12;
4846         else if (parent == &vdo_axi_clk)
4847                 sel = 13;
4848         else if (parent == &osc_clk)
4849                 sel = 14;
4850         else if (parent == &gpu2d_core_clk[0])
4851                 sel = 15;
4852         else if (parent == &gpu3d_core_clk[0])
4853                 sel = 16;
4854         else if (parent == &usdhc2_clk)
4855                 sel = 17;
4856         else if (parent == &ssi1_clk)
4857                 sel = 18;
4858         else if (parent == &ssi2_clk)
4859                 sel = 19;
4860         else if (parent == &ssi3_clk)
4861                 sel = 20;
4862         else if (parent == &gpu3d_shader_clk)
4863                 sel = 21;
4864         else if (parent == &can_clk_root)
4865                 sel = 23;
4866         else if (parent == &ldb_di0_clk)
4867                 sel = 24;
4868         else if (parent == &ldb_di1_clk)
4869                 sel = 25;
4870         else if (parent == &esai_clk)
4871                 sel = 26;
4872         else if (parent == &uart_clk[0])
4873                 sel = 28;
4874         else if (parent == &spdif0_clk[0])
4875                 sel = 29;
4876         else if (parent == &hsi_tx_clk[0])
4877                 sel = 31;
4878         else
4879                 return -EINVAL;
4880
4881         reg = __raw_readl(MXC_CCM_CCOSR);
4882         reg &= ~MXC_CCM_CCOSR_CKO2_SEL_MASK;
4883         reg |= sel << MXC_CCM_CCOSR_CKO2_SEL_OFFSET;
4884         __raw_writel(reg, MXC_CCM_CCOSR);
4885         return 0;
4886 }
4887
4888 static unsigned long _clk_clko2_get_rate(struct clk *clk)
4889 {
4890         u32 reg = __raw_readl(MXC_CCM_CCOSR);
4891         u32 div = ((reg & MXC_CCM_CCOSR_CKO2_DIV_MASK) >>
4892                         MXC_CCM_CCOSR_CKO2_DIV_OFFSET) + 1;
4893         return clk_get_rate(clk->parent) / div;
4894 }
4895
4896 static int _clk_clko2_set_rate(struct clk *clk, unsigned long rate)
4897 {
4898         u32 reg;
4899         u32 parent_rate = clk_get_rate(clk->parent);
4900         u32 div = parent_rate / rate;
4901
4902         if (div == 0)
4903                 div++;
4904         if (((parent_rate / div) != rate) || (div > 8))
4905                 return -EINVAL;
4906
4907         reg = __raw_readl(MXC_CCM_CCOSR);
4908         reg &= ~MXC_CCM_CCOSR_CKO2_DIV_MASK;
4909         reg |= (div - 1) << MXC_CCM_CCOSR_CKO2_DIV_OFFSET;
4910         __raw_writel(reg, MXC_CCM_CCOSR);
4911         return 0;
4912 }
4913
4914 static struct clk clko_clk = {
4915         __INIT_CLK_DEBUG(clko_clk)
4916         .parent = &pll2_528_bus_main_clk,
4917         .enable = _clk_enable1,
4918         .enable_reg = MXC_CCM_CCOSR,
4919         .enable_shift = MXC_CCM_CCOSR_CKOL_EN_OFFSET,
4920         .disable = _clk_disable1,
4921         .set_parent = _clk_clko_set_parent,
4922         .set_rate = _clk_clko_set_rate,
4923         .get_rate = _clk_clko_get_rate,
4924         .round_rate = _clk_clko_round_rate,
4925 };
4926
4927 static struct clk clko2_clk = {
4928         __INIT_CLK_DEBUG(clko2_clk)
4929         .parent = &usdhc4_clk,
4930         .enable = _clk_enable1,
4931         .enable_reg = MXC_CCM_CCOSR,
4932         .enable_shift = MXC_CCM_CCOSR_CKO2_EN_OFFSET,
4933         .disable = _clk_disable1,
4934         .set_parent = _clk_clko2_set_parent,
4935         .set_rate = _clk_clko2_set_rate,
4936         .get_rate = _clk_clko2_get_rate,
4937         .round_rate = _clk_clko_round_rate,
4938 };
4939
4940 static struct clk perfmon0_clk = {
4941         __INIT_CLK_DEBUG(perfmon0_clk)
4942         .parent = &mmdc_ch0_axi_clk[0],
4943         .enable = _clk_enable1,
4944         .enable_reg = MXC_CCM_CCGR4,
4945         .enable_shift = MXC_CCM_CCGRx_CG1_OFFSET,
4946         .disable = _clk_disable1,
4947 };
4948
4949 static struct clk perfmon1_clk = {
4950         __INIT_CLK_DEBUG(perfmon1_clk)
4951         .parent = &ipu1_clk,
4952         .enable = _clk_enable1,
4953         .enable_reg = MXC_CCM_CCGR4,
4954         .enable_shift = MXC_CCM_CCGRx_CG2_OFFSET,
4955         .disable = _clk_disable1,
4956 };
4957
4958 static struct clk perfmon2_clk = {
4959         __INIT_CLK_DEBUG(perfmon2_clk)
4960         .parent = &mmdc_ch0_axi_clk[0],
4961         .enable = _clk_enable1,
4962         .enable_reg = MXC_CCM_CCGR4,
4963         .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET,
4964         .disable = _clk_disable1,
4965 };
4966
4967 static struct clk dummy_clk = {
4968         .id = 0,
4969 };
4970
4971 #define _REGISTER_CLOCK(d, n, c) \
4972         { \
4973                 .dev_id = d, \
4974                 .con_id = n, \
4975                 .clk = &c, \
4976         }
4977
4978
4979 static struct clk_lookup lookups[] = {
4980         _REGISTER_CLOCK(NULL, "osc", osc_clk),
4981         _REGISTER_CLOCK(NULL, "ckih", ckih_clk),
4982         _REGISTER_CLOCK(NULL, "ckih2", ckih2_clk),
4983         _REGISTER_CLOCK(NULL, "ckil", ckil_clk),
4984         _REGISTER_CLOCK(NULL, "pll1_main_clk", pll1_sys_main_clk),
4985         _REGISTER_CLOCK(NULL, "pll1_sw_clk", pll1_sw_clk),
4986         _REGISTER_CLOCK(NULL, "pll2", pll2_528_bus_main_clk),
4987         _REGISTER_CLOCK(NULL, "pll2_pfd_400M", pll2_pfd_400M),
4988         _REGISTER_CLOCK(NULL, "pll2_pfd_352M", pll2_pfd_352M),
4989         _REGISTER_CLOCK(NULL, "pll2_pfd_594M", pll2_pfd_594M),
4990         _REGISTER_CLOCK(NULL, "pll2_200M", pll2_200M),
4991         _REGISTER_CLOCK(NULL, "pll3_main_clk", pll3_usb_otg_main_clk),
4992         _REGISTER_CLOCK(NULL, "pll3_pfd_508M", pll3_pfd_508M),
4993         _REGISTER_CLOCK(NULL, "pll3_pfd_454M", pll3_pfd_454M),
4994         _REGISTER_CLOCK(NULL, "pll3_pfd_720M", pll3_pfd_720M),
4995         _REGISTER_CLOCK(NULL, "pll3_pfd_540M", pll3_pfd_540M),
4996         _REGISTER_CLOCK(NULL, "pll3_sw_clk", pll3_sw_clk),
4997         _REGISTER_CLOCK(NULL, "pll3_120M", pll3_120M),
4998         _REGISTER_CLOCK(NULL, "pll3_120M", pll3_80M),
4999         _REGISTER_CLOCK(NULL, "pll3_120M", pll3_60M),
5000         _REGISTER_CLOCK(NULL, "pll4", pll4_audio_main_clk),
5001         _REGISTER_CLOCK(NULL, "pll5", pll5_video_main_clk),
5002         _REGISTER_CLOCK(NULL, "pll6", pll6_mlb150_main_clk),
5003         _REGISTER_CLOCK(NULL, "pll3", pll7_usb_host_main_clk),
5004         _REGISTER_CLOCK(NULL, "pll4", pll8_enet_main_clk),
5005         _REGISTER_CLOCK(NULL, "cpu_clk", cpu_clk),
5006         _REGISTER_CLOCK("smp_twd", NULL, twd_clk),
5007         _REGISTER_CLOCK(NULL, "periph_clk", periph_clk),
5008         _REGISTER_CLOCK(NULL, "axi_clk", axi_clk),
5009         _REGISTER_CLOCK(NULL, "mmdc_ch0_axi", mmdc_ch0_axi_clk[0]),
5010         _REGISTER_CLOCK(NULL, "mmdc_ch1_axi", mmdc_ch1_axi_clk[0]),
5011         _REGISTER_CLOCK(NULL, "ahb", ahb_clk),
5012         _REGISTER_CLOCK(NULL, "ipg_clk", ipg_clk),
5013         _REGISTER_CLOCK(NULL, "ipg_perclk", ipg_perclk),
5014         _REGISTER_CLOCK(NULL, "spba", spba_clk),
5015         _REGISTER_CLOCK("imx-sdma", NULL, sdma_clk[0]),
5016         _REGISTER_CLOCK(NULL, "gpu2d_axi_clk", gpu2d_axi_clk),
5017         _REGISTER_CLOCK(NULL, "gpu3d_axi_clk", gpu3d_axi_clk),
5018         _REGISTER_CLOCK(NULL, "pcie_axi_clk", pcie_axi_clk),
5019         _REGISTER_CLOCK(NULL, "vdo_axi_clk", vdo_axi_clk),
5020         _REGISTER_CLOCK(NULL, "iim_clk", iim_clk),
5021         _REGISTER_CLOCK(NULL, "i2c_clk", i2c_clk[0]),
5022         _REGISTER_CLOCK("imx-i2c.1", NULL, i2c_clk[1]),
5023         _REGISTER_CLOCK("imx-i2c.2", NULL, i2c_clk[2]),
5024         _REGISTER_CLOCK(NULL, "vpu_clk", vpu_clk[0]),
5025         _REGISTER_CLOCK(NULL, "ipu1_clk", ipu1_clk),
5026         _REGISTER_CLOCK(NULL, "ipu2_clk", ipu2_clk),
5027         _REGISTER_CLOCK("sdhci-esdhc-imx.0", NULL, usdhc1_clk),
5028         _REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL, usdhc2_clk),
5029         _REGISTER_CLOCK("sdhci-esdhc-imx.2", NULL, usdhc3_clk),
5030         _REGISTER_CLOCK("sdhci-esdhc-imx.3", NULL, usdhc4_clk),
5031         _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk),
5032         _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk),
5033         _REGISTER_CLOCK("imx-ssi.2", NULL, ssi3_clk),
5034         _REGISTER_CLOCK(NULL, "ipu1_di0_clk", ipu1_di_clk[0]),
5035         _REGISTER_CLOCK(NULL, "ipu1_di1_clk", ipu1_di_clk[1]),
5036         _REGISTER_CLOCK(NULL, "ipu2_di0_clk", ipu2_di_clk[0]),
5037         _REGISTER_CLOCK(NULL, "ipu2_di1_clk", ipu2_di_clk[1]),
5038         _REGISTER_CLOCK(NULL, "can_root_clk", can_clk_root),
5039         _REGISTER_CLOCK("imx6q-flexcan.0", NULL, can1_clk[0]),
5040         _REGISTER_CLOCK("imx6q-flexcan.1", NULL, can2_clk[0]),
5041         _REGISTER_CLOCK(NULL, "ldb_di0_clk", ldb_di0_clk),
5042         _REGISTER_CLOCK(NULL, "ldb_di1_clk", ldb_di1_clk),
5043         _REGISTER_CLOCK("mxc_spdif.0", NULL, spdif0_clk[0]),
5044         _REGISTER_CLOCK(NULL, "esai_clk", esai_clk),
5045         _REGISTER_CLOCK("imx6q-ecspi.0", NULL, ecspi_clk[0]),
5046         _REGISTER_CLOCK("imx6q-ecspi.1", NULL, ecspi_clk[1]),
5047         _REGISTER_CLOCK("imx6q-ecspi.2", NULL, ecspi_clk[2]),
5048         _REGISTER_CLOCK("imx6q-ecspi.3", NULL, ecspi_clk[3]),
5049         _REGISTER_CLOCK("imx6q-ecspi.4", NULL, ecspi_clk[4]),
5050         _REGISTER_CLOCK(NULL, "emi_slow_clk", emi_slow_clk),
5051         _REGISTER_CLOCK(NULL, "emi_clk", emi_clk),
5052         _REGISTER_CLOCK(NULL, "enfc_clk", enfc_clk),
5053         _REGISTER_CLOCK("imx-uart.0", NULL, uart_clk[0]),
5054         _REGISTER_CLOCK("imx-uart.1", NULL, uart_clk[0]),
5055         _REGISTER_CLOCK("imx-uart.2", NULL, uart_clk[0]),
5056         _REGISTER_CLOCK("imx-uart.3", NULL, uart_clk[0]),
5057         _REGISTER_CLOCK(NULL, "hsi_tx", hsi_tx_clk[0]),
5058         _REGISTER_CLOCK(NULL, "caam_clk", caam_clk[0]),
5059         _REGISTER_CLOCK(NULL, "asrc_clk", asrc_clk[0]),
5060         _REGISTER_CLOCK(NULL, "asrc_serial_clk", asrc_clk[1]),
5061         _REGISTER_CLOCK("mxs-dma-apbh", NULL, apbh_dma_clk),
5062         _REGISTER_CLOCK(NULL, "openvg_axi_clk", openvg_axi_clk),
5063         _REGISTER_CLOCK(NULL, "gpu3d_clk", gpu3d_core_clk[0]),
5064         _REGISTER_CLOCK(NULL, "gpu2d_clk", gpu2d_core_clk[0]),
5065         _REGISTER_CLOCK(NULL, "gpu3d_shader_clk", gpu3d_shader_clk),
5066         _REGISTER_CLOCK(NULL, "gpt", gpt_clk[0]),
5067         _REGISTER_CLOCK("imx6q-gpmi-nand.0", NULL, gpmi_nand_clk[0]),
5068         _REGISTER_CLOCK(NULL, "gpmi-apb", gpmi_nand_clk[1]),
5069         _REGISTER_CLOCK(NULL, "bch", gpmi_nand_clk[2]),
5070         _REGISTER_CLOCK(NULL, "bch-apb", gpmi_nand_clk[3]),
5071         _REGISTER_CLOCK(NULL, "pl301_mx6qperl-bch", gpmi_nand_clk[4]),
5072         _REGISTER_CLOCK("mxc_pwm.0", NULL, pwm_clk[0]),
5073         _REGISTER_CLOCK("mxc_pwm.1", NULL, pwm_clk[1]),
5074         _REGISTER_CLOCK("mxc_pwm.2", NULL, pwm_clk[2]),
5075         _REGISTER_CLOCK("mxc_pwm.3", NULL, pwm_clk[3]),
5076         _REGISTER_CLOCK(NULL, "pcie_clk", pcie_clk[0]),
5077         _REGISTER_CLOCK("fec.0", NULL, enet_clk[0]),
5078         _REGISTER_CLOCK(NULL, "imx_sata_clk", sata_clk[0]),
5079         _REGISTER_CLOCK(NULL, "usboh3_clk", usboh3_clk[0]),
5080         _REGISTER_CLOCK(NULL, "usb_phy1_clk", usb_phy1_clk),
5081         _REGISTER_CLOCK(NULL, "usb_phy3_clk", usb_phy3_clk),
5082         _REGISTER_CLOCK(NULL, "usb_phy4_clk", usb_phy4_clk),
5083         _REGISTER_CLOCK("imx2-wdt.0", NULL, dummy_clk),
5084         _REGISTER_CLOCK("imx2-wdt.1", NULL, dummy_clk),
5085         _REGISTER_CLOCK(NULL, "hdmi_isfr_clk", hdmi_clk[0]),
5086         _REGISTER_CLOCK(NULL, "hdmi_iahb_clk", hdmi_clk[1]),
5087         _REGISTER_CLOCK(NULL, "mipi_pllref_clk", mipi_pllref_clk),
5088         _REGISTER_CLOCK(NULL, NULL, vdoa_clk),
5089         _REGISTER_CLOCK(NULL, NULL, aips_tz2_clk),
5090         _REGISTER_CLOCK(NULL, NULL, aips_tz1_clk),
5091         _REGISTER_CLOCK(NULL, "clko_clk", clko_clk),
5092         _REGISTER_CLOCK(NULL, "clko2_clk", clko2_clk),
5093         _REGISTER_CLOCK(NULL, "pxp_axi", ipu2_clk),
5094         _REGISTER_CLOCK(NULL, "epdc_axi", ipu2_clk),
5095         _REGISTER_CLOCK(NULL, "epdc_pix", ipu2_di_clk[1]),
5096         _REGISTER_CLOCK("mxs-perfmon.0", "perfmon", perfmon0_clk),
5097         _REGISTER_CLOCK("mxs-perfmon.1", "perfmon", perfmon1_clk),
5098         _REGISTER_CLOCK("mxs-perfmon.2", "perfmon", perfmon2_clk),
5099         _REGISTER_CLOCK(NULL, "mlb150_clk", mlb150_clk),
5100         _REGISTER_CLOCK(NULL, "anaclk_1", anaclk_1),
5101         _REGISTER_CLOCK(NULL, "anaclk_2", anaclk_2),
5102 };
5103
5104 static void clk_tree_init(void)
5105
5106 {
5107         unsigned int reg;
5108
5109         reg = __raw_readl(MMDC_MDMISC_OFFSET);
5110         if ((reg & MMDC_MDMISC_DDR_TYPE_MASK) ==
5111                 (0x1 << MMDC_MDMISC_DDR_TYPE_OFFSET) ||
5112                 cpu_is_mx6dl()) {
5113                 clk_set_parent(&periph_clk, &pll2_pfd_400M);
5114                 printk(KERN_INFO "Set periph_clk's parent to pll2_pfd_400M!\n");
5115         }
5116 }
5117
5118
5119 int __init mx6_clocks_init(unsigned long ckil, unsigned long osc,
5120         unsigned long ckih1, unsigned long ckih2)
5121 {
5122         __iomem void *base;
5123         int i;
5124
5125         external_low_reference = ckil;
5126         external_high_reference = ckih1;
5127         ckih2_reference = ckih2;
5128         oscillator_reference = osc;
5129
5130         apll_base = ioremap(ANATOP_BASE_ADDR, SZ_4K);
5131
5132         for (i = 0; i < ARRAY_SIZE(lookups); i++) {
5133                 clkdev_add(&lookups[i]);
5134                 clk_debug_register(lookups[i].clk);
5135         }
5136
5137         /* Disable un-necessary PFDs & PLLs */
5138
5139         /* keep correct count. */
5140         clk_enable(&cpu_clk);
5141         clk_enable(&periph_clk);
5142
5143         clk_tree_init();
5144
5145         if (pll2_pfd_400M.usecount == 0 && cpu_is_mx6q())
5146                 pll2_pfd_400M.disable(&pll2_pfd_400M);
5147         pll2_pfd_352M.disable(&pll2_pfd_352M);
5148         pll2_pfd_594M.disable(&pll2_pfd_594M);
5149
5150 #if !defined(CONFIG_FEC_1588)
5151         pll3_pfd_454M.disable(&pll3_pfd_454M);
5152         pll3_pfd_508M.disable(&pll3_pfd_508M);
5153         pll3_pfd_540M.disable(&pll3_pfd_540M);
5154         pll3_pfd_720M.disable(&pll3_pfd_720M);
5155
5156         pll3_usb_otg_main_clk.disable(&pll3_usb_otg_main_clk);
5157 #endif
5158         pll4_audio_main_clk.disable(&pll4_audio_main_clk);
5159         pll5_video_main_clk.disable(&pll5_video_main_clk);
5160         pll6_mlb150_main_clk.disable(&pll6_mlb150_main_clk);
5161         pll7_usb_host_main_clk.disable(&pll7_usb_host_main_clk);
5162         pll8_enet_main_clk.disable(&pll8_enet_main_clk);
5163
5164         sata_clk[0].disable(&sata_clk[0]);
5165         pcie_clk[0].disable(&pcie_clk[0]);
5166
5167         /* Initialize Audio and Video PLLs to valid frequency (650MHz). */
5168         clk_set_rate(&pll4_audio_main_clk, 650000000);
5169         clk_set_rate(&pll5_video_main_clk, 650000000);
5170
5171         clk_set_parent(&ipu1_di_clk[0], &pll5_video_main_clk);
5172         clk_set_parent(&ipu1_di_clk[1], &pll5_video_main_clk);
5173         clk_set_parent(&ipu2_di_clk[0], &pll5_video_main_clk);
5174         clk_set_parent(&ipu2_di_clk[1], &pll5_video_main_clk);
5175
5176         clk_set_parent(&emi_clk, &pll2_pfd_400M);
5177         clk_set_rate(&emi_clk, 200000000);
5178
5179         clk_set_parent(&gpu3d_shader_clk, &pll2_pfd_594M);
5180         clk_set_rate(&gpu3d_shader_clk, 594000000);
5181         clk_set_parent(&gpu3d_core_clk[0], &mmdc_ch0_axi_clk[0]);
5182         clk_set_rate(&gpu3d_core_clk[0], 528000000);
5183         if (cpu_is_mx6dl()) {
5184                 /*on mx6dl, 2d core clock sources from 3d shader core clock*/
5185                 clk_set_parent(&gpu2d_core_clk[0], &gpu3d_shader_clk);
5186                 /* on mx6dl gpu3d_axi_clk source from mmdc0 directly */
5187                 clk_set_parent(&gpu3d_axi_clk, &mmdc_ch0_axi_clk[0]);
5188                 /* on mx6dl gpu2d_axi_clk source from mmdc0 directly */
5189                 clk_set_parent(&gpu2d_axi_clk, &mmdc_ch0_axi_clk[0]);
5190
5191                 /* set axi_clk parent to pll3_pfd_540M */
5192                 clk_set_parent(&axi_clk, &pll3_pfd_540M);
5193
5194                 /* on mx6dl, max ipu clock is 274M */
5195                 clk_set_parent(&ipu1_clk, &pll3_pfd_540M);
5196                 clk_set_parent(&ldb_di0_clk, &pll2_pfd_352M);
5197                 clk_set_parent(&ldb_di1_clk, &pll2_pfd_352M);
5198         }
5199         if (cpu_is_mx6q())
5200                 clk_set_parent(&gpu2d_core_clk[0], &pll3_usb_otg_main_clk);
5201
5202         /* PCLK camera - J5 */
5203         clk_set_parent(&clko2_clk, &osc_clk);
5204         clk_set_rate(&clko2_clk, 2400000);
5205
5206         clk_set_parent(&clko_clk, &ipg_clk);
5207         /*
5208          * FIXME: asrc needs to use asrc_serial(spdif1) clock to do sample
5209          * rate convertion and this clock frequency can not be too high, set
5210          * it to the minimum value 7.5Mhz to make asrc work properly.
5211          */
5212         clk_set_parent(&asrc_clk[1], &pll3_sw_clk);
5213         clk_set_rate(&asrc_clk[1], 7500000);
5214
5215         /* set the GPMI clock to default frequency : 20MHz */
5216         clk_set_rate(&enfc_clk, enfc_clk.round_rate(&enfc_clk, 20000000));
5217
5218         mx6_cpu_op_init();
5219         cpu_op_tbl = get_cpu_op(&cpu_op_nr);
5220
5221         /* Gate off all possible clocks */
5222         if (mxc_jtag_enabled) {
5223                 __raw_writel(3 << MXC_CCM_CCGRx_CG11_OFFSET |
5224                              3 << MXC_CCM_CCGRx_CG2_OFFSET |
5225                              3 << MXC_CCM_CCGRx_CG1_OFFSET |
5226                              3 << MXC_CCM_CCGRx_CG0_OFFSET, MXC_CCM_CCGR0);
5227         } else {
5228                 __raw_writel(1 << MXC_CCM_CCGRx_CG11_OFFSET |
5229                              3 << MXC_CCM_CCGRx_CG2_OFFSET |
5230                              3 << MXC_CCM_CCGRx_CG1_OFFSET |
5231                              3 << MXC_CCM_CCGRx_CG0_OFFSET, MXC_CCM_CCGR0);
5232         }
5233         __raw_writel(3 << MXC_CCM_CCGRx_CG10_OFFSET, MXC_CCM_CCGR1);
5234         __raw_writel(1 << MXC_CCM_CCGRx_CG12_OFFSET |
5235                      1 << MXC_CCM_CCGRx_CG11_OFFSET |
5236                      3 << MXC_CCM_CCGRx_CG10_OFFSET |
5237                      3 << MXC_CCM_CCGRx_CG9_OFFSET |
5238                      3 << MXC_CCM_CCGRx_CG8_OFFSET, MXC_CCM_CCGR2);
5239         __raw_writel(1 << MXC_CCM_CCGRx_CG14_OFFSET |
5240                      3 << MXC_CCM_CCGRx_CG13_OFFSET |
5241                      3 << MXC_CCM_CCGRx_CG12_OFFSET |
5242                      3 << MXC_CCM_CCGRx_CG11_OFFSET |
5243                      3 << MXC_CCM_CCGRx_CG10_OFFSET, MXC_CCM_CCGR3);
5244         __raw_writel(3 << MXC_CCM_CCGRx_CG7_OFFSET |
5245                         1 << MXC_CCM_CCGRx_CG6_OFFSET |
5246                         1 << MXC_CCM_CCGRx_CG4_OFFSET, MXC_CCM_CCGR4);
5247         __raw_writel(1 << MXC_CCM_CCGRx_CG0_OFFSET, MXC_CCM_CCGR5);
5248
5249         __raw_writel(0, MXC_CCM_CCGR6);
5250
5251         /* Lower the ipg_perclk frequency to 8.25MHz. */
5252         clk_set_rate(&ipg_perclk, 8250000);
5253
5254         /* S/PDIF */
5255         clk_set_parent(&spdif0_clk[0], &pll3_pfd_454M);
5256
5257         /* pxp & epdc */
5258         clk_set_parent(&ipu2_clk, &pll2_pfd_400M);
5259         clk_set_rate(&ipu2_clk, 200000000);
5260
5261         if (mx6q_revision() == IMX_CHIP_REVISION_1_0) {
5262                 gpt_clk[0].parent = &ipg_perclk;
5263                 gpt_clk[0].get_rate = NULL;
5264         } else {
5265                 /* Here we use OSC 24M as GPT's clock source, no need to
5266                 enable gpt serial clock*/
5267                 gpt_clk[0].secondary = NULL;
5268         }
5269
5270         if (cpu_is_mx6dl()) {
5271                 if (epdc_enabled)
5272                         clk_set_parent(&ipu2_di_clk[1], &pll5_video_main_clk);
5273                 else
5274                         clk_set_parent(&ipu2_di_clk[1], &pll3_pfd_540M);
5275         }
5276
5277         base = ioremap(GPT_BASE_ADDR, SZ_4K);
5278         mxc_timer_init(&gpt_clk[0], base, MXC_INT_GPT);
5279
5280         lp_high_freq = 0;
5281         lp_med_freq = 0;
5282
5283         return 0;
5284
5285 }