arch/arm/mach-mx6/clock.c

   1
   2 /*
   3  * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
   4  */
   5
   6 /*
   7  * The code contained herein is licensed under the GNU General Public
   8  * License. You may obtain a copy of the GNU General Public License
   9  * Version 2 or later at the following locations:
  10  *
  11  * http://www.opensource.org/licenses/gpl-license.html
  12  * http://www.gnu.org/copyleft/gpl.html
  13  */
  14
  15 #include <linux/kernel.h>
  16 #include <linux/init.h>
  17 #include <linux/types.h>
  18 #include <linux/time.h>
  19 #include <linux/hrtimer.h>
  20 #include <linux/mm.h>
  21 #include <linux/errno.h>
  22 #include <linux/delay.h>
  23 #include <linux/clk.h>
  24 #include <linux/io.h>
  25 #include <linux/clkdev.h>
  26 #include <asm/div64.h>
  27 #include <mach/hardware.h>
  28 #include <mach/common.h>
  29 #include <mach/clock.h>
  30 #include <mach/mxc_dvfs.h>
  31 #include "crm_regs.h"
  32 #include "cpu_op-mx6.h"
  33
  34 #ifdef CONFIG_CLK_DEBUG
  35 #define __INIT_CLK_DEBUG(n)     .name = #n,
  36 #else
  37 #define __INIT_CLK_DEBUG(n)
  38 #endif
  39
  40 extern u32 arm_max_freq;
  41 extern int mxc_jtag_enabled;
  42 extern struct cpu_op *(*get_cpu_op)(int *op);
  43 extern int mx6_set_cpu_voltage(u32 cpu_volt);
  44
  45 extern int lp_high_freq;
  46 extern int lp_med_freq;
  47
  48 void __iomem *apll_base;
  49 static struct clk pll1_sys_main_clk;
  50 static struct clk pll2_528_bus_main_clk;
  51 static struct clk pll2_pfd_400M;
  52 static struct clk pll3_usb_otg_main_clk;
  53 static struct clk pll4_audio_main_clk;
  54 static struct clk pll5_video_main_clk;
  55 static struct clk pll6_MLB_main_clk;
  56 static struct clk pll7_usb_host_main_clk;
  57 static struct clk pll8_enet_main_clk;
  58 static struct clk apbh_dma_clk;
  59 static struct clk openvg_axi_clk;
  60 static struct clk enfc_clk;
  61 static struct clk ipu1_di_clk_root;
  62 static struct clk ipu2_di_clk_root;
  63 static struct clk usdhc3_clk;
  64
  65 static struct cpu_op *cpu_op_tbl;
  66 static int cpu_op_nr;
  67
  68 #define SPIN_DELAY      1200000 /* in nanoseconds */
  69
  70 #define AUDIO_VIDEO_MIN_CLK_FREQ        650000000
  71 #define AUDIO_VIDEO_MAX_CLK_FREQ        1300000000
  72
  73 #define WAIT(exp, timeout) \
  74 ({ \
  75         struct timespec nstimeofday; \
  76         struct timespec curtime; \
  77         int result = 1; \
  78         getnstimeofday(&nstimeofday); \
  79         while (!(exp)) { \
  80                 getnstimeofday(&curtime); \
  81                 if ((curtime.tv_nsec - nstimeofday.tv_nsec) > (timeout)) { \
  82                         result = 0; \
  83                         break; \
  84                 } \
  85         } \
  86         result; \
  87 })
  88
  89 /* External clock values passed-in by the board code */
  90 static unsigned long external_high_reference, external_low_reference;
  91 static unsigned long oscillator_reference, ckih2_reference;
  92
  93 static void __calc_pre_post_dividers(u32 max_podf, u32 div, u32 *pre, u32 *post)
  94 {
  95         u32 min_pre, temp_pre, old_err, err;
  96
  97         /* Some of the podfs are 3 bits while others are 6 bits.
  98           * Handle both cases here.
  99           */
 100         if (div >= 512 && (max_podf == 64)) {
 101                 /* For pre = 3bits and podf = 6 bits, max divider is 512. */
 102                 *pre = 8;
 103                 *post = 64;
 104         } else if (div >= 64 && (max_podf == 8)) {
 105                 /* For pre = 3bits and podf = 3 bits, max divider is 64. */
 106                 *pre = 8;
 107                 *post = 8;
 108         } else if (div >= 8) {
 109                 /* Find the minimum pre-divider for a max podf */
 110                 if (max_podf == 64)
 111                         min_pre = (div - 1) / (1 << 6) + 1;
 112                 else
 113                         min_pre = (div - 1) / (1 << 3) + 1;
 114                 old_err = 8;
 115                 /* Now loop through to find the max pre-divider. */
 116                 for (temp_pre = 8; temp_pre >= min_pre; temp_pre--) {
 117                         err = div % temp_pre;
 118                         if (err == 0) {
 119                                 *pre = temp_pre;
 120                                 break;
 121                         }
 122                         err = temp_pre - err;
 123                         if (err < old_err) {
 124                                 old_err = err;
 125                                 *pre = temp_pre;
 126                         }
 127                 }
 128                 *post = (div + *pre - 1) / *pre;
 129         } else if (div < 8) {
 130                 *pre = div;
 131                 *post = 1;
 132         }
 133 }
 134
 135 static int _clk_enable(struct clk *clk)
 136 {
 137         u32 reg;
 138         reg = __raw_readl(clk->enable_reg);
 139         reg |= MXC_CCM_CCGRx_CG_MASK << clk->enable_shift;
 140         __raw_writel(reg, clk->enable_reg);
 141
 142         if (clk->flags & AHB_HIGH_SET_POINT)
 143                 lp_high_freq++;
 144         else if (clk->flags & AHB_MED_SET_POINT)
 145                 lp_med_freq++;
 146
 147         return 0;
 148 }
 149
 150 static void _clk_disable(struct clk *clk)
 151 {
 152         u32 reg;
 153         reg = __raw_readl(clk->enable_reg);
 154         reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift);
 155         __raw_writel(reg, clk->enable_reg);
 156
 157         if (clk->flags & AHB_HIGH_SET_POINT)
 158                 lp_high_freq--;
 159         else if (clk->flags & AHB_MED_SET_POINT)
 160                 lp_med_freq--;
 161 }
 162
 163 static void _clk_disable_inwait(struct clk *clk)
 164 {
 165         u32 reg;
 166         reg = __raw_readl(clk->enable_reg);
 167         reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift);
 168         reg |= 1 << clk->enable_shift;
 169         __raw_writel(reg, clk->enable_reg);
 170 }
 171
 172 /*
 173  * For the 4-to-1 muxed input clock
 174  */
 175 static inline u32 _get_mux(struct clk *parent, struct clk *m0,
 176                            struct clk *m1, struct clk *m2, struct clk *m3)
 177 {
 178         if (parent == m0)
 179                 return 0;
 180         else if (parent == m1)
 181                 return 1;
 182         else if (parent == m2)
 183                 return 2;
 184         else if (parent == m3)
 185                 return 3;
 186         else
 187                 BUG();
 188
 189         return 0;
 190 }
 191
 192 static inline void __iomem *_get_pll_base(struct clk *pll)
 193 {
 194         if (pll == &pll1_sys_main_clk)
 195                 return PLL1_SYS_BASE_ADDR;
 196         else if (pll == &pll2_528_bus_main_clk)
 197                 return PLL2_528_BASE_ADDR;
 198         else if (pll == &pll3_usb_otg_main_clk)
 199                 return PLL3_480_USB1_BASE_ADDR;
 200         else if (pll == &pll4_audio_main_clk)
 201                 return PLL4_AUDIO_BASE_ADDR;
 202         else if (pll == &pll5_video_main_clk)
 203                 return PLL5_VIDEO_BASE_ADDR;
 204         else if (pll == &pll6_MLB_main_clk)
 205                 return PLL6_MLB_BASE_ADDR;
 206         else if (pll == &pll7_usb_host_main_clk)
 207                 return PLL7_480_USB2_BASE_ADDR;
 208         else if (pll == &pll8_enet_main_clk)
 209                 return PLL8_ENET_BASE_ADDR;
 210         else
 211                 BUG();
 212         return NULL;
 213 }
 214
 215
 216 /*
 217  * For the 6-to-1 muxed input clock
 218  */
 219 static inline u32 _get_mux6(struct clk *parent, struct clk *m0, struct clk *m1,
 220                             struct clk *m2, struct clk *m3, struct clk *m4,
 221                             struct clk *m5)
 222 {
 223         if (parent == m0)
 224                 return 0;
 225         else if (parent == m1)
 226                 return 1;
 227         else if (parent == m2)
 228                 return 2;
 229         else if (parent == m3)
 230                 return 3;
 231         else if (parent == m4)
 232                 return 4;
 233         else if (parent == m5)
 234                 return 5;
 235         else
 236                 BUG();
 237
 238         return 0;
 239 }
 240 static unsigned long get_high_reference_clock_rate(struct clk *clk)
 241 {
 242         return external_high_reference;
 243 }
 244
 245 static unsigned long get_low_reference_clock_rate(struct clk *clk)
 246 {
 247         return external_low_reference;
 248 }
 249
 250 static unsigned long get_oscillator_reference_clock_rate(struct clk *clk)
 251 {
 252         return oscillator_reference;
 253 }
 254
 255 static unsigned long get_ckih2_reference_clock_rate(struct clk *clk)
 256 {
 257         return ckih2_reference;
 258 }
 259
 260 /* External high frequency clock */
 261 static struct clk ckih_clk = {
 262         __INIT_CLK_DEBUG(ckih_clk)
 263         .get_rate = get_high_reference_clock_rate,
 264 };
 265
 266 static struct clk ckih2_clk = {
 267         __INIT_CLK_DEBUG(ckih2_clk)
 268         .get_rate = get_ckih2_reference_clock_rate,
 269 };
 270
 271 static struct clk osc_clk = {
 272         __INIT_CLK_DEBUG(osc_clk)
 273         .get_rate = get_oscillator_reference_clock_rate,
 274 };
 275
 276 /* External low frequency (32kHz) clock */
 277 static struct clk ckil_clk = {
 278         __INIT_CLK_DEBUG(ckil_clk)
 279         .get_rate = get_low_reference_clock_rate,
 280 };
 281
 282 static unsigned long pfd_round_rate(struct clk *clk, unsigned long rate)
 283 {
 284         u32 frac;
 285         u64 tmp;
 286
 287         tmp = (u64)clk_get_rate(clk->parent) * 18;
 288         tmp += rate/2;
 289         do_div(tmp, rate);
 290         frac = tmp;
 291         frac = frac < 12 ? 12 : frac;
 292         frac = frac > 35 ? 35 : frac;
 293         tmp = (u64)clk_get_rate(clk->parent) * 18;
 294         do_div(tmp, frac);
 295         return tmp;
 296 }
 297
 298 static unsigned long pfd_get_rate(struct clk *clk)
 299 {
 300         u32 frac;
 301         u64 tmp;
 302         tmp = (u64)clk_get_rate(clk->parent) * 18;
 303
 304         if (apbh_dma_clk.usecount == 0)
 305                 apbh_dma_clk.enable(&apbh_dma_clk);
 306
 307         frac = (__raw_readl(clk->enable_reg) >> clk->enable_shift) &
 308                         ANADIG_PFD_FRAC_MASK;
 309
 310         do_div(tmp, frac);
 311
 312         return tmp;
 313 }
 314
 315 static int pfd_set_rate(struct clk *clk, unsigned long rate)
 316 {
 317         u32 frac;
 318         u64 tmp;
 319         tmp = (u64)clk_get_rate(clk->parent) * 18;
 320
 321         if (apbh_dma_clk.usecount == 0)
 322                 apbh_dma_clk.enable(&apbh_dma_clk);
 323
 324         /* Round up the divider so that we don't set a rate
 325           * higher than what is requested. */
 326         tmp += rate/2;
 327         do_div(tmp, rate);
 328         frac = tmp;
 329         frac = frac < 12 ? 12 : frac;
 330         frac = frac > 35 ? 35 : frac;
 331         /* clear clk frac bits */
 332         __raw_writel(ANADIG_PFD_FRAC_MASK << clk->enable_shift,
 333                         (int)clk->enable_reg + 8);
 334         /* set clk frac bits */
 335         __raw_writel(frac << clk->enable_shift,
 336                         (int)clk->enable_reg + 4);
 337
 338         tmp = (u64)clk_get_rate(clk->parent) * 18;
 339         do_div(tmp, frac);
 340
 341         if (apbh_dma_clk.usecount == 0)
 342                 apbh_dma_clk.disable(&apbh_dma_clk);
 343         return 0;
 344 }
 345
 346 static int _clk_pfd_enable(struct clk *clk)
 347 {
 348         if (apbh_dma_clk.usecount == 0)
 349                 apbh_dma_clk.enable(&apbh_dma_clk);
 350
 351         /* clear clk gate bit */
 352         __raw_writel((1 << (clk->enable_shift + 7)),
 353                         (int)clk->enable_reg + 8);
 354
 355         if (apbh_dma_clk.usecount == 0)
 356                 apbh_dma_clk.disable(&apbh_dma_clk);
 357
 358         return 0;
 359 }
 360
 361 static void _clk_pfd_disable(struct clk *clk)
 362 {
 363         if (apbh_dma_clk.usecount == 0)
 364                 apbh_dma_clk.enable(&apbh_dma_clk);
 365
 366         /* set clk gate bit */
 367         __raw_writel((1 << (clk->enable_shift + 7)),
 368                         (int)clk->enable_reg + 4);
 369
 370         if (apbh_dma_clk.usecount == 0)
 371                 apbh_dma_clk.disable(&apbh_dma_clk);
 372 }
 373
 374 static int _clk_pll_enable(struct clk *clk)
 375 {
 376         unsigned int reg;
 377         void __iomem *pllbase;
 378
 379         pllbase = _get_pll_base(clk);
 380
 381         reg = __raw_readl(pllbase);
 382         reg &= ~ANADIG_PLL_BYPASS;
 383         reg &= ~ANADIG_PLL_POWER_DOWN;
 384
 385         /* The 480MHz PLLs have the opposite definition for power bit. */
 386         if (clk == &pll3_usb_otg_main_clk || clk == &pll7_usb_host_main_clk)
 387                 reg |= ANADIG_PLL_POWER_DOWN;
 388
 389         __raw_writel(reg, pllbase);
 390
 391         /* Wait for PLL to lock */
 392         if (!WAIT(__raw_readl(pllbase) & ANADIG_PLL_LOCK,
 393                                 SPIN_DELAY))
 394                 panic("pll enable failed\n");
 395
 396         /* Enable the PLL output now*/
 397         reg = __raw_readl(pllbase);
 398         reg |= ANADIG_PLL_ENABLE;
 399         __raw_writel(reg, pllbase);
 400
 401         return 0;
 402 }
 403
 404 static void _clk_pll_disable(struct clk *clk)
 405 {
 406         unsigned int reg;
 407         void __iomem *pllbase;
 408
 409         pllbase = _get_pll_base(clk);
 410
 411         reg = __raw_readl(pllbase);
 412         reg |= ANADIG_PLL_BYPASS;
 413         reg &= ~ANADIG_PLL_ENABLE;
 414
 415         __raw_writel(reg, pllbase);
 416 }
 417
 418 static unsigned long  _clk_pll1_main_get_rate(struct clk *clk)
 419 {
 420         unsigned int div;
 421         unsigned long val;
 422
 423         div = __raw_readl(PLL1_SYS_BASE_ADDR) & ANADIG_PLL_SYS_DIV_SELECT_MASK;
 424         val = (clk_get_rate(clk->parent) * div) / 2;
 425         return val;
 426 }
 427
 428 static int _clk_pll1_main_set_rate(struct clk *clk, unsigned long rate)
 429 {
 430         unsigned int reg,  div;
 431
 432         if (rate < AUDIO_VIDEO_MIN_CLK_FREQ || rate > AUDIO_VIDEO_MAX_CLK_FREQ)
 433                 return -EINVAL;
 434
 435         div = (rate * 2) / clk_get_rate(clk->parent) ;
 436
 437         reg = __raw_readl(PLL1_SYS_BASE_ADDR) & ~ANADIG_PLL_SYS_DIV_SELECT_MASK;
 438         reg |= div;
 439         __raw_writel(reg, PLL1_SYS_BASE_ADDR);
 440
 441         return 0;
 442 }
 443
 444 static struct clk pll1_sys_main_clk = {
 445         __INIT_CLK_DEBUG(pll1_sys_main_clk)
 446         .parent = &osc_clk,
 447         .get_rate = _clk_pll1_main_get_rate,
 448         .set_rate = _clk_pll1_main_set_rate,
 449         .enable = _clk_pll_enable,
 450         .disable = _clk_pll_disable,
 451 };
 452
 453 static int _clk_pll1_sw_set_parent(struct clk *clk, struct clk *parent)
 454 {
 455         u32 reg;
 456
 457         reg = __raw_readl(MXC_CCM_CCSR);
 458
 459         if (parent == &pll1_sys_main_clk) {
 460                 reg &= ~MXC_CCM_CCSR_PLL1_SW_CLK_SEL;
 461                 __raw_writel(reg, MXC_CCM_CCSR);
 462                 /* Set the step_clk parent to be lp_apm, to save power. */
 463                 reg = __raw_readl(MXC_CCM_CCSR);
 464                 reg = (reg & ~MXC_CCM_CCSR_STEP_SEL);
 465         } else {
 466                 /* Set STEP_CLK to be the parent*/
 467                 if (parent == &osc_clk) {
 468                         /* Set STEP_CLK to be sourced from LPAPM. */
 469                         reg = __raw_readl(MXC_CCM_CCSR);
 470                         reg = (reg & ~MXC_CCM_CCSR_STEP_SEL);
 471                         __raw_writel(reg, MXC_CCM_CCSR);
 472                 } else {
 473                         /* Set STEP_CLK to be sourced from PLL2-PDF (400MHz). */
 474                         reg = __raw_readl(MXC_CCM_CCSR);
 475                         reg |= MXC_CCM_CCSR_STEP_SEL;
 476                         __raw_writel(reg, MXC_CCM_CCSR);
 477
 478                 }
 479                 reg = __raw_readl(MXC_CCM_CCSR);
 480                 reg |= MXC_CCM_CCSR_PLL1_SW_CLK_SEL;
 481         }
 482         __raw_writel(reg, MXC_CCM_CCSR);
 483         return 0;
 484 }
 485
 486 static unsigned long _clk_pll1_sw_get_rate(struct clk *clk)
 487 {
 488         return clk_get_rate(clk->parent);
 489 }
 490
 491 static struct clk pll1_sw_clk = {
 492         __INIT_CLK_DEBUG(pll1_sw_clk)
 493         .parent = &pll1_sys_main_clk,
 494         .set_parent = _clk_pll1_sw_set_parent,
 495         .get_rate = _clk_pll1_sw_get_rate,
 496 };
 497
 498 static unsigned long _clk_pll2_main_get_rate(struct clk *clk)
 499 {
 500         unsigned int div;
 501         unsigned long val;
 502
 503         div = __raw_readl(PLL2_528_BASE_ADDR) & ANADIG_PLL_528_DIV_SELECT;
 504
 505         if (div == 1)
 506                 val = clk_get_rate(clk->parent) * 22;
 507
 508         else
 509                 val = clk_get_rate(clk->parent) * 20;
 510
 511         return val;
 512 }
 513
 514 static int _clk_pll2_main_set_rate(struct clk *clk, unsigned long rate)
 515 {
 516         unsigned int reg,  div;
 517
 518         if (rate == 528000000)
 519                 div = 1;
 520         else if (rate == 480000000)
 521                 div = 0;
 522         else
 523                 return -EINVAL;
 524
 525         reg = __raw_readl(PLL2_528_BASE_ADDR);
 526         reg &= ~ANADIG_PLL_528_DIV_SELECT;
 527         reg |= div;
 528         __raw_writel(reg, PLL2_528_BASE_ADDR);
 529
 530         return 0;
 531 }
 532
 533 static struct clk pll2_528_bus_main_clk = {
 534         __INIT_CLK_DEBUG(pll2_528_bus_main_clk)
 535         .parent = &osc_clk,
 536         .get_rate = _clk_pll2_main_get_rate,
 537         .set_rate = _clk_pll2_main_set_rate,
 538         .enable = _clk_pll_enable,
 539         .disable = _clk_pll_disable,
 540 };
 541
 542 static struct clk pll2_pfd_400M = {
 543         __INIT_CLK_DEBUG(pll2_pfd_400M)
 544         .parent = &pll2_528_bus_main_clk,
 545         .enable_reg = (void *)PFD_528_BASE_ADDR,
 546         .enable_shift = ANADIG_PFD2_FRAC_OFFSET,
 547         .enable = _clk_pfd_enable,
 548         .disable = _clk_pfd_disable,
 549         .get_rate = pfd_get_rate,
 550         .set_rate = pfd_set_rate,
 551         .get_rate = pfd_get_rate,
 552         .round_rate = pfd_round_rate,
 553 };
 554
 555 static struct clk pll2_pfd_352M = {
 556         __INIT_CLK_DEBUG(pll2_pfd_352M)
 557         .parent = &pll2_528_bus_main_clk,
 558         .enable_reg = (void *)PFD_528_BASE_ADDR,
 559         .enable_shift = ANADIG_PFD0_FRAC_OFFSET,
 560         .enable = _clk_pfd_enable,
 561         .disable = _clk_pfd_disable,
 562         .set_rate = pfd_set_rate,
 563         .get_rate = pfd_get_rate,
 564         .round_rate = pfd_round_rate,
 565 };
 566
 567 static struct clk pll2_pfd_594M = {
 568         __INIT_CLK_DEBUG(pll2_pfd_594M)
 569         .parent = &pll2_528_bus_main_clk,
 570         .enable_reg = (void *)PFD_528_BASE_ADDR,
 571         .enable_shift = ANADIG_PFD1_FRAC_OFFSET,
 572         .enable = _clk_pfd_enable,
 573         .disable = _clk_pfd_disable,
 574         .set_rate = pfd_set_rate,
 575         .get_rate = pfd_get_rate,
 576         .round_rate = pfd_round_rate,
 577 };
 578
 579 static unsigned long _clk_pll2_200M_get_rate(struct clk *clk)
 580 {
 581         return clk_get_rate(clk->parent) / 2;
 582 }
 583
 584 static struct clk pll2_200M = {
 585         __INIT_CLK_DEBUG(pll2_200M)
 586         .parent = &pll2_pfd_400M,
 587         .get_rate = _clk_pll2_200M_get_rate,
 588 };
 589
 590 static unsigned long _clk_pll3_usb_otg_get_rate(struct clk *clk)
 591 {
 592         unsigned int div;
 593         unsigned long val;
 594
 595         div = __raw_readl(PLL3_480_USB1_BASE_ADDR)
 596                 & ANADIG_PLL_480_DIV_SELECT_MASK;
 597
 598         if (div == 1)
 599                 val = clk_get_rate(clk->parent) * 22;
 600         else
 601                 val = clk_get_rate(clk->parent) * 20;
 602         return val;
 603 }
 604
 605 static int _clk_pll3_usb_otg_set_rate(struct clk *clk, unsigned long rate)
 606 {
 607         unsigned int reg,  div;
 608
 609         if (rate == 528000000)
 610                 div = 1;
 611         else if (rate == 480000000)
 612                 div = 0;
 613         else
 614                 return -EINVAL;
 615
 616         reg = __raw_readl(PLL3_480_USB1_BASE_ADDR);
 617         reg &= ~ANADIG_PLL_480_DIV_SELECT_MASK;
 618         reg |= div;
 619         __raw_writel(reg, PLL3_480_USB1_BASE_ADDR);
 620
 621         return 0;
 622 }
 623
 624
 625 /* same as pll3_main_clk. These two clocks should always be the same */
 626 static struct clk pll3_usb_otg_main_clk = {
 627         __INIT_CLK_DEBUG(pll3_usb_otg_main_clk)
 628         .parent = &osc_clk,
 629         .enable = _clk_pll_enable,
 630         .disable = _clk_pll_disable,
 631         .set_rate = _clk_pll3_usb_otg_set_rate,
 632         .get_rate = _clk_pll3_usb_otg_get_rate,
 633 };
 634
 635 /* for USB OTG */
 636 static struct clk usb_phy1_clk = {
 637         __INIT_CLK_DEBUG(usb_phy1_clk)
 638         .parent = &pll3_usb_otg_main_clk,
 639         .set_rate = _clk_pll3_usb_otg_set_rate,
 640         .get_rate = _clk_pll3_usb_otg_get_rate,
 641 };
 642
 643 /* For HSIC port 1 */
 644 static struct clk usb_phy3_clk = {
 645         __INIT_CLK_DEBUG(usb_phy3_clk)
 646         .parent = &pll3_usb_otg_main_clk,
 647         .set_rate = _clk_pll3_usb_otg_set_rate,
 648         .get_rate = _clk_pll3_usb_otg_get_rate,
 649 };
 650
 651 /* For HSIC port 2 */
 652 static struct clk usb_phy4_clk = {
 653         __INIT_CLK_DEBUG(usb_phy4_clk)
 654         .parent = &pll3_usb_otg_main_clk,
 655         .set_rate = _clk_pll3_usb_otg_set_rate,
 656         .get_rate = _clk_pll3_usb_otg_get_rate,
 657 };
 658
 659 static struct clk pll3_pfd_508M = {
 660         __INIT_CLK_DEBUG(pll3_pfd_508M)
 661         .parent = &pll3_usb_otg_main_clk,
 662         .enable_reg = (void *)PFD_480_BASE_ADDR,
 663         .enable_shift = ANADIG_PFD2_FRAC_OFFSET,
 664         .enable = _clk_pfd_enable,
 665         .disable = _clk_pfd_disable,
 666         .set_rate = pfd_set_rate,
 667         .get_rate = pfd_get_rate,
 668         .round_rate = pfd_round_rate,
 669 };
 670
 671 static struct clk pll3_pfd_454M = {
 672         __INIT_CLK_DEBUG(pll3_pfd_454M)
 673         .parent = &pll3_usb_otg_main_clk,
 674         .enable_reg = (void *)PFD_480_BASE_ADDR,
 675         .enable_shift = ANADIG_PFD3_FRAC_OFFSET,
 676         .enable = _clk_pfd_enable,
 677         .disable = _clk_pfd_disable,
 678         .set_rate = pfd_set_rate,
 679         .get_rate = pfd_get_rate,
 680         .round_rate = pfd_round_rate,
 681 };
 682
 683 static struct clk pll3_pfd_720M = {
 684         __INIT_CLK_DEBUG(pll3_pfd_720M)
 685         .parent = &pll3_usb_otg_main_clk,
 686         .enable_reg = (void *)PFD_480_BASE_ADDR,
 687         .enable_shift = ANADIG_PFD0_FRAC_OFFSET,
 688         .enable = _clk_pfd_enable,
 689         .disable = _clk_pfd_disable,
 690         .set_rate = pfd_set_rate,
 691         .get_rate = pfd_get_rate,
 692         .round_rate = pfd_round_rate,
 693 };
 694
 695 static struct clk pll3_pfd_540M = {
 696         __INIT_CLK_DEBUG(pll3_pfd_540M)
 697         .parent = &pll3_usb_otg_main_clk,
 698         .enable_reg = (void *)PFD_480_BASE_ADDR,
 699         .enable_shift = ANADIG_PFD1_FRAC_OFFSET,
 700         .enable = _clk_pfd_enable,
 701         .disable = _clk_pfd_disable,
 702         .set_rate = pfd_set_rate,
 703         .get_rate = pfd_get_rate,
 704         .round_rate = pfd_round_rate,
 705         .get_rate = pfd_get_rate,
 706 };
 707
 708 static unsigned long _clk_pll3_sw_get_rate(struct clk *clk)
 709 {
 710         return clk_get_rate(clk->parent);
 711 }
 712
 713 /* same as pll3_main_clk. These two clocks should always be the same */
 714 static struct clk pll3_sw_clk = {
 715         __INIT_CLK_DEBUG(pll3_sw_clk)
 716         .parent = &pll3_usb_otg_main_clk,
 717         .get_rate = _clk_pll3_sw_get_rate,
 718 };
 719
 720 static unsigned long _clk_pll3_120M_get_rate(struct clk *clk)
 721 {
 722         return clk_get_rate(clk->parent) / 4;
 723 }
 724
 725 static struct clk pll3_120M = {
 726         __INIT_CLK_DEBUG(pll3_120M)
 727         .parent = &pll3_sw_clk,
 728         .get_rate = _clk_pll3_120M_get_rate,
 729 };
 730
 731 static unsigned long _clk_pll3_80M_get_rate(struct clk *clk)
 732 {
 733         return clk_get_rate(clk->parent) / 6;
 734 }
 735
 736 static struct clk pll3_80M = {
 737         __INIT_CLK_DEBUG(pll3_80M)
 738         .parent = &pll3_sw_clk,
 739         .get_rate = _clk_pll3_80M_get_rate,
 740 };
 741
 742 static unsigned long _clk_pll3_60M_get_rate(struct clk *clk)
 743 {
 744         return clk_get_rate(clk->parent) / 8;
 745 }
 746
 747 static struct clk pll3_60M = {
 748         __INIT_CLK_DEBUG(pll3_60M)
 749         .parent = &pll3_sw_clk,
 750         .get_rate = _clk_pll3_60M_get_rate,
 751 };
 752
 753 static unsigned long  _clk_audio_video_get_rate(struct clk *clk)
 754 {
 755         unsigned int div, mfn, mfd;
 756         unsigned long rate;
 757         unsigned int parent_rate = clk_get_rate(clk->parent);
 758         void __iomem *pllbase;
 759
 760         if (clk == &pll4_audio_main_clk)
 761                 pllbase = PLL4_AUDIO_BASE_ADDR;
 762         else
 763                 pllbase = PLL5_VIDEO_BASE_ADDR;
 764
 765         div = __raw_readl(pllbase) & ANADIG_PLL_SYS_DIV_SELECT_MASK;
 766         mfn = __raw_readl(pllbase + PLL_NUM_DIV_OFFSET);
 767         mfd = __raw_readl(pllbase + PLL_DENOM_DIV_OFFSET);
 768
 769         rate = (parent_rate * div) + ((parent_rate / mfd) * mfn);
 770
 771         return rate;
 772 }
 773
 774 static int _clk_audio_video_set_rate(struct clk *clk, unsigned long rate)
 775 {
 776         unsigned int reg,  div;
 777         unsigned int mfn, mfd = 1000000;
 778         s64 temp64;
 779         unsigned int parent_rate = clk_get_rate(clk->parent);
 780         void __iomem *pllbase;
 781
 782         if ((rate < AUDIO_VIDEO_MIN_CLK_FREQ) ||
 783                 (rate > AUDIO_VIDEO_MAX_CLK_FREQ))
 784                 return -EINVAL;
 785
 786         if (clk == &pll4_audio_main_clk)
 787                 pllbase = PLL4_AUDIO_BASE_ADDR;
 788         else
 789                 pllbase = PLL5_VIDEO_BASE_ADDR;
 790
 791         div = rate / parent_rate ;
 792         temp64 = (u64) (rate - (div * parent_rate));
 793         temp64 *= mfd;
 794         do_div(temp64, parent_rate);
 795         mfn = temp64;
 796
 797         reg = __raw_readl(pllbase) & ~ANADIG_PLL_SYS_DIV_SELECT_MASK;
 798         reg |= div;
 799         __raw_writel(reg, pllbase);
 800         __raw_writel(mfn, pllbase + PLL_NUM_DIV_OFFSET);
 801         __raw_writel(mfd, pllbase + PLL_DENOM_DIV_OFFSET);
 802
 803         return 0;
 804 }
 805
 806 static unsigned long _clk_audio_video_round_rate(struct clk *clk,
 807                                                 unsigned long rate)
 808 {
 809         if (rate < AUDIO_VIDEO_MIN_CLK_FREQ)
 810                 return AUDIO_VIDEO_MIN_CLK_FREQ;
 811
 812         if (rate > AUDIO_VIDEO_MAX_CLK_FREQ)
 813                 return AUDIO_VIDEO_MAX_CLK_FREQ;
 814
 815         return rate;
 816 }
 817
 818
 819 static struct clk pll4_audio_main_clk = {
 820         __INIT_CLK_DEBUG(pll4_audio_main_clk)
 821         .parent = &osc_clk,
 822         .enable = _clk_pll_enable,
 823         .disable = _clk_pll_disable,
 824         .set_rate = _clk_audio_video_set_rate,
 825         .get_rate = _clk_audio_video_get_rate,
 826         .round_rate = _clk_audio_video_round_rate,
 827 };
 828
 829
 830 static struct clk pll5_video_main_clk = {
 831         __INIT_CLK_DEBUG(pll5_video_main_clk)
 832         .parent = &osc_clk,
 833         .enable = _clk_pll_enable,
 834         .disable = _clk_pll_disable,
 835         .set_rate = _clk_audio_video_set_rate,
 836         .get_rate = _clk_audio_video_get_rate,
 837         .round_rate = _clk_audio_video_round_rate,
 838 };
 839
 840 static struct clk pll6_MLB_main_clk = {
 841         __INIT_CLK_DEBUG(pll6_MLB_main_clk)
 842         .parent = &osc_clk,
 843         .enable = _clk_pll_enable,
 844         .disable = _clk_pll_disable,
 845 };
 846
 847 static unsigned long _clk_pll7_usb_otg_get_rate(struct clk *clk)
 848 {
 849         unsigned int div;
 850         unsigned long val;
 851
 852         div = __raw_readl(PLL7_480_USB2_BASE_ADDR)
 853                 & ANADIG_PLL_480_DIV_SELECT_MASK;
 854
 855         if (div == 1)
 856                 val = clk_get_rate(clk->parent) * 22;
 857         else
 858                 val = clk_get_rate(clk->parent) * 20;
 859         return val;
 860 }
 861
 862 static int _clk_pll7_usb_otg_set_rate(struct clk *clk, unsigned long rate)
 863 {
 864         unsigned int reg,  div;
 865
 866         if (rate == 528000000)
 867                 div = 1;
 868         else if (rate == 480000000)
 869                 div = 0;
 870         else
 871                 return -EINVAL;
 872
 873         reg = __raw_readl(PLL7_480_USB2_BASE_ADDR);
 874         reg &= ~ANADIG_PLL_480_DIV_SELECT_MASK;
 875         reg |= div;
 876         __raw_writel(reg, PLL7_480_USB2_BASE_ADDR);
 877
 878         return 0;
 879 }
 880
 881 static struct clk pll7_usb_host_main_clk = {
 882         __INIT_CLK_DEBUG(pll7_usb_host_main_clk)
 883         .parent = &osc_clk,
 884         .enable = _clk_pll_enable,
 885         .disable = _clk_pll_disable,
 886         .set_rate = _clk_pll7_usb_otg_set_rate,
 887         .get_rate = _clk_pll7_usb_otg_get_rate,
 888
 889 };
 890
 891 static struct clk pll8_enet_main_clk = {
 892         __INIT_CLK_DEBUG(pll8_enet_main_clk)
 893         .parent = &osc_clk,
 894         .enable = _clk_pll_enable,
 895         .disable = _clk_pll_disable,
 896 };
 897
 898 static unsigned long _clk_arm_get_rate(struct clk *clk)
 899 {
 900         u32 cacrr, div;
 901
 902         cacrr = __raw_readl(MXC_CCM_CACRR);
 903         div = (cacrr & MXC_CCM_CACRR_ARM_PODF_MASK) + 1;
 904         return clk_get_rate(clk->parent) / div;
 905 }
 906
 907 static int _clk_arm_set_rate(struct clk *clk, unsigned long rate)
 908 {
 909         int i;
 910         u32 div;
 911         u32 parent_rate;
 912
 913
 914         for (i = 0; i < cpu_op_nr; i++) {
 915                 if (rate == cpu_op_tbl[i].cpu_rate)
 916                         break;
 917         }
 918         if (i >= cpu_op_nr)
 919                 return -EINVAL;
 920
 921         if (cpu_op_tbl[i].pll_rate != clk_get_rate(&pll1_sys_main_clk)) {
 922                 /* Change the PLL1 rate. */
 923                 if (pll2_pfd_400M.usecount != 0)
 924                         pll1_sw_clk.set_parent(&pll1_sw_clk, &pll2_pfd_400M);
 925                 else
 926                         pll1_sw_clk.set_parent(&pll1_sw_clk, &osc_clk);
 927                 pll1_sys_main_clk.set_rate(&pll1_sys_main_clk, cpu_op_tbl[i].pll_rate);
 928                 pll1_sw_clk.set_parent(&pll1_sw_clk, &pll1_sys_main_clk);
 929         }
 930
 931         parent_rate = clk_get_rate(clk->parent);
 932         div = parent_rate / rate;
 933
 934         if (div == 0)
 935                 div = 1;
 936
 937         if ((parent_rate / div) > rate)
 938                 div++;
 939
 940         if (div > 8)
 941                 return -1;
 942
 943         __raw_writel(div - 1, MXC_CCM_CACRR);
 944
 945         return 0;
 946 }
 947
 948 static struct clk cpu_clk = {
 949         __INIT_CLK_DEBUG(cpu_clk)
 950         .parent = &pll1_sw_clk,
 951         .set_rate = _clk_arm_set_rate,
 952         .get_rate = _clk_arm_get_rate,
 953 };
 954
 955 static int _clk_periph_set_parent(struct clk *clk, struct clk *parent)
 956 {
 957         u32 reg;
 958         int mux;
 959
 960         mux = _get_mux6(parent, &pll2_528_bus_main_clk, &pll2_pfd_400M,
 961                 &pll2_pfd_352M, &pll2_200M, &pll3_sw_clk, &osc_clk);
 962
 963         if (mux <= 3) {
 964                 /* Set the pre_periph_clk multiplexer */
 965                 reg = __raw_readl(MXC_CCM_CBCMR);
 966                 reg &= ~MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK;
 967                 reg |= mux << MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET;
 968                 __raw_writel(reg, MXC_CCM_CBCMR);
 969
 970                 /* Set the periph_clk_sel multiplexer. */
 971                 reg = __raw_readl(MXC_CCM_CBCDR);
 972                 reg &= ~MXC_CCM_CBCDR_PERIPH_CLK_SEL;
 973                 __raw_writel(reg, MXC_CCM_CBCDR);
 974         } else {
 975                 reg = __raw_readl(MXC_CCM_CBCDR);
 976                 /* Set the periph_clk2_podf divider to divide by 1. */
 977                 reg &= ~MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK;
 978                 __raw_writel(reg, MXC_CCM_CBCDR);
 979
 980                 /* Set the periph_clk2_sel mux. */
 981                 reg = __raw_readl(MXC_CCM_CBCMR);
 982                 reg &= ~MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK;
 983                 reg |= ((mux - 4) << MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET);
 984                 __raw_writel(reg, MXC_CCM_CBCMR);
 985
 986                 while (__raw_readl(MXC_CCM_CDHIPR))
 987                         ;
 988
 989                 reg = __raw_readl(MXC_CCM_CBCDR);
 990                 /* Set periph_clk_sel to select periph_clk2. */
 991                 reg |= MXC_CCM_CBCDR_PERIPH_CLK_SEL;
 992                 __raw_writel(reg, MXC_CCM_CBCDR);
 993         }
 994
 995         if (!WAIT(!(__raw_readl(MXC_CCM_CDHIPR)
 996              & MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY), SPIN_DELAY))
 997                 panic("_clk_periph_set_parent failed\n");
 998
 999         return 0;
1000 }
1001
1002 static unsigned long _clk_periph_get_rate(struct clk *clk)
1003 {
1004         u32 div = 1;
1005         u32 reg;
1006         unsigned long val;
1007
1008         if ((clk->parent == &pll3_sw_clk) || (clk->parent == &osc_clk)) {
1009                 reg = __raw_readl(MXC_CCM_CBCDR)
1010                         & MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK;
1011                 div = (reg >> MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET) + 1;
1012         }
1013         val = clk_get_rate(clk->parent) / div;
1014         return val;
1015 }
1016
1017 static struct clk periph_clk = {
1018         __INIT_CLK_DEBUG(periph_clk)
1019         .parent = &pll2_528_bus_main_clk,
1020         .set_parent = _clk_periph_set_parent,
1021         .get_rate = _clk_periph_get_rate,
1022 };
1023
1024 static unsigned long _clk_axi_get_rate(struct clk *clk)
1025 {
1026         u32 div, reg;
1027         unsigned long val;
1028
1029         reg = __raw_readl(MXC_CCM_CBCDR) & MXC_CCM_CBCDR_AXI_PODF_MASK;
1030         div = (reg >> MXC_CCM_CBCDR_AXI_PODF_OFFSET);
1031
1032         val = clk_get_rate(clk->parent) / (div + 1);
1033         return val;
1034 }
1035
1036 static int _clk_axi_set_rate(struct clk *clk, unsigned long rate)
1037 {
1038         u32 reg, div;
1039         u32 parent_rate = clk_get_rate(clk->parent);
1040
1041         div = parent_rate / rate;
1042
1043         if (div == 0)
1044                 div++;
1045         if (((parent_rate / div) != rate) || (div > 8))
1046                 return -EINVAL;
1047
1048         reg = __raw_readl(MXC_CCM_CBCDR);
1049         reg &= ~MXC_CCM_CBCDR_AXI_PODF_MASK;
1050         reg |= (div - 1) << MXC_CCM_CBCDR_AXI_PODF_OFFSET;
1051         __raw_writel(reg, MXC_CCM_CBCDR);
1052
1053         if (!WAIT(!(__raw_readl(MXC_CCM_CDHIPR)
1054              & MXC_CCM_CDHIPR_AXI_PODF_BUSY), SPIN_DELAY))
1055                 panic("pll _clk_axi_a_set_rate failed\n");
1056
1057         return 0;
1058 }
1059
1060 static unsigned long _clk_axi_round_rate(struct clk *clk,
1061                                                 unsigned long rate)
1062 {
1063         u32 div;
1064         u32 parent_rate = clk_get_rate(clk->parent);
1065
1066         div = parent_rate / rate;
1067
1068         /* Make sure rate is not greater than the maximum
1069          * value for the clock.
1070          * Also prevent a div of 0.
1071          */
1072
1073         if (div > 8)
1074                 div = 8;
1075         else if (div == 0)
1076                 div++;
1077
1078         return parent_rate / div;
1079 }
1080
1081 static int _clk_axi_set_parent(struct clk *clk, struct clk *parent)
1082 {
1083         u32 reg;
1084         int mux;
1085
1086         mux = _get_mux6(parent, &periph_clk, &pll2_pfd_400M,
1087                                 &pll3_pfd_540M, NULL, NULL, NULL);
1088
1089         if (mux == 0) {
1090                 /* Set the AXI_SEL mux */
1091                 reg = __raw_readl(MXC_CCM_CBCDR) & ~MXC_CCM_CBCDR_AXI_SEL;
1092                 __raw_writel(reg, MXC_CCM_CBCDR);
1093         } else {
1094                 /* Set the AXI_ALT_SEL mux. */
1095                 reg = __raw_readl(MXC_CCM_CBCDR)
1096                         & ~MXC_CCM_CBCDR_AXI_ALT_SEL_MASK;
1097                 reg = ((mux - 1) << MXC_CCM_CBCDR_AXI_ALT_SEL_OFFSET);
1098                 __raw_writel(reg, MXC_CCM_CBCDR);
1099
1100                 /* Set the AXI_SEL mux */
1101                 reg = __raw_readl(MXC_CCM_CBCDR) & ~MXC_CCM_CBCDR_AXI_SEL;
1102                 reg |= MXC_CCM_CBCDR_AXI_SEL;
1103                 __raw_writel(reg, MXC_CCM_CBCDR);
1104         }
1105         return 0;
1106 }
1107
1108 static struct clk axi_clk = {
1109         __INIT_CLK_DEBUG(axi_clk)
1110         .parent = &periph_clk,
1111         .set_parent = _clk_axi_set_parent,
1112         .set_rate = _clk_axi_set_rate,
1113         .get_rate = _clk_axi_get_rate,
1114         .round_rate = _clk_axi_round_rate,
1115 };
1116
1117 static unsigned long _clk_ahb_get_rate(struct clk *clk)
1118 {
1119         u32 reg, div;
1120
1121         reg = __raw_readl(MXC_CCM_CBCDR);
1122         div = ((reg & MXC_CCM_CBCDR_AHB_PODF_MASK) >>
1123                MXC_CCM_CBCDR_AHB_PODF_OFFSET) + 1;
1124
1125         return clk_get_rate(clk->parent) / div;
1126 }
1127
1128 static int _clk_ahb_set_rate(struct clk *clk, unsigned long rate)
1129 {
1130         u32 reg, div;
1131         u32 parent_rate = clk_get_rate(clk->parent);
1132
1133         div = parent_rate / rate;
1134         if (div == 0)
1135                 div++;
1136         if (((parent_rate / div) != rate) || (div > 8))
1137                 return -EINVAL;
1138
1139         reg = __raw_readl(MXC_CCM_CBCDR);
1140         reg &= ~MXC_CCM_CBCDR_AHB_PODF_MASK;
1141         reg |= (div - 1) << MXC_CCM_CBCDR_AHB_PODF_OFFSET;
1142         __raw_writel(reg, MXC_CCM_CBCDR);
1143
1144         if (!WAIT(!(__raw_readl(MXC_CCM_CDHIPR) & MXC_CCM_CDHIPR_AHB_PODF_BUSY),
1145                                 SPIN_DELAY))
1146                         panic("_clk_ahb_set_rate failed\n");
1147
1148         return 0;
1149 }
1150
1151 static unsigned long _clk_ahb_round_rate(struct clk *clk,
1152                                                 unsigned long rate)
1153 {
1154         u32 div;
1155         u32 parent_rate = clk_get_rate(clk->parent);
1156
1157         div = parent_rate / rate;
1158
1159         /* Make sure rate is not greater than the maximum value for the clock.
1160          * Also prevent a div of 0.
1161          */
1162         if (div == 0)
1163                 div++;
1164
1165         if (div > 8)
1166                 div = 8;
1167
1168         return parent_rate / div;
1169 }
1170
1171 static struct clk ahb_clk = {
1172         __INIT_CLK_DEBUG(ahb_clk)
1173         .parent = &periph_clk,
1174         .get_rate = _clk_ahb_get_rate,
1175         .set_rate = _clk_ahb_set_rate,
1176         .round_rate = _clk_ahb_round_rate,
1177 };
1178
1179 static unsigned long _clk_ipg_get_rate(struct clk *clk)
1180 {
1181         u32 reg, div;
1182
1183         reg = __raw_readl(MXC_CCM_CBCDR);
1184         div = ((reg & MXC_CCM_CBCDR_IPG_PODF_MASK) >>
1185                 MXC_CCM_CBCDR_IPG_PODF_OFFSET) + 1;
1186
1187         return clk_get_rate(clk->parent) / div;
1188 }
1189
1190
1191 static struct clk ipg_clk = {
1192         __INIT_CLK_DEBUG(ipg_clk)
1193         .parent = &ahb_clk,
1194         .get_rate = _clk_ipg_get_rate,
1195 };
1196
1197 static struct clk tzasc1_clk = {
1198         __INIT_CLK_DEBUG(tzasc1_clk)
1199         .id = 0,
1200         .parent = &ipg_clk,
1201         .enable_reg = MXC_CCM_CCGR2,
1202         .enable_shift = MXC_CCM_CCGRx_CG11_OFFSET,
1203         .enable = _clk_enable,
1204         .disable = _clk_disable_inwait,
1205 };
1206
1207 static struct clk tzasc2_clk = {
1208         __INIT_CLK_DEBUG(tzasc2_clk)
1209         .id = 0,
1210         .parent = &ipg_clk,
1211         .enable_reg = MXC_CCM_CCGR2,
1212         .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET,
1213         .enable = _clk_enable,
1214         .disable = _clk_disable_inwait,
1215 };
1216
1217 static struct clk mx6fast1_clk = {
1218         __INIT_CLK_DEBUG(mx6fast1_clk)
1219         .id = 0,
1220         .parent = &ahb_clk,
1221         .enable_reg = MXC_CCM_CCGR4,
1222         .enable_shift = MXC_CCM_CCGRx_CG4_OFFSET,
1223         .enable = _clk_enable,
1224         .disable = _clk_disable_inwait,
1225 };
1226
1227 static struct clk mx6per1_clk = {
1228         __INIT_CLK_DEBUG(mx6per1_clk)
1229         .id = 0,
1230         .parent = &ahb_clk,
1231         .secondary = &mx6fast1_clk,
1232         .enable_reg = MXC_CCM_CCGR4,
1233         .enable_shift = MXC_CCM_CCGRx_CG6_OFFSET,
1234         .enable = _clk_enable,
1235         .disable = _clk_disable_inwait,
1236 };
1237
1238 static struct clk mx6per2_clk = {
1239         __INIT_CLK_DEBUG(mx6per2_clk)
1240         .id = 0,
1241         .parent = &ahb_clk,
1242         .enable_reg = MXC_CCM_CCGR4,
1243         .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
1244         .enable = _clk_enable,
1245         .disable = _clk_disable_inwait,
1246 };
1247
1248 static unsigned long _clk_mmdc_ch0_axi_get_rate(struct clk *clk)
1249 {
1250         u32 reg, div;
1251
1252         reg = __raw_readl(MXC_CCM_CBCDR);
1253         div = ((reg & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
1254                         MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET) + 1;
1255
1256         return clk_get_rate(clk->parent) / div;
1257 }
1258
1259 static int _clk_mmdc_ch0_axi_set_rate(struct clk *clk, unsigned long rate)
1260 {
1261         u32 reg, div;
1262         u32 parent_rate = clk_get_rate(clk->parent);
1263
1264         div = parent_rate / rate;
1265         if (div == 0)
1266                 div++;
1267         if (((parent_rate / div) != rate) || (div > 8))
1268                 return -EINVAL;
1269
1270         reg = __raw_readl(MXC_CCM_CBCDR);
1271         reg &= ~MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK;
1272         reg |= (div - 1) << MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
1273         __raw_writel(reg, MXC_CCM_CBCDR);
1274
1275         if (!WAIT(!(__raw_readl(MXC_CCM_CDHIPR)
1276                 & MXC_CCM_CDHIPR_MMDC_CH0_PODF_BUSY),
1277                                 SPIN_DELAY))
1278                         panic("_clk_mmdc_ch0_axi_set_rate failed\n");
1279
1280         return 0;
1281 }
1282
1283 static unsigned long _clk_mmdc_ch0_axi_round_rate(struct clk *clk,
1284                                                 unsigned long rate)
1285 {
1286         u32 div;
1287         u32 parent_rate = clk_get_rate(clk->parent);
1288
1289         div = parent_rate / rate;
1290
1291         /* Make sure rate is not greater than the maximum value for the clock.
1292          * Also prevent a div of 0.
1293          */
1294         if (div == 0)
1295                 div++;
1296
1297         if (div > 8)
1298                 div = 8;
1299
1300         return parent_rate / div;
1301 }
1302
1303 static struct clk mmdc_ch0_axi_clk[] = {
1304         {
1305         __INIT_CLK_DEBUG(mmdc_ch0_axi_clk)
1306         .id = 0,
1307         .parent = &periph_clk,
1308         .enable = _clk_enable,
1309         .disable = _clk_disable_inwait,
1310         .enable_reg = MXC_CCM_CCGR3,
1311         .enable_shift = MXC_CCM_CCGRx_CG10_OFFSET,
1312         .secondary = &mmdc_ch0_axi_clk[1],
1313         .get_rate = _clk_mmdc_ch0_axi_get_rate,
1314         .set_rate = _clk_mmdc_ch0_axi_set_rate,
1315         .round_rate = _clk_mmdc_ch0_axi_round_rate,
1316         },
1317         {
1318         __INIT_CLK_DEBUG(mmdc_ch0_ipg_clk)
1319         .id = 0,
1320         .parent = &ipg_clk,
1321         .enable = _clk_enable,
1322         .disable = _clk_disable_inwait,
1323         .enable_reg = MXC_CCM_CCGR3,
1324         .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET,
1325         .secondary = &tzasc1_clk,
1326         },
1327 };
1328
1329 static unsigned long _clk_mmdc_ch1_axi_get_rate(struct clk *clk)
1330 {
1331         u32 reg, div;
1332
1333         reg = __raw_readl(MXC_CCM_CBCDR);
1334         div = ((reg & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) >>
1335                         MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET) + 1;
1336
1337         return clk_get_rate(clk->parent) / div;
1338 }
1339
1340 static int _clk_mmdc_ch1_axi_set_rate(struct clk *clk, unsigned long rate)
1341 {
1342         u32 reg, div;
1343         u32 parent_rate = clk_get_rate(clk->parent);
1344
1345         div = parent_rate / rate;
1346         if (div == 0)
1347                 div++;
1348         if (((parent_rate / div) != rate) || (div > 8))
1349                 return -EINVAL;
1350
1351         reg = __raw_readl(MXC_CCM_CBCDR);
1352         reg &= ~MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK;
1353         reg |= (div - 1) << MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
1354         __raw_writel(reg, MXC_CCM_CBCDR);
1355
1356         if (!WAIT(!(__raw_readl(MXC_CCM_CDHIPR)
1357                 & MXC_CCM_CDHIPR_MMDC_CH1_PODF_BUSY), SPIN_DELAY))
1358                         panic("_clk_mmdc_ch1_axi_set_rate failed\n");
1359
1360         return 0;
1361 }
1362
1363 static unsigned long _clk_mmdc_ch1_axi_round_rate(struct clk *clk,
1364                                                 unsigned long rate)
1365 {
1366         u32 div;
1367         u32 parent_rate = clk_get_rate(clk->parent);
1368
1369         div = parent_rate / rate;
1370
1371         /* Make sure rate is not greater than the maximum value for the clock.
1372          * Also prevent a div of 0.
1373          */
1374         if (div == 0)
1375                 div++;
1376
1377         if (div > 8)
1378                 div = 8;
1379
1380         return parent_rate / div;
1381 }
1382
1383 static struct clk mmdc_ch1_axi_clk[] = {
1384         {
1385         __INIT_CLK_DEBUG(mmdc_ch1_axi_clk)
1386         .id = 0,
1387         .parent = &pll2_pfd_400M,
1388         .enable = _clk_enable,
1389         .disable = _clk_disable,
1390         .enable_reg = MXC_CCM_CCGR3,
1391         .enable_shift = MXC_CCM_CCGRx_CG11_OFFSET,
1392         .secondary = &mmdc_ch1_axi_clk[1],
1393         .get_rate = _clk_mmdc_ch1_axi_get_rate,
1394         .set_rate = _clk_mmdc_ch1_axi_set_rate,
1395         .round_rate = _clk_mmdc_ch1_axi_round_rate,
1396         },
1397         {
1398         .id = 1,
1399         __INIT_CLK_DEBUG(mmdc_ch1_ipg_clk)
1400         .parent = &ipg_clk,
1401         .enable = _clk_enable,
1402         .disable = _clk_disable,
1403         .enable_reg = MXC_CCM_CCGR3,
1404         .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
1405         .secondary = &tzasc2_clk,
1406         },
1407 };
1408
1409 static struct clk ocram_clk = {
1410         __INIT_CLK_DEBUG(ocram_clk)
1411         .id = 0,
1412         .parent = &ahb_clk,
1413         .enable_reg = MXC_CCM_CCGR3,
1414         .enable_shift = MXC_CCM_CCGRx_CG14_OFFSET,
1415         .enable = _clk_enable,
1416         .disable = _clk_disable_inwait,
1417 };
1418
1419 static unsigned long _clk_ipg_perclk_get_rate(struct clk *clk)
1420 {
1421         u32 reg, div;
1422
1423         reg = __raw_readl(MXC_CCM_CSCMR1);
1424         div = ((reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK) >>
1425                         MXC_CCM_CSCMR1_PERCLK_PODF_OFFSET) + 1;
1426
1427         return clk_get_rate(clk->parent) / div;
1428 }
1429
1430 static int _clk_ipg_perclk_set_rate(struct clk *clk, unsigned long rate)
1431 {
1432         u32 reg, div;
1433         u32 parent_rate = clk_get_rate(clk->parent);
1434
1435         div = parent_rate / rate;
1436         if (div == 0)
1437                 div++;
1438         if (((parent_rate / div) != rate) || (div > 64))
1439                 return -EINVAL;
1440
1441         reg = __raw_readl(MXC_CCM_CSCMR1);
1442         reg &= ~MXC_CCM_CSCMR1_PERCLK_PODF_MASK;
1443         reg |= (div - 1) << MXC_CCM_CSCMR1_PERCLK_PODF_OFFSET;
1444         __raw_writel(reg, MXC_CCM_CSCMR1);
1445
1446         return 0;
1447 }
1448
1449
1450 static unsigned long _clk_ipg_perclk_round_rate(struct clk *clk,
1451                                                 unsigned long rate)
1452 {
1453         u32 div;
1454         u32 parent_rate = clk_get_rate(clk->parent);
1455
1456         div = parent_rate / rate;
1457
1458         /* Make sure rate is not greater than the maximum value for the clock.
1459          * Also prevent a div of 0.
1460          */
1461         if (div == 0)
1462                 div++;
1463
1464         if (div > 64)
1465                 div = 64;
1466
1467         return parent_rate / div;
1468 }
1469
1470 static struct clk ipg_perclk = {
1471         __INIT_CLK_DEBUG(ipg_perclk)
1472         .parent = &ipg_clk,
1473         .get_rate = _clk_ipg_perclk_get_rate,
1474         .set_rate = _clk_ipg_perclk_set_rate,
1475         .round_rate = _clk_ipg_perclk_round_rate,
1476 };
1477
1478 static struct clk spba_clk = {
1479         __INIT_CLK_DEBUG(spba_clk)
1480         .parent = &ipg_clk,
1481         .enable_reg = MXC_CCM_CCGR5,
1482         .enable_shift = MXC_CCM_CCGRx_CG6_OFFSET,
1483         .enable = _clk_enable,
1484         .disable = _clk_disable,
1485 };
1486
1487 static struct clk sdma_clk[] = {
1488         {
1489          __INIT_CLK_DEBUG(sdma_clk)
1490          .parent = &ahb_clk,
1491          .enable_reg = MXC_CCM_CCGR5,
1492          .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET,
1493          .enable = _clk_enable,
1494          .disable = _clk_disable,
1495          .secondary = &sdma_clk[1],
1496         },
1497         {
1498          .parent = &mx6per1_clk,
1499 #ifdef CONFIG_SDMA_IRAM
1500          .secondary = &ocram_clk,
1501 #else
1502         .secondary = &mmdc_ch0_axi_clk[0],
1503 #endif
1504         },
1505 };
1506
1507 static int _clk_gpu2d_axi_set_parent(struct clk *clk, struct clk *parent)
1508 {
1509         u32 reg = __raw_readl(MXC_CCM_CBCMR) & ~MXC_CCM_CBCMR_GPU2D_AXI_CLK_SEL;
1510
1511         if (parent == &ahb_clk)
1512                 reg |= MXC_CCM_CBCMR_GPU2D_AXI_CLK_SEL;
1513
1514         __raw_writel(reg, MXC_CCM_CBCMR);
1515
1516         return 0;
1517 }
1518
1519 static struct clk gpu2d_axi_clk = {
1520         __INIT_CLK_DEBUG(gpu2d_axi_clk)
1521         .parent = &axi_clk,
1522         .secondary = &openvg_axi_clk,
1523         .set_parent = _clk_gpu2d_axi_set_parent,
1524 };
1525
1526 static int _clk_gpu3d_axi_set_parent(struct clk *clk, struct clk *parent)
1527 {
1528         u32 reg = __raw_readl(MXC_CCM_CBCMR) & ~MXC_CCM_CBCMR_GPU3D_AXI_CLK_SEL;
1529
1530         if (parent == &ahb_clk)
1531                 reg |= MXC_CCM_CBCMR_GPU3D_AXI_CLK_SEL;
1532
1533         __raw_writel(reg, MXC_CCM_CBCMR);
1534
1535         return 0;
1536 }
1537
1538 static struct clk gpu3d_axi_clk = {
1539         __INIT_CLK_DEBUG(gpu3d_axi_clk)
1540         .parent = &axi_clk,
1541         .secondary = &mmdc_ch0_axi_clk[0],
1542         .set_parent = _clk_gpu3d_axi_set_parent,
1543 };
1544
1545 static int _clk_pcie_axi_set_parent(struct clk *clk, struct clk *parent)
1546 {
1547         u32 reg = __raw_readl(MXC_CCM_CBCMR) & ~MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL;
1548
1549         if (parent == &ahb_clk)
1550                 reg |= MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL;
1551
1552         __raw_writel(reg, MXC_CCM_CBCMR);
1553
1554         return 0;
1555 }
1556
1557 static struct clk pcie_axi_clk = {
1558         __INIT_CLK_DEBUG(pcie_axi_clk)
1559         .parent = &axi_clk,
1560         .set_parent = _clk_pcie_axi_set_parent,
1561 };
1562
1563 static int _clk_vdo_axi_set_parent(struct clk *clk, struct clk *parent)
1564 {
1565         u32 reg = __raw_readl(MXC_CCM_CBCMR) & ~MXC_CCM_CBCMR_VDOAXI_CLK_SEL;
1566
1567         if (parent == &ahb_clk)
1568                 reg |= MXC_CCM_CBCMR_VDOAXI_CLK_SEL;
1569
1570         __raw_writel(reg, MXC_CCM_CBCMR);
1571
1572         return 0;
1573 }
1574
1575 static struct clk vdo_axi_clk = {
1576         __INIT_CLK_DEBUG(vdo_axi_clk)
1577         .parent = &axi_clk,
1578         .enable_reg = MXC_CCM_CCGR6,
1579         .enable_shift = MXC_CCM_CCGRx_CG6_OFFSET,
1580         .enable = _clk_enable,
1581         .disable = _clk_disable,
1582         .set_parent = _clk_vdo_axi_set_parent,
1583 };
1584
1585 static struct clk vdoa_clk = {
1586         __INIT_CLK_DEBUG(vdoa_clk)
1587         .id = 0,
1588         .parent = &axi_clk,
1589         .secondary = &mx6fast1_clk,
1590         .enable_reg = MXC_CCM_CCGR2,
1591         .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
1592         .enable = _clk_enable,
1593         .disable = _clk_disable,
1594 };
1595
1596 static struct clk gpt_clk[] = {
1597         {
1598         __INIT_CLK_DEBUG(gpt_clk)
1599          .parent = &ipg_perclk,
1600          .id = 0,
1601          .enable_reg = MXC_CCM_CCGR1,
1602          .enable_shift = MXC_CCM_CCGRx_CG10_OFFSET,
1603          .enable = _clk_enable,
1604          .disable = _clk_disable,
1605          .secondary = &gpt_clk[1],
1606          },
1607         {
1608         __INIT_CLK_DEBUG(gpt_serial_clk)
1609          .id = 0,
1610          .enable_reg = MXC_CCM_CCGR1,
1611          .enable_shift = MXC_CCM_CCGRx_CG11_OFFSET,
1612          .enable = _clk_enable,
1613          .disable = _clk_disable,
1614          },
1615 };
1616
1617 static unsigned long _clk_iim_get_rate(struct clk *clk)
1618 {
1619         return clk_get_rate(clk->parent);
1620 }
1621
1622 static struct clk iim_clk = {
1623         __INIT_CLK_DEBUG(iim_clk)
1624         .parent = &ipg_clk,
1625         .enable = _clk_enable,
1626         .enable_reg = MXC_CCM_CCGR2,
1627         .enable_shift = MXC_CCM_CCGRx_CG6_OFFSET,
1628         .disable = _clk_disable,
1629         .get_rate = _clk_iim_get_rate,
1630 };
1631
1632 static struct clk i2c_clk[] = {
1633         {
1634         __INIT_CLK_DEBUG(i2c_clk_0)
1635          .id = 0,
1636          .parent = &ipg_perclk,
1637          .enable_reg = MXC_CCM_CCGR2,
1638          .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET,
1639          .enable = _clk_enable,
1640          .disable = _clk_disable,
1641          },
1642         {
1643         __INIT_CLK_DEBUG(i2c_clk_1)
1644          .id = 1,
1645          .parent = &ipg_perclk,
1646          .enable_reg = MXC_CCM_CCGR2,
1647          .enable_shift = MXC_CCM_CCGRx_CG4_OFFSET,
1648          .enable = _clk_enable,
1649          .disable = _clk_disable,
1650          },
1651         {
1652         __INIT_CLK_DEBUG(i2c_clk_2)
1653          .id = 2,
1654          .parent = &ipg_perclk,
1655          .enable_reg = MXC_CCM_CCGR2,
1656          .enable_shift = MXC_CCM_CCGRx_CG5_OFFSET,
1657          .enable = _clk_enable,
1658          .disable = _clk_disable,
1659          },
1660 };
1661
1662 static int _clk_vpu_axi_set_parent(struct clk *clk, struct clk *parent)
1663 {
1664         int mux;
1665         u32 reg = __raw_readl(MXC_CCM_CBCMR)
1666                 & ~MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK;
1667
1668         mux = _get_mux6(parent, &axi_clk, &pll2_pfd_400M,
1669                 &pll2_pfd_352M, NULL, NULL, NULL);
1670
1671         reg |= (mux << MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET);
1672
1673         __raw_writel(reg, MXC_CCM_CBCMR);
1674
1675         return 0;
1676 }
1677
1678 static unsigned long _clk_vpu_axi_get_rate(struct clk *clk)
1679 {
1680         u32 reg, div;
1681
1682         reg = __raw_readl(MXC_CCM_CSCDR1);
1683         div = ((reg & MXC_CCM_CSCDR1_VPU_AXI_PODF_MASK) >>
1684                         MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET) + 1;
1685
1686         return clk_get_rate(clk->parent) / div;
1687 }
1688
1689 static int _clk_vpu_axi_set_rate(struct clk *clk, unsigned long rate)
1690 {
1691         u32 reg, div;
1692         u32 parent_rate = clk_get_rate(clk->parent);
1693
1694         div = parent_rate / rate;
1695         if (div == 0)
1696                 div++;
1697         if (((parent_rate / div) != rate) || (div > 8))
1698                 return -EINVAL;
1699
1700         reg = __raw_readl(MXC_CCM_CSCDR1);
1701         reg &= ~MXC_CCM_CSCDR1_VPU_AXI_PODF_MASK;
1702         reg |= (div - 1) << MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET;
1703         __raw_writel(reg, MXC_CCM_CSCDR1);
1704
1705         return 0;
1706 }
1707
1708 static unsigned long _clk_vpu_axi_round_rate(struct clk *clk,
1709                                                 unsigned long rate)
1710 {
1711         u32 div;
1712         u32 parent_rate = clk_get_rate(clk->parent);
1713
1714         div = parent_rate / rate;
1715
1716         /* Make sure rate is not greater than the maximum value for the clock.
1717          * Also prevent a div of 0.
1718          */
1719         if (div == 0)
1720                 div++;
1721
1722         if (div > 8)
1723                 div = 8;
1724
1725         return parent_rate / div;
1726 }
1727
1728 static struct clk vpu_clk[] = {
1729         {
1730         __INIT_CLK_DEBUG(vpu_clk)
1731         .parent = &axi_clk,
1732         .enable_reg = MXC_CCM_CCGR6,
1733         .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
1734         .enable = _clk_enable,
1735         .disable = _clk_disable,
1736         .set_parent = _clk_vpu_axi_set_parent,
1737         .round_rate = _clk_vpu_axi_round_rate,
1738         .set_rate = _clk_vpu_axi_set_rate,
1739         .get_rate = _clk_vpu_axi_get_rate,
1740         .secondary = &vpu_clk[1],
1741         },
1742         {
1743         .parent =  &mmdc_ch0_axi_clk[0],
1744         .secondary = &vpu_clk[2],
1745         },
1746         {
1747         .parent =  &mx6fast1_clk,
1748         .secondary = &ocram_clk,
1749         },
1750
1751 };
1752
1753 static int _clk_ipu1_set_parent(struct clk *clk, struct clk *parent)
1754 {
1755         int mux;
1756         u32 reg = __raw_readl(MXC_CCM_CSCDR3)
1757                 & ~MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_MASK;
1758
1759         mux = _get_mux6(parent, &mmdc_ch0_axi_clk[0],
1760                 &pll2_pfd_400M, &pll3_120M, &pll3_pfd_540M, NULL, NULL);
1761
1762         reg |= (mux << MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_OFFSET);
1763
1764         __raw_writel(reg, MXC_CCM_CSCDR3);
1765
1766         return 0;
1767 }
1768
1769 static unsigned long _clk_ipu1_get_rate(struct clk *clk)
1770 {
1771         u32 reg, div;
1772
1773         reg = __raw_readl(MXC_CCM_CSCDR3);
1774         div = ((reg & MXC_CCM_CSCDR3_IPU1_HSP_PODF_MASK) >>
1775                         MXC_CCM_CSCDR3_IPU1_HSP_PODF_OFFSET) + 1;
1776
1777         return clk_get_rate(clk->parent) / div;
1778 }
1779
1780 static int _clk_ipu1_set_rate(struct clk *clk, unsigned long rate)
1781 {
1782         u32 reg, div;
1783         u32 parent_rate = clk_get_rate(clk->parent);
1784
1785         div = parent_rate / rate;
1786         if (div == 0)
1787                 div++;
1788         if (((parent_rate / div) != rate) || (div > 8))
1789                 return -EINVAL;
1790
1791         reg = __raw_readl(MXC_CCM_CSCDR3);
1792         reg &= ~MXC_CCM_CSCDR3_IPU1_HSP_PODF_MASK;
1793         reg |= (div - 1) << MXC_CCM_CSCDR3_IPU1_HSP_PODF_OFFSET;
1794         __raw_writel(reg, MXC_CCM_CSCDR3);
1795
1796         return 0;
1797 }
1798
1799 static unsigned long _clk_ipu_round_rate(struct clk *clk,
1800                                                 unsigned long rate)
1801 {
1802         u32 div;
1803         u32 parent_rate = clk_get_rate(clk->parent);
1804
1805         div = parent_rate / rate;
1806
1807         /* Make sure rate is not greater than the maximum value for the clock.
1808          * Also prevent a div of 0.
1809          */
1810         if (div == 0)
1811                 div++;
1812
1813         if (div > 8)
1814                 div = 8;
1815
1816         return parent_rate / div;
1817 }
1818
1819 static struct clk ipu1_clk = {
1820         __INIT_CLK_DEBUG(ipu1_clk)
1821         .parent = &mmdc_ch0_axi_clk[0],
1822         .secondary = &mmdc_ch0_axi_clk[0],
1823         .enable_reg = MXC_CCM_CCGR3,
1824         .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET,
1825         .enable = _clk_enable,
1826         .disable = _clk_disable,
1827         .set_parent = _clk_ipu1_set_parent,
1828         .round_rate = _clk_ipu_round_rate,
1829         .set_rate = _clk_ipu1_set_rate,
1830         .get_rate = _clk_ipu1_get_rate,
1831         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
1832 };
1833
1834 static int _clk_cko1_clk0_set_parent(struct clk *clk, struct clk *parent)
1835 {
1836         u32 sel, reg;
1837
1838         if (parent == &pll3_sw_clk)
1839                 sel = 0;
1840         else if (parent == &pll2_528_bus_main_clk)
1841                 sel = 1;
1842         else if (parent == &pll1_sys_main_clk)
1843                 sel = 2;
1844         else if (parent == &pll5_video_main_clk)
1845                 sel = 3;
1846         else if (parent == &axi_clk)
1847                 sel = 5;
1848         else if (parent == &enfc_clk)
1849                 sel = 6;
1850         else if (parent == &ipu1_di_clk_root)
1851                 sel = 7;
1852         else if (parent == &ipu1_di_clk_root)
1853                 sel = 8;
1854         else if (parent == &ipu2_di_clk_root)
1855                 sel = 9;
1856         else if (parent == &ipu2_di_clk_root)
1857                 sel = 10;
1858         else if (parent == &ahb_clk)
1859                 sel = 11;
1860         else if (parent == &ipg_clk)
1861                 sel = 12;
1862         else if (parent == &ipg_perclk)
1863                 sel = 13;
1864         else if (parent == &ckil_clk)
1865                 sel = 14;
1866         else if (parent == &pll4_audio_main_clk)
1867                 sel = 15;
1868         else
1869                 return -EINVAL;
1870
1871         reg = __raw_readl(MXC_CCM_CCOSR);
1872         reg &= ~MXC_CCM_CCOSR_CKOL_SEL_MASK;
1873         reg |= sel << MXC_CCM_CCOSR_CKOL_SEL_OFFSET;
1874         __raw_writel(reg, MXC_CCM_CCOSR);
1875         return 0;
1876 }
1877
1878 static unsigned long _clk_cko1_round_rate(struct clk *clk,
1879                                                 unsigned long rate)
1880 {
1881         u32 div;
1882         u32 parent_rate = clk_get_rate(clk->parent);
1883
1884         div = parent_rate / rate;
1885
1886         /* Make sure rate is not greater than the maximum value for the clock.
1887          * Also prevent a div of 0.
1888          */
1889         if (div == 0)
1890                 div++;
1891
1892         if (div > 8)
1893                 div = 8;
1894
1895         return parent_rate / div;
1896 }
1897
1898 static int _clk_cko1_set_rate(struct clk *clk, unsigned long rate)
1899 {
1900         u32 reg, div;
1901         u32 parent_rate = clk_get_rate(clk->parent);
1902
1903         div = parent_rate / rate;
1904         if (div == 0)
1905                 div++;
1906         if (((parent_rate / div) != rate) || (div > 8))
1907                 return -EINVAL;
1908
1909         reg = __raw_readl(MXC_CCM_CCOSR);
1910         reg &= ~MXC_CCM_CCOSR_CKOL_DIV_MASK;
1911         reg |= div << MXC_CCM_CCOSR_CKOL_DIV_OFFSET;
1912         __raw_writel(reg, MXC_CCM_CCOSR);
1913
1914         return 0;
1915 }
1916
1917 static unsigned long _clk_cko1_get_rate(struct clk *clk)
1918 {
1919         u32 reg, div;
1920
1921         reg = __raw_readl(MXC_CCM_CCOSR);
1922         div = ((reg & MXC_CCM_CCOSR_CKOL_DIV_MASK) >>
1923                         MXC_CCM_CCOSR_CKOL_DIV_OFFSET) + 1;
1924
1925         return clk_get_rate(clk->parent) / div;
1926 }
1927
1928 static int cko1_clk_enable(struct clk *clk)
1929 {
1930         u32 reg;
1931         reg = __raw_readl(clk->enable_reg);
1932         reg |= clk->enable_shift;
1933         __raw_writel(reg, clk->enable_reg);
1934
1935         return 0;
1936 }
1937
1938 static struct clk cko1_clk0 = {
1939         __INIT_CLK_DEBUG(cko1_clk0)
1940         .parent = &ipg_clk,
1941         .enable_reg = MXC_CCM_CCOSR,
1942         .enable_shift = MXC_CCM_CCOSR_CKOL_EN,
1943         .enable = cko1_clk_enable,
1944         .disable = _clk_disable,
1945         .set_parent = _clk_cko1_clk0_set_parent,
1946         .round_rate = _clk_cko1_round_rate,
1947         .set_rate = _clk_cko1_set_rate,
1948         .get_rate = _clk_cko1_get_rate,
1949 };
1950
1951 static int _clk_ipu2_set_parent(struct clk *clk, struct clk *parent)
1952 {
1953         int mux;
1954         u32 reg = __raw_readl(MXC_CCM_CSCDR3)
1955                 & ~MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_MASK;
1956
1957         mux = _get_mux6(parent, &mmdc_ch0_axi_clk[0],
1958                 &pll2_pfd_400M, &pll3_120M, &pll3_pfd_540M, NULL, NULL);
1959
1960         reg |= (mux << MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_OFFSET);
1961
1962         __raw_writel(reg, MXC_CCM_CSCDR3);
1963
1964         return 0;
1965 }
1966
1967 static unsigned long _clk_ipu2_get_rate(struct clk *clk)
1968 {
1969         u32 reg, div;
1970
1971         reg = __raw_readl(MXC_CCM_CSCDR3);
1972         div = ((reg & MXC_CCM_CSCDR3_IPU2_HSP_PODF_MASK) >>
1973                         MXC_CCM_CSCDR3_IPU2_HSP_PODF_OFFSET) + 1;
1974
1975         return clk_get_rate(clk->parent) / div;
1976 }
1977
1978 static int _clk_ipu2_set_rate(struct clk *clk, unsigned long rate)
1979 {
1980         u32 reg, div;
1981         u32 parent_rate = clk_get_rate(clk->parent);
1982
1983         div = parent_rate / rate;
1984         if (div == 0)
1985                 div++;
1986         if (((parent_rate / div) != rate) || (div > 8))
1987                 return -EINVAL;
1988
1989         reg = __raw_readl(MXC_CCM_CSCDR3);
1990         reg &= ~MXC_CCM_CSCDR3_IPU2_HSP_PODF_MASK;
1991         reg |= (div - 1) << MXC_CCM_CSCDR3_IPU2_HSP_PODF_OFFSET;
1992         __raw_writel(reg, MXC_CCM_CSCDR3);
1993
1994         return 0;
1995 }
1996
1997 static struct clk ipu2_clk = {
1998         __INIT_CLK_DEBUG(ipu2_clk)
1999         .parent = &mmdc_ch0_axi_clk[0],
2000         .secondary = &mmdc_ch0_axi_clk[0],
2001         .enable_reg = MXC_CCM_CCGR3,
2002         .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET,
2003         .enable = _clk_enable,
2004         .disable = _clk_disable,
2005         .set_parent = _clk_ipu2_set_parent,
2006         .round_rate = _clk_ipu_round_rate,
2007         .set_rate = _clk_ipu2_set_rate,
2008         .get_rate = _clk_ipu2_get_rate,
2009         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
2010 };
2011
2012 static struct clk usdhc_dep_clk = {
2013         .parent = &mmdc_ch0_axi_clk[0],
2014         .secondary = &mx6per1_clk,
2015         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
2016         };
2017
2018 static unsigned long _clk_usdhc_round_rate(struct clk *clk,
2019                                                 unsigned long rate)
2020 {
2021         u32 div;
2022         u32 parent_rate = clk_get_rate(clk->parent);
2023
2024         div = parent_rate / rate;
2025
2026         /* Make sure rate is not greater than the maximum value for the clock.
2027          * Also prevent a div of 0.
2028          */
2029         if (div == 0)
2030                 div++;
2031
2032         if (div > 8)
2033                 div = 8;
2034
2035         return parent_rate / div;
2036 }
2037
2038 static int _clk_usdhc1_set_parent(struct clk *clk, struct clk *parent)
2039 {
2040         u32 reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_USDHC1_CLK_SEL;
2041
2042         if (parent == &pll2_pfd_352M)
2043                 reg |= (MXC_CCM_CSCMR1_USDHC1_CLK_SEL);
2044
2045         __raw_writel(reg, MXC_CCM_CSCMR1);
2046
2047         return 0;
2048 }
2049
2050 static unsigned long _clk_usdhc1_get_rate(struct clk *clk)
2051 {
2052         u32 reg, div;
2053
2054         reg = __raw_readl(MXC_CCM_CSCDR1);
2055         div = ((reg & MXC_CCM_CSCDR1_USDHC1_PODF_MASK) >>
2056                         MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET) + 1;
2057
2058         return clk_get_rate(clk->parent) / div;
2059 }
2060
2061 static int _clk_usdhc1_set_rate(struct clk *clk, unsigned long rate)
2062 {
2063         u32 reg, div;
2064         u32 parent_rate = clk_get_rate(clk->parent);
2065
2066         div = parent_rate / rate;
2067         if (div == 0)
2068                 div++;
2069         if (((parent_rate / div) != rate) || (div > 8))
2070                 return -EINVAL;
2071
2072         reg = __raw_readl(MXC_CCM_CSCDR1);
2073         reg &= ~MXC_CCM_CSCDR1_USDHC1_PODF_MASK;
2074         reg |= (div - 1) << MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET;
2075         __raw_writel(reg, MXC_CCM_CSCDR1);
2076
2077         return 0;
2078 }
2079
2080 static struct clk usdhc1_clk = {
2081         __INIT_CLK_DEBUG(usdhc1_clk)
2082         .id = 0,
2083         .parent = &pll2_pfd_400M,
2084         .secondary = &usdhc_dep_clk,
2085         .enable_reg = MXC_CCM_CCGR6,
2086         .enable_shift = MXC_CCM_CCGRx_CG1_OFFSET,
2087         .enable = _clk_enable,
2088         .disable = _clk_disable,
2089         .set_parent = _clk_usdhc1_set_parent,
2090         .round_rate = _clk_usdhc_round_rate,
2091         .set_rate = _clk_usdhc1_set_rate,
2092         .get_rate = _clk_usdhc1_get_rate,
2093         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
2094 };
2095
2096 static int _clk_usdhc2_set_parent(struct clk *clk, struct clk *parent)
2097 {
2098         u32 reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_USDHC2_CLK_SEL;
2099
2100         if (parent == &pll2_pfd_352M)
2101                 reg |= (MXC_CCM_CSCMR1_USDHC2_CLK_SEL);
2102
2103         __raw_writel(reg, MXC_CCM_CSCMR1);
2104
2105         return 0;
2106 }
2107
2108 static unsigned long _clk_usdhc2_get_rate(struct clk *clk)
2109 {
2110         u32 reg, div;
2111
2112         reg = __raw_readl(MXC_CCM_CSCDR1);
2113         div = ((reg & MXC_CCM_CSCDR1_USDHC2_PODF_MASK) >>
2114                         MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET) + 1;
2115
2116         return clk_get_rate(clk->parent) / div;
2117 }
2118
2119 static int _clk_usdhc2_set_rate(struct clk *clk, unsigned long rate)
2120 {
2121         u32 reg, div;
2122         u32 parent_rate = clk_get_rate(clk->parent);
2123
2124         div = parent_rate / rate;
2125         if (div == 0)
2126                 div++;
2127         if (((parent_rate / div) != rate) || (div > 8))
2128                 return -EINVAL;
2129
2130         reg = __raw_readl(MXC_CCM_CSCDR1);
2131         reg &= ~MXC_CCM_CSCDR1_USDHC2_PODF_MASK;
2132         reg |= (div - 1) << MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET;
2133         __raw_writel(reg, MXC_CCM_CSCDR1);
2134
2135         return 0;
2136 }
2137
2138 static struct clk usdhc2_clk = {
2139         __INIT_CLK_DEBUG(usdhc2_clk)
2140         .id = 1,
2141         .parent = &pll2_pfd_400M,
2142         .secondary = &usdhc_dep_clk,
2143         .enable_reg = MXC_CCM_CCGR6,
2144         .enable_shift = MXC_CCM_CCGRx_CG2_OFFSET,
2145         .enable = _clk_enable,
2146         .disable = _clk_disable,
2147         .set_parent = _clk_usdhc2_set_parent,
2148         .round_rate = _clk_usdhc_round_rate,
2149         .set_rate = _clk_usdhc2_set_rate,
2150         .get_rate = _clk_usdhc2_get_rate,
2151         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
2152 };
2153
2154 static int _clk_usdhc3_set_parent(struct clk *clk, struct clk *parent)
2155 {
2156         u32 reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_USDHC3_CLK_SEL;
2157
2158         if (parent == &pll2_pfd_352M)
2159                 reg |= (MXC_CCM_CSCMR1_USDHC3_CLK_SEL);
2160
2161         __raw_writel(reg, MXC_CCM_CSCMR1);
2162
2163         return 0;
2164 }
2165
2166 static unsigned long _clk_usdhc3_get_rate(struct clk *clk)
2167 {
2168         u32 reg, div;
2169
2170         reg = __raw_readl(MXC_CCM_CSCDR1);
2171         div = ((reg & MXC_CCM_CSCDR1_USDHC3_PODF_MASK) >>
2172                         MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET) + 1;
2173
2174         return clk_get_rate(clk->parent) / div;
2175 }
2176
2177 static int _clk_usdhc3_set_rate(struct clk *clk, unsigned long rate)
2178 {
2179         u32 reg, div;
2180         u32 parent_rate = clk_get_rate(clk->parent);
2181
2182         div = parent_rate / rate;
2183         if (div == 0)
2184                 div++;
2185         if (((parent_rate / div) != rate) || (div > 8))
2186                 return -EINVAL;
2187
2188         reg = __raw_readl(MXC_CCM_CSCDR1);
2189         reg &= ~MXC_CCM_CSCDR1_USDHC3_PODF_MASK;
2190         reg |= (div - 1) << MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET;
2191         __raw_writel(reg, MXC_CCM_CSCDR1);
2192
2193         return 0;
2194 }
2195
2196
2197 static struct clk usdhc3_clk = {
2198         __INIT_CLK_DEBUG(usdhc3_clk)
2199         .id = 2,
2200         .parent = &pll2_pfd_400M,
2201         .secondary = &usdhc_dep_clk,
2202         .enable_reg = MXC_CCM_CCGR6,
2203         .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET,
2204         .enable = _clk_enable,
2205         .disable = _clk_disable,
2206         .set_parent = _clk_usdhc3_set_parent,
2207         .round_rate = _clk_usdhc_round_rate,
2208         .set_rate = _clk_usdhc3_set_rate,
2209         .get_rate = _clk_usdhc3_get_rate,
2210         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
2211 };
2212
2213 static int _clk_usdhc4_set_parent(struct clk *clk, struct clk *parent)
2214 {
2215         u32 reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_USDHC4_CLK_SEL;
2216
2217         if (parent == &pll2_pfd_352M)
2218                 reg |= (MXC_CCM_CSCMR1_USDHC4_CLK_SEL);
2219
2220         __raw_writel(reg, MXC_CCM_CSCMR1);
2221
2222         return 0;
2223 }
2224
2225 static unsigned long _clk_usdhc4_get_rate(struct clk *clk)
2226 {
2227         u32 reg, div;
2228
2229         reg = __raw_readl(MXC_CCM_CSCDR1);
2230         div = ((reg & MXC_CCM_CSCDR1_USDHC4_PODF_MASK) >>
2231                         MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET) + 1;
2232
2233         return clk_get_rate(clk->parent) / div;
2234 }
2235
2236 static int _clk_usdhc4_set_rate(struct clk *clk, unsigned long rate)
2237 {
2238         u32 reg, div;
2239         u32 parent_rate = clk_get_rate(clk->parent);
2240
2241         div = parent_rate / rate;
2242         if (div == 0)
2243                 div++;
2244         if (((parent_rate / div) != rate) || (div > 8))
2245                 return -EINVAL;
2246
2247         reg = __raw_readl(MXC_CCM_CSCDR1);
2248         reg &= ~MXC_CCM_CSCDR1_USDHC4_PODF_MASK;
2249         reg |= (div - 1) << MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET;
2250         __raw_writel(reg, MXC_CCM_CSCDR1);
2251
2252         return 0;
2253 }
2254
2255
2256 static struct clk usdhc4_clk = {
2257         __INIT_CLK_DEBUG(usdhc4_clk)
2258         .id = 3,
2259         .parent = &pll2_pfd_400M,
2260         .secondary = &usdhc_dep_clk,
2261         .enable_reg = MXC_CCM_CCGR6,
2262         .enable_shift = MXC_CCM_CCGRx_CG4_OFFSET,
2263         .enable = _clk_enable,
2264         .disable = _clk_disable,
2265         .set_parent = _clk_usdhc4_set_parent,
2266         .round_rate = _clk_usdhc_round_rate,
2267         .set_rate = _clk_usdhc4_set_rate,
2268         .get_rate = _clk_usdhc4_get_rate,
2269         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
2270 };
2271
2272 static unsigned long _clk_ssi_round_rate(struct clk *clk,
2273                                                 unsigned long rate)
2274 {
2275         u32 pre, post;
2276         u32 parent_rate = clk_get_rate(clk->parent);
2277         u32 div = parent_rate / rate;
2278
2279         if (parent_rate % rate)
2280                 div++;
2281
2282         __calc_pre_post_dividers(1 << 6, div, &pre, &post);
2283
2284         return parent_rate / (pre * post);
2285 }
2286
2287 static unsigned long _clk_ssi1_get_rate(struct clk *clk)
2288 {
2289         u32 reg, prediv, podf;
2290
2291         reg = __raw_readl(MXC_CCM_CS1CDR);
2292
2293         prediv = ((reg & MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK)
2294                 >> MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET) + 1;
2295         podf = ((reg & MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK)
2296                 >> MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET) + 1;
2297
2298         return clk_get_rate(clk->parent) / (prediv * podf);
2299 }
2300
2301 static int _clk_ssi1_set_rate(struct clk *clk, unsigned long rate)
2302 {
2303         u32 reg, div, pre, post;
2304         u32 parent_rate = clk_get_rate(clk->parent);
2305
2306         div = parent_rate / rate;
2307         if (div == 0)
2308                 div++;
2309         if (((parent_rate / div) != rate) || div > 512)
2310                 return -EINVAL;
2311
2312         __calc_pre_post_dividers(1 << 6, div, &pre, &post);
2313
2314         reg = __raw_readl(MXC_CCM_CS1CDR);
2315         reg &= ~(MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK |
2316                  MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK);
2317         reg |= (post - 1) << MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET;
2318         reg |= (pre - 1) << MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET;
2319
2320         __raw_writel(reg, MXC_CCM_CS1CDR);
2321
2322         return 0;
2323 }
2324
2325
2326 static int _clk_ssi1_set_parent(struct clk *clk, struct clk *parent)
2327 {
2328         u32 reg, mux;
2329
2330         reg = __raw_readl(MXC_CCM_CSCMR1)
2331                 & ~MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK;
2332
2333         mux = _get_mux6(parent, &pll3_pfd_508M, &pll3_pfd_454M,
2334                         &pll4_audio_main_clk, NULL, NULL, NULL);
2335         reg |= (mux << MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET);
2336
2337         __raw_writel(reg, MXC_CCM_CSCMR1);
2338
2339         return 0;
2340 }
2341
2342 static struct clk ssi1_clk = {
2343         __INIT_CLK_DEBUG(ssi1_clk)
2344         .parent = &pll3_pfd_508M,
2345         .enable_reg = MXC_CCM_CCGR5,
2346         .enable_shift = MXC_CCM_CCGRx_CG9_OFFSET,
2347         .enable = _clk_enable,
2348         .disable = _clk_disable,
2349         .set_parent = _clk_ssi1_set_parent,
2350         .set_rate = _clk_ssi1_set_rate,
2351         .round_rate = _clk_ssi_round_rate,
2352         .get_rate = _clk_ssi1_get_rate,
2353 #ifdef CONFIG_SND_MXC_SOC_IRAM
2354          .secondary = &ocram_clk,
2355 #else
2356          .secondary = &mmdc_ch0_axi_clk[0],
2357 #endif
2358 };
2359
2360 static unsigned long _clk_ssi2_get_rate(struct clk *clk)
2361 {
2362         u32 reg, prediv, podf;
2363
2364         reg = __raw_readl(MXC_CCM_CS2CDR);
2365
2366         prediv = ((reg & MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK)
2367                 >> MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET) + 1;
2368         podf = ((reg & MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK)
2369                 >> MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET) + 1;
2370
2371         return clk_get_rate(clk->parent) / (prediv * podf);
2372 }
2373
2374 static int _clk_ssi2_set_rate(struct clk *clk, unsigned long rate)
2375 {
2376         u32 reg, div, pre, post;
2377         u32 parent_rate = clk_get_rate(clk->parent);
2378
2379         div = parent_rate / rate;
2380         if (div == 0)
2381                 div++;
2382         if (((parent_rate / div) != rate) || div > 512)
2383                 return -EINVAL;
2384
2385         __calc_pre_post_dividers(1 << 6, div, &pre, &post);
2386
2387         reg = __raw_readl(MXC_CCM_CS2CDR);
2388         reg &= ~(MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK |
2389                  MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK);
2390         reg |= (post - 1) << MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET;
2391         reg |= (pre - 1) << MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET;
2392
2393         __raw_writel(reg, MXC_CCM_CS2CDR);
2394
2395         return 0;
2396 }
2397
2398
2399 static int _clk_ssi2_set_parent(struct clk *clk, struct clk *parent)
2400 {
2401         u32 reg, mux;
2402
2403         reg = __raw_readl(MXC_CCM_CSCMR1)
2404                 & ~MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK;
2405
2406         mux = _get_mux6(parent, &pll3_pfd_508M, &pll3_pfd_454M,
2407                         &pll4_audio_main_clk, NULL, NULL, NULL);
2408         reg |= (mux << MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET);
2409
2410         __raw_writel(reg, MXC_CCM_CSCMR1);
2411
2412         return 0;
2413 }
2414
2415 static struct clk ssi2_clk = {
2416         __INIT_CLK_DEBUG(ssi2_clk)
2417         .parent = &pll3_pfd_508M,
2418         .enable_reg = MXC_CCM_CCGR5,
2419         .enable_shift = MXC_CCM_CCGRx_CG10_OFFSET,
2420         .enable = _clk_enable,
2421         .disable = _clk_disable,
2422         .set_parent = _clk_ssi2_set_parent,
2423         .set_rate = _clk_ssi2_set_rate,
2424         .round_rate = _clk_ssi_round_rate,
2425         .get_rate = _clk_ssi2_get_rate,
2426 #ifdef CONFIG_SND_MXC_SOC_IRAM
2427          .secondary = &ocram_clk,
2428 #else
2429          .secondary = &mmdc_ch0_axi_clk[0],
2430 #endif
2431 };
2432
2433 static unsigned long _clk_ssi3_get_rate(struct clk *clk)
2434 {
2435         u32 reg, prediv, podf;
2436
2437         reg = __raw_readl(MXC_CCM_CS1CDR);
2438
2439         prediv = ((reg & MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK)
2440                 >> MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET) + 1;
2441         podf = ((reg & MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK)
2442                 >> MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET) + 1;
2443
2444         return clk_get_rate(clk->parent) / (prediv * podf);
2445 }
2446
2447 static int _clk_ssi3_set_rate(struct clk *clk, unsigned long rate)
2448 {
2449         u32 reg, div, pre, post;
2450         u32 parent_rate = clk_get_rate(clk->parent);
2451
2452         div = parent_rate / rate;
2453         if (div == 0)
2454                 div++;
2455         if (((parent_rate / div) != rate) || div > 512)
2456                 return -EINVAL;
2457
2458         __calc_pre_post_dividers(1 << 6, div, &pre, &post);
2459
2460         reg = __raw_readl(MXC_CCM_CS1CDR);
2461         reg &= ~(MXC_CCM_CS1CDR_SSI3_CLK_PODF_MASK|
2462                  MXC_CCM_CS1CDR_SSI3_CLK_PRED_MASK);
2463         reg |= (post - 1) << MXC_CCM_CS1CDR_SSI3_CLK_PODF_OFFSET;
2464         reg |= (pre - 1) << MXC_CCM_CS1CDR_SSI3_CLK_PRED_OFFSET;
2465
2466         __raw_writel(reg, MXC_CCM_CS1CDR);
2467
2468         return 0;
2469 }
2470
2471
2472 static int _clk_ssi3_set_parent(struct clk *clk, struct clk *parent)
2473 {
2474         u32 reg, mux;
2475
2476         reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_SSI3_CLK_SEL_MASK;
2477
2478         mux = _get_mux6(parent, &pll3_pfd_508M, &pll3_pfd_454M,
2479                                 &pll4_audio_main_clk, NULL, NULL, NULL);
2480         reg |= (mux << MXC_CCM_CSCMR1_SSI3_CLK_SEL_OFFSET);
2481
2482         __raw_writel(reg, MXC_CCM_CSCMR1);
2483
2484         return 0;
2485 }
2486
2487 static struct clk ssi3_clk = {
2488         __INIT_CLK_DEBUG(ssi3_clk)
2489         .parent = &pll3_pfd_508M,
2490         .enable_reg = MXC_CCM_CCGR5,
2491         .enable_shift = MXC_CCM_CCGRx_CG11_OFFSET,
2492         .enable = _clk_enable,
2493         .disable = _clk_disable,
2494         .set_parent = _clk_ssi3_set_parent,
2495         .set_rate = _clk_ssi3_set_rate,
2496         .round_rate = _clk_ssi_round_rate,
2497         .get_rate = _clk_ssi3_get_rate,
2498 #ifdef CONFIG_SND_MXC_SOC_IRAM
2499          .secondary = &ocram_clk,
2500 #else
2501          .secondary = &mmdc_ch0_axi_clk[0],
2502 #endif
2503 };
2504
2505 static unsigned long _clk_ldb_di_round_rate(struct clk *clk,
2506                                                 unsigned long rate)
2507 {
2508         u32 parent_rate = clk_get_rate(clk->parent);
2509
2510         if (rate * 7 <= parent_rate + parent_rate/20)
2511                 return parent_rate / 7;
2512         else
2513                 return 2 * parent_rate / 7;
2514 }
2515
2516 static unsigned long _clk_ldb_di0_get_rate(struct clk *clk)
2517 {
2518         u32 div;
2519
2520         div = __raw_readl(MXC_CCM_CSCMR2) &
2521                 MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
2522
2523         if (div)
2524                 return clk_get_rate(clk->parent) / 7;
2525
2526         return (2 * clk_get_rate(clk->parent)) / 7;
2527 }
2528
2529 static int _clk_ldb_di0_set_rate(struct clk *clk, unsigned long rate)
2530 {
2531         u32 reg, div = 0;
2532         u32 parent_rate = clk_get_rate(clk->parent);
2533
2534         if (rate * 7 <= parent_rate + parent_rate/20) {
2535                 div = 7;
2536                 rate = parent_rate / 7;
2537         } else
2538                 rate = 2 * parent_rate / 7;
2539
2540         reg = __raw_readl(MXC_CCM_CSCMR2);
2541         if (div == 7)
2542                 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
2543         else
2544                 reg &= ~MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
2545
2546         __raw_writel(reg, MXC_CCM_CSCMR2);
2547
2548         return 0;
2549 }
2550
2551 static int _clk_ldb_di0_set_parent(struct clk *clk, struct clk *parent)
2552 {
2553         u32 reg, mux;
2554
2555         reg = __raw_readl(MXC_CCM_CS2CDR)
2556                 & ~MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK;
2557
2558         mux = _get_mux6(parent, &pll5_video_main_clk,
2559                 &pll2_pfd_352M, &pll2_pfd_400M, &pll3_pfd_540M,
2560                 &pll3_usb_otg_main_clk, NULL);
2561         reg |= (mux << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET);
2562
2563         __raw_writel(reg, MXC_CCM_CS2CDR);
2564
2565         return 0;
2566 }
2567
2568 static struct clk ldb_di0_clk = {
2569          __INIT_CLK_DEBUG(ldb_di0_clk)
2570         .id = 0,
2571         .parent = &pll3_pfd_540M,
2572         .enable_reg = MXC_CCM_CCGR3,
2573         .enable_shift = MXC_CCM_CCGRx_CG6_OFFSET,
2574         .enable = _clk_enable,
2575         .disable = _clk_disable,
2576         .set_parent = _clk_ldb_di0_set_parent,
2577         .set_rate = _clk_ldb_di0_set_rate,
2578         .round_rate = _clk_ldb_di_round_rate,
2579         .get_rate = _clk_ldb_di0_get_rate,
2580         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
2581 };
2582
2583 static unsigned long _clk_ldb_di1_get_rate(struct clk *clk)
2584 {
2585         u32 div;
2586
2587         div = __raw_readl(MXC_CCM_CSCMR2) &
2588                 MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
2589
2590         if (div)
2591                 return clk_get_rate(clk->parent) / 7;
2592
2593         return (2 * clk_get_rate(clk->parent)) / 7;
2594 }
2595
2596 static int _clk_ldb_di1_set_rate(struct clk *clk, unsigned long rate)
2597 {
2598         u32 reg, div = 0;
2599         u32 parent_rate = clk_get_rate(clk->parent);
2600
2601         if (rate * 7 <= parent_rate + parent_rate/20) {
2602                 div = 7;
2603                 rate = parent_rate / 7;
2604         } else
2605                 rate = 2 * parent_rate / 7;
2606
2607         reg = __raw_readl(MXC_CCM_CSCMR2);
2608         if (div == 7)
2609                 reg |= MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
2610         else
2611                 reg &= ~MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
2612
2613         __raw_writel(reg, MXC_CCM_CSCMR2);
2614
2615         return 0;
2616 }
2617
2618 static int _clk_ldb_di1_set_parent(struct clk *clk, struct clk *parent)
2619 {
2620         u32 reg, mux;
2621
2622         reg = __raw_readl(MXC_CCM_CS2CDR)
2623                 & ~MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK;
2624
2625         mux = _get_mux6(parent, &pll5_video_main_clk,
2626                 &pll2_pfd_352M, &pll2_pfd_400M, &pll3_pfd_540M,
2627                 &pll3_usb_otg_main_clk, NULL);
2628         reg |= (mux << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
2629
2630         __raw_writel(reg, MXC_CCM_CS2CDR);
2631
2632         return 0;
2633 }
2634
2635 static struct clk ldb_di1_clk = {
2636          __INIT_CLK_DEBUG(ldb_di1_clk)
2637         .id = 0,
2638         .parent = &pll3_pfd_540M,
2639         .enable_reg = MXC_CCM_CCGR3,
2640         .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
2641         .enable = _clk_enable,
2642         .disable = _clk_disable,
2643         .set_parent = _clk_ldb_di1_set_parent,
2644         .set_rate = _clk_ldb_di1_set_rate,
2645         .round_rate = _clk_ldb_di_round_rate,
2646         .get_rate = _clk_ldb_di1_get_rate,
2647         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
2648 };
2649
2650
2651 static unsigned long _clk_ipu_di_round_rate(struct clk *clk,
2652                                                 unsigned long rate)
2653 {
2654         u32 div;
2655         u32 parent_rate = clk_get_rate(clk->parent);
2656
2657         if ((clk->parent == &ldb_di0_clk) ||
2658                 (clk->parent == &ldb_di1_clk))
2659                 return parent_rate;
2660
2661         div = parent_rate / rate;
2662
2663         /* Make sure rate is not greater than the maximum value for the clock.
2664          * Also prevent a div of 0.
2665          */
2666         if (div == 0)
2667                 div++;
2668
2669         if (div > 8)
2670                 div = 8;
2671
2672         return parent_rate / div;
2673 }
2674
2675 static unsigned long _clk_ipu1_di0_get_rate(struct clk *clk)
2676 {
2677         u32 reg, div;
2678
2679         if ((clk->parent == &ldb_di0_clk) ||
2680                 (clk->parent == &ldb_di1_clk))
2681                 return clk_get_rate(clk->parent);
2682
2683         reg = __raw_readl(MXC_CCM_CHSCCDR);
2684
2685         div = ((reg & MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK) >>
2686                          MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET) + 1;
2687
2688         return clk_get_rate(clk->parent) / div;
2689 }
2690
2691 static int _clk_ipu1_di0_set_rate(struct clk *clk, unsigned long rate)
2692 {
2693         u32 reg, div;
2694         u32 parent_rate = clk_get_rate(clk->parent);
2695
2696         if ((clk->parent == &ldb_di0_clk) ||
2697                 (clk->parent == &ldb_di1_clk)) {
2698                 if (parent_rate == rate)
2699                         return 0;
2700                 else
2701                         return -EINVAL;
2702         }
2703
2704         div = parent_rate / rate;
2705         if (div == 0)
2706                 div++;
2707         if (((parent_rate / div) != rate) || (div > 8))
2708                 return -EINVAL;
2709
2710         reg = __raw_readl(MXC_CCM_CHSCCDR);
2711         reg &= ~MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK;
2712         reg |= (div - 1) << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET;
2713         __raw_writel(reg, MXC_CCM_CHSCCDR);
2714
2715         return 0;
2716 }
2717
2718
2719 static int _clk_ipu1_di0_set_parent(struct clk *clk, struct clk *parent)
2720 {
2721         u32 reg, mux;
2722
2723         if (parent == &ldb_di0_clk)
2724                 mux = 0x3;
2725         else if (parent == &ldb_di1_clk)
2726                 mux = 0x4;
2727         else {
2728                 reg = __raw_readl(MXC_CCM_CHSCCDR)
2729                         & ~MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK;
2730
2731                 mux = _get_mux6(parent, &mmdc_ch0_axi_clk[0],
2732                                 &pll3_usb_otg_main_clk, &pll5_video_main_clk,
2733                                 &pll2_pfd_352M, &pll2_pfd_400M, &pll3_pfd_540M);
2734                 reg |= (mux << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
2735
2736                 __raw_writel(reg, MXC_CCM_CHSCCDR);
2737
2738                 /* Derive clock from divided pre-muxed ipu1_di0 clock.*/
2739                 mux = 0;
2740         }
2741
2742         reg = __raw_readl(MXC_CCM_CHSCCDR)
2743                 & ~MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK;
2744         __raw_writel(reg | (mux << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET),
2745                 MXC_CCM_CHSCCDR);
2746
2747         return 0;
2748 }
2749
2750 static unsigned long _clk_ipu1_di1_get_rate(struct clk *clk)
2751 {
2752         u32 reg, div;
2753
2754         if ((clk->parent == &ldb_di0_clk) ||
2755                 (clk->parent == &ldb_di1_clk))
2756                 return clk_get_rate(clk->parent);
2757
2758         reg = __raw_readl(MXC_CCM_CHSCCDR);
2759
2760         div = ((reg & MXC_CCM_CHSCCDR_IPU1_DI1_PODF_MASK)
2761                         >> MXC_CCM_CHSCCDR_IPU1_DI1_PODF_OFFSET) + 1;
2762
2763         return clk_get_rate(clk->parent) / div;
2764 }
2765
2766 static int _clk_ipu1_di1_set_rate(struct clk *clk, unsigned long rate)
2767 {
2768         u32 reg, div;
2769         u32 parent_rate = clk_get_rate(clk->parent);
2770
2771         if ((clk->parent == &ldb_di0_clk) ||
2772                 (clk->parent == &ldb_di1_clk)) {
2773                 if (parent_rate == rate)
2774                         return 0;
2775                 else
2776                         return -EINVAL;
2777         }
2778
2779         div = parent_rate / rate;
2780         if (div == 0)
2781                 div++;
2782         if (((parent_rate / div) != rate) || (div > 8))
2783                 return -EINVAL;
2784
2785         reg = __raw_readl(MXC_CCM_CHSCCDR);
2786         reg &= ~MXC_CCM_CHSCCDR_IPU1_DI1_PODF_MASK;
2787         reg |= (div - 1) << MXC_CCM_CHSCCDR_IPU1_DI1_PODF_OFFSET;
2788         __raw_writel(reg, MXC_CCM_CHSCCDR);
2789
2790         return 0;
2791 }
2792
2793
2794 static int _clk_ipu1_di1_set_parent(struct clk *clk, struct clk *parent)
2795 {
2796         u32 reg, mux;
2797
2798         if (parent == &ldb_di0_clk)
2799                 mux = 0x3;
2800         else if (parent == &ldb_di1_clk)
2801                 mux = 0x4;
2802         else {
2803                 reg = __raw_readl(MXC_CCM_CHSCCDR)
2804                         & ~MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_MASK;
2805
2806                 mux = _get_mux6(parent, &mmdc_ch0_axi_clk[0],
2807                                 &pll3_usb_otg_main_clk, &pll5_video_main_clk,
2808                                 &pll2_pfd_352M, &pll2_pfd_400M, &pll3_pfd_540M);
2809                 reg |= (mux << MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_OFFSET);
2810
2811                 __raw_writel(reg, MXC_CCM_CHSCCDR);
2812
2813                 /* Derive clock from divided pre-muxed ipu1_di0 clock.*/
2814                 mux = 0;
2815         }
2816         reg = __raw_readl(MXC_CCM_CHSCCDR)
2817                 & ~MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_MASK;
2818         __raw_writel(reg | (mux << MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET),
2819                 MXC_CCM_CHSCCDR);
2820
2821         return 0;
2822 }
2823
2824 static struct clk ipu1_di_clk[] = {
2825         {
2826          __INIT_CLK_DEBUG(ipu1_di_clk_0)
2827         .id = 0,
2828         .parent = &pll5_video_main_clk,
2829         .enable_reg = MXC_CCM_CCGR3,
2830         .enable_shift = MXC_CCM_CCGRx_CG1_OFFSET,
2831         .enable = _clk_enable,
2832         .disable = _clk_disable,
2833         .set_parent = _clk_ipu1_di0_set_parent,
2834         .set_rate = _clk_ipu1_di0_set_rate,
2835         .round_rate = _clk_ipu_di_round_rate,
2836         .get_rate = _clk_ipu1_di0_get_rate,
2837         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
2838         },
2839         {
2840          __INIT_CLK_DEBUG(ipu1_di_clk_1)
2841         .id = 1,
2842         .parent = &pll5_video_main_clk,
2843         .enable_reg = MXC_CCM_CCGR3,
2844         .enable_shift = MXC_CCM_CCGRx_CG2_OFFSET,
2845         .enable = _clk_enable,
2846         .disable = _clk_disable,
2847         .set_parent = _clk_ipu1_di1_set_parent,
2848         .set_rate = _clk_ipu1_di1_set_rate,
2849         .round_rate = _clk_ipu_di_round_rate,
2850         .get_rate = _clk_ipu1_di1_get_rate,
2851         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
2852         },
2853 };
2854
2855 static unsigned long _clk_ipu2_di0_get_rate(struct clk *clk)
2856 {
2857         u32 reg, div;
2858
2859         if ((clk->parent == &ldb_di0_clk) ||
2860                 (clk->parent == &ldb_di1_clk))
2861                 return clk_get_rate(clk->parent);
2862
2863         reg = __raw_readl(MXC_CCM_CSCDR2);
2864
2865         div = ((reg & MXC_CCM_CSCDR2_IPU2_DI0_PODF_MASK) >>
2866                         MXC_CCM_CSCDR2_IPU2_DI0_PODF_OFFSET) + 1;
2867
2868         return clk_get_rate(clk->parent) / div;
2869 }
2870
2871 static int _clk_ipu2_di0_set_rate(struct clk *clk, unsigned long rate)
2872 {
2873         u32 reg, div;
2874         u32 parent_rate = clk_get_rate(clk->parent);
2875
2876         if ((clk->parent == &ldb_di0_clk) ||
2877                 (clk->parent == &ldb_di1_clk)) {
2878                 if (parent_rate == rate)
2879                         return 0;
2880                 else
2881                         return -EINVAL;
2882         }
2883
2884         div = parent_rate / rate;
2885         if (div == 0)
2886                 div++;
2887         if (((parent_rate / div) != rate) || (div > 8))
2888                 return -EINVAL;
2889
2890         reg = __raw_readl(MXC_CCM_CSCDR2);
2891         reg &= ~MXC_CCM_CSCDR2_IPU2_DI0_PODF_MASK;
2892         reg |= (div - 1) << MXC_CCM_CSCDR2_IPU2_DI0_PODF_OFFSET;
2893         __raw_writel(reg, MXC_CCM_CSCDR2);
2894
2895         return 0;
2896 }
2897
2898 static int _clk_ipu2_di0_set_parent(struct clk *clk, struct clk *parent)
2899 {
2900         u32 reg, mux;
2901
2902         if (parent == &ldb_di0_clk)
2903                 mux = 0x3;
2904         else if (parent == &ldb_di1_clk)
2905                 mux = 0x4;
2906         else {
2907                 reg = __raw_readl(MXC_CCM_CSCDR2)
2908                         & ~MXC_CCM_CSCDR2_IPU2_DI0_PRE_CLK_SEL_MASK;
2909
2910                 mux = _get_mux6(parent, &mmdc_ch0_axi_clk[0],
2911                                 &pll3_usb_otg_main_clk, &pll5_video_main_clk,
2912                                 &pll2_pfd_352M, &pll2_pfd_400M, &pll3_pfd_540M);
2913                 reg |= (mux << MXC_CCM_CSCDR2_IPU2_DI0_PRE_CLK_SEL_OFFSET);
2914
2915                 __raw_writel(reg, MXC_CCM_CSCDR2);
2916
2917                 /* Derive clock from divided pre-muxed ipu2_di0 clock.*/
2918                 mux = 0;
2919         }
2920         reg = __raw_readl(MXC_CCM_CSCDR2)
2921                 & ~MXC_CCM_CSCDR2_IPU2_DI0_CLK_SEL_MASK;
2922         __raw_writel(reg | (mux << MXC_CCM_CSCDR2_IPU2_DI0_CLK_SEL_OFFSET),
2923                 MXC_CCM_CSCDR2);
2924
2925         return 0;
2926 }
2927
2928 static unsigned long _clk_ipu2_di1_get_rate(struct clk *clk)
2929 {
2930         u32 reg, div;
2931
2932         if ((clk->parent == &ldb_di0_clk) ||
2933                 (clk->parent == &ldb_di1_clk))
2934                 return clk_get_rate(clk->parent);
2935
2936         reg = __raw_readl(MXC_CCM_CSCDR2);
2937
2938         div = ((reg & MXC_CCM_CSCDR2_IPU2_DI1_PODF_MASK)
2939                 >> MXC_CCM_CSCDR2_IPU2_DI1_PODF_OFFSET) + 1;
2940
2941         return clk_get_rate(clk->parent) / div;
2942 }
2943
2944 static int _clk_ipu2_di1_set_rate(struct clk *clk, unsigned long rate)
2945 {
2946         u32 reg, div;
2947         u32 parent_rate = clk_get_rate(clk->parent);
2948
2949         if ((clk->parent == &ldb_di0_clk) ||
2950                 (clk->parent == &ldb_di1_clk)) {
2951                 if (parent_rate == rate)
2952                         return 0;
2953                 else
2954                         return -EINVAL;
2955         }
2956
2957         div = parent_rate / rate;
2958         if (div == 0)
2959                 div++;
2960         if (((parent_rate / div) != rate) || (div > 8))
2961                 return -EINVAL;
2962
2963         reg = __raw_readl(MXC_CCM_CSCDR2);
2964         reg &= ~MXC_CCM_CSCDR2_IPU2_DI1_PODF_MASK;
2965         reg |= (div - 1) << MXC_CCM_CSCDR2_IPU2_DI1_PODF_OFFSET;
2966         __raw_writel(reg, MXC_CCM_CSCDR2);
2967
2968         return 0;
2969 }
2970
2971 static int _clk_ipu2_di1_set_parent(struct clk *clk, struct clk *parent)
2972 {
2973         u32 reg, mux;
2974
2975         if (parent == &ldb_di0_clk)
2976                 mux = 0x3;
2977         else if (parent == &ldb_di1_clk)
2978                 mux = 0x4;
2979         else {
2980                 reg = __raw_readl(MXC_CCM_CSCDR2)
2981                         & ~MXC_CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_MASK;
2982
2983                 mux = _get_mux6(parent, &mmdc_ch0_axi_clk[0],
2984                                 &pll3_usb_otg_main_clk, &pll5_video_main_clk,
2985                                 &pll2_pfd_352M, &pll2_pfd_400M, &pll3_pfd_540M);
2986                 reg |= (mux << MXC_CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_OFFSET);
2987
2988                 __raw_writel(reg, MXC_CCM_CSCDR2);
2989
2990                 /* Derive clock from divided pre-muxed ipu1_di0 clock.*/
2991                 mux = 0;
2992         }
2993         reg = __raw_readl(MXC_CCM_CSCDR2)
2994                 & ~MXC_CCM_CSCDR2_IPU2_DI1_CLK_SEL_MASK;
2995         __raw_writel(reg | (mux << MXC_CCM_CSCDR2_IPU2_DI1_CLK_SEL_OFFSET),
2996                 MXC_CCM_CSCDR2);
2997
2998         return 0;
2999 }
3000
3001 static struct clk ipu2_di_clk[] = {
3002         {
3003          __INIT_CLK_DEBUG(ipu2_di_clk_0)
3004         .id = 0,
3005         .parent = &pll5_video_main_clk,
3006         .enable_reg = MXC_CCM_CCGR3,
3007         .enable_shift = MXC_CCM_CCGRx_CG4_OFFSET,
3008         .enable = _clk_enable,
3009         .disable = _clk_disable,
3010         .set_parent = _clk_ipu2_di0_set_parent,
3011         .set_rate = _clk_ipu2_di0_set_rate,
3012         .round_rate = _clk_ipu_di_round_rate,
3013         .get_rate = _clk_ipu2_di0_get_rate,
3014         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
3015         },
3016         {
3017          __INIT_CLK_DEBUG(ipu2_di_clk_1)
3018         .id = 1,
3019         .parent = &pll5_video_main_clk,
3020         .enable_reg = MXC_CCM_CCGR3,
3021         .enable_shift = MXC_CCM_CCGRx_CG5_OFFSET,
3022         .enable = _clk_enable,
3023         .disable = _clk_disable,
3024         .set_parent = _clk_ipu2_di1_set_parent,
3025         .set_rate = _clk_ipu2_di1_set_rate,
3026         .round_rate = _clk_ipu_di_round_rate,
3027         .get_rate = _clk_ipu2_di1_get_rate,
3028         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
3029         },
3030 };
3031
3032 static unsigned long _clk_can_root_round_rate(struct clk *clk,
3033                                                 unsigned long rate)
3034 {
3035         u32 div;
3036         u32 parent_rate = clk_get_rate(clk->parent);
3037
3038         div = parent_rate / rate;
3039
3040         /* Make sure rate is not greater than the maximum value for the clock.
3041          * Also prevent a div of 0.
3042          */
3043         if (div == 0)
3044                 div++;
3045
3046         if (div > 64)
3047                 div = 64;
3048
3049         return parent_rate / div;
3050 }
3051
3052 static int _clk_can_root_set_rate(struct clk *clk, unsigned long rate)
3053 {
3054         u32 reg, div;
3055         u32 parent_rate = clk_get_rate(clk->parent);
3056
3057         div = parent_rate / rate;
3058         if (div == 0)
3059                 div++;
3060         if (((parent_rate / div) != rate) || (div > 64))
3061                 return -EINVAL;
3062
3063         reg = __raw_readl(MXC_CCM_CSCMR2) & MXC_CCM_CSCMR2_CAN_CLK_PODF_MASK;
3064         reg |= ((div - 1) << MXC_CCM_CSCMR2_CAN_CLK_PODF_OFFSET);
3065
3066         __raw_writel(reg, MXC_CCM_CSCMR2);
3067
3068         return 0;
3069 }
3070
3071 static unsigned long _clk_can_root_get_rate(struct clk *clk)
3072 {
3073         u32 reg, div;
3074         unsigned long val;
3075
3076         reg = __raw_readl(MXC_CCM_CSCMR2) & MXC_CCM_CSCMR2_CAN_CLK_PODF_MASK;
3077         div = (reg >> MXC_CCM_CSCMR2_CAN_CLK_PODF_OFFSET) + 1;
3078         val = clk_get_rate(clk->parent) / div;
3079
3080         return val;
3081 }
3082
3083 static struct clk can_clk_root = {
3084          __INIT_CLK_DEBUG(can_clk_root)
3085         .parent = &pll3_60M,
3086         .set_rate = _clk_can_root_set_rate,
3087         .get_rate = _clk_can_root_get_rate,
3088         .round_rate = _clk_can_root_round_rate,
3089 };
3090
3091 static struct clk can2_clk[] = {
3092         {
3093          __INIT_CLK_DEBUG(can2_module_clk)
3094         .id = 0,
3095         .parent = &can_clk_root,
3096         .enable_reg = MXC_CCM_CCGR0,
3097         .enable_shift = MXC_CCM_CCGRx_CG9_OFFSET,
3098         .enable = _clk_enable,
3099         .disable = _clk_disable,
3100         .secondary = &can2_clk[1],
3101         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
3102         },
3103         {
3104          __INIT_CLK_DEBUG(can2_serial_clk)
3105         .id = 1,
3106         .parent = &can_clk_root,
3107         .enable_reg = MXC_CCM_CCGR0,
3108         .enable_shift = MXC_CCM_CCGRx_CG10_OFFSET,
3109         .enable = _clk_enable,
3110         .disable = _clk_disable,
3111         },
3112 };
3113
3114
3115 static struct clk can1_clk[] = {
3116         {
3117          __INIT_CLK_DEBUG(can1_module_clk)
3118         .id = 0,
3119         .parent = &can_clk_root,
3120         .enable_reg = MXC_CCM_CCGR0,
3121         .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
3122         .enable = _clk_enable,
3123         .disable = _clk_disable,
3124         .secondary = &can1_clk[1],
3125         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
3126         },
3127         {
3128          __INIT_CLK_DEBUG(can1_serial_clk)
3129         .id = 1,
3130         .parent = &can_clk_root,
3131         .enable_reg = MXC_CCM_CCGR0,
3132         .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET,
3133         .enable = _clk_enable,
3134         .disable = _clk_disable,
3135         },
3136 };
3137
3138 static unsigned long _clk_spdif_round_rate(struct clk *clk,
3139                                                 unsigned long rate)
3140 {
3141         u32 pre, post;
3142         u32 parent_rate = clk_get_rate(clk->parent);
3143         u32 div = parent_rate / rate;
3144
3145         if (parent_rate % rate)
3146                 div++;
3147
3148         __calc_pre_post_dividers(1 << 3, div, &pre, &post);
3149
3150         return parent_rate / (pre * post);
3151 }
3152
3153 static int _clk_spdif0_set_parent(struct clk *clk, struct clk *parent)
3154 {
3155         u32 reg, mux;
3156
3157         reg = __raw_readl(MXC_CCM_CDCDR)
3158                 & ~MXC_CCM_CDCDR_SPDIF0_CLK_SEL_MASK;
3159
3160         mux = _get_mux6(parent, &pll4_audio_main_clk,
3161                 &pll3_pfd_508M, &pll3_pfd_454M,
3162                 &pll3_sw_clk, NULL, NULL);
3163         reg |= mux << MXC_CCM_CDCDR_SPDIF0_CLK_SEL_OFFSET;
3164
3165         __raw_writel(reg, MXC_CCM_CDCDR);
3166
3167         return 0;
3168 }
3169
3170 static unsigned long _clk_spdif0_get_rate(struct clk *clk)
3171 {
3172         u32 reg, pred, podf;
3173
3174         reg = __raw_readl(MXC_CCM_CDCDR);
3175
3176         pred = ((reg & MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK)
3177                 >> MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET) + 1;
3178         podf = ((reg & MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK)
3179                 >> MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET) + 1;
3180
3181         return clk_get_rate(clk->parent) / (pred * podf);
3182 }
3183
3184 static int _clk_spdif0_set_rate(struct clk *clk, unsigned long rate)
3185 {
3186         u32 reg, div, pre, post;
3187         u32 parent_rate = clk_get_rate(clk->parent);
3188
3189         div = parent_rate / rate;
3190         if (div == 0)
3191                 div++;
3192         if (((parent_rate / div) != rate) || div > 64)
3193                 return -EINVAL;
3194
3195         __calc_pre_post_dividers(1 << 3, div, &pre, &post);
3196
3197         reg = __raw_readl(MXC_CCM_CDCDR);
3198         reg &= ~(MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK|
3199                  MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK);
3200         reg |= (post - 1) << MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET;
3201         reg |= (pre - 1) << MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET;
3202
3203         __raw_writel(reg, MXC_CCM_CDCDR);
3204
3205         return 0;
3206 }
3207
3208 static struct clk spdif0_clk[] = {
3209         {
3210         __INIT_CLK_DEBUG(spdif0_clk_0)
3211         .id = 0,
3212         .parent = &pll3_sw_clk,
3213          .enable = _clk_enable,
3214          .enable_reg = MXC_CCM_CCGR5,
3215          .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
3216          .disable = _clk_disable,
3217          .secondary = &spdif0_clk[1],
3218          .set_rate = _clk_spdif0_set_rate,
3219          .get_rate = _clk_spdif0_get_rate,
3220          .set_parent = _clk_spdif0_set_parent,
3221          .round_rate = _clk_spdif_round_rate,
3222         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
3223         },
3224         {
3225         __INIT_CLK_DEBUG(spdif0_clk_1)
3226          .id = 1,
3227          .parent = &ipg_clk,
3228          .secondary = &spba_clk,
3229          },
3230 };
3231
3232 static unsigned long _clk_esai_round_rate(struct clk *clk,
3233                                                 unsigned long rate)
3234 {
3235         u32 pre, post;
3236         u32 parent_rate = clk_get_rate(clk->parent);
3237         u32 div = parent_rate / rate;
3238
3239         if (parent_rate % rate)
3240                 div++;
3241
3242         __calc_pre_post_dividers(1 << 3, div, &pre, &post);
3243
3244         return parent_rate / (pre * post);
3245 }
3246
3247 static int _clk_esai_set_parent(struct clk *clk, struct clk *parent)
3248 {
3249         u32 reg, mux;
3250
3251         reg = __raw_readl(MXC_CCM_CSCMR2) & ~MXC_CCM_CSCMR2_ESAI_CLK_SEL_MASK;
3252
3253         mux = _get_mux6(parent, &pll4_audio_main_clk, &pll3_pfd_508M,
3254                         &pll3_pfd_454M, &pll3_sw_clk, NULL, NULL);
3255         reg |= mux << MXC_CCM_CSCMR2_ESAI_CLK_SEL_OFFSET;
3256
3257         __raw_writel(reg, MXC_CCM_CSCMR2);
3258
3259         return 0;
3260 }
3261
3262 static unsigned long _clk_esai_get_rate(struct clk *clk)
3263 {
3264         u32 reg, pred, podf;
3265
3266         reg = __raw_readl(MXC_CCM_CS1CDR);
3267
3268         pred = ((reg & MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK)
3269                 >> MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET) + 1;
3270         podf = ((reg & MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK)
3271                 >> MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET) + 1;
3272
3273         return clk_get_rate(clk->parent) / (pred * podf);
3274 }
3275
3276 static int _clk_esai_set_rate(struct clk *clk, unsigned long rate)
3277 {
3278         u32 reg, div, pre, post;
3279         u32 parent_rate = clk_get_rate(clk->parent);
3280
3281         div = parent_rate / rate;
3282         if (div == 0)
3283                 div++;
3284         if (((parent_rate / div) != rate) || div > 64)
3285                 return -EINVAL;
3286
3287         __calc_pre_post_dividers(1 << 3, div, &pre, &post);
3288
3289         reg = __raw_readl(MXC_CCM_CS1CDR);
3290         reg &= ~(MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK|
3291                  MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK);
3292         reg |= (post - 1) << MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET;
3293         reg |= (pre - 1) << MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET;
3294
3295         __raw_writel(reg, MXC_CCM_CS1CDR);
3296
3297         return 0;
3298 }
3299
3300 static struct clk esai_clk = {
3301         __INIT_CLK_DEBUG(esai_clk)
3302          .id = 0,
3303          .parent = &pll3_sw_clk,
3304          .secondary = &spba_clk,
3305          .enable_reg = MXC_CCM_CCGR1,
3306          .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET,
3307          .enable = _clk_enable,
3308          .disable = _clk_disable,
3309          .set_rate = _clk_esai_set_rate,
3310          .get_rate = _clk_esai_get_rate,
3311          .set_parent = _clk_esai_set_parent,
3312          .round_rate = _clk_esai_round_rate,
3313 };
3314
3315 static int _clk_enet_enable(struct clk *clk)
3316 {
3317         unsigned int reg;
3318
3319         /* Enable ENET ref clock */
3320         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
3321         reg &= ~ANADIG_PLL_BYPASS;
3322         reg &= ~ANADIG_PLL_ENABLE;
3323         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
3324
3325         _clk_enable(clk);
3326         return 0;
3327 }
3328
3329 static void _clk_enet_disable(struct clk *clk)
3330 {
3331         unsigned int reg;
3332
3333         _clk_disable(clk);
3334
3335         /* Enable ENET ref clock */
3336         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
3337         reg |= ANADIG_PLL_BYPASS;
3338         reg |= ANADIG_PLL_ENABLE;
3339         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
3340 }
3341
3342 static int _clk_enet_set_rate(struct clk *clk, unsigned long rate)
3343 {
3344         unsigned int reg, div = 1;
3345
3346         switch (rate) {
3347         case 25000000:
3348                 div = 0;
3349                 break;
3350         case 50000000:
3351                 div = 1;
3352                 break;
3353         case 100000000:
3354                 div = 2;
3355                 break;
3356         case 125000000:
3357                 div = 3;
3358                 break;
3359         default:
3360                 return -EINVAL;
3361         }
3362         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
3363         reg &= ~ANADIG_PLL_ENET_DIV_SELECT_MASK;
3364         reg |= (div << ANADIG_PLL_ENET_DIV_SELECT_OFFSET);
3365         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
3366
3367         return 0;
3368 }
3369
3370 static unsigned long _clk_enet_get_rate(struct clk *clk)
3371 {
3372         unsigned int div;
3373
3374         div = (__raw_readl(PLL8_ENET_BASE_ADDR))
3375                 & ANADIG_PLL_ENET_DIV_SELECT_MASK;
3376
3377         switch (div) {
3378         case 0:
3379                 div = 20;
3380                 break;
3381         case 1:
3382                 div = 10;
3383                 break;
3384         case 3:
3385                 div = 5;
3386                 break;
3387         case 4:
3388                 div = 4;
3389                 break;
3390         }
3391
3392         return 500000000 / div;
3393 }
3394
3395 static struct clk enet_clk[] = {
3396         {
3397         __INIT_CLK_DEBUG(enet_clk)
3398          .id = 0,
3399          .parent = &pll8_enet_main_clk,
3400          .enable_reg = MXC_CCM_CCGR1,
3401          .enable_shift = MXC_CCM_CCGRx_CG5_OFFSET,
3402          .enable = _clk_enet_enable,
3403          .disable = _clk_enet_disable,
3404          .set_rate = _clk_enet_set_rate,
3405          .get_rate = _clk_enet_get_rate,
3406         .secondary = &enet_clk[1],
3407         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
3408         },
3409         {
3410         .parent = &mmdc_ch0_axi_clk[0],
3411         .secondary = &mx6per1_clk,
3412         },
3413 };
3414
3415 static struct clk ecspi_clk[] = {
3416         {
3417         __INIT_CLK_DEBUG(ecspi0_clk)
3418         .id = 0,
3419         .parent = &pll3_60M,
3420         .secondary = &spba_clk,
3421         .enable_reg = MXC_CCM_CCGR1,
3422         .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET,
3423         .enable = _clk_enable,
3424         .disable = _clk_disable,
3425         },
3426         {
3427         __INIT_CLK_DEBUG(ecspi1_clk)
3428         .id = 1,
3429         .parent = &pll3_60M,
3430         .secondary = &spba_clk,
3431         .enable_reg = MXC_CCM_CCGR1,
3432         .enable_shift = MXC_CCM_CCGRx_CG1_OFFSET,
3433         .enable = _clk_enable,
3434         .disable = _clk_disable,
3435         },
3436         {
3437         __INIT_CLK_DEBUG(ecspi2_clk)
3438         .id = 2,
3439         .parent = &pll3_60M,
3440         .secondary = &spba_clk,
3441         .enable_reg = MXC_CCM_CCGR1,
3442         .enable_shift = MXC_CCM_CCGRx_CG2_OFFSET,
3443         .enable = _clk_enable,
3444         .disable = _clk_disable,
3445         },
3446         {
3447         __INIT_CLK_DEBUG(ecspi3_clk)
3448         .id = 3,
3449         .parent = &pll3_60M,
3450         .secondary = &spba_clk,
3451         .enable_reg = MXC_CCM_CCGR1,
3452         .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET,
3453         .enable = _clk_enable,
3454         .disable = _clk_disable,
3455         },
3456         {
3457         __INIT_CLK_DEBUG(ecspi4_clk)
3458         .id = 4,
3459         .parent = &pll3_60M,
3460         .secondary = &spba_clk,
3461         .enable_reg = MXC_CCM_CCGR1,
3462         .enable_shift = MXC_CCM_CCGRx_CG4_OFFSET,
3463         .enable = _clk_enable,
3464         .disable = _clk_disable,
3465         },
3466 };
3467
3468 static unsigned long _clk_emi_slow_round_rate(struct clk *clk,
3469                                                 unsigned long rate)
3470 {
3471         u32 div;
3472         u32 parent_rate = clk_get_rate(clk->parent);
3473
3474         div = parent_rate / rate;
3475
3476         /* Make sure rate is not greater than the maximum value for the clock.
3477          * Also prevent a div of 0.
3478          */
3479         if (div == 0)
3480                 div++;
3481
3482         if (div > 8)
3483                 div = 8;
3484
3485         return parent_rate / div;
3486 }
3487
3488 static int _clk_emi_slow_set_parent(struct clk *clk, struct clk *parent)
3489 {
3490         int mux;
3491         u32 reg = __raw_readl(MXC_CCM_CSCMR1)
3492                 & ~MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK;
3493
3494         mux = _get_mux6(parent, &axi_clk, &pll3_usb_otg_main_clk,
3495                                 &pll2_pfd_400M, &pll2_pfd_352M, NULL, NULL);
3496         reg |= (mux << MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET);
3497         __raw_writel(reg, MXC_CCM_CSCMR1);
3498
3499         return 0;
3500 }
3501
3502 static unsigned long _clk_emi_slow_get_rate(struct clk *clk)
3503 {
3504         u32 reg, div;
3505
3506         reg = __raw_readl(MXC_CCM_CSCMR1);
3507         div = ((reg & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK) >>
3508                         MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET) + 1;
3509
3510         return clk_get_rate(clk->parent) / div;
3511 }
3512
3513 static int _clk_emi_slow_set_rate(struct clk *clk, unsigned long rate)
3514 {
3515         u32 reg, div;
3516         u32 parent_rate = clk_get_rate(clk->parent);
3517
3518         div = parent_rate / rate;
3519         if (div == 0)
3520                 div++;
3521         if (((parent_rate / div) != rate) || (div > 8))
3522                 return -EINVAL;
3523
3524         reg = __raw_readl(MXC_CCM_CSCMR1);
3525         reg &= ~MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK;
3526         reg |= (div - 1) << MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET;
3527         __raw_writel(reg, MXC_CCM_CSCMR1);
3528
3529         return 0;
3530 }
3531
3532 static struct clk emi_slow_clk = {
3533         __INIT_CLK_DEBUG(emi_slow_clk)
3534          .id = 0,
3535          .parent = &axi_clk,
3536          .enable_reg = MXC_CCM_CCGR6,
3537          .enable_shift = MXC_CCM_CCGRx_CG5_OFFSET,
3538          .enable = _clk_enable,
3539          .disable = _clk_disable,
3540          .set_rate = _clk_emi_slow_set_rate,
3541          .get_rate = _clk_emi_slow_get_rate,
3542          .round_rate = _clk_emi_slow_round_rate,
3543          .set_parent = _clk_emi_slow_set_parent,
3544 };
3545
3546 static unsigned long _clk_emi_round_rate(struct clk *clk,
3547                                                 unsigned long rate)
3548 {
3549         u32 div;
3550         u32 parent_rate = clk_get_rate(clk->parent);
3551
3552         div = parent_rate / rate;
3553
3554         /* Make sure rate is not greater than the maximum value for the clock.
3555          * Also prevent a div of 0.
3556          */
3557         if (div == 0)
3558                 div++;
3559
3560         if (div > 8)
3561                 div = 8;
3562
3563         return parent_rate / div;
3564 }
3565
3566 static int _clk_emi_set_parent(struct clk *clk, struct clk *parent)
3567 {
3568         int mux;
3569         u32 reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_ACLK_EMI_MASK;
3570
3571         mux = _get_mux6(parent, &axi_clk, &pll3_usb_otg_main_clk,
3572                         &pll2_pfd_400M, &pll2_pfd_352M, NULL, NULL);
3573         reg |= (mux << MXC_CCM_CSCMR1_ACLK_EMI_OFFSET);
3574         __raw_writel(reg, MXC_CCM_CSCMR1);
3575
3576         return 0;
3577 }
3578
3579 static unsigned long _clk_emi_get_rate(struct clk *clk)
3580 {
3581         u32 reg, div;
3582
3583         reg = __raw_readl(MXC_CCM_CSCMR1);
3584         div = ((reg & MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK) >>
3585                         MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET) + 1;
3586
3587         return clk_get_rate(clk->parent) / div;
3588 }
3589
3590 static int _clk_emi_set_rate(struct clk *clk, unsigned long rate)
3591 {
3592         u32 reg, div;
3593         u32 parent_rate = clk_get_rate(clk->parent);
3594
3595         div = parent_rate / rate;
3596         if (div == 0)
3597                 div++;
3598         if (((parent_rate / div) != rate) || (div > 8))
3599                 return -EINVAL;
3600
3601         reg = __raw_readl(MXC_CCM_CSCMR1);
3602         reg &= ~MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK;
3603         reg |= (div - 1) << MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET;
3604         __raw_writel(reg, MXC_CCM_CSCMR1);
3605
3606         return 0;
3607 }
3608
3609 static struct clk emi_clk = {
3610         __INIT_CLK_DEBUG(emi_clk)
3611          .id = 0,
3612          .parent = &axi_clk,
3613          .set_rate = _clk_emi_set_rate,
3614          .get_rate = _clk_emi_get_rate,
3615          .round_rate = _clk_emi_round_rate,
3616          .set_parent = _clk_emi_set_parent,
3617 };
3618
3619 static unsigned long _clk_enfc_round_rate(struct clk *clk,
3620                                                 unsigned long rate)
3621 {
3622         u32 pre, post;
3623         u32 parent_rate = clk_get_rate(clk->parent);
3624         u32 div = parent_rate / rate;
3625
3626         if (parent_rate % rate)
3627                 div++;
3628
3629         __calc_pre_post_dividers(1 << 6, div, &pre, &post);
3630
3631         return parent_rate / (pre * post);
3632 }
3633
3634 static int _clk_enfc_set_parent(struct clk *clk, struct clk *parent)
3635 {
3636         u32 reg, mux;
3637
3638         reg = __raw_readl(MXC_CCM_CS2CDR)
3639                 & ~MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK;
3640
3641         mux = _get_mux6(parent, &pll2_pfd_352M,
3642                 &pll2_528_bus_main_clk, &pll3_usb_otg_main_clk,
3643                 &pll2_pfd_400M, NULL, NULL);
3644         reg |= mux << MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET;
3645
3646         __raw_writel(reg, MXC_CCM_CS2CDR);
3647
3648         return 0;
3649 }
3650
3651 static unsigned long _clk_enfc_get_rate(struct clk *clk)
3652 {
3653         u32 reg, pred, podf;
3654
3655         reg = __raw_readl(MXC_CCM_CS2CDR);
3656
3657         pred = ((reg & MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK)
3658                 >> MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET) + 1;
3659         podf = ((reg & MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK)
3660                 >> MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET) + 1;
3661
3662         return clk_get_rate(clk->parent) / (pred * podf);
3663 }
3664
3665 static int _clk_enfc_set_rate(struct clk *clk, unsigned long rate)
3666 {
3667         u32 reg, div, pre, post;
3668         u32 parent_rate = clk_get_rate(clk->parent);
3669
3670         div = parent_rate / rate;
3671         if (div == 0)
3672                 div++;
3673         if (((parent_rate / div) != rate) || div > 512)
3674                 return -EINVAL;
3675
3676         __calc_pre_post_dividers(1 << 6, div, &pre, &post);
3677
3678         reg = __raw_readl(MXC_CCM_CS2CDR);
3679         reg &= ~(MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK|
3680                  MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK);
3681         reg |= (post - 1) << MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET;
3682         reg |= (pre - 1) << MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET;
3683
3684         __raw_writel(reg, MXC_CCM_CS2CDR);
3685
3686         return 0;
3687 }
3688
3689 static struct clk enfc_clk = {
3690         __INIT_CLK_DEBUG(enfc_clk)
3691          .id = 0,
3692          .parent = &pll2_pfd_352M,
3693          .enable_reg = MXC_CCM_CCGR2,
3694          .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
3695          .enable = _clk_enable,
3696          .disable = _clk_disable,
3697          .set_rate = _clk_enfc_set_rate,
3698          .get_rate = _clk_enfc_get_rate,
3699          .round_rate = _clk_enfc_round_rate,
3700          .set_parent = _clk_enfc_set_parent,
3701 };
3702
3703 static unsigned long _clk_uart_round_rate(struct clk *clk,
3704                                                 unsigned long rate)
3705 {
3706         u32 div;
3707         u32 parent_rate = clk_get_rate(clk->parent);
3708
3709         div = parent_rate / rate;
3710
3711         /* Make sure rate is not greater than the maximum value for the clock.
3712          * Also prevent a div of 0.
3713          */
3714         if (div == 0)
3715                 div++;
3716
3717         if (div > 64)
3718                 div = 64;
3719
3720         return parent_rate / div;
3721 }
3722
3723 static int _clk_uart_set_rate(struct clk *clk, unsigned long rate)
3724 {
3725         u32 reg, div;
3726         u32 parent_rate = clk_get_rate(clk->parent);
3727
3728         div = parent_rate / rate;
3729         if (div == 0)
3730                 div++;
3731         if (((parent_rate / div) != rate) || (div > 64))
3732                 return -EINVAL;
3733
3734         reg = __raw_readl(MXC_CCM_CSCDR1) & MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
3735         reg |= ((div - 1) << MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET);
3736
3737         __raw_writel(reg, MXC_CCM_CSCDR1);
3738
3739         return 0;
3740 }
3741
3742 static unsigned long _clk_uart_get_rate(struct clk *clk)
3743 {
3744         u32 reg, div;
3745         unsigned long val;
3746
3747         reg = __raw_readl(MXC_CCM_CSCDR1) & MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
3748         div = (reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET) + 1;
3749         val = clk_get_rate(clk->parent) / div;
3750
3751         return val;
3752 }
3753
3754 static struct clk uart_clk[] = {
3755         {
3756         __INIT_CLK_DEBUG(uart_clk)
3757          .id = 0,
3758          .parent = &pll3_80M,
3759          .enable_reg = MXC_CCM_CCGR5,
3760          .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET,
3761          .enable = _clk_enable,
3762          .disable = _clk_disable,
3763          .secondary = &uart_clk[1],
3764          .set_rate = _clk_uart_set_rate,
3765          .get_rate = _clk_uart_get_rate,
3766          .round_rate = _clk_uart_round_rate,
3767         },
3768         {
3769         __INIT_CLK_DEBUG(uart_serial_clk)
3770          .id = 1,
3771          .enable_reg = MXC_CCM_CCGR5,
3772          .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
3773          .enable = _clk_enable,
3774          .disable = _clk_disable,
3775         },
3776 };
3777
3778 static unsigned long _clk_hsi_tx_round_rate(struct clk *clk,
3779                                                 unsigned long rate)
3780 {
3781         u32 div;
3782         u32 parent_rate = clk_get_rate(clk->parent);
3783
3784         div = parent_rate / rate;
3785
3786         /* Make sure rate is not greater than the maximum value for the clock.
3787          * Also prevent a div of 0.
3788          */
3789         if (div == 0)
3790                 div++;
3791
3792         if (div > 8)
3793                 div = 8;
3794
3795         return parent_rate / div;
3796 }
3797
3798 static int _clk_hsi_tx_set_parent(struct clk *clk, struct clk *parent)
3799 {
3800         u32 reg = __raw_readl(MXC_CCM_CDCDR) & ~MXC_CCM_CDCDR_HSI_TX_CLK_SEL;
3801
3802         if (parent == &pll2_pfd_400M)
3803                 reg |= (MXC_CCM_CDCDR_HSI_TX_CLK_SEL);
3804
3805         __raw_writel(reg, MXC_CCM_CDCDR);
3806
3807         return 0;
3808 }
3809
3810 static unsigned long _clk_hsi_tx_get_rate(struct clk *clk)
3811 {
3812         u32 reg, div;
3813
3814         reg = __raw_readl(MXC_CCM_CDCDR);
3815         div = ((reg & MXC_CCM_CDCDR_HSI_TX_PODF_MASK) >>
3816                         MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET) + 1;
3817
3818         return clk_get_rate(clk->parent) / div;
3819 }
3820
3821 static int _clk_hsi_tx_set_rate(struct clk *clk, unsigned long rate)
3822 {
3823         u32 reg, div;
3824         u32 parent_rate = clk_get_rate(clk->parent);
3825
3826         div = parent_rate / rate;
3827         if (div == 0)
3828                 div++;
3829         if (((parent_rate / div) != rate) || (div > 8))
3830                 return -EINVAL;
3831
3832         reg = __raw_readl(MXC_CCM_CDCDR);
3833         reg &= ~MXC_CCM_CDCDR_HSI_TX_PODF_MASK;
3834         reg |= (div - 1) << MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET;
3835         __raw_writel(reg, MXC_CCM_CDCDR);
3836
3837         return 0;
3838 }
3839
3840 static struct clk hsi_tx_clk[] = {
3841         {
3842          __INIT_CLK_DEBUG(hsi_tx_clk)
3843         .id = 0,
3844          .parent = &pll2_pfd_400M,
3845         .enable_reg = MXC_CCM_CCGR3,
3846         .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET,
3847         .enable = _clk_enable,
3848         .disable = _clk_disable,
3849         .set_parent = _clk_hsi_tx_set_parent,
3850         .round_rate = _clk_hsi_tx_round_rate,
3851         .set_rate = _clk_hsi_tx_set_rate,
3852         .get_rate = _clk_hsi_tx_get_rate,
3853          .secondary = &hsi_tx_clk[1],
3854         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
3855         },
3856         {
3857         .parent = &mx6per1_clk,
3858         .secondary = &mx6per2_clk,
3859          },
3860 };
3861
3862 static struct clk mipi_pllref_clk = {
3863          __INIT_CLK_DEBUG(mipi_pllref_clk)
3864         .id = 0,
3865         .parent = &pll3_pfd_540M,
3866         .enable_reg = MXC_CCM_CCGR3,
3867         .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET,
3868         .enable = _clk_enable,
3869         .disable = _clk_disable,
3870 };
3871
3872 static struct clk hdmi_clk[] = {
3873         {
3874          __INIT_CLK_DEBUG(hdmi_isfr_clk)
3875         .id = 0,
3876         .parent = &pll3_pfd_540M,
3877         .enable_reg = MXC_CCM_CCGR2,
3878         .enable_shift = MXC_CCM_CCGRx_CG2_OFFSET,
3879         .enable = _clk_enable,
3880         .disable = _clk_disable,
3881         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
3882         },
3883         {
3884          __INIT_CLK_DEBUG(hdmi_iahb_clk)
3885         .id = 1,
3886          .parent = &ahb_clk,
3887         .enable_reg = MXC_CCM_CCGR2,
3888         .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET,
3889         .enable = _clk_enable,
3890         .disable = _clk_disable,
3891         },
3892 };
3893
3894 static struct clk caam_clk[] = {
3895         {
3896          __INIT_CLK_DEBUG(caam_mem_clk)
3897         .id = 0,
3898         .enable_reg = MXC_CCM_CCGR0,
3899         .enable_shift = MXC_CCM_CCGRx_CG4_OFFSET,
3900         .enable = _clk_enable,
3901         .disable = _clk_disable,
3902         .secondary = &caam_clk[1],
3903         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
3904         },
3905         {
3906          __INIT_CLK_DEBUG(caam_aclk_clk)
3907         .id = 1,
3908         .enable_reg = MXC_CCM_CCGR0,
3909         .enable_shift = MXC_CCM_CCGRx_CG5_OFFSET,
3910         .enable = _clk_enable,
3911         .disable = _clk_disable,
3912         .secondary = &caam_clk[2],
3913         },
3914         {
3915          __INIT_CLK_DEBUG(caam_ipg_clk)
3916         .id = 2,
3917         .enable_reg = MXC_CCM_CCGR0,
3918         .enable_shift = MXC_CCM_CCGRx_CG4_OFFSET,
3919         .enable = _clk_enable,
3920         .disable = _clk_disable,
3921         .parent = &mmdc_ch0_axi_clk[0],
3922         .secondary = &mx6per1_clk,
3923         },
3924 };
3925
3926 static int _clk_asrc_serial_set_parent(struct clk *clk, struct clk *parent)
3927 {
3928         u32 reg, mux;
3929
3930         reg = __raw_readl(MXC_CCM_CDCDR) & ~MXC_CCM_CDCDR_SPDIF1_CLK_SEL_MASK;
3931
3932         mux = _get_mux6(parent, &pll4_audio_main_clk, &pll3_pfd_508M,
3933                         &pll3_pfd_454M, &pll3_sw_clk, NULL, NULL);
3934         reg |= mux << MXC_CCM_CDCDR_SPDIF1_CLK_SEL_OFFSET;
3935
3936         __raw_writel(reg, MXC_CCM_CDCDR);
3937
3938         return 0;
3939 }
3940
3941 static unsigned long _clk_asrc_serial_get_rate(struct clk *clk)
3942 {
3943         u32 reg, pred, podf;
3944
3945         reg = __raw_readl(MXC_CCM_CDCDR);
3946
3947         pred = ((reg & MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK)
3948                 >> MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET) + 1;
3949         podf = ((reg & MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK)
3950                 >> MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET) + 1;
3951
3952         return clk_get_rate(clk->parent) / (pred * podf);
3953 }
3954
3955 static int _clk_asrc_serial_set_rate(struct clk *clk, unsigned long rate)
3956 {
3957         u32 reg, div, pre, post;
3958         u32 parent_rate = clk_get_rate(clk->parent);
3959
3960         div = parent_rate / rate;
3961         if (div == 0)
3962                 div++;
3963         if (((parent_rate / div) != rate) || div > 64)
3964                 return -EINVAL;
3965
3966         __calc_pre_post_dividers(1 << 3, div, &pre, &post);
3967
3968         reg = __raw_readl(MXC_CCM_CDCDR);
3969         reg &= ~(MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK|
3970                  MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK);
3971         reg |= (post - 1) << MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET;
3972         reg |= (pre - 1) << MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET;
3973
3974         __raw_writel(reg, MXC_CCM_CDCDR);
3975
3976         return 0;
3977 }
3978
3979 static unsigned long _clk_asrc_serial_round_rate(struct clk *clk,
3980                                                 unsigned long rate)
3981 {
3982         u32 pre, post;
3983         u32 parent_rate = clk_get_rate(clk->parent);
3984         u32 div = parent_rate / rate;
3985
3986         if (parent_rate % rate)
3987                 div++;
3988
3989         __calc_pre_post_dividers(1 << 3, div, &pre, &post);
3990
3991         return parent_rate / (pre * post);
3992 }
3993
3994 static struct clk asrc_clk[] = {
3995         {
3996         __INIT_CLK_DEBUG(asrc_clk)
3997         .id = 0,
3998         .parent = &pll4_audio_main_clk,
3999         .enable_reg = MXC_CCM_CCGR0,
4000         .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET,
4001         .enable = _clk_enable,
4002         .disable = _clk_disable,
4003         .secondary = &spba_clk,
4004         },
4005         {
4006         /*In the MX6 spec, asrc_serial_clk is listed as SPDIF1 clk
4007          * This clock can never be gated and does  not have any
4008          * CCGR bits associated with it.
4009          */
4010         __INIT_CLK_DEBUG(asrc_serial_clk)
4011         .id = 1,
4012         .parent = &pll3_sw_clk,
4013          .set_rate = _clk_asrc_serial_set_rate,
4014          .get_rate = _clk_asrc_serial_get_rate,
4015          .set_parent = _clk_asrc_serial_set_parent,
4016          .round_rate = _clk_asrc_serial_round_rate,
4017         },
4018 };
4019
4020 static struct clk apbh_dma_clk = {
4021         __INIT_CLK_DEBUG(apbh_dma_clk)
4022         .parent = &usdhc3_clk,
4023         .secondary = &mx6per1_clk,
4024         .enable = _clk_enable,
4025         .disable = _clk_disable_inwait,
4026         .enable_reg = MXC_CCM_CCGR0,
4027         .enable_shift = MXC_CCM_CCGRx_CG2_OFFSET,
4028 };
4029
4030 static struct clk aips_tz2_clk = {
4031         __INIT_CLK_DEBUG(aips_tz2_clk)
4032         .parent = &ahb_clk,
4033         .enable_reg = MXC_CCM_CCGR0,
4034         .enable_shift = MXC_CCM_CCGRx_CG1_OFFSET,
4035         .enable = _clk_enable,
4036         .disable = _clk_disable_inwait,
4037 };
4038
4039 static struct clk aips_tz1_clk = {
4040         __INIT_CLK_DEBUG(aips_tz1_clk)
4041         .parent = &ahb_clk,
4042         .enable_reg = MXC_CCM_CCGR0,
4043         .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET,
4044         .enable = _clk_enable,
4045         .disable = _clk_disable_inwait,
4046 };
4047
4048
4049 static struct clk openvg_axi_clk = {
4050         __INIT_CLK_DEBUG(openvg_axi_clk)
4051         .parent = &gpu2d_axi_clk,
4052         .enable = _clk_enable,
4053         .enable_reg = MXC_CCM_CCGR3,
4054         .enable_shift = MXC_CCM_CCGRx_CG15_OFFSET,
4055         .disable = _clk_disable,
4056         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
4057 };
4058
4059 static unsigned long _clk_gpu3d_core_round_rate(struct clk *clk,
4060                                                 unsigned long rate)
4061 {
4062         u32 div;
4063         u32 parent_rate = clk_get_rate(clk->parent);
4064
4065         div = parent_rate / rate;
4066
4067         /* Make sure rate is not greater than the maximum value for the clock.
4068          * Also prevent a div of 0.
4069          */
4070         if (div == 0)
4071                 div++;
4072
4073         if (div > 8)
4074                 div = 8;
4075
4076         return parent_rate / div;
4077 }
4078
4079 static int _clk_gpu3d_core_set_parent(struct clk *clk, struct clk *parent)
4080 {
4081         int mux;
4082         u32 reg = __raw_readl(MXC_CCM_CBCMR)
4083                 & ~MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK;
4084
4085         mux = _get_mux6(parent, &mmdc_ch0_axi_clk[0],
4086                 &pll3_usb_otg_main_clk,
4087                 &pll2_pfd_594M, &pll2_pfd_400M, NULL, NULL);
4088         reg |= (mux << MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET);
4089         __raw_writel(reg, MXC_CCM_CBCMR);
4090
4091         return 0;
4092 }
4093
4094 static unsigned long _clk_gpu3d_core_get_rate(struct clk *clk)
4095 {
4096         u32 reg, div;
4097
4098         reg = __raw_readl(MXC_CCM_CBCMR);
4099         div = ((reg & MXC_CCM_CBCMR_GPU3D_CORE_PODF_MASK) >>
4100                         MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET) + 1;
4101
4102         return clk_get_rate(clk->parent) / div;
4103 }
4104
4105 static int _clk_gpu3d_core_set_rate(struct clk *clk, unsigned long rate)
4106 {
4107         u32 reg, div;
4108         u32 parent_rate = clk_get_rate(clk->parent);
4109
4110         div = parent_rate / rate;
4111         if (div == 0)
4112                 div++;
4113         if (div > 8)
4114                 div = 8;
4115
4116         reg = __raw_readl(MXC_CCM_CBCMR);
4117         reg &= ~MXC_CCM_CBCMR_GPU3D_CORE_PODF_MASK;
4118         reg |= (div - 1) << MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET;
4119         __raw_writel(reg, MXC_CCM_CBCMR);
4120
4121         return 0;
4122 }
4123
4124 static struct clk gpu3d_core_clk[] = {
4125         {
4126         __INIT_CLK_DEBUG(gpu3d_core_clk)
4127         .parent = &pll2_pfd_594M,
4128         .enable = _clk_enable,
4129         .enable_reg = MXC_CCM_CCGR1,
4130         .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
4131         .disable = _clk_disable,
4132         .set_parent = _clk_gpu3d_core_set_parent,
4133         .set_rate = _clk_gpu3d_core_set_rate,
4134         .get_rate = _clk_gpu3d_core_get_rate,
4135         .round_rate = _clk_gpu3d_core_round_rate,
4136         .secondary = &gpu3d_core_clk[1],
4137         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
4138         },
4139         {
4140         .parent = &gpu3d_axi_clk,
4141         .secondary = &mx6fast1_clk,
4142         },
4143 };
4144
4145 static unsigned long _clk_gpu2d_core_round_rate(struct clk *clk,
4146                                                 unsigned long rate)
4147 {
4148         u32 div;
4149         u32 parent_rate = clk_get_rate(clk->parent);
4150
4151         div = parent_rate / rate;
4152
4153         /* Make sure rate is not greater than the maximum value for the clock.
4154          * Also prevent a div of 0.
4155          */
4156         if (div == 0)
4157                 div++;
4158
4159         if (div > 8)
4160                 div = 8;
4161
4162         return parent_rate / div;
4163 }
4164
4165 static int _clk_gpu2d_core_set_parent(struct clk *clk, struct clk *parent)
4166 {
4167         int mux;
4168         u32 reg = __raw_readl(MXC_CCM_CBCMR) &
4169                                 ~MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK;
4170
4171         mux = _get_mux6(parent, &axi_clk, &pll3_usb_otg_main_clk,
4172                 &pll2_pfd_352M, &pll2_pfd_400M, NULL, NULL);
4173         reg |= (mux << MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET);
4174         __raw_writel(reg, MXC_CCM_CBCMR);
4175
4176         return 0;
4177 }
4178
4179 static unsigned long _clk_gpu2d_core_get_rate(struct clk *clk)
4180 {
4181         u32 reg, div;
4182
4183         reg = __raw_readl(MXC_CCM_CBCMR);
4184         div = ((reg & MXC_CCM_CBCMR_GPU2D_CORE_PODF_MASK) >>
4185                         MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET) + 1;
4186
4187         return clk_get_rate(clk->parent) / div;
4188 }
4189
4190 static int _clk_gpu2d_core_set_rate(struct clk *clk, unsigned long rate)
4191 {
4192         u32 reg, div;
4193         u32 parent_rate = clk_get_rate(clk->parent);
4194
4195         div = parent_rate / rate;
4196         if (div == 0)
4197                 div++;
4198         if (((parent_rate / div) != rate) || (div > 8))
4199                 return -EINVAL;
4200
4201         reg = __raw_readl(MXC_CCM_CBCMR);
4202         reg &= ~MXC_CCM_CBCMR_GPU3D_CORE_PODF_MASK;
4203         reg |= (div - 1) << MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET;
4204         __raw_writel(reg, MXC_CCM_CBCMR);
4205
4206         return 0;
4207 }
4208 static struct clk gpu2d_core_clk[] = {
4209         {
4210         __INIT_CLK_DEBUG(gpu2d_core_clk)
4211         .parent = &pll2_pfd_352M,
4212         .enable = _clk_enable,
4213         .enable_reg = MXC_CCM_CCGR1,
4214         .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET,
4215         .disable = _clk_disable,
4216         .set_parent = _clk_gpu2d_core_set_parent,
4217         .set_rate = _clk_gpu2d_core_set_rate,
4218         .get_rate = _clk_gpu2d_core_get_rate,
4219         .round_rate = _clk_gpu2d_core_round_rate,
4220         .secondary = &gpu2d_core_clk[1],
4221         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
4222         },
4223         {
4224         .parent = &gpu2d_axi_clk,
4225         .secondary = &mx6fast1_clk,
4226         },
4227 };
4228
4229 static unsigned long _clk_gpu3d_shader_round_rate(struct clk *clk,
4230                                                 unsigned long rate)
4231 {
4232         u32 div;
4233         u32 parent_rate = clk_get_rate(clk->parent);
4234
4235         div = parent_rate / rate;
4236
4237         /* Make sure rate is not greater than the maximum value for the clock.
4238          * Also prevent a div of 0.
4239          */
4240         if (div == 0)
4241                 div++;
4242
4243         if (div > 8)
4244                 div = 8;
4245
4246         return parent_rate / div;
4247 }
4248
4249 static int _clk_gpu3d_shader_set_parent(struct clk *clk, struct clk *parent)
4250 {
4251         int mux;
4252         u32 reg = __raw_readl(MXC_CCM_CBCMR)
4253                 & ~MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_MASK;
4254
4255         mux = _get_mux6(parent, &mmdc_ch0_axi_clk[0],
4256                 &pll3_usb_otg_main_clk,
4257                 &pll2_pfd_594M, &pll3_pfd_720M, NULL, NULL);
4258         reg |= (mux << MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET);
4259         __raw_writel(reg, MXC_CCM_CBCMR);
4260
4261         return 0;
4262 }
4263
4264 static unsigned long _clk_gpu3d_shader_get_rate(struct clk *clk)
4265 {
4266         u32 reg, div;
4267
4268         reg = __raw_readl(MXC_CCM_CBCMR);
4269         div = ((reg & MXC_CCM_CBCMR_GPU3D_SHADER_PODF_MASK) >>
4270                         MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET) + 1;
4271
4272         return clk_get_rate(clk->parent) / div;
4273 }
4274
4275 static int _clk_gpu3d_shader_set_rate(struct clk *clk, unsigned long rate)
4276 {
4277         u32 reg, div;
4278         u32 parent_rate = clk_get_rate(clk->parent);
4279
4280         div = parent_rate / rate;
4281         if (div == 0)
4282                 div++;
4283         if (div > 8)
4284                 div = 8;
4285
4286         reg = __raw_readl(MXC_CCM_CBCMR);
4287         reg &= ~MXC_CCM_CBCMR_GPU3D_SHADER_PODF_MASK;
4288         reg |= (div - 1) << MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET;
4289         __raw_writel(reg, MXC_CCM_CBCMR);
4290
4291         return 0;
4292 }
4293
4294
4295 static struct clk gpu3d_shader_clk = {
4296         __INIT_CLK_DEBUG(gpu3d_shader_clk)
4297         .parent = &pll3_pfd_720M,
4298         .secondary = &mmdc_ch0_axi_clk[0],
4299         .enable = _clk_enable,
4300         .enable_reg = MXC_CCM_CCGR1,
4301         .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
4302         .disable = _clk_disable,
4303         .set_parent = _clk_gpu3d_shader_set_parent,
4304         .set_rate = _clk_gpu3d_shader_set_rate,
4305         .get_rate = _clk_gpu3d_shader_get_rate,
4306         .round_rate = _clk_gpu3d_shader_round_rate,
4307         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
4308 };
4309
4310 /* set the parent by the ipcg table */
4311 static struct clk gpmi_nfc_clk[] = {
4312         {       /* gpmi_io_clk */
4313         __INIT_CLK_DEBUG(gpmi_io_clk)
4314         .parent = &enfc_clk,
4315         .secondary = &gpmi_nfc_clk[1],
4316         .enable = _clk_enable,
4317         .enable_reg = MXC_CCM_CCGR4,
4318         .enable_shift = MXC_CCM_CCGRx_CG14_OFFSET,
4319         .disable = _clk_disable,
4320         },
4321         {       /* gpmi_apb_clk */
4322         __INIT_CLK_DEBUG(gpmi_apb_clk)
4323         .parent = &usdhc3_clk,
4324         .secondary = &gpmi_nfc_clk[2],
4325         .enable = _clk_enable,
4326         .enable_reg = MXC_CCM_CCGR4,
4327         .enable_shift = MXC_CCM_CCGRx_CG15_OFFSET,
4328         .disable = _clk_disable,
4329         },
4330         {       /* bch_clk */
4331         __INIT_CLK_DEBUG(gpmi_bch_clk)
4332         .parent = &usdhc4_clk,
4333         .secondary = &gpmi_nfc_clk[3],
4334         .enable = _clk_enable,
4335         .enable_reg = MXC_CCM_CCGR4,
4336         .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
4337         .disable = _clk_disable,
4338         },
4339         {       /* bch_apb_clk */
4340         __INIT_CLK_DEBUG(gpmi_bch_apb_clk)
4341         .parent = &usdhc3_clk,
4342         .secondary = &gpmi_nfc_clk[4],
4343         .enable = _clk_enable,
4344         .enable_reg = MXC_CCM_CCGR4,
4345         .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET,
4346         .disable = _clk_disable,
4347         },
4348         {       /* bch relative clk */
4349         __INIT_CLK_DEBUG(pl301_mx6qperl_bch)
4350         .parent = &mx6per1_clk,
4351         .secondary = &mmdc_ch0_axi_clk[0],
4352         },
4353 };
4354
4355 static struct clk pwm_clk[] = {
4356         {
4357         __INIT_CLK_DEBUG(pwm_clk_0)
4358          .parent = &ipg_perclk,
4359          .id = 0,
4360          .enable_reg = MXC_CCM_CCGR4,
4361          .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET,
4362          .enable = _clk_enable,
4363          .disable = _clk_disable,
4364          },
4365         {
4366         __INIT_CLK_DEBUG(pwm_clk_1)
4367          .parent = &ipg_perclk,
4368          .id = 1,
4369          .enable_reg = MXC_CCM_CCGR4,
4370          .enable_shift = MXC_CCM_CCGRx_CG9_OFFSET,
4371          .enable = _clk_enable,
4372          .disable = _clk_disable,
4373          },
4374         {
4375         __INIT_CLK_DEBUG(pwm_clk_2)
4376          .parent = &ipg_perclk,
4377          .id = 2,
4378          .enable_reg = MXC_CCM_CCGR4,
4379          .enable_shift = MXC_CCM_CCGRx_CG10_OFFSET,
4380          .enable = _clk_enable,
4381          .disable = _clk_disable,
4382          },
4383         {
4384         __INIT_CLK_DEBUG(pwm_clk_3)
4385          .parent = &ipg_perclk,
4386          .id = 3,
4387          .enable_reg = MXC_CCM_CCGR4,
4388          .enable_shift = MXC_CCM_CCGRx_CG11_OFFSET,
4389          .enable = _clk_enable,
4390          .disable = _clk_disable,
4391          },
4392 };
4393
4394 static int _clk_pcie_enable(struct clk *clk)
4395 {
4396         unsigned int reg;
4397
4398         /* Enable SATA ref clock */
4399         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
4400         reg |= ANADIG_PLL_ENET_EN_PCIE;
4401         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
4402
4403         _clk_enable(clk);
4404
4405         return 0;
4406 }
4407
4408 static void _clk_pcie_disable(struct clk *clk)
4409 {
4410         unsigned int reg;
4411
4412         _clk_disable(clk);
4413
4414         /* Disable SATA ref clock */
4415         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
4416         reg &= ~ANADIG_PLL_ENET_EN_PCIE;
4417         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
4418 }
4419
4420 static struct clk pcie_clk[] = {
4421         {
4422         __INIT_CLK_DEBUG(pcie_clk)
4423         .parent = &pcie_axi_clk,
4424         .enable = _clk_pcie_enable,
4425         .disable = _clk_pcie_disable,
4426         .enable_reg = MXC_CCM_CCGR4,
4427         .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET,
4428         .secondary = &pcie_clk[1],
4429         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
4430         },
4431         {
4432         .parent = &mmdc_ch0_axi_clk[0],
4433         .secondary = &mx6fast1_clk,
4434         },
4435 };
4436
4437 static int _clk_sata_enable(struct clk *clk)
4438 {
4439         unsigned int reg;
4440
4441         /* Clear Power Down and Enable PLLs */
4442         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
4443         reg &= ~ANADIG_PLL_ENET_POWER_DOWN;
4444         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
4445
4446         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
4447         reg |= ANADIG_PLL_ENET_EN;
4448         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
4449
4450         /* Waiting for the PLL is locked */
4451         if (!WAIT(ANADIG_PLL_ENET_LOCK & __raw_readl(PLL8_ENET_BASE_ADDR),
4452                                 SPIN_DELAY))
4453                 panic("pll8 lock failed\n");
4454
4455         /* Disable the bypass */
4456         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
4457         reg &= ~ANADIG_PLL_ENET_BYPASS;
4458         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
4459
4460         /* Enable SATA ref clock */
4461         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
4462         reg |= ANADIG_PLL_ENET_EN_SATA;
4463         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
4464
4465         _clk_enable(clk);
4466
4467         return 0;
4468 }
4469
4470 static void _clk_sata_disable(struct clk *clk)
4471 {
4472         unsigned int reg;
4473
4474         _clk_disable(clk);
4475
4476         /* Disable SATA ref clock */
4477         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
4478         reg &= ~ANADIG_PLL_ENET_EN_SATA;
4479         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
4480 }
4481
4482 static struct clk sata_clk[] = {
4483         {
4484         __INIT_CLK_DEBUG(sata_clk)
4485         .parent = &ipg_clk,
4486         .enable = _clk_sata_enable,
4487         .enable_reg = MXC_CCM_CCGR5,
4488         .enable_shift = MXC_CCM_CCGRx_CG2_OFFSET,
4489         .disable = _clk_sata_disable,
4490         .secondary = &sata_clk[1],
4491         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
4492         },
4493         {
4494         .parent = &mmdc_ch0_axi_clk[0],
4495         .secondary = &mx6per1_clk,
4496         }
4497 };
4498
4499 static struct clk usboh3_clk[] = {
4500         {
4501         __INIT_CLK_DEBUG(usboh3_clk)
4502         .parent = &ahb_clk,
4503         .enable = _clk_enable,
4504         .enable_reg = MXC_CCM_CCGR6,
4505         .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET,
4506         .disable = _clk_disable,
4507         .secondary = &usboh3_clk[1],
4508         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
4509         },
4510         {
4511         .parent = &mmdc_ch0_axi_clk[0],
4512         .secondary = &mx6per1_clk,
4513         },
4514 };
4515
4516 static int _clk_enable1(struct clk *clk)
4517 {
4518         u32 reg;
4519         reg = __raw_readl(clk->enable_reg);
4520         reg |= 1 << clk->enable_shift;
4521         __raw_writel(reg, clk->enable_reg);
4522
4523         return 0;
4524 }
4525
4526 static void _clk_disable1(struct clk *clk)
4527 {
4528         u32 reg;
4529         reg = __raw_readl(clk->enable_reg);
4530         reg &= ~(1 << clk->enable_shift);
4531         __raw_writel(reg, clk->enable_reg);
4532 }
4533
4534 static int _clk_clko_set_parent(struct clk *clk, struct clk *parent)
4535 {
4536         u32 sel, reg;
4537
4538         if (parent == &pll3_usb_otg_main_clk)
4539                 sel = 0;
4540         else if (parent == &pll2_528_bus_main_clk)
4541                 sel = 1;
4542         else if (parent == &pll1_sys_main_clk)
4543                 sel = 2;
4544         else if (parent == &pll5_video_main_clk)
4545                 sel = 3;
4546         else if (parent == &axi_clk)
4547                 sel = 5;
4548         else if (parent == &enfc_clk)
4549                 sel = 6;
4550         else if (parent == &ipu1_di_clk[0])
4551                 sel = 7;
4552         else if (parent == &ipu1_di_clk[1])
4553                 sel = 8;
4554         else if (parent == &ipu2_di_clk[0])
4555                 sel = 9;
4556         else if (parent == &ipu2_di_clk[1])
4557                 sel = 10;
4558         else if (parent == &ahb_clk)
4559                 sel = 11;
4560         else if (parent == &ipg_clk)
4561                 sel = 12;
4562         else if (parent == &ipg_perclk)
4563                 sel = 13;
4564         else if (parent == &ckil_clk)
4565                 sel = 14;
4566         else if (parent == &pll4_audio_main_clk)
4567                 sel = 15;
4568         else
4569                 return -EINVAL;
4570
4571         reg = __raw_readl(MXC_CCM_CCOSR);
4572         reg &= ~MXC_CCM_CCOSR_CKOL_SEL_MASK;
4573         reg |= sel << MXC_CCM_CCOSR_CKOL_SEL_OFFSET;
4574         __raw_writel(reg, MXC_CCM_CCOSR);
4575         return 0;
4576 }
4577
4578 static unsigned long _clk_clko_get_rate(struct clk *clk)
4579 {
4580         u32 reg = __raw_readl(MXC_CCM_CCOSR);
4581         u32 div = ((reg & MXC_CCM_CCOSR_CKOL_DIV_MASK) >>
4582                         MXC_CCM_CCOSR_CKOL_DIV_OFFSET) + 1;
4583         return clk_get_rate(clk->parent) / div;
4584 }
4585
4586 static int _clk_clko_set_rate(struct clk *clk, unsigned long rate)
4587 {
4588         u32 reg;
4589         u32 parent_rate = clk_get_rate(clk->parent);
4590         u32 div = parent_rate / rate;
4591
4592         if (div == 0)
4593                 div++;
4594         if (((parent_rate / div) != rate) || (div > 8))
4595                 return -EINVAL;
4596
4597         reg = __raw_readl(MXC_CCM_CCOSR);
4598         reg &= ~MXC_CCM_CCOSR_CKOL_DIV_MASK;
4599         reg |= (div - 1) << MXC_CCM_CCOSR_CKOL_DIV_OFFSET;
4600         __raw_writel(reg, MXC_CCM_CCOSR);
4601         return 0;
4602 }
4603
4604 static unsigned long _clk_clko_round_rate(struct clk *clk,
4605                                                 unsigned long rate)
4606 {
4607         u32 parent_rate = clk_get_rate(clk->parent);
4608         u32 div = parent_rate / rate;
4609
4610         /* Make sure rate is not greater than the maximum value for the clock.
4611          * Also prevent a div of 0.
4612          */
4613         if (div == 0)
4614                 div++;
4615         if (div > 8)
4616                 div = 8;
4617         return parent_rate / div;
4618 }
4619
4620 static struct clk clko_clk = {
4621         __INIT_CLK_DEBUG(clko_clk)
4622         .parent = &pll2_528_bus_main_clk,
4623         .enable = _clk_enable1,
4624         .enable_reg = MXC_CCM_CCOSR,
4625         .enable_shift = MXC_CCM_CCOSR_CKOL_EN_OFFSET,
4626         .disable = _clk_disable1,
4627         .set_parent = _clk_clko_set_parent,
4628         .set_rate = _clk_clko_set_rate,
4629         .get_rate = _clk_clko_get_rate,
4630         .round_rate = _clk_clko_round_rate,
4631 };
4632
4633 static struct clk dummy_clk = {
4634         .id = 0,
4635 };
4636
4637 #define _REGISTER_CLOCK(d, n, c) \
4638         { \
4639                 .dev_id = d, \
4640                 .con_id = n, \
4641                 .clk = &c, \
4642         }
4643
4644
4645 static struct clk_lookup lookups[] = {
4646         _REGISTER_CLOCK(NULL, "osc", osc_clk),
4647         _REGISTER_CLOCK(NULL, "ckih", ckih_clk),
4648         _REGISTER_CLOCK(NULL, "ckih2", ckih2_clk),
4649         _REGISTER_CLOCK(NULL, "ckil", ckil_clk),
4650         _REGISTER_CLOCK(NULL, "pll1_main_clk", pll1_sys_main_clk),
4651         _REGISTER_CLOCK(NULL, "pll1_sw_clk", pll1_sw_clk),
4652         _REGISTER_CLOCK(NULL, "pll2", pll2_528_bus_main_clk),
4653         _REGISTER_CLOCK(NULL, "pll2_pfd_400M", pll2_pfd_400M),
4654         _REGISTER_CLOCK(NULL, "pll2_pfd_352M", pll2_pfd_352M),
4655         _REGISTER_CLOCK(NULL, "pll2_pfd_594M", pll2_pfd_594M),
4656         _REGISTER_CLOCK(NULL, "pll2_200M", pll2_200M),
4657         _REGISTER_CLOCK(NULL, "pll3_main_clk", pll3_usb_otg_main_clk),
4658         _REGISTER_CLOCK(NULL, "pll3_pfd_508M", pll3_pfd_508M),
4659         _REGISTER_CLOCK(NULL, "pll3_pfd_454M", pll3_pfd_454M),
4660         _REGISTER_CLOCK(NULL, "pll3_pfd_720M", pll3_pfd_720M),
4661         _REGISTER_CLOCK(NULL, "pll3_pfd_540M", pll3_pfd_540M),
4662         _REGISTER_CLOCK(NULL, "pll3_sw_clk", pll3_sw_clk),
4663         _REGISTER_CLOCK(NULL, "pll3_120M", pll3_120M),
4664         _REGISTER_CLOCK(NULL, "pll3_120M", pll3_80M),
4665         _REGISTER_CLOCK(NULL, "pll3_120M", pll3_60M),
4666         _REGISTER_CLOCK(NULL, "pll4", pll4_audio_main_clk),
4667         _REGISTER_CLOCK(NULL, "pll5", pll5_video_main_clk),
4668         _REGISTER_CLOCK(NULL, "pll4", pll6_MLB_main_clk),
4669         _REGISTER_CLOCK(NULL, "pll3", pll7_usb_host_main_clk),
4670         _REGISTER_CLOCK(NULL, "pll4", pll8_enet_main_clk),
4671         _REGISTER_CLOCK(NULL, "cpu_clk", cpu_clk),
4672         _REGISTER_CLOCK(NULL, "periph_clk", periph_clk),
4673         _REGISTER_CLOCK(NULL, "axi_clk", axi_clk),
4674         _REGISTER_CLOCK(NULL, "mmdc_ch0_axi", mmdc_ch0_axi_clk[0]),
4675         _REGISTER_CLOCK(NULL, "mmdc_ch1_axi", mmdc_ch1_axi_clk[0]),
4676         _REGISTER_CLOCK(NULL, "ahb", ahb_clk),
4677         _REGISTER_CLOCK(NULL, "ipg_clk", ipg_clk),
4678         _REGISTER_CLOCK(NULL, "ipg_perclk", ipg_perclk),
4679         _REGISTER_CLOCK(NULL, "spba", spba_clk),
4680         _REGISTER_CLOCK("imx-sdma", NULL, sdma_clk[0]),
4681         _REGISTER_CLOCK(NULL, "gpu2d_axi_clk", gpu2d_axi_clk),
4682         _REGISTER_CLOCK(NULL, "gpu3d_axi_clk", gpu3d_axi_clk),
4683         _REGISTER_CLOCK(NULL, "pcie_axi_clk", pcie_axi_clk),
4684         _REGISTER_CLOCK(NULL, "vdo_axi_clk", vdo_axi_clk),
4685         _REGISTER_CLOCK(NULL, "iim_clk", iim_clk),
4686         _REGISTER_CLOCK(NULL, "i2c_clk", i2c_clk[0]),
4687         _REGISTER_CLOCK("imx-i2c.1", NULL, i2c_clk[1]),
4688         _REGISTER_CLOCK("imx-i2c.2", NULL, i2c_clk[2]),
4689         _REGISTER_CLOCK(NULL, "vpu_clk", vpu_clk[0]),
4690         _REGISTER_CLOCK(NULL, "ipu1_clk", ipu1_clk),
4691         _REGISTER_CLOCK(NULL, "ipu2_clk", ipu2_clk),
4692         _REGISTER_CLOCK(NULL, "cko1_clk0", cko1_clk0),
4693         _REGISTER_CLOCK("sdhci-esdhc-imx.0", NULL, usdhc1_clk),
4694         _REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL, usdhc2_clk),
4695         _REGISTER_CLOCK("sdhci-esdhc-imx.2", NULL, usdhc3_clk),
4696         _REGISTER_CLOCK("sdhci-esdhc-imx.3", NULL, usdhc4_clk),
4697         _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk),
4698         _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk),
4699         _REGISTER_CLOCK("imx-ssi.2", NULL, ssi3_clk),
4700         _REGISTER_CLOCK(NULL, "ipu1_di0_clk", ipu1_di_clk[0]),
4701         _REGISTER_CLOCK(NULL, "ipu1_di1_clk", ipu1_di_clk[1]),
4702         _REGISTER_CLOCK(NULL, "ipu2_di0_clk", ipu2_di_clk[0]),
4703         _REGISTER_CLOCK(NULL, "ipu2_di1_clk", ipu2_di_clk[1]),
4704         _REGISTER_CLOCK(NULL, "can_root_clk", can_clk_root),
4705         _REGISTER_CLOCK("imx6q-flexcan.0", NULL, can1_clk[0]),
4706         _REGISTER_CLOCK("imx6q-flexcan.1", NULL, can2_clk[0]),
4707         _REGISTER_CLOCK(NULL, "ldb_di0_clk", ldb_di0_clk),
4708         _REGISTER_CLOCK(NULL, "ldb_di1_clk", ldb_di1_clk),
4709         _REGISTER_CLOCK("mxc_spdif.0", NULL, spdif0_clk[0]),
4710         _REGISTER_CLOCK(NULL, "esai_clk", esai_clk),
4711         _REGISTER_CLOCK("imx6q-ecspi.0", NULL, ecspi_clk[0]),
4712         _REGISTER_CLOCK("imx6q-ecspi.1", NULL, ecspi_clk[1]),
4713         _REGISTER_CLOCK("imx6q-ecspi.2", NULL, ecspi_clk[2]),
4714         _REGISTER_CLOCK("imx6q-ecspi.3", NULL, ecspi_clk[3]),
4715         _REGISTER_CLOCK("imx6q-ecspi.4", NULL, ecspi_clk[4]),
4716         _REGISTER_CLOCK(NULL, "emi_slow_clk", emi_slow_clk),
4717         _REGISTER_CLOCK(NULL, "emi_clk", emi_clk),
4718         _REGISTER_CLOCK(NULL, "enfc_clk", enfc_clk),
4719         _REGISTER_CLOCK("imx-uart.0", NULL, uart_clk[0]),
4720         _REGISTER_CLOCK("imx-uart.1", NULL, uart_clk[0]),
4721         _REGISTER_CLOCK("imx-uart.2", NULL, uart_clk[0]),
4722         _REGISTER_CLOCK("imx-uart.3", NULL, uart_clk[0]),
4723         _REGISTER_CLOCK(NULL, "hsi_tx", hsi_tx_clk[0]),
4724         _REGISTER_CLOCK(NULL, "caam_clk", caam_clk[0]),
4725         _REGISTER_CLOCK(NULL, "asrc_clk", asrc_clk[0]),
4726         _REGISTER_CLOCK(NULL, "asrc_serial_clk", asrc_clk[1]),
4727         _REGISTER_CLOCK("mxs-dma-apbh", NULL, apbh_dma_clk),
4728         _REGISTER_CLOCK(NULL, "openvg_axi_clk", openvg_axi_clk),
4729         _REGISTER_CLOCK(NULL, "gpu3d_clk", gpu3d_core_clk[0]),
4730         _REGISTER_CLOCK(NULL, "gpu2d_clk", gpu2d_core_clk[0]),
4731         _REGISTER_CLOCK(NULL, "gpu3d_shader_clk", gpu3d_shader_clk),
4732         _REGISTER_CLOCK(NULL, "gpt", gpt_clk[0]),
4733         _REGISTER_CLOCK("imx6q-gpmi-nfc.0", NULL, gpmi_nfc_clk[0]),
4734         _REGISTER_CLOCK(NULL, "gpmi-apb", gpmi_nfc_clk[1]),
4735         _REGISTER_CLOCK(NULL, "bch", gpmi_nfc_clk[2]),
4736         _REGISTER_CLOCK(NULL, "bch-apb", gpmi_nfc_clk[3]),
4737         _REGISTER_CLOCK(NULL, "pl301_mx6qperl-bch", gpmi_nfc_clk[4]),
4738         _REGISTER_CLOCK("mxc_pwm.0", NULL, pwm_clk[0]),
4739         _REGISTER_CLOCK("mxc_pwm.1", NULL, pwm_clk[1]),
4740         _REGISTER_CLOCK("mxc_pwm.2", NULL, pwm_clk[2]),
4741         _REGISTER_CLOCK("mxc_pwm.3", NULL, pwm_clk[3]),
4742         _REGISTER_CLOCK(NULL, "pcie_clk", pcie_clk[0]),
4743         _REGISTER_CLOCK("fec.0", NULL, enet_clk[0]),
4744         _REGISTER_CLOCK(NULL, "imx_sata_clk", sata_clk[0]),
4745         _REGISTER_CLOCK(NULL, "usboh3_clk", usboh3_clk[0]),
4746         _REGISTER_CLOCK(NULL, "usb_phy1_clk", usb_phy1_clk),
4747         _REGISTER_CLOCK(NULL, "usb_phy3_clk", usb_phy3_clk),
4748         _REGISTER_CLOCK(NULL, "usb_phy4_clk", usb_phy4_clk),
4749         _REGISTER_CLOCK("imx2-wdt.0", NULL, dummy_clk),
4750         _REGISTER_CLOCK("imx2-wdt.1", NULL, dummy_clk),
4751         _REGISTER_CLOCK(NULL, "hdmi_isfr_clk", hdmi_clk[0]),
4752         _REGISTER_CLOCK(NULL, "hdmi_iahb_clk", hdmi_clk[1]),
4753         _REGISTER_CLOCK(NULL, "mipi_pllref_clk", mipi_pllref_clk),
4754         _REGISTER_CLOCK(NULL, NULL, vdoa_clk),
4755         _REGISTER_CLOCK(NULL, NULL, aips_tz2_clk),
4756         _REGISTER_CLOCK(NULL, NULL, aips_tz1_clk),
4757         _REGISTER_CLOCK(NULL, "clko_clk", clko_clk),
4758 };
4759
4760
4761 static void clk_tree_init(void)
4762
4763 {
4764         unsigned int reg;
4765
4766         reg = __raw_readl(MMDC_MDMISC_OFFSET);
4767         if ((reg & MMDC_MDMISC_DDR_TYPE_MASK) ==
4768                 (0x1 << MMDC_MDMISC_DDR_TYPE_OFFSET)) {
4769                 clk_set_parent(&periph_clk, &pll2_pfd_400M);
4770                 printk(KERN_INFO "Set periph_clk's parent to pll2_pfd_400M!\n");
4771         }
4772 }
4773
4774
4775 int __init mx6_clocks_init(unsigned long ckil, unsigned long osc,
4776         unsigned long ckih1, unsigned long ckih2)
4777 {
4778         __iomem void *base;
4779         int i;
4780
4781         external_low_reference = ckil;
4782         external_high_reference = ckih1;
4783         ckih2_reference = ckih2;
4784         oscillator_reference = osc;
4785
4786         apll_base = ioremap(ANATOP_BASE_ADDR, SZ_4K);
4787
4788         for (i = 0; i < ARRAY_SIZE(lookups); i++) {
4789                 clkdev_add(&lookups[i]);
4790                 clk_debug_register(lookups[i].clk);
4791         }
4792
4793         /* Disable un-necessary PFDs & PLLs */
4794
4795         /* keep correct count. */
4796         clk_enable(&cpu_clk);
4797         clk_enable(&periph_clk);
4798
4799         clk_tree_init();
4800
4801         if (pll2_pfd_400M.usecount == 0)
4802                 pll2_pfd_400M.disable(&pll2_pfd_400M);
4803         pll2_pfd_352M.disable(&pll2_pfd_352M);
4804         pll2_pfd_594M.disable(&pll2_pfd_594M);
4805
4806 #if !defined(CONFIG_FEC_1588)
4807         pll3_pfd_454M.disable(&pll3_pfd_454M);
4808         pll3_pfd_508M.disable(&pll3_pfd_508M);
4809         pll3_pfd_540M.disable(&pll3_pfd_540M);
4810         pll3_pfd_720M.disable(&pll3_pfd_720M);
4811
4812         pll3_usb_otg_main_clk.disable(&pll3_usb_otg_main_clk);
4813 #endif
4814         pll4_audio_main_clk.disable(&pll4_audio_main_clk);
4815         pll5_video_main_clk.disable(&pll5_video_main_clk);
4816         pll6_MLB_main_clk.disable(&pll6_MLB_main_clk);
4817         pll7_usb_host_main_clk.disable(&pll7_usb_host_main_clk);
4818         pll8_enet_main_clk.disable(&pll8_enet_main_clk);
4819
4820         sata_clk[0].disable(&sata_clk[0]);
4821         pcie_clk[0].disable(&pcie_clk[0]);
4822
4823         /* Initialize Audio and Video PLLs to valid frequency (650MHz). */
4824         clk_set_rate(&pll4_audio_main_clk, 650000000);
4825         clk_set_rate(&pll5_video_main_clk, 650000000);
4826
4827         clk_set_parent(&ipu1_di_clk[0], &pll5_video_main_clk);
4828         clk_set_parent(&ipu1_di_clk[1], &pll5_video_main_clk);
4829         clk_set_parent(&ipu2_di_clk[0], &pll5_video_main_clk);
4830         clk_set_parent(&ipu2_di_clk[1], &pll5_video_main_clk);
4831
4832         clk_set_parent(&cko1_clk0, &ipg_clk);
4833         clk_set_rate(&cko1_clk0, 22000000);
4834         clk_enable(&cko1_clk0);
4835
4836         clk_set_parent(&emi_clk, &pll2_pfd_400M);
4837         clk_set_rate(&emi_clk, 200000000);
4838
4839         clk_set_parent(&gpu3d_shader_clk, &pll2_pfd_594M);
4840         clk_set_rate(&gpu3d_shader_clk, 594000000);
4841         clk_set_parent(&gpu3d_core_clk[0], &mmdc_ch0_axi_clk[0]);
4842         clk_set_rate(&gpu3d_core_clk[0], 528000000);
4843
4844         /*
4845          * FIXME: asrc needs to use asrc_serial(spdif1) clock to do sample
4846          * rate convertion and this clock frequency can not be too high, set
4847          * it to the minimum value 7.5Mhz to make asrc work properly.
4848          */
4849         clk_set_parent(&asrc_clk[1], &pll3_sw_clk);
4850         clk_set_rate(&asrc_clk[1], 7500000);
4851
4852         /* set the NAND to 11MHz. Too fast will cause dma timeout. */
4853         clk_set_rate(&enfc_clk, enfc_clk.round_rate(&enfc_clk, 11000000));
4854
4855         mx6_cpu_op_init();
4856         cpu_op_tbl = get_cpu_op(&cpu_op_nr);
4857
4858         /* Gate off all possible clocks */
4859         if (mxc_jtag_enabled) {
4860                 __raw_writel(3 << MXC_CCM_CCGRx_CG11_OFFSET |
4861                              3 << MXC_CCM_CCGRx_CG2_OFFSET |
4862                              3 << MXC_CCM_CCGRx_CG1_OFFSET |
4863                              3 << MXC_CCM_CCGRx_CG0_OFFSET, MXC_CCM_CCGR0);
4864         } else {
4865                 __raw_writel(1 << MXC_CCM_CCGRx_CG11_OFFSET |
4866                              3 << MXC_CCM_CCGRx_CG2_OFFSET |
4867                              3 << MXC_CCM_CCGRx_CG1_OFFSET |
4868                              3 << MXC_CCM_CCGRx_CG0_OFFSET, MXC_CCM_CCGR0);
4869         }
4870         __raw_writel(3 << MXC_CCM_CCGRx_CG10_OFFSET, MXC_CCM_CCGR1);
4871         __raw_writel(1 << MXC_CCM_CCGRx_CG12_OFFSET |
4872                      1 << MXC_CCM_CCGRx_CG11_OFFSET |
4873                      3 << MXC_CCM_CCGRx_CG10_OFFSET |
4874                      3 << MXC_CCM_CCGRx_CG9_OFFSET |
4875                      3 << MXC_CCM_CCGRx_CG8_OFFSET, MXC_CCM_CCGR2);
4876         __raw_writel(1 << MXC_CCM_CCGRx_CG14_OFFSET |
4877                      3 << MXC_CCM_CCGRx_CG13_OFFSET |
4878                      3 << MXC_CCM_CCGRx_CG12_OFFSET |
4879                      3 << MXC_CCM_CCGRx_CG11_OFFSET |
4880                      3 << MXC_CCM_CCGRx_CG10_OFFSET, MXC_CCM_CCGR3);
4881         __raw_writel(3 << MXC_CCM_CCGRx_CG7_OFFSET |
4882                         1 << MXC_CCM_CCGRx_CG6_OFFSET |
4883                         1 << MXC_CCM_CCGRx_CG4_OFFSET, MXC_CCM_CCGR4);
4884         __raw_writel(1 << MXC_CCM_CCGRx_CG0_OFFSET, MXC_CCM_CCGR5);
4885
4886         __raw_writel(0, MXC_CCM_CCGR6);
4887
4888         /* Lower the ipg_perclk frequency to 8.25MHz. */
4889         clk_set_rate(&ipg_perclk, 8250000);
4890
4891         /* S/PDIF */
4892         clk_set_parent(&spdif0_clk[0], &pll3_pfd_454M);
4893
4894         base = ioremap(GPT_BASE_ADDR, SZ_4K);
4895         mxc_timer_init(&gpt_clk[0], base, MXC_INT_GPT);
4896
4897         /* Set the core to max frequency requested. */
4898         mx6_set_cpu_voltage(cpu_op_tbl[0].cpu_voltage);
4899         clk_set_rate(&cpu_clk, cpu_op_tbl[0].pll_rate);
4900
4901         lp_high_freq = 0;
4902         lp_med_freq = 0;
4903
4904         return 0;
4905
4906 }