arch/arm/mach-mx6/clock.c

   1
   2 /*
   3  * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved.
   4  */
   5
   6 /*
   7  * The code contained herein is licensed under the GNU General Public
   8  * License. You may obtain a copy of the GNU General Public License
   9  * Version 2 or later at the following locations:
  10  *
  11  * http://www.opensource.org/licenses/gpl-license.html
  12  * http://www.gnu.org/copyleft/gpl.html
  13  */
  14
  15 #include <linux/kernel.h>
  16 #include <linux/init.h>
  17 #include <linux/types.h>
  18 #include <linux/time.h>
  19 #include <linux/hrtimer.h>
  20 #include <linux/mm.h>
  21 #include <linux/errno.h>
  22 #include <linux/delay.h>
  23 #include <linux/clk.h>
  24 #include <linux/io.h>
  25 #include <linux/clkdev.h>
  26 #include <linux/regulator/consumer.h>
  27 #include <asm/div64.h>
  28 #include <mach/hardware.h>
  29 #include <mach/common.h>
  30 #include <mach/clock.h>
  31 #include <mach/mxc_dvfs.h>
  32 #include "crm_regs.h"
  33 #include "cpu_op-mx6.h"
  34 #include "regs-anadig.h"
  35
  36 #ifdef CONFIG_CLK_DEBUG
  37 #define __INIT_CLK_DEBUG(n)     .name = #n,
  38 #else
  39 #define __INIT_CLK_DEBUG(n)
  40 #endif
  41
  42 extern u32 arm_max_freq;
  43 extern int mxc_jtag_enabled;
  44 extern struct regulator *cpu_regulator;
  45 extern struct cpu_op *(*get_cpu_op)(int *op);
  46 extern int lp_high_freq;
  47 extern int lp_med_freq;
  48 extern int mx6q_revision(void);
  49
  50 void __iomem *apll_base;
  51 static struct clk pll1_sys_main_clk;
  52 static struct clk pll2_528_bus_main_clk;
  53 static struct clk pll2_pfd_400M;
  54 static struct clk pll3_usb_otg_main_clk;
  55 static struct clk pll4_audio_main_clk;
  56 static struct clk pll5_video_main_clk;
  57 static struct clk pll6_mlb150_main_clk;
  58 static struct clk pll7_usb_host_main_clk;
  59 static struct clk pll8_enet_main_clk;
  60 static struct clk apbh_dma_clk;
  61 static struct clk openvg_axi_clk;
  62 static struct clk enfc_clk;
  63 static struct clk usdhc3_clk;
  64
  65 static struct cpu_op *cpu_op_tbl;
  66 static int cpu_op_nr;
  67
  68 #define SPIN_DELAY      1200000 /* in nanoseconds */
  69
  70 #define AUDIO_VIDEO_MIN_CLK_FREQ        650000000
  71 #define AUDIO_VIDEO_MAX_CLK_FREQ        1300000000
  72
  73 /* We need to check the exp status again after timer expiration,
  74  * as there might be interrupt coming between the first time exp
  75  * and the time reading, then the time reading may be several ms
  76  * after the exp checking due to the irq handle, so we need to
  77  * check it to make sure the exp return the right value after
  78  * timer expiration. */
  79 #define WAIT(exp, timeout) \
  80 ({ \
  81         struct timespec nstimeofday; \
  82         struct timespec curtime; \
  83         int result = 1; \
  84         getnstimeofday(&nstimeofday); \
  85         while (!(exp)) { \
  86                 getnstimeofday(&curtime); \
  87                 if ((curtime.tv_nsec - nstimeofday.tv_nsec) > (timeout)) { \
  88                         if (!(exp)) \
  89                                 result = 0; \
  90                         break; \
  91                 } \
  92         } \
  93         result; \
  94 })
  95
  96 /* External clock values passed-in by the board code */
  97 static unsigned long external_high_reference, external_low_reference;
  98 static unsigned long oscillator_reference, ckih2_reference;
  99 static unsigned long anaclk_1_reference, anaclk_2_reference;
 100
 101 /* For MX 6DL/S, Video PLL may be used by synchronous display devices,
 102  * such as HDMI or LVDS, and also by the EPDC.  If EPDC is in use,
 103  * it must use the Video PLL to achieve the clock frequencies it needs.
 104  * So if EPDC is in use, the "epdc" string should be added to kernel
 105  * parameters, in order to set the EPDC parent clock to the Video PLL.
 106  * This will have an impact on the behavior of HDMI and LVDS.
 107  */
 108 int epdc_enabled;
 109 static int __init epdc_setup(char *__unused)
 110 {
 111         epdc_enabled = 1;
 112         return 1;
 113 }
 114 __setup("epdc", epdc_setup);
 115
 116 static void __calc_pre_post_dividers(u32 max_podf, u32 div, u32 *pre, u32 *post)
 117 {
 118         u32 min_pre, temp_pre, old_err, err;
 119
 120         /* Some of the podfs are 3 bits while others are 6 bits.
 121           * Handle both cases here.
 122           */
 123         if (div >= 512 && (max_podf == 64)) {
 124                 /* For pre = 3bits and podf = 6 bits, max divider is 512. */
 125                 *pre = 8;
 126                 *post = 64;
 127         } else if (div >= 64 && (max_podf == 8)) {
 128                 /* For pre = 3bits and podf = 3 bits, max divider is 64. */
 129                 *pre = 8;
 130                 *post = 8;
 131         } else if (div >= 8) {
 132                 /* Find the minimum pre-divider for a max podf */
 133                 if (max_podf == 64)
 134                         min_pre = (div - 1) / (1 << 6) + 1;
 135                 else
 136                         min_pre = (div - 1) / (1 << 3) + 1;
 137                 old_err = 8;
 138                 /* Now loop through to find the max pre-divider. */
 139                 for (temp_pre = 8; temp_pre >= min_pre; temp_pre--) {
 140                         err = div % temp_pre;
 141                         if (err == 0) {
 142                                 *pre = temp_pre;
 143                                 break;
 144                         }
 145                         err = temp_pre - err;
 146                         if (err < old_err) {
 147                                 old_err = err;
 148                                 *pre = temp_pre;
 149                         }
 150                 }
 151                 *post = (div + *pre - 1) / *pre;
 152         } else if (div < 8) {
 153                 *pre = div;
 154                 *post = 1;
 155         }
 156 }
 157
 158 static int _clk_enable(struct clk *clk)
 159 {
 160         u32 reg;
 161         reg = __raw_readl(clk->enable_reg);
 162         reg |= MXC_CCM_CCGRx_CG_MASK << clk->enable_shift;
 163         __raw_writel(reg, clk->enable_reg);
 164
 165         if (clk->flags & AHB_HIGH_SET_POINT)
 166                 lp_high_freq++;
 167         else if (clk->flags & AHB_MED_SET_POINT)
 168                 lp_med_freq++;
 169
 170         return 0;
 171 }
 172
 173 static void _clk_disable(struct clk *clk)
 174 {
 175         u32 reg;
 176         reg = __raw_readl(clk->enable_reg);
 177         reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift);
 178         __raw_writel(reg, clk->enable_reg);
 179
 180         if (clk->flags & AHB_HIGH_SET_POINT)
 181                 lp_high_freq--;
 182         else if (clk->flags & AHB_MED_SET_POINT)
 183                 lp_med_freq--;
 184 }
 185
 186 static void _clk_disable_inwait(struct clk *clk)
 187 {
 188         u32 reg;
 189         reg = __raw_readl(clk->enable_reg);
 190         reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift);
 191         reg |= 1 << clk->enable_shift;
 192         __raw_writel(reg, clk->enable_reg);
 193 }
 194
 195 /*
 196  * For the 4-to-1 muxed input clock
 197  */
 198 static inline u32 _get_mux(struct clk *parent, struct clk *m0,
 199                            struct clk *m1, struct clk *m2, struct clk *m3)
 200 {
 201         if (parent == m0)
 202                 return 0;
 203         else if (parent == m1)
 204                 return 1;
 205         else if (parent == m2)
 206                 return 2;
 207         else if (parent == m3)
 208                 return 3;
 209         else
 210                 BUG();
 211
 212         return 0;
 213 }
 214
 215 static inline void __iomem *_get_pll_base(struct clk *pll)
 216 {
 217         if (pll == &pll1_sys_main_clk)
 218                 return PLL1_SYS_BASE_ADDR;
 219         else if (pll == &pll2_528_bus_main_clk)
 220                 return PLL2_528_BASE_ADDR;
 221         else if (pll == &pll3_usb_otg_main_clk)
 222                 return PLL3_480_USB1_BASE_ADDR;
 223         else if (pll == &pll4_audio_main_clk)
 224                 return PLL4_AUDIO_BASE_ADDR;
 225         else if (pll == &pll5_video_main_clk)
 226                 return PLL5_VIDEO_BASE_ADDR;
 227         else if (pll == &pll6_mlb150_main_clk)
 228                 return PLL6_MLB_BASE_ADDR;
 229         else if (pll == &pll7_usb_host_main_clk)
 230                 return PLL7_480_USB2_BASE_ADDR;
 231         else if (pll == &pll8_enet_main_clk)
 232                 return PLL8_ENET_BASE_ADDR;
 233         else
 234                 BUG();
 235         return NULL;
 236 }
 237
 238
 239 /*
 240  * For the 6-to-1 muxed input clock
 241  */
 242 static inline u32 _get_mux6(struct clk *parent, struct clk *m0, struct clk *m1,
 243                             struct clk *m2, struct clk *m3, struct clk *m4,
 244                             struct clk *m5)
 245 {
 246         if (parent == m0)
 247                 return 0;
 248         else if (parent == m1)
 249                 return 1;
 250         else if (parent == m2)
 251                 return 2;
 252         else if (parent == m3)
 253                 return 3;
 254         else if (parent == m4)
 255                 return 4;
 256         else if (parent == m5)
 257                 return 5;
 258         else
 259                 BUG();
 260
 261         return 0;
 262 }
 263 static unsigned long get_high_reference_clock_rate(struct clk *clk)
 264 {
 265         return external_high_reference;
 266 }
 267
 268 static unsigned long get_low_reference_clock_rate(struct clk *clk)
 269 {
 270         return external_low_reference;
 271 }
 272
 273 static unsigned long get_oscillator_reference_clock_rate(struct clk *clk)
 274 {
 275         return oscillator_reference;
 276 }
 277
 278 static unsigned long get_ckih2_reference_clock_rate(struct clk *clk)
 279 {
 280         return ckih2_reference;
 281 }
 282
 283 static unsigned long _clk_anaclk_1_get_rate(struct clk *clk)
 284 {
 285         return anaclk_1_reference;
 286 }
 287
 288 static int _clk_anaclk_1_set_rate(struct clk *clk, unsigned long rate)
 289 {
 290         anaclk_1_reference = rate;
 291         return 0;
 292 }
 293
 294 static unsigned long _clk_anaclk_2_get_rate(struct clk *clk)
 295 {
 296         return anaclk_2_reference;
 297 }
 298
 299 static int _clk_anaclk_2_set_rate(struct clk *clk, unsigned long rate)
 300 {
 301         anaclk_2_reference = rate;
 302         return 0;
 303 }
 304
 305 /* External high frequency clock */
 306 static struct clk ckih_clk = {
 307         __INIT_CLK_DEBUG(ckih_clk)
 308         .get_rate = get_high_reference_clock_rate,
 309 };
 310
 311 static struct clk ckih2_clk = {
 312         __INIT_CLK_DEBUG(ckih2_clk)
 313         .get_rate = get_ckih2_reference_clock_rate,
 314 };
 315
 316 static struct clk osc_clk = {
 317         __INIT_CLK_DEBUG(osc_clk)
 318         .get_rate = get_oscillator_reference_clock_rate,
 319 };
 320
 321 /* External low frequency (32kHz) clock */
 322 static struct clk ckil_clk = {
 323         __INIT_CLK_DEBUG(ckil_clk)
 324         .get_rate = get_low_reference_clock_rate,
 325 };
 326
 327 static struct clk anaclk_1 = {
 328         __INIT_CLK_DEBUG(anaclk_1)
 329         .get_rate = _clk_anaclk_1_get_rate,
 330         .set_rate = _clk_anaclk_1_set_rate,
 331 };
 332
 333 static struct clk anaclk_2 = {
 334         __INIT_CLK_DEBUG(anaclk_2)
 335         .get_rate = _clk_anaclk_2_get_rate,
 336         .set_rate = _clk_anaclk_2_set_rate,
 337 };
 338
 339 static unsigned long pfd_round_rate(struct clk *clk, unsigned long rate)
 340 {
 341         u32 frac;
 342         u64 tmp;
 343
 344         tmp = (u64)clk_get_rate(clk->parent) * 18;
 345         tmp += rate/2;
 346         do_div(tmp, rate);
 347         frac = tmp;
 348         frac = frac < 12 ? 12 : frac;
 349         frac = frac > 35 ? 35 : frac;
 350         tmp = (u64)clk_get_rate(clk->parent) * 18;
 351         do_div(tmp, frac);
 352         return tmp;
 353 }
 354
 355 static unsigned long pfd_get_rate(struct clk *clk)
 356 {
 357         u32 frac;
 358         u64 tmp;
 359         tmp = (u64)clk_get_rate(clk->parent) * 18;
 360
 361         if (apbh_dma_clk.usecount == 0)
 362                 apbh_dma_clk.enable(&apbh_dma_clk);
 363
 364         frac = (__raw_readl(clk->enable_reg) >> clk->enable_shift) &
 365                         ANADIG_PFD_FRAC_MASK;
 366
 367         do_div(tmp, frac);
 368
 369         return tmp;
 370 }
 371
 372 static int pfd_set_rate(struct clk *clk, unsigned long rate)
 373 {
 374         u32 frac;
 375         u64 tmp;
 376         tmp = (u64)clk_get_rate(clk->parent) * 18;
 377
 378         if (apbh_dma_clk.usecount == 0)
 379                 apbh_dma_clk.enable(&apbh_dma_clk);
 380
 381         /* Round up the divider so that we don't set a rate
 382           * higher than what is requested. */
 383         tmp += rate/2;
 384         do_div(tmp, rate);
 385         frac = tmp;
 386         frac = frac < 12 ? 12 : frac;
 387         frac = frac > 35 ? 35 : frac;
 388         /* clear clk frac bits */
 389         __raw_writel(ANADIG_PFD_FRAC_MASK << clk->enable_shift,
 390                         (int)clk->enable_reg + 8);
 391         /* set clk frac bits */
 392         __raw_writel(frac << clk->enable_shift,
 393                         (int)clk->enable_reg + 4);
 394
 395         if (apbh_dma_clk.usecount == 0)
 396                 apbh_dma_clk.disable(&apbh_dma_clk);
 397         return 0;
 398 }
 399
 400 static int _clk_pfd_enable(struct clk *clk)
 401 {
 402         if (apbh_dma_clk.usecount == 0)
 403                 apbh_dma_clk.enable(&apbh_dma_clk);
 404
 405         /* clear clk gate bit */
 406         __raw_writel((1 << (clk->enable_shift + 7)),
 407                         (int)clk->enable_reg + 8);
 408
 409         if (apbh_dma_clk.usecount == 0)
 410                 apbh_dma_clk.disable(&apbh_dma_clk);
 411
 412         return 0;
 413 }
 414
 415 static void _clk_pfd_disable(struct clk *clk)
 416 {
 417         if (apbh_dma_clk.usecount == 0)
 418                 apbh_dma_clk.enable(&apbh_dma_clk);
 419
 420         /* set clk gate bit */
 421         __raw_writel((1 << (clk->enable_shift + 7)),
 422                         (int)clk->enable_reg + 4);
 423
 424         if (apbh_dma_clk.usecount == 0)
 425                 apbh_dma_clk.disable(&apbh_dma_clk);
 426 }
 427
 428 static int _clk_pll_enable(struct clk *clk)
 429 {
 430         unsigned int reg;
 431         void __iomem *pllbase;
 432
 433         pllbase = _get_pll_base(clk);
 434
 435         reg = __raw_readl(pllbase);
 436         reg &= ~ANADIG_PLL_BYPASS;
 437         reg &= ~ANADIG_PLL_POWER_DOWN;
 438
 439         /* The 480MHz PLLs have the opposite definition for power bit. */
 440         if (clk == &pll3_usb_otg_main_clk || clk == &pll7_usb_host_main_clk)
 441                 reg |= ANADIG_PLL_POWER_DOWN;
 442
 443         __raw_writel(reg, pllbase);
 444
 445         /* It will power on pll3 */
 446         if (clk == &pll3_usb_otg_main_clk)
 447                 __raw_writel(BM_ANADIG_ANA_MISC2_CONTROL0, apll_base + HW_ANADIG_ANA_MISC2_CLR);
 448
 449         /* Wait for PLL to lock */
 450         if (!WAIT(__raw_readl(pllbase) & ANADIG_PLL_LOCK,
 451                                 SPIN_DELAY))
 452                 panic("pll enable failed\n");
 453
 454         /* Enable the PLL output now*/
 455         reg = __raw_readl(pllbase);
 456         reg |= ANADIG_PLL_ENABLE;
 457         __raw_writel(reg, pllbase);
 458
 459         return 0;
 460 }
 461
 462 static void _clk_pll_disable(struct clk *clk)
 463 {
 464         unsigned int reg;
 465         void __iomem *pllbase;
 466
 467         pllbase = _get_pll_base(clk);
 468
 469         reg = __raw_readl(pllbase);
 470         reg |= ANADIG_PLL_BYPASS;
 471         reg &= ~ANADIG_PLL_ENABLE;
 472
 473         __raw_writel(reg, pllbase);
 474
 475         /*
 476          * It will power off PLL3's power, it is the TO1.1 fix
 477          * Please see TKT064178 for detail.
 478          */
 479         if (clk == &pll3_usb_otg_main_clk)
 480                 __raw_writel(BM_ANADIG_ANA_MISC2_CONTROL0, apll_base + HW_ANADIG_ANA_MISC2_SET);
 481 }
 482
 483 static unsigned long  _clk_pll1_main_get_rate(struct clk *clk)
 484 {
 485         unsigned int div;
 486         unsigned long val;
 487
 488         div = __raw_readl(PLL1_SYS_BASE_ADDR) & ANADIG_PLL_SYS_DIV_SELECT_MASK;
 489         val = (clk_get_rate(clk->parent) * div) / 2;
 490         return val;
 491 }
 492
 493 static int _clk_pll1_main_set_rate(struct clk *clk, unsigned long rate)
 494 {
 495         unsigned int reg,  div;
 496
 497         if (rate < AUDIO_VIDEO_MIN_CLK_FREQ || rate > AUDIO_VIDEO_MAX_CLK_FREQ)
 498                 return -EINVAL;
 499
 500         div = (rate * 2) / clk_get_rate(clk->parent) ;
 501
 502         reg = __raw_readl(PLL1_SYS_BASE_ADDR) & ~ANADIG_PLL_SYS_DIV_SELECT_MASK;
 503         reg |= div;
 504         __raw_writel(reg, PLL1_SYS_BASE_ADDR);
 505
 506         return 0;
 507 }
 508
 509 static struct clk pll1_sys_main_clk = {
 510         __INIT_CLK_DEBUG(pll1_sys_main_clk)
 511         .parent = &osc_clk,
 512         .get_rate = _clk_pll1_main_get_rate,
 513         .set_rate = _clk_pll1_main_set_rate,
 514         .enable = _clk_pll_enable,
 515         .disable = _clk_pll_disable,
 516 };
 517
 518 static int _clk_pll1_sw_set_parent(struct clk *clk, struct clk *parent)
 519 {
 520         u32 reg;
 521
 522         reg = __raw_readl(MXC_CCM_CCSR);
 523
 524         if (parent == &pll1_sys_main_clk) {
 525                 reg &= ~MXC_CCM_CCSR_PLL1_SW_CLK_SEL;
 526                 __raw_writel(reg, MXC_CCM_CCSR);
 527                 /* Set the step_clk parent to be lp_apm, to save power. */
 528                 reg = __raw_readl(MXC_CCM_CCSR);
 529                 reg = (reg & ~MXC_CCM_CCSR_STEP_SEL);
 530         } else {
 531                 /* Set STEP_CLK to be the parent*/
 532                 if (parent == &osc_clk) {
 533                         /* Set STEP_CLK to be sourced from LPAPM. */
 534                         reg = __raw_readl(MXC_CCM_CCSR);
 535                         reg = (reg & ~MXC_CCM_CCSR_STEP_SEL);
 536                         __raw_writel(reg, MXC_CCM_CCSR);
 537                 } else {
 538                         /* Set STEP_CLK to be sourced from PLL2-PDF (400MHz). */
 539                         reg = __raw_readl(MXC_CCM_CCSR);
 540                         reg |= MXC_CCM_CCSR_STEP_SEL;
 541                         __raw_writel(reg, MXC_CCM_CCSR);
 542
 543                 }
 544                 reg = __raw_readl(MXC_CCM_CCSR);
 545                 reg |= MXC_CCM_CCSR_PLL1_SW_CLK_SEL;
 546         }
 547         __raw_writel(reg, MXC_CCM_CCSR);
 548         return 0;
 549 }
 550
 551 static unsigned long _clk_pll1_sw_get_rate(struct clk *clk)
 552 {
 553         return clk_get_rate(clk->parent);
 554 }
 555
 556 static struct clk pll1_sw_clk = {
 557         __INIT_CLK_DEBUG(pll1_sw_clk)
 558         .parent = &pll1_sys_main_clk,
 559         .set_parent = _clk_pll1_sw_set_parent,
 560         .get_rate = _clk_pll1_sw_get_rate,
 561 };
 562
 563 static unsigned long _clk_pll2_main_get_rate(struct clk *clk)
 564 {
 565         unsigned int div;
 566         unsigned long val;
 567
 568         div = __raw_readl(PLL2_528_BASE_ADDR) & ANADIG_PLL_528_DIV_SELECT;
 569
 570         if (div == 1)
 571                 val = clk_get_rate(clk->parent) * 22;
 572
 573         else
 574                 val = clk_get_rate(clk->parent) * 20;
 575
 576         return val;
 577 }
 578
 579 static int _clk_pll2_main_set_rate(struct clk *clk, unsigned long rate)
 580 {
 581         unsigned int reg,  div;
 582
 583         if (rate == 528000000)
 584                 div = 1;
 585         else if (rate == 480000000)
 586                 div = 0;
 587         else
 588                 return -EINVAL;
 589
 590         reg = __raw_readl(PLL2_528_BASE_ADDR);
 591         reg &= ~ANADIG_PLL_528_DIV_SELECT;
 592         reg |= div;
 593         __raw_writel(reg, PLL2_528_BASE_ADDR);
 594
 595         return 0;
 596 }
 597
 598 static struct clk pll2_528_bus_main_clk = {
 599         __INIT_CLK_DEBUG(pll2_528_bus_main_clk)
 600         .parent = &osc_clk,
 601         .get_rate = _clk_pll2_main_get_rate,
 602         .set_rate = _clk_pll2_main_set_rate,
 603         .enable = _clk_pll_enable,
 604         .disable = _clk_pll_disable,
 605 };
 606
 607 static struct clk pll2_pfd_400M = {
 608         __INIT_CLK_DEBUG(pll2_pfd_400M)
 609         .parent = &pll2_528_bus_main_clk,
 610         .enable_reg = (void *)PFD_528_BASE_ADDR,
 611         .enable_shift = ANADIG_PFD2_FRAC_OFFSET,
 612         .enable = _clk_pfd_enable,
 613         .disable = _clk_pfd_disable,
 614         .get_rate = pfd_get_rate,
 615         .set_rate = pfd_set_rate,
 616         .get_rate = pfd_get_rate,
 617         .round_rate = pfd_round_rate,
 618 };
 619
 620 static struct clk pll2_pfd_352M = {
 621         __INIT_CLK_DEBUG(pll2_pfd_352M)
 622         .parent = &pll2_528_bus_main_clk,
 623         .enable_reg = (void *)PFD_528_BASE_ADDR,
 624         .enable_shift = ANADIG_PFD0_FRAC_OFFSET,
 625         .enable = _clk_pfd_enable,
 626         .disable = _clk_pfd_disable,
 627         .set_rate = pfd_set_rate,
 628         .get_rate = pfd_get_rate,
 629         .round_rate = pfd_round_rate,
 630 };
 631
 632 static struct clk pll2_pfd_594M = {
 633         __INIT_CLK_DEBUG(pll2_pfd_594M)
 634         .parent = &pll2_528_bus_main_clk,
 635         .enable_reg = (void *)PFD_528_BASE_ADDR,
 636         .enable_shift = ANADIG_PFD1_FRAC_OFFSET,
 637         .enable = _clk_pfd_enable,
 638         .disable = _clk_pfd_disable,
 639         .set_rate = pfd_set_rate,
 640         .get_rate = pfd_get_rate,
 641         .round_rate = pfd_round_rate,
 642 };
 643
 644 static unsigned long _clk_pll2_200M_get_rate(struct clk *clk)
 645 {
 646         return clk_get_rate(clk->parent) / 2;
 647 }
 648
 649 static struct clk pll2_200M = {
 650         __INIT_CLK_DEBUG(pll2_200M)
 651         .parent = &pll2_pfd_400M,
 652         .get_rate = _clk_pll2_200M_get_rate,
 653 };
 654
 655 static unsigned long _clk_pll3_usb_otg_get_rate(struct clk *clk)
 656 {
 657         unsigned int div;
 658         unsigned long val;
 659
 660         div = __raw_readl(PLL3_480_USB1_BASE_ADDR)
 661                 & ANADIG_PLL_480_DIV_SELECT_MASK;
 662
 663         if (div == 1)
 664                 val = clk_get_rate(clk->parent) * 22;
 665         else
 666                 val = clk_get_rate(clk->parent) * 20;
 667         return val;
 668 }
 669
 670 static int _clk_pll3_usb_otg_set_rate(struct clk *clk, unsigned long rate)
 671 {
 672         unsigned int reg,  div;
 673
 674         if (rate == 528000000)
 675                 div = 1;
 676         else if (rate == 480000000)
 677                 div = 0;
 678         else
 679                 return -EINVAL;
 680
 681         reg = __raw_readl(PLL3_480_USB1_BASE_ADDR);
 682         reg &= ~ANADIG_PLL_480_DIV_SELECT_MASK;
 683         reg |= div;
 684         __raw_writel(reg, PLL3_480_USB1_BASE_ADDR);
 685
 686         return 0;
 687 }
 688
 689
 690 /* same as pll3_main_clk. These two clocks should always be the same */
 691 static struct clk pll3_usb_otg_main_clk = {
 692         __INIT_CLK_DEBUG(pll3_usb_otg_main_clk)
 693         .parent = &osc_clk,
 694         .enable = _clk_pll_enable,
 695         .disable = _clk_pll_disable,
 696         .set_rate = _clk_pll3_usb_otg_set_rate,
 697         .get_rate = _clk_pll3_usb_otg_get_rate,
 698 };
 699
 700 /* for USB OTG */
 701 static struct clk usb_phy1_clk = {
 702         __INIT_CLK_DEBUG(usb_phy1_clk)
 703         .parent = &pll3_usb_otg_main_clk,
 704         .set_rate = _clk_pll3_usb_otg_set_rate,
 705         .get_rate = _clk_pll3_usb_otg_get_rate,
 706 };
 707
 708 /* For HSIC port 1 */
 709 static struct clk usb_phy3_clk = {
 710         __INIT_CLK_DEBUG(usb_phy3_clk)
 711         .parent = &pll3_usb_otg_main_clk,
 712         .set_rate = _clk_pll3_usb_otg_set_rate,
 713         .get_rate = _clk_pll3_usb_otg_get_rate,
 714 };
 715
 716 /* For HSIC port 2 */
 717 static struct clk usb_phy4_clk = {
 718         __INIT_CLK_DEBUG(usb_phy4_clk)
 719         .parent = &pll3_usb_otg_main_clk,
 720         .set_rate = _clk_pll3_usb_otg_set_rate,
 721         .get_rate = _clk_pll3_usb_otg_get_rate,
 722 };
 723
 724 static struct clk pll3_pfd_508M = {
 725         __INIT_CLK_DEBUG(pll3_pfd_508M)
 726         .parent = &pll3_usb_otg_main_clk,
 727         .enable_reg = (void *)PFD_480_BASE_ADDR,
 728         .enable_shift = ANADIG_PFD2_FRAC_OFFSET,
 729         .enable = _clk_pfd_enable,
 730         .disable = _clk_pfd_disable,
 731         .set_rate = pfd_set_rate,
 732         .get_rate = pfd_get_rate,
 733         .round_rate = pfd_round_rate,
 734 };
 735
 736 static struct clk pll3_pfd_454M = {
 737         __INIT_CLK_DEBUG(pll3_pfd_454M)
 738         .parent = &pll3_usb_otg_main_clk,
 739         .enable_reg = (void *)PFD_480_BASE_ADDR,
 740         .enable_shift = ANADIG_PFD3_FRAC_OFFSET,
 741         .enable = _clk_pfd_enable,
 742         .disable = _clk_pfd_disable,
 743         .set_rate = pfd_set_rate,
 744         .get_rate = pfd_get_rate,
 745         .round_rate = pfd_round_rate,
 746 };
 747
 748 static struct clk pll3_pfd_720M = {
 749         __INIT_CLK_DEBUG(pll3_pfd_720M)
 750         .parent = &pll3_usb_otg_main_clk,
 751         .enable_reg = (void *)PFD_480_BASE_ADDR,
 752         .enable_shift = ANADIG_PFD0_FRAC_OFFSET,
 753         .enable = _clk_pfd_enable,
 754         .disable = _clk_pfd_disable,
 755         .set_rate = pfd_set_rate,
 756         .get_rate = pfd_get_rate,
 757         .round_rate = pfd_round_rate,
 758 };
 759
 760 static struct clk pll3_pfd_540M = {
 761         __INIT_CLK_DEBUG(pll3_pfd_540M)
 762         .parent = &pll3_usb_otg_main_clk,
 763         .enable_reg = (void *)PFD_480_BASE_ADDR,
 764         .enable_shift = ANADIG_PFD1_FRAC_OFFSET,
 765         .enable = _clk_pfd_enable,
 766         .disable = _clk_pfd_disable,
 767         .set_rate = pfd_set_rate,
 768         .get_rate = pfd_get_rate,
 769         .round_rate = pfd_round_rate,
 770         .get_rate = pfd_get_rate,
 771 };
 772
 773 static unsigned long _clk_pll3_sw_get_rate(struct clk *clk)
 774 {
 775         return clk_get_rate(clk->parent);
 776 }
 777
 778 /* same as pll3_main_clk. These two clocks should always be the same */
 779 static struct clk pll3_sw_clk = {
 780         __INIT_CLK_DEBUG(pll3_sw_clk)
 781         .parent = &pll3_usb_otg_main_clk,
 782         .get_rate = _clk_pll3_sw_get_rate,
 783 };
 784
 785 static unsigned long _clk_pll3_120M_get_rate(struct clk *clk)
 786 {
 787         return clk_get_rate(clk->parent) / 4;
 788 }
 789
 790 static struct clk pll3_120M = {
 791         __INIT_CLK_DEBUG(pll3_120M)
 792         .parent = &pll3_sw_clk,
 793         .get_rate = _clk_pll3_120M_get_rate,
 794 };
 795
 796 static unsigned long _clk_pll3_80M_get_rate(struct clk *clk)
 797 {
 798         return clk_get_rate(clk->parent) / 6;
 799 }
 800
 801 static struct clk pll3_80M = {
 802         __INIT_CLK_DEBUG(pll3_80M)
 803         .parent = &pll3_sw_clk,
 804         .get_rate = _clk_pll3_80M_get_rate,
 805 };
 806
 807 static unsigned long _clk_pll3_60M_get_rate(struct clk *clk)
 808 {
 809         return clk_get_rate(clk->parent) / 8;
 810 }
 811
 812 static struct clk pll3_60M = {
 813         __INIT_CLK_DEBUG(pll3_60M)
 814         .parent = &pll3_sw_clk,
 815         .get_rate = _clk_pll3_60M_get_rate,
 816 };
 817
 818 static unsigned long  _clk_audio_video_get_rate(struct clk *clk)
 819 {
 820         unsigned int div, mfn, mfd;
 821         unsigned long rate;
 822         unsigned int parent_rate = clk_get_rate(clk->parent);
 823         void __iomem *pllbase;
 824         int rev = mx6q_revision();
 825         unsigned int test_div_sel, control3, post_div = 1;
 826
 827         if (clk == &pll4_audio_main_clk)
 828                 pllbase = PLL4_AUDIO_BASE_ADDR;
 829         else
 830                 pllbase = PLL5_VIDEO_BASE_ADDR;
 831
 832         if ((rev >= IMX_CHIP_REVISION_1_1) || cpu_is_mx6dl()) {
 833                 test_div_sel = (__raw_readl(pllbase)
 834                         & ANADIG_PLL_AV_TEST_DIV_SEL_MASK)
 835                         >> ANADIG_PLL_AV_TEST_DIV_SEL_OFFSET;
 836                 if (test_div_sel == 0)
 837                         post_div = 4;
 838                 else if (test_div_sel == 1)
 839                         post_div = 2;
 840
 841                 if (clk == &pll5_video_main_clk) {
 842                         control3 = (__raw_readl(ANA_MISC2_BASE_ADDR)
 843                                 & ANADIG_ANA_MISC2_CONTROL3_MASK)
 844                                 >> ANADIG_ANA_MISC2_CONTROL3_OFFSET;
 845                         if (control3 == 1)
 846                                 post_div *= 2;
 847                         else if (control3 == 3)
 848                                 post_div *= 4;
 849                 }
 850         }
 851
 852         div = __raw_readl(pllbase) & ANADIG_PLL_SYS_DIV_SELECT_MASK;
 853         mfn = __raw_readl(pllbase + PLL_NUM_DIV_OFFSET);
 854         mfd = __raw_readl(pllbase + PLL_DENOM_DIV_OFFSET);
 855
 856         rate = (parent_rate * div) + ((parent_rate / mfd) * mfn);
 857         rate = rate / post_div;
 858
 859         return rate;
 860 }
 861
 862 static int _clk_audio_video_set_rate(struct clk *clk, unsigned long rate)
 863 {
 864         unsigned int reg,  div;
 865         unsigned int mfn, mfd = 1000000;
 866         s64 temp64;
 867         unsigned int parent_rate = clk_get_rate(clk->parent);
 868         void __iomem *pllbase;
 869         unsigned long min_clk_rate, pre_div_rate;
 870         int rev = mx6q_revision();
 871         u32 test_div_sel = 2;
 872         u32 control3 = 0;
 873
 874         if ((rev < IMX_CHIP_REVISION_1_1) && !cpu_is_mx6dl())
 875                 min_clk_rate = AUDIO_VIDEO_MIN_CLK_FREQ;
 876         else if (clk == &pll4_audio_main_clk)
 877                 min_clk_rate = AUDIO_VIDEO_MIN_CLK_FREQ / 4;
 878         else
 879                 min_clk_rate = AUDIO_VIDEO_MIN_CLK_FREQ / 16;
 880
 881         if ((rate < min_clk_rate) || (rate > AUDIO_VIDEO_MAX_CLK_FREQ))
 882                 return -EINVAL;
 883
 884         if (clk == &pll4_audio_main_clk)
 885                 pllbase = PLL4_AUDIO_BASE_ADDR;
 886         else
 887                 pllbase = PLL5_VIDEO_BASE_ADDR;
 888
 889         pre_div_rate = rate;
 890         if ((rev >= IMX_CHIP_REVISION_1_1) || cpu_is_mx6dl()) {
 891                 while (pre_div_rate < AUDIO_VIDEO_MIN_CLK_FREQ) {
 892                         pre_div_rate *= 2;
 893                         /*
 894                          * test_div_sel field values:
 895                          * 2 -> Divide by 1
 896                          * 1 -> Divide by 2
 897                          * 0 -> Divide by 4
 898                          *
 899                          * control3 field values:
 900                          * 0 -> Divide by 1
 901                          * 1 -> Divide by 2
 902                          * 3 -> Divide by 4
 903                          */
 904                         if (test_div_sel != 0)
 905                                 test_div_sel--;
 906                         else {
 907                                 control3++;
 908                                 if (control3 == 2)
 909                                         control3++;
 910                         }
 911                 }
 912         }
 913
 914         div = pre_div_rate / parent_rate;
 915         temp64 = (u64) (pre_div_rate - (div * parent_rate));
 916         temp64 *= mfd;
 917         do_div(temp64, parent_rate);
 918         mfn = temp64;
 919
 920         reg = __raw_readl(pllbase)
 921                         & ~ANADIG_PLL_SYS_DIV_SELECT_MASK
 922                         & ~ANADIG_PLL_AV_TEST_DIV_SEL_MASK;
 923         reg |= div |
 924                 (test_div_sel << ANADIG_PLL_AV_TEST_DIV_SEL_OFFSET);
 925         __raw_writel(reg, pllbase);
 926         __raw_writel(mfn, pllbase + PLL_NUM_DIV_OFFSET);
 927         __raw_writel(mfd, pllbase + PLL_DENOM_DIV_OFFSET);
 928
 929         if (rev >= IMX_CHIP_REVISION_1_1) {
 930                 reg = __raw_readl(ANA_MISC2_BASE_ADDR)
 931                         & ~ANADIG_ANA_MISC2_CONTROL3_MASK;
 932                 reg |= control3 << ANADIG_ANA_MISC2_CONTROL3_OFFSET;
 933                 __raw_writel(reg, ANA_MISC2_BASE_ADDR);
 934         }
 935
 936         return 0;
 937 }
 938
 939 static unsigned long _clk_audio_video_round_rate(struct clk *clk,
 940                                                 unsigned long rate)
 941 {
 942         unsigned long min_clk_rate;
 943         unsigned int div, post_div = 1;
 944         unsigned int mfn, mfd = 1000000;
 945         s64 temp64;
 946         unsigned int parent_rate = clk_get_rate(clk->parent);
 947         unsigned long pre_div_rate;
 948         u32 test_div_sel = 2;
 949         u32 control3 = 0;
 950         unsigned long final_rate;
 951         int rev = mx6q_revision();
 952
 953         if ((rev < IMX_CHIP_REVISION_1_1) && !cpu_is_mx6dl())
 954                 min_clk_rate = AUDIO_VIDEO_MIN_CLK_FREQ;
 955         else if (clk == &pll4_audio_main_clk)
 956                 min_clk_rate = AUDIO_VIDEO_MIN_CLK_FREQ / 4;
 957         else
 958                 min_clk_rate = AUDIO_VIDEO_MIN_CLK_FREQ / 16;
 959
 960         if (rate < min_clk_rate)
 961                 return min_clk_rate;
 962
 963         if (rate > AUDIO_VIDEO_MAX_CLK_FREQ)
 964                 return AUDIO_VIDEO_MAX_CLK_FREQ;
 965
 966         pre_div_rate = rate;
 967         if ((rev >= IMX_CHIP_REVISION_1_1) || cpu_is_mx6dl()) {
 968                 while (pre_div_rate < AUDIO_VIDEO_MIN_CLK_FREQ) {
 969                         pre_div_rate *= 2;
 970                         post_div *= 2;
 971                         if (test_div_sel != 0)
 972                                 test_div_sel--;
 973                         else {
 974                                 control3++;
 975                                 if (control3 == 2)
 976                                         control3++;
 977                         }
 978                 }
 979         }
 980
 981         div = pre_div_rate / parent_rate;
 982         temp64 = (u64) (pre_div_rate - (div * parent_rate));
 983         temp64 *= mfd;
 984         do_div(temp64, parent_rate);
 985         mfn = temp64;
 986
 987         final_rate = (parent_rate * div) + ((parent_rate / mfd) * mfn);
 988         final_rate = final_rate / post_div;
 989
 990         return final_rate;
 991 }
 992
 993 static int _clk_audio_video_set_parent(struct clk *clk, struct clk *parent)
 994 {
 995         u32 reg;
 996         int mux;
 997         void __iomem *pllbase;
 998
 999         if (clk == &pll4_audio_main_clk)
1000                 pllbase = PLL4_AUDIO_BASE_ADDR;
1001         else
1002                 pllbase = PLL5_VIDEO_BASE_ADDR;
1003
1004         reg = __raw_readl(pllbase) & ~ANADIG_PLL_BYPASS_CLK_SRC_MASK;
1005         mux = _get_mux6(parent, &osc_clk, &anaclk_1, &anaclk_2,
1006                                 NULL, NULL, NULL);
1007         reg |= mux << ANADIG_PLL_BYPASS_CLK_SRC_OFFSET;
1008         __raw_writel(reg, pllbase);
1009
1010         /* Set anaclk_x as input */
1011         if (parent == &anaclk_1) {
1012                 reg = __raw_readl(ANADIG_MISC1_REG);
1013                 reg |= (ANATOP_LVDS_CLK1_IBEN_MASK &
1014                                 ~ANATOP_LVDS_CLK1_OBEN_MASK);
1015                 __raw_writel(reg, ANADIG_MISC1_REG);
1016         } else if (parent == &anaclk_2) {
1017                 reg = __raw_readl(ANADIG_MISC1_REG);
1018                 reg |= (ANATOP_LVDS_CLK2_IBEN_MASK &
1019                                 ~ANATOP_LVDS_CLK2_OBEN_MASK);
1020                 __raw_writel(reg, ANADIG_MISC1_REG);
1021         }
1022
1023         return 0;
1024 }
1025
1026 static struct clk pll4_audio_main_clk = {
1027         __INIT_CLK_DEBUG(pll4_audio_main_clk)
1028         .parent = &osc_clk,
1029         .enable = _clk_pll_enable,
1030         .disable = _clk_pll_disable,
1031         .set_rate = _clk_audio_video_set_rate,
1032         .get_rate = _clk_audio_video_get_rate,
1033         .round_rate = _clk_audio_video_round_rate,
1034         .set_parent = _clk_audio_video_set_parent,
1035 };
1036
1037 static struct clk pll5_video_main_clk = {
1038         __INIT_CLK_DEBUG(pll5_video_main_clk)
1039         .parent = &osc_clk,
1040         .enable = _clk_pll_enable,
1041         .disable = _clk_pll_disable,
1042         .set_rate = _clk_audio_video_set_rate,
1043         .get_rate = _clk_audio_video_get_rate,
1044         .round_rate = _clk_audio_video_round_rate,
1045         .set_parent = _clk_audio_video_set_parent,
1046 };
1047
1048 static int _clk_pll_mlb_main_enable(struct clk *clk)
1049 {
1050         unsigned int reg;
1051         void __iomem *pllbase;
1052
1053         pllbase = _get_pll_base(clk);
1054
1055         reg = __raw_readl(pllbase);
1056         reg &= ~ANADIG_PLL_BYPASS;
1057
1058         reg = 0x0da20000;
1059         __raw_writel(reg, pllbase);
1060
1061         /* Wait for PLL to lock */
1062         if (!WAIT(__raw_readl(pllbase) & ANADIG_PLL_LOCK,
1063                 SPIN_DELAY))
1064                 panic("pll enable failed\n");
1065
1066         return 0;
1067 }
1068
1069 static struct clk pll6_mlb150_main_clk = {
1070         __INIT_CLK_DEBUG(pll6_mlb150_main_clk)
1071         .parent = &osc_clk,
1072         .enable = _clk_pll_mlb_main_enable,
1073         .disable = _clk_pll_disable,
1074 };
1075
1076 static unsigned long _clk_pll7_usb_otg_get_rate(struct clk *clk)
1077 {
1078         unsigned int div;
1079         unsigned long val;
1080
1081         div = __raw_readl(PLL7_480_USB2_BASE_ADDR)
1082                 & ANADIG_PLL_480_DIV_SELECT_MASK;
1083
1084         if (div == 1)
1085                 val = clk_get_rate(clk->parent) * 22;
1086         else
1087                 val = clk_get_rate(clk->parent) * 20;
1088         return val;
1089 }
1090
1091 static int _clk_pll7_usb_otg_set_rate(struct clk *clk, unsigned long rate)
1092 {
1093         unsigned int reg,  div;
1094
1095         if (rate == 528000000)
1096                 div = 1;
1097         else if (rate == 480000000)
1098                 div = 0;
1099         else
1100                 return -EINVAL;
1101
1102         reg = __raw_readl(PLL7_480_USB2_BASE_ADDR);
1103         reg &= ~ANADIG_PLL_480_DIV_SELECT_MASK;
1104         reg |= div;
1105         __raw_writel(reg, PLL7_480_USB2_BASE_ADDR);
1106
1107         return 0;
1108 }
1109
1110 static struct clk pll7_usb_host_main_clk = {
1111         __INIT_CLK_DEBUG(pll7_usb_host_main_clk)
1112         .parent = &osc_clk,
1113         .enable = _clk_pll_enable,
1114         .disable = _clk_pll_disable,
1115         .set_rate = _clk_pll7_usb_otg_set_rate,
1116         .get_rate = _clk_pll7_usb_otg_get_rate,
1117
1118 };
1119
1120 static struct clk pll8_enet_main_clk = {
1121         __INIT_CLK_DEBUG(pll8_enet_main_clk)
1122         .parent = &osc_clk,
1123         .enable = _clk_pll_enable,
1124         .disable = _clk_pll_disable,
1125 };
1126
1127 static unsigned long _clk_arm_get_rate(struct clk *clk)
1128 {
1129         u32 cacrr, div;
1130
1131         cacrr = __raw_readl(MXC_CCM_CACRR);
1132         div = (cacrr & MXC_CCM_CACRR_ARM_PODF_MASK) + 1;
1133         return clk_get_rate(clk->parent) / div;
1134 }
1135
1136 static int _clk_arm_set_rate(struct clk *clk, unsigned long rate)
1137 {
1138         int i;
1139         u32 div;
1140         u32 parent_rate;
1141
1142
1143         for (i = 0; i < cpu_op_nr; i++) {
1144                 if (rate == cpu_op_tbl[i].cpu_rate)
1145                         break;
1146         }
1147         if (i >= cpu_op_nr)
1148                 return -EINVAL;
1149
1150         if (cpu_op_tbl[i].pll_rate != clk_get_rate(&pll1_sys_main_clk)) {
1151                 /* Change the PLL1 rate. */
1152                 if (pll2_pfd_400M.usecount != 0)
1153                         pll1_sw_clk.set_parent(&pll1_sw_clk, &pll2_pfd_400M);
1154                 else
1155                         pll1_sw_clk.set_parent(&pll1_sw_clk, &osc_clk);
1156                 pll1_sys_main_clk.set_rate(&pll1_sys_main_clk, cpu_op_tbl[i].pll_rate);
1157                 pll1_sw_clk.set_parent(&pll1_sw_clk, &pll1_sys_main_clk);
1158         }
1159
1160         parent_rate = clk_get_rate(clk->parent);
1161         div = parent_rate / rate;
1162
1163         if (div == 0)
1164                 div = 1;
1165
1166         if ((parent_rate / div) > rate)
1167                 div++;
1168
1169         if (div > 8)
1170                 return -1;
1171
1172         __raw_writel(div - 1, MXC_CCM_CACRR);
1173
1174         return 0;
1175 }
1176
1177 static struct clk cpu_clk = {
1178         __INIT_CLK_DEBUG(cpu_clk)
1179         .parent = &pll1_sw_clk,
1180         .set_rate = _clk_arm_set_rate,
1181         .get_rate = _clk_arm_get_rate,
1182 };
1183
1184 static int _clk_periph_set_parent(struct clk *clk, struct clk *parent)
1185 {
1186         u32 reg;
1187         int mux;
1188
1189         mux = _get_mux6(parent, &pll2_528_bus_main_clk, &pll2_pfd_400M,
1190                 &pll2_pfd_352M, &pll2_200M, &pll3_sw_clk, &osc_clk);
1191
1192         if (mux <= 3) {
1193                 /* Set the pre_periph_clk multiplexer */
1194                 reg = __raw_readl(MXC_CCM_CBCMR);
1195                 reg &= ~MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK;
1196                 reg |= mux << MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET;
1197                 __raw_writel(reg, MXC_CCM_CBCMR);
1198
1199                 /* Set the periph_clk_sel multiplexer. */
1200                 reg = __raw_readl(MXC_CCM_CBCDR);
1201                 reg &= ~MXC_CCM_CBCDR_PERIPH_CLK_SEL;
1202                 __raw_writel(reg, MXC_CCM_CBCDR);
1203         } else {
1204                 reg = __raw_readl(MXC_CCM_CBCDR);
1205                 /* Set the periph_clk2_podf divider to divide by 1. */
1206                 reg &= ~MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK;
1207                 __raw_writel(reg, MXC_CCM_CBCDR);
1208
1209                 /* Set the periph_clk2_sel mux. */
1210                 reg = __raw_readl(MXC_CCM_CBCMR);
1211                 reg &= ~MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK;
1212                 reg |= ((mux - 4) << MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET);
1213                 __raw_writel(reg, MXC_CCM_CBCMR);
1214
1215                 while (__raw_readl(MXC_CCM_CDHIPR))
1216                         ;
1217
1218                 reg = __raw_readl(MXC_CCM_CBCDR);
1219                 /* Set periph_clk_sel to select periph_clk2. */
1220                 reg |= MXC_CCM_CBCDR_PERIPH_CLK_SEL;
1221                 __raw_writel(reg, MXC_CCM_CBCDR);
1222         }
1223
1224         if (!WAIT(!(__raw_readl(MXC_CCM_CDHIPR)
1225              & MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY), SPIN_DELAY))
1226                 panic("_clk_periph_set_parent failed\n");
1227
1228         return 0;
1229 }
1230
1231 static unsigned long _clk_periph_get_rate(struct clk *clk)
1232 {
1233         u32 div = 1;
1234         u32 reg;
1235         unsigned long val;
1236
1237         if ((clk->parent == &pll3_sw_clk) || (clk->parent == &osc_clk)) {
1238                 reg = __raw_readl(MXC_CCM_CBCDR)
1239                         & MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK;
1240                 div = (reg >> MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET) + 1;
1241         }
1242         val = clk_get_rate(clk->parent) / div;
1243         return val;
1244 }
1245
1246 static struct clk periph_clk = {
1247         __INIT_CLK_DEBUG(periph_clk)
1248         .parent = &pll2_528_bus_main_clk,
1249         .set_parent = _clk_periph_set_parent,
1250         .get_rate = _clk_periph_get_rate,
1251 };
1252
1253 static unsigned long _clk_axi_get_rate(struct clk *clk)
1254 {
1255         u32 div, reg;
1256         unsigned long val;
1257
1258         reg = __raw_readl(MXC_CCM_CBCDR) & MXC_CCM_CBCDR_AXI_PODF_MASK;
1259         div = (reg >> MXC_CCM_CBCDR_AXI_PODF_OFFSET);
1260
1261         val = clk_get_rate(clk->parent) / (div + 1);
1262         return val;
1263 }
1264
1265 static int _clk_axi_set_rate(struct clk *clk, unsigned long rate)
1266 {
1267         u32 reg, div;
1268         u32 parent_rate = clk_get_rate(clk->parent);
1269
1270         div = parent_rate / rate;
1271
1272         if (div == 0)
1273                 div++;
1274         if (((parent_rate / div) != rate) || (div > 8))
1275                 return -EINVAL;
1276
1277         reg = __raw_readl(MXC_CCM_CBCDR);
1278         reg &= ~MXC_CCM_CBCDR_AXI_PODF_MASK;
1279         reg |= (div - 1) << MXC_CCM_CBCDR_AXI_PODF_OFFSET;
1280         __raw_writel(reg, MXC_CCM_CBCDR);
1281
1282         if (!WAIT(!(__raw_readl(MXC_CCM_CDHIPR)
1283              & MXC_CCM_CDHIPR_AXI_PODF_BUSY), SPIN_DELAY))
1284                 panic("pll _clk_axi_a_set_rate failed\n");
1285
1286         return 0;
1287 }
1288
1289 static unsigned long _clk_axi_round_rate(struct clk *clk,
1290                                                 unsigned long rate)
1291 {
1292         u32 div;
1293         u32 parent_rate = clk_get_rate(clk->parent);
1294
1295         div = parent_rate / rate;
1296
1297         /* Make sure rate is not greater than the maximum
1298          * value for the clock.
1299          * Also prevent a div of 0.
1300          */
1301
1302         if (div > 8)
1303                 div = 8;
1304         else if (div == 0)
1305                 div++;
1306
1307         return parent_rate / div;
1308 }
1309
1310 static int _clk_axi_set_parent(struct clk *clk, struct clk *parent)
1311 {
1312         u32 reg;
1313         int mux;
1314
1315         mux = _get_mux6(parent, &periph_clk, &pll2_pfd_400M,
1316                                 &pll3_pfd_540M, NULL, NULL, NULL);
1317
1318         if (mux == 0) {
1319                 /* Set the AXI_SEL mux */
1320                 reg = __raw_readl(MXC_CCM_CBCDR) & ~MXC_CCM_CBCDR_AXI_SEL;
1321                 __raw_writel(reg, MXC_CCM_CBCDR);
1322         } else {
1323                 /* Set the AXI_ALT_SEL mux. */
1324                 reg = __raw_readl(MXC_CCM_CBCDR)
1325                         & ~MXC_CCM_CBCDR_AXI_ALT_SEL_MASK;
1326                 reg |= ((mux - 1) << MXC_CCM_CBCDR_AXI_ALT_SEL_OFFSET);
1327                 __raw_writel(reg, MXC_CCM_CBCDR);
1328
1329                 /* Set the AXI_SEL mux */
1330                 reg = __raw_readl(MXC_CCM_CBCDR) & ~MXC_CCM_CBCDR_AXI_SEL;
1331                 reg |= MXC_CCM_CBCDR_AXI_SEL;
1332                 __raw_writel(reg, MXC_CCM_CBCDR);
1333         }
1334         return 0;
1335 }
1336
1337 static struct clk axi_clk = {
1338         __INIT_CLK_DEBUG(axi_clk)
1339         .parent = &periph_clk,
1340         .set_parent = _clk_axi_set_parent,
1341         .set_rate = _clk_axi_set_rate,
1342         .get_rate = _clk_axi_get_rate,
1343         .round_rate = _clk_axi_round_rate,
1344 };
1345
1346 static unsigned long _clk_ahb_get_rate(struct clk *clk)
1347 {
1348         u32 reg, div;
1349
1350         reg = __raw_readl(MXC_CCM_CBCDR);
1351         div = ((reg & MXC_CCM_CBCDR_AHB_PODF_MASK) >>
1352                MXC_CCM_CBCDR_AHB_PODF_OFFSET) + 1;
1353
1354         return clk_get_rate(clk->parent) / div;
1355 }
1356
1357 static int _clk_ahb_set_rate(struct clk *clk, unsigned long rate)
1358 {
1359         u32 reg, div;
1360         u32 parent_rate = clk_get_rate(clk->parent);
1361
1362         div = parent_rate / rate;
1363         if (div == 0)
1364                 div++;
1365         if (((parent_rate / div) != rate) || (div > 8))
1366                 return -EINVAL;
1367
1368         reg = __raw_readl(MXC_CCM_CBCDR);
1369         reg &= ~MXC_CCM_CBCDR_AHB_PODF_MASK;
1370         reg |= (div - 1) << MXC_CCM_CBCDR_AHB_PODF_OFFSET;
1371         __raw_writel(reg, MXC_CCM_CBCDR);
1372
1373         if (!WAIT(!(__raw_readl(MXC_CCM_CDHIPR) & MXC_CCM_CDHIPR_AHB_PODF_BUSY),
1374                                 SPIN_DELAY))
1375                         panic("_clk_ahb_set_rate failed\n");
1376
1377         return 0;
1378 }
1379
1380 static unsigned long _clk_ahb_round_rate(struct clk *clk,
1381                                                 unsigned long rate)
1382 {
1383         u32 div;
1384         u32 parent_rate = clk_get_rate(clk->parent);
1385
1386         div = parent_rate / rate;
1387
1388         /* Make sure rate is not greater than the maximum value for the clock.
1389          * Also prevent a div of 0.
1390          */
1391         if (div == 0)
1392                 div++;
1393
1394         if (div > 8)
1395                 div = 8;
1396
1397         return parent_rate / div;
1398 }
1399
1400 static struct clk ahb_clk = {
1401         __INIT_CLK_DEBUG(ahb_clk)
1402         .parent = &periph_clk,
1403         .get_rate = _clk_ahb_get_rate,
1404         .set_rate = _clk_ahb_set_rate,
1405         .round_rate = _clk_ahb_round_rate,
1406 };
1407
1408 static unsigned long _clk_ipg_get_rate(struct clk *clk)
1409 {
1410         u32 reg, div;
1411
1412         reg = __raw_readl(MXC_CCM_CBCDR);
1413         div = ((reg & MXC_CCM_CBCDR_IPG_PODF_MASK) >>
1414                 MXC_CCM_CBCDR_IPG_PODF_OFFSET) + 1;
1415
1416         return clk_get_rate(clk->parent) / div;
1417 }
1418
1419
1420 static struct clk ipg_clk = {
1421         __INIT_CLK_DEBUG(ipg_clk)
1422         .parent = &ahb_clk,
1423         .get_rate = _clk_ipg_get_rate,
1424 };
1425
1426 static struct clk tzasc1_clk = {
1427         __INIT_CLK_DEBUG(tzasc1_clk)
1428         .id = 0,
1429         .parent = &ipg_clk,
1430         .enable_reg = MXC_CCM_CCGR2,
1431         .enable_shift = MXC_CCM_CCGRx_CG11_OFFSET,
1432         .enable = _clk_enable,
1433         .disable = _clk_disable_inwait,
1434 };
1435
1436 static struct clk tzasc2_clk = {
1437         __INIT_CLK_DEBUG(tzasc2_clk)
1438         .id = 0,
1439         .parent = &ipg_clk,
1440         .enable_reg = MXC_CCM_CCGR2,
1441         .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET,
1442         .enable = _clk_enable,
1443         .disable = _clk_disable_inwait,
1444 };
1445
1446 static struct clk mx6fast1_clk = {
1447         __INIT_CLK_DEBUG(mx6fast1_clk)
1448         .id = 0,
1449         .parent = &ahb_clk,
1450         .enable_reg = MXC_CCM_CCGR4,
1451         .enable_shift = MXC_CCM_CCGRx_CG4_OFFSET,
1452         .enable = _clk_enable,
1453         .disable = _clk_disable_inwait,
1454 };
1455
1456 static struct clk mx6per1_clk = {
1457         __INIT_CLK_DEBUG(mx6per1_clk)
1458         .id = 0,
1459         .parent = &ahb_clk,
1460         .secondary = &mx6fast1_clk,
1461         .enable_reg = MXC_CCM_CCGR4,
1462         .enable_shift = MXC_CCM_CCGRx_CG6_OFFSET,
1463         .enable = _clk_enable,
1464         .disable = _clk_disable_inwait,
1465 };
1466
1467 static struct clk mx6per2_clk = {
1468         __INIT_CLK_DEBUG(mx6per2_clk)
1469         .id = 0,
1470         .parent = &ahb_clk,
1471         .enable_reg = MXC_CCM_CCGR4,
1472         .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
1473         .enable = _clk_enable,
1474         .disable = _clk_disable_inwait,
1475 };
1476
1477 static unsigned long _clk_mmdc_ch0_axi_get_rate(struct clk *clk)
1478 {
1479         u32 reg, div;
1480
1481         reg = __raw_readl(MXC_CCM_CBCDR);
1482         div = ((reg & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
1483                         MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET) + 1;
1484
1485         return clk_get_rate(clk->parent) / div;
1486 }
1487
1488 static int _clk_mmdc_ch0_axi_set_rate(struct clk *clk, unsigned long rate)
1489 {
1490         u32 reg, div;
1491         u32 parent_rate = clk_get_rate(clk->parent);
1492
1493         div = parent_rate / rate;
1494         if (div == 0)
1495                 div++;
1496         if (((parent_rate / div) != rate) || (div > 8))
1497                 return -EINVAL;
1498
1499         reg = __raw_readl(MXC_CCM_CBCDR);
1500         reg &= ~MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK;
1501         reg |= (div - 1) << MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
1502         __raw_writel(reg, MXC_CCM_CBCDR);
1503
1504         if (!WAIT(!(__raw_readl(MXC_CCM_CDHIPR)
1505                 & MXC_CCM_CDHIPR_MMDC_CH0_PODF_BUSY),
1506                                 SPIN_DELAY))
1507                         panic("_clk_mmdc_ch0_axi_set_rate failed\n");
1508
1509         return 0;
1510 }
1511
1512 static unsigned long _clk_mmdc_ch0_axi_round_rate(struct clk *clk,
1513                                                 unsigned long rate)
1514 {
1515         u32 div;
1516         u32 parent_rate = clk_get_rate(clk->parent);
1517
1518         div = parent_rate / rate;
1519
1520         /* Make sure rate is not greater than the maximum value for the clock.
1521          * Also prevent a div of 0.
1522          */
1523         if (div == 0)
1524                 div++;
1525
1526         if (div > 8)
1527                 div = 8;
1528
1529         return parent_rate / div;
1530 }
1531
1532 static struct clk mmdc_ch0_axi_clk[] = {
1533         {
1534         __INIT_CLK_DEBUG(mmdc_ch0_axi_clk)
1535         .id = 0,
1536         .parent = &periph_clk,
1537         .enable = _clk_enable,
1538         .disable = _clk_disable_inwait,
1539         .enable_reg = MXC_CCM_CCGR3,
1540         .enable_shift = MXC_CCM_CCGRx_CG10_OFFSET,
1541         .secondary = &mmdc_ch0_axi_clk[1],
1542         .get_rate = _clk_mmdc_ch0_axi_get_rate,
1543         .set_rate = _clk_mmdc_ch0_axi_set_rate,
1544         .round_rate = _clk_mmdc_ch0_axi_round_rate,
1545         },
1546         {
1547         __INIT_CLK_DEBUG(mmdc_ch0_ipg_clk)
1548         .id = 0,
1549         .parent = &ipg_clk,
1550         .enable = _clk_enable,
1551         .disable = _clk_disable_inwait,
1552         .enable_reg = MXC_CCM_CCGR3,
1553         .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET,
1554         .secondary = &tzasc1_clk,
1555         },
1556 };
1557
1558 static unsigned long _clk_mmdc_ch1_axi_get_rate(struct clk *clk)
1559 {
1560         u32 reg, div;
1561
1562         reg = __raw_readl(MXC_CCM_CBCDR);
1563         div = ((reg & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) >>
1564                         MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET) + 1;
1565
1566         return clk_get_rate(clk->parent) / div;
1567 }
1568
1569 static int _clk_mmdc_ch1_axi_set_rate(struct clk *clk, unsigned long rate)
1570 {
1571         u32 reg, div;
1572         u32 parent_rate = clk_get_rate(clk->parent);
1573
1574         div = parent_rate / rate;
1575         if (div == 0)
1576                 div++;
1577         if (((parent_rate / div) != rate) || (div > 8))
1578                 return -EINVAL;
1579
1580         reg = __raw_readl(MXC_CCM_CBCDR);
1581         reg &= ~MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK;
1582         reg |= (div - 1) << MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
1583         __raw_writel(reg, MXC_CCM_CBCDR);
1584
1585         if (!WAIT(!(__raw_readl(MXC_CCM_CDHIPR)
1586                 & MXC_CCM_CDHIPR_MMDC_CH1_PODF_BUSY), SPIN_DELAY))
1587                         panic("_clk_mmdc_ch1_axi_set_rate failed\n");
1588
1589         return 0;
1590 }
1591
1592 static unsigned long _clk_mmdc_ch1_axi_round_rate(struct clk *clk,
1593                                                 unsigned long rate)
1594 {
1595         u32 div;
1596         u32 parent_rate = clk_get_rate(clk->parent);
1597
1598         div = parent_rate / rate;
1599
1600         /* Make sure rate is not greater than the maximum value for the clock.
1601          * Also prevent a div of 0.
1602          */
1603         if (div == 0)
1604                 div++;
1605
1606         if (div > 8)
1607                 div = 8;
1608
1609         return parent_rate / div;
1610 }
1611
1612 static struct clk mmdc_ch1_axi_clk[] = {
1613         {
1614         __INIT_CLK_DEBUG(mmdc_ch1_axi_clk)
1615         .id = 0,
1616         .parent = &pll2_pfd_400M,
1617         .enable = _clk_enable,
1618         .disable = _clk_disable,
1619         .enable_reg = MXC_CCM_CCGR3,
1620         .enable_shift = MXC_CCM_CCGRx_CG11_OFFSET,
1621         .secondary = &mmdc_ch1_axi_clk[1],
1622         .get_rate = _clk_mmdc_ch1_axi_get_rate,
1623         .set_rate = _clk_mmdc_ch1_axi_set_rate,
1624         .round_rate = _clk_mmdc_ch1_axi_round_rate,
1625         },
1626         {
1627         .id = 1,
1628         __INIT_CLK_DEBUG(mmdc_ch1_ipg_clk)
1629         .parent = &ipg_clk,
1630         .enable = _clk_enable,
1631         .disable = _clk_disable,
1632         .enable_reg = MXC_CCM_CCGR3,
1633         .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
1634         .secondary = &tzasc2_clk,
1635         },
1636 };
1637
1638 static struct clk ocram_clk = {
1639         __INIT_CLK_DEBUG(ocram_clk)
1640         .id = 0,
1641         .parent = &ahb_clk,
1642         .enable_reg = MXC_CCM_CCGR3,
1643         .enable_shift = MXC_CCM_CCGRx_CG14_OFFSET,
1644         .enable = _clk_enable,
1645         .disable = _clk_disable_inwait,
1646 };
1647
1648 static unsigned long _clk_ipg_perclk_get_rate(struct clk *clk)
1649 {
1650         u32 reg, div;
1651
1652         reg = __raw_readl(MXC_CCM_CSCMR1);
1653         div = ((reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK) >>
1654                         MXC_CCM_CSCMR1_PERCLK_PODF_OFFSET) + 1;
1655
1656         return clk_get_rate(clk->parent) / div;
1657 }
1658
1659 static int _clk_ipg_perclk_set_rate(struct clk *clk, unsigned long rate)
1660 {
1661         u32 reg, div;
1662         u32 parent_rate = clk_get_rate(clk->parent);
1663
1664         div = parent_rate / rate;
1665         if (div == 0)
1666                 div++;
1667         if (((parent_rate / div) != rate) || (div > 64))
1668                 return -EINVAL;
1669
1670         reg = __raw_readl(MXC_CCM_CSCMR1);
1671         reg &= ~MXC_CCM_CSCMR1_PERCLK_PODF_MASK;
1672         reg |= (div - 1) << MXC_CCM_CSCMR1_PERCLK_PODF_OFFSET;
1673         __raw_writel(reg, MXC_CCM_CSCMR1);
1674
1675         return 0;
1676 }
1677
1678
1679 static unsigned long _clk_ipg_perclk_round_rate(struct clk *clk,
1680                                                 unsigned long rate)
1681 {
1682         u32 div;
1683         u32 parent_rate = clk_get_rate(clk->parent);
1684
1685         div = parent_rate / rate;
1686
1687         /* Make sure rate is not greater than the maximum value for the clock.
1688          * Also prevent a div of 0.
1689          */
1690         if (div == 0)
1691                 div++;
1692
1693         if (div > 64)
1694                 div = 64;
1695
1696         return parent_rate / div;
1697 }
1698
1699 static struct clk ipg_perclk = {
1700         __INIT_CLK_DEBUG(ipg_perclk)
1701         .parent = &ipg_clk,
1702         .get_rate = _clk_ipg_perclk_get_rate,
1703         .set_rate = _clk_ipg_perclk_set_rate,
1704         .round_rate = _clk_ipg_perclk_round_rate,
1705 };
1706
1707 static struct clk spba_clk = {
1708         __INIT_CLK_DEBUG(spba_clk)
1709         .parent = &ipg_clk,
1710         .enable_reg = MXC_CCM_CCGR5,
1711         .enable_shift = MXC_CCM_CCGRx_CG6_OFFSET,
1712         .enable = _clk_enable,
1713         .disable = _clk_disable,
1714 };
1715
1716 static struct clk sdma_clk[] = {
1717         {
1718          __INIT_CLK_DEBUG(sdma_clk)
1719          .parent = &ahb_clk,
1720          .enable_reg = MXC_CCM_CCGR5,
1721          .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET,
1722          .enable = _clk_enable,
1723          .disable = _clk_disable,
1724          .secondary = &sdma_clk[1],
1725         },
1726         {
1727          .parent = &mx6per1_clk,
1728 #ifdef CONFIG_SDMA_IRAM
1729          .secondary = &ocram_clk,
1730 #else
1731         .secondary = &mmdc_ch0_axi_clk[0],
1732 #endif
1733         },
1734 };
1735
1736 static int _clk_gpu2d_axi_set_parent(struct clk *clk, struct clk *parent)
1737 {
1738         u32 reg = __raw_readl(MXC_CCM_CBCMR) & ~MXC_CCM_CBCMR_GPU2D_AXI_CLK_SEL;
1739
1740         if (parent == &ahb_clk)
1741                 reg |= MXC_CCM_CBCMR_GPU2D_AXI_CLK_SEL;
1742
1743         __raw_writel(reg, MXC_CCM_CBCMR);
1744
1745         return 0;
1746 }
1747
1748 static struct clk gpu2d_axi_clk = {
1749         __INIT_CLK_DEBUG(gpu2d_axi_clk)
1750         .parent = &axi_clk,
1751         .secondary = &openvg_axi_clk,
1752         .set_parent = _clk_gpu2d_axi_set_parent,
1753 };
1754
1755 static int _clk_gpu3d_axi_set_parent(struct clk *clk, struct clk *parent)
1756 {
1757         u32 reg = __raw_readl(MXC_CCM_CBCMR) & ~MXC_CCM_CBCMR_GPU3D_AXI_CLK_SEL;
1758
1759         if (parent == &ahb_clk)
1760                 reg |= MXC_CCM_CBCMR_GPU3D_AXI_CLK_SEL;
1761
1762         __raw_writel(reg, MXC_CCM_CBCMR);
1763
1764         return 0;
1765 }
1766
1767 static struct clk gpu3d_axi_clk = {
1768         __INIT_CLK_DEBUG(gpu3d_axi_clk)
1769         .parent = &axi_clk,
1770         .secondary = &mmdc_ch0_axi_clk[0],
1771         .set_parent = _clk_gpu3d_axi_set_parent,
1772 };
1773
1774 static int _clk_pcie_axi_set_parent(struct clk *clk, struct clk *parent)
1775 {
1776         u32 reg = __raw_readl(MXC_CCM_CBCMR) & ~MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL;
1777
1778         if (parent == &ahb_clk)
1779                 reg |= MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL;
1780
1781         __raw_writel(reg, MXC_CCM_CBCMR);
1782
1783         return 0;
1784 }
1785
1786 static struct clk pcie_axi_clk = {
1787         __INIT_CLK_DEBUG(pcie_axi_clk)
1788         .parent = &axi_clk,
1789         .set_parent = _clk_pcie_axi_set_parent,
1790 };
1791
1792 static int _clk_vdo_axi_set_parent(struct clk *clk, struct clk *parent)
1793 {
1794         u32 reg = __raw_readl(MXC_CCM_CBCMR) & ~MXC_CCM_CBCMR_VDOAXI_CLK_SEL;
1795
1796         if (parent == &ahb_clk)
1797                 reg |= MXC_CCM_CBCMR_VDOAXI_CLK_SEL;
1798
1799         __raw_writel(reg, MXC_CCM_CBCMR);
1800
1801         return 0;
1802 }
1803
1804 static struct clk vdo_axi_clk = {
1805         __INIT_CLK_DEBUG(vdo_axi_clk)
1806         .parent = &axi_clk,
1807         .enable_reg = MXC_CCM_CCGR6,
1808         .enable_shift = MXC_CCM_CCGRx_CG6_OFFSET,
1809         .enable = _clk_enable,
1810         .disable = _clk_disable,
1811         .set_parent = _clk_vdo_axi_set_parent,
1812 };
1813
1814 static struct clk vdoa_clk = {
1815         __INIT_CLK_DEBUG(vdoa_clk)
1816         .id = 0,
1817         .parent = &axi_clk,
1818         .secondary = &mx6fast1_clk,
1819         .enable_reg = MXC_CCM_CCGR2,
1820         .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
1821         .enable = _clk_enable,
1822         .disable = _clk_disable,
1823 };
1824
1825 static unsigned long _clk_gpt_get_rate(struct clk *clk)
1826 {
1827         unsigned long rate;
1828
1829         if (mx6q_revision() == IMX_CHIP_REVISION_1_0)
1830                 return clk_get_rate(clk->parent);
1831
1832         rate = mx6_timer_rate();
1833         if (!rate)
1834                 return clk_get_rate(clk->parent);
1835
1836         return rate;
1837 }
1838
1839 static struct clk gpt_clk[] = {
1840         {
1841         __INIT_CLK_DEBUG(gpt_clk)
1842          .parent = &osc_clk,
1843          .id = 0,
1844          .enable_reg = MXC_CCM_CCGR1,
1845          .enable_shift = MXC_CCM_CCGRx_CG10_OFFSET,
1846          .enable = _clk_enable,
1847          .disable = _clk_disable,
1848          .get_rate = _clk_gpt_get_rate,
1849          .secondary = &gpt_clk[1],
1850          },
1851         {
1852         __INIT_CLK_DEBUG(gpt_serial_clk)
1853          .id = 0,
1854          .enable_reg = MXC_CCM_CCGR1,
1855          .enable_shift = MXC_CCM_CCGRx_CG11_OFFSET,
1856          .enable = _clk_enable,
1857          .disable = _clk_disable,
1858          },
1859 };
1860
1861 static unsigned long _clk_iim_get_rate(struct clk *clk)
1862 {
1863         return clk_get_rate(clk->parent);
1864 }
1865
1866 static struct clk iim_clk = {
1867         __INIT_CLK_DEBUG(iim_clk)
1868         .parent = &ipg_clk,
1869         .enable = _clk_enable,
1870         .enable_reg = MXC_CCM_CCGR2,
1871         .enable_shift = MXC_CCM_CCGRx_CG6_OFFSET,
1872         .disable = _clk_disable,
1873         .get_rate = _clk_iim_get_rate,
1874 };
1875
1876 static struct clk i2c_clk[] = {
1877         {
1878         __INIT_CLK_DEBUG(i2c_clk_0)
1879          .id = 0,
1880          .parent = &ipg_perclk,
1881          .enable_reg = MXC_CCM_CCGR2,
1882          .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET,
1883          .enable = _clk_enable,
1884          .disable = _clk_disable,
1885          },
1886         {
1887         __INIT_CLK_DEBUG(i2c_clk_1)
1888          .id = 1,
1889          .parent = &ipg_perclk,
1890          .enable_reg = MXC_CCM_CCGR2,
1891          .enable_shift = MXC_CCM_CCGRx_CG4_OFFSET,
1892          .enable = _clk_enable,
1893          .disable = _clk_disable,
1894          },
1895         {
1896         __INIT_CLK_DEBUG(i2c_clk_2)
1897          .id = 2,
1898          .parent = &ipg_perclk,
1899          .enable_reg = MXC_CCM_CCGR2,
1900          .enable_shift = MXC_CCM_CCGRx_CG5_OFFSET,
1901          .enable = _clk_enable,
1902          .disable = _clk_disable,
1903          },
1904 };
1905
1906 static int _clk_vpu_axi_set_parent(struct clk *clk, struct clk *parent)
1907 {
1908         int mux;
1909         u32 reg = __raw_readl(MXC_CCM_CBCMR)
1910                 & ~MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK;
1911
1912         mux = _get_mux6(parent, &axi_clk, &pll2_pfd_400M,
1913                 &pll2_pfd_352M, NULL, NULL, NULL);
1914
1915         reg |= (mux << MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET);
1916
1917         __raw_writel(reg, MXC_CCM_CBCMR);
1918
1919         return 0;
1920 }
1921
1922 static unsigned long _clk_vpu_axi_get_rate(struct clk *clk)
1923 {
1924         u32 reg, div;
1925
1926         reg = __raw_readl(MXC_CCM_CSCDR1);
1927         div = ((reg & MXC_CCM_CSCDR1_VPU_AXI_PODF_MASK) >>
1928                         MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET) + 1;
1929
1930         return clk_get_rate(clk->parent) / div;
1931 }
1932
1933 static int _clk_vpu_axi_set_rate(struct clk *clk, unsigned long rate)
1934 {
1935         u32 reg, div;
1936         u32 parent_rate = clk_get_rate(clk->parent);
1937
1938         div = parent_rate / rate;
1939         if (div == 0)
1940                 div++;
1941         if (((parent_rate / div) != rate) || (div > 8))
1942                 return -EINVAL;
1943
1944         reg = __raw_readl(MXC_CCM_CSCDR1);
1945         reg &= ~MXC_CCM_CSCDR1_VPU_AXI_PODF_MASK;
1946         reg |= (div - 1) << MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET;
1947         __raw_writel(reg, MXC_CCM_CSCDR1);
1948
1949         return 0;
1950 }
1951
1952 static unsigned long _clk_vpu_axi_round_rate(struct clk *clk,
1953                                                 unsigned long rate)
1954 {
1955         u32 div;
1956         u32 parent_rate = clk_get_rate(clk->parent);
1957
1958         div = parent_rate / rate;
1959
1960         /* Make sure rate is not greater than the maximum value for the clock.
1961          * Also prevent a div of 0.
1962          */
1963         if (div == 0)
1964                 div++;
1965
1966         if (div > 8)
1967                 div = 8;
1968
1969         return parent_rate / div;
1970 }
1971
1972 static struct clk vpu_clk[] = {
1973         {
1974         __INIT_CLK_DEBUG(vpu_clk)
1975         .parent = &axi_clk,
1976         .enable_reg = MXC_CCM_CCGR6,
1977         .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
1978         .enable = _clk_enable,
1979         .disable = _clk_disable,
1980         .set_parent = _clk_vpu_axi_set_parent,
1981         .round_rate = _clk_vpu_axi_round_rate,
1982         .set_rate = _clk_vpu_axi_set_rate,
1983         .get_rate = _clk_vpu_axi_get_rate,
1984         .secondary = &vpu_clk[1],
1985         },
1986         {
1987         .parent =  &mmdc_ch0_axi_clk[0],
1988         .secondary = &vpu_clk[2],
1989         },
1990         {
1991         .parent =  &mx6fast1_clk,
1992         .secondary = &ocram_clk,
1993         },
1994
1995 };
1996
1997 static int _clk_ipu1_set_parent(struct clk *clk, struct clk *parent)
1998 {
1999         int mux;
2000         u32 reg = __raw_readl(MXC_CCM_CSCDR3)
2001                 & ~MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_MASK;
2002
2003         mux = _get_mux6(parent, &mmdc_ch0_axi_clk[0],
2004                 &pll2_pfd_400M, &pll3_120M, &pll3_pfd_540M, NULL, NULL);
2005
2006         reg |= (mux << MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_OFFSET);
2007
2008         __raw_writel(reg, MXC_CCM_CSCDR3);
2009
2010         return 0;
2011 }
2012
2013 static unsigned long _clk_ipu1_get_rate(struct clk *clk)
2014 {
2015         u32 reg, div;
2016
2017         reg = __raw_readl(MXC_CCM_CSCDR3);
2018         div = ((reg & MXC_CCM_CSCDR3_IPU1_HSP_PODF_MASK) >>
2019                         MXC_CCM_CSCDR3_IPU1_HSP_PODF_OFFSET) + 1;
2020
2021         return clk_get_rate(clk->parent) / div;
2022 }
2023
2024 static int _clk_ipu1_set_rate(struct clk *clk, unsigned long rate)
2025 {
2026         u32 reg, div;
2027         u32 parent_rate = clk_get_rate(clk->parent);
2028
2029         div = parent_rate / rate;
2030         if (div == 0)
2031                 div++;
2032         if (((parent_rate / div) != rate) || (div > 8))
2033                 return -EINVAL;
2034
2035         reg = __raw_readl(MXC_CCM_CSCDR3);
2036         reg &= ~MXC_CCM_CSCDR3_IPU1_HSP_PODF_MASK;
2037         reg |= (div - 1) << MXC_CCM_CSCDR3_IPU1_HSP_PODF_OFFSET;
2038         __raw_writel(reg, MXC_CCM_CSCDR3);
2039
2040         return 0;
2041 }
2042
2043 static unsigned long _clk_ipu_round_rate(struct clk *clk,
2044                                                 unsigned long rate)
2045 {
2046         u32 div;
2047         u32 parent_rate = clk_get_rate(clk->parent);
2048
2049         div = parent_rate / rate;
2050
2051         /* Make sure rate is not greater than the maximum value for the clock.
2052          * Also prevent a div of 0.
2053          */
2054         if (div == 0)
2055                 div++;
2056
2057         if (div > 8)
2058                 div = 8;
2059
2060         return parent_rate / div;
2061 }
2062
2063 static struct clk ipu1_clk = {
2064         __INIT_CLK_DEBUG(ipu1_clk)
2065         .parent = &mmdc_ch0_axi_clk[0],
2066         .secondary = &mmdc_ch0_axi_clk[0],
2067         .enable_reg = MXC_CCM_CCGR3,
2068         .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET,
2069         .enable = _clk_enable,
2070         .disable = _clk_disable,
2071         .set_parent = _clk_ipu1_set_parent,
2072         .round_rate = _clk_ipu_round_rate,
2073         .set_rate = _clk_ipu1_set_rate,
2074         .get_rate = _clk_ipu1_get_rate,
2075         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
2076 };
2077
2078 static int _clk_ipu2_set_parent(struct clk *clk, struct clk *parent)
2079 {
2080         int mux;
2081         u32 reg = __raw_readl(MXC_CCM_CSCDR3)
2082                 & ~MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_MASK;
2083
2084         mux = _get_mux6(parent, &mmdc_ch0_axi_clk[0],
2085                 &pll2_pfd_400M, &pll3_120M, &pll3_pfd_540M, NULL, NULL);
2086
2087         reg |= (mux << MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_OFFSET);
2088
2089         __raw_writel(reg, MXC_CCM_CSCDR3);
2090
2091         return 0;
2092 }
2093
2094 static unsigned long _clk_ipu2_get_rate(struct clk *clk)
2095 {
2096         u32 reg, div;
2097
2098         reg = __raw_readl(MXC_CCM_CSCDR3);
2099         div = ((reg & MXC_CCM_CSCDR3_IPU2_HSP_PODF_MASK) >>
2100                         MXC_CCM_CSCDR3_IPU2_HSP_PODF_OFFSET) + 1;
2101
2102         return clk_get_rate(clk->parent) / div;
2103 }
2104
2105 static int _clk_ipu2_set_rate(struct clk *clk, unsigned long rate)
2106 {
2107         u32 reg, div;
2108         u32 parent_rate = clk_get_rate(clk->parent);
2109
2110         div = parent_rate / rate;
2111         if (div == 0)
2112                 div++;
2113         if (((parent_rate / div) != rate) || (div > 8))
2114                 return -EINVAL;
2115
2116         reg = __raw_readl(MXC_CCM_CSCDR3);
2117         reg &= ~MXC_CCM_CSCDR3_IPU2_HSP_PODF_MASK;
2118         reg |= (div - 1) << MXC_CCM_CSCDR3_IPU2_HSP_PODF_OFFSET;
2119         __raw_writel(reg, MXC_CCM_CSCDR3);
2120
2121         return 0;
2122 }
2123
2124 static struct clk ipu2_clk = {
2125         __INIT_CLK_DEBUG(ipu2_clk)
2126         .parent = &mmdc_ch0_axi_clk[0],
2127         .secondary = &mmdc_ch0_axi_clk[0],
2128         .enable_reg = MXC_CCM_CCGR3,
2129         .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET,
2130         .enable = _clk_enable,
2131         .disable = _clk_disable,
2132         .set_parent = _clk_ipu2_set_parent,
2133         .round_rate = _clk_ipu_round_rate,
2134         .set_rate = _clk_ipu2_set_rate,
2135         .get_rate = _clk_ipu2_get_rate,
2136         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
2137 };
2138
2139 static struct clk usdhc_dep_clk = {
2140         .parent = &mmdc_ch0_axi_clk[0],
2141         .secondary = &mx6per1_clk,
2142         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
2143         };
2144
2145 static unsigned long _clk_usdhc_round_rate(struct clk *clk,
2146                                                 unsigned long rate)
2147 {
2148         u32 div;
2149         u32 parent_rate = clk_get_rate(clk->parent);
2150
2151         div = parent_rate / rate;
2152
2153         /* Make sure rate is not greater than the maximum value for the clock.
2154          * Also prevent a div of 0.
2155          */
2156         if (div == 0)
2157                 div++;
2158
2159         if (div > 8)
2160                 div = 8;
2161
2162         return parent_rate / div;
2163 }
2164
2165 static int _clk_usdhc1_set_parent(struct clk *clk, struct clk *parent)
2166 {
2167         u32 reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_USDHC1_CLK_SEL;
2168
2169         if (parent == &pll2_pfd_352M)
2170                 reg |= (MXC_CCM_CSCMR1_USDHC1_CLK_SEL);
2171
2172         __raw_writel(reg, MXC_CCM_CSCMR1);
2173
2174         return 0;
2175 }
2176
2177 static unsigned long _clk_usdhc1_get_rate(struct clk *clk)
2178 {
2179         u32 reg, div;
2180
2181         reg = __raw_readl(MXC_CCM_CSCDR1);
2182         div = ((reg & MXC_CCM_CSCDR1_USDHC1_PODF_MASK) >>
2183                         MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET) + 1;
2184
2185         return clk_get_rate(clk->parent) / div;
2186 }
2187
2188 static int _clk_usdhc1_set_rate(struct clk *clk, unsigned long rate)
2189 {
2190         u32 reg, div;
2191         u32 parent_rate = clk_get_rate(clk->parent);
2192
2193         div = parent_rate / rate;
2194         if (div == 0)
2195                 div++;
2196         if (((parent_rate / div) != rate) || (div > 8))
2197                 return -EINVAL;
2198
2199         reg = __raw_readl(MXC_CCM_CSCDR1);
2200         reg &= ~MXC_CCM_CSCDR1_USDHC1_PODF_MASK;
2201         reg |= (div - 1) << MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET;
2202         __raw_writel(reg, MXC_CCM_CSCDR1);
2203
2204         return 0;
2205 }
2206
2207 static struct clk usdhc1_clk = {
2208         __INIT_CLK_DEBUG(usdhc1_clk)
2209         .id = 0,
2210         .parent = &pll2_pfd_400M,
2211         .secondary = &usdhc_dep_clk,
2212         .enable_reg = MXC_CCM_CCGR6,
2213         .enable_shift = MXC_CCM_CCGRx_CG1_OFFSET,
2214         .enable = _clk_enable,
2215         .disable = _clk_disable,
2216         .set_parent = _clk_usdhc1_set_parent,
2217         .round_rate = _clk_usdhc_round_rate,
2218         .set_rate = _clk_usdhc1_set_rate,
2219         .get_rate = _clk_usdhc1_get_rate,
2220         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
2221 };
2222
2223 static int _clk_usdhc2_set_parent(struct clk *clk, struct clk *parent)
2224 {
2225         u32 reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_USDHC2_CLK_SEL;
2226
2227         if (parent == &pll2_pfd_352M)
2228                 reg |= (MXC_CCM_CSCMR1_USDHC2_CLK_SEL);
2229
2230         __raw_writel(reg, MXC_CCM_CSCMR1);
2231
2232         return 0;
2233 }
2234
2235 static unsigned long _clk_usdhc2_get_rate(struct clk *clk)
2236 {
2237         u32 reg, div;
2238
2239         reg = __raw_readl(MXC_CCM_CSCDR1);
2240         div = ((reg & MXC_CCM_CSCDR1_USDHC2_PODF_MASK) >>
2241                         MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET) + 1;
2242
2243         return clk_get_rate(clk->parent) / div;
2244 }
2245
2246 static int _clk_usdhc2_set_rate(struct clk *clk, unsigned long rate)
2247 {
2248         u32 reg, div;
2249         u32 parent_rate = clk_get_rate(clk->parent);
2250
2251         div = parent_rate / rate;
2252         if (div == 0)
2253                 div++;
2254         if (((parent_rate / div) != rate) || (div > 8))
2255                 return -EINVAL;
2256
2257         reg = __raw_readl(MXC_CCM_CSCDR1);
2258         reg &= ~MXC_CCM_CSCDR1_USDHC2_PODF_MASK;
2259         reg |= (div - 1) << MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET;
2260         __raw_writel(reg, MXC_CCM_CSCDR1);
2261
2262         return 0;
2263 }
2264
2265 static struct clk usdhc2_clk = {
2266         __INIT_CLK_DEBUG(usdhc2_clk)
2267         .id = 1,
2268         .parent = &pll2_pfd_400M,
2269         .secondary = &usdhc_dep_clk,
2270         .enable_reg = MXC_CCM_CCGR6,
2271         .enable_shift = MXC_CCM_CCGRx_CG2_OFFSET,
2272         .enable = _clk_enable,
2273         .disable = _clk_disable,
2274         .set_parent = _clk_usdhc2_set_parent,
2275         .round_rate = _clk_usdhc_round_rate,
2276         .set_rate = _clk_usdhc2_set_rate,
2277         .get_rate = _clk_usdhc2_get_rate,
2278         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
2279 };
2280
2281 static int _clk_usdhc3_set_parent(struct clk *clk, struct clk *parent)
2282 {
2283         u32 reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_USDHC3_CLK_SEL;
2284
2285         if (parent == &pll2_pfd_352M)
2286                 reg |= (MXC_CCM_CSCMR1_USDHC3_CLK_SEL);
2287
2288         __raw_writel(reg, MXC_CCM_CSCMR1);
2289
2290         return 0;
2291 }
2292
2293 static unsigned long _clk_usdhc3_get_rate(struct clk *clk)
2294 {
2295         u32 reg, div;
2296
2297         reg = __raw_readl(MXC_CCM_CSCDR1);
2298         div = ((reg & MXC_CCM_CSCDR1_USDHC3_PODF_MASK) >>
2299                         MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET) + 1;
2300
2301         return clk_get_rate(clk->parent) / div;
2302 }
2303
2304 static int _clk_usdhc3_set_rate(struct clk *clk, unsigned long rate)
2305 {
2306         u32 reg, div;
2307         u32 parent_rate = clk_get_rate(clk->parent);
2308
2309         div = parent_rate / rate;
2310         if (div == 0)
2311                 div++;
2312         if (((parent_rate / div) != rate) || (div > 8))
2313                 return -EINVAL;
2314
2315         reg = __raw_readl(MXC_CCM_CSCDR1);
2316         reg &= ~MXC_CCM_CSCDR1_USDHC3_PODF_MASK;
2317         reg |= (div - 1) << MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET;
2318         __raw_writel(reg, MXC_CCM_CSCDR1);
2319
2320         return 0;
2321 }
2322
2323
2324 static struct clk usdhc3_clk = {
2325         __INIT_CLK_DEBUG(usdhc3_clk)
2326         .id = 2,
2327         .parent = &pll2_pfd_400M,
2328         .secondary = &usdhc_dep_clk,
2329         .enable_reg = MXC_CCM_CCGR6,
2330         .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET,
2331         .enable = _clk_enable,
2332         .disable = _clk_disable,
2333         .set_parent = _clk_usdhc3_set_parent,
2334         .round_rate = _clk_usdhc_round_rate,
2335         .set_rate = _clk_usdhc3_set_rate,
2336         .get_rate = _clk_usdhc3_get_rate,
2337         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
2338 };
2339
2340 static int _clk_usdhc4_set_parent(struct clk *clk, struct clk *parent)
2341 {
2342         u32 reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_USDHC4_CLK_SEL;
2343
2344         if (parent == &pll2_pfd_352M)
2345                 reg |= (MXC_CCM_CSCMR1_USDHC4_CLK_SEL);
2346
2347         __raw_writel(reg, MXC_CCM_CSCMR1);
2348
2349         return 0;
2350 }
2351
2352 static unsigned long _clk_usdhc4_get_rate(struct clk *clk)
2353 {
2354         u32 reg, div;
2355
2356         reg = __raw_readl(MXC_CCM_CSCDR1);
2357         div = ((reg & MXC_CCM_CSCDR1_USDHC4_PODF_MASK) >>
2358                         MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET) + 1;
2359
2360         return clk_get_rate(clk->parent) / div;
2361 }
2362
2363 static int _clk_usdhc4_set_rate(struct clk *clk, unsigned long rate)
2364 {
2365         u32 reg, div;
2366         u32 parent_rate = clk_get_rate(clk->parent);
2367
2368         div = parent_rate / rate;
2369         if (div == 0)
2370                 div++;
2371         if (((parent_rate / div) != rate) || (div > 8))
2372                 return -EINVAL;
2373
2374         reg = __raw_readl(MXC_CCM_CSCDR1);
2375         reg &= ~MXC_CCM_CSCDR1_USDHC4_PODF_MASK;
2376         reg |= (div - 1) << MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET;
2377         __raw_writel(reg, MXC_CCM_CSCDR1);
2378
2379         return 0;
2380 }
2381
2382
2383 static struct clk usdhc4_clk = {
2384         __INIT_CLK_DEBUG(usdhc4_clk)
2385         .id = 3,
2386         .parent = &pll2_pfd_400M,
2387         .secondary = &usdhc_dep_clk,
2388         .enable_reg = MXC_CCM_CCGR6,
2389         .enable_shift = MXC_CCM_CCGRx_CG4_OFFSET,
2390         .enable = _clk_enable,
2391         .disable = _clk_disable,
2392         .set_parent = _clk_usdhc4_set_parent,
2393         .round_rate = _clk_usdhc_round_rate,
2394         .set_rate = _clk_usdhc4_set_rate,
2395         .get_rate = _clk_usdhc4_get_rate,
2396         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
2397 };
2398
2399 static unsigned long _clk_ssi_round_rate(struct clk *clk,
2400                                                 unsigned long rate)
2401 {
2402         u32 pre, post;
2403         u32 parent_rate = clk_get_rate(clk->parent);
2404         u32 div = parent_rate / rate;
2405
2406         if (parent_rate % rate)
2407                 div++;
2408
2409         __calc_pre_post_dividers(1 << 6, div, &pre, &post);
2410
2411         return parent_rate / (pre * post);
2412 }
2413
2414 static unsigned long _clk_ssi1_get_rate(struct clk *clk)
2415 {
2416         u32 reg, prediv, podf;
2417
2418         reg = __raw_readl(MXC_CCM_CS1CDR);
2419
2420         prediv = ((reg & MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK)
2421                 >> MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET) + 1;
2422         podf = ((reg & MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK)
2423                 >> MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET) + 1;
2424
2425         return clk_get_rate(clk->parent) / (prediv * podf);
2426 }
2427
2428 static int _clk_ssi1_set_rate(struct clk *clk, unsigned long rate)
2429 {
2430         u32 reg, div, pre, post;
2431         u32 parent_rate = clk_get_rate(clk->parent);
2432
2433         div = parent_rate / rate;
2434         if (div == 0)
2435                 div++;
2436         if (((parent_rate / div) != rate) || div > 512)
2437                 return -EINVAL;
2438
2439         __calc_pre_post_dividers(1 << 6, div, &pre, &post);
2440
2441         reg = __raw_readl(MXC_CCM_CS1CDR);
2442         reg &= ~(MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK |
2443                  MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK);
2444         reg |= (post - 1) << MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET;
2445         reg |= (pre - 1) << MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET;
2446
2447         __raw_writel(reg, MXC_CCM_CS1CDR);
2448
2449         return 0;
2450 }
2451
2452
2453 static int _clk_ssi1_set_parent(struct clk *clk, struct clk *parent)
2454 {
2455         u32 reg, mux;
2456
2457         reg = __raw_readl(MXC_CCM_CSCMR1)
2458                 & ~MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK;
2459
2460         mux = _get_mux6(parent, &pll3_pfd_508M, &pll3_pfd_454M,
2461                         &pll4_audio_main_clk, NULL, NULL, NULL);
2462         reg |= (mux << MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET);
2463
2464         __raw_writel(reg, MXC_CCM_CSCMR1);
2465
2466         return 0;
2467 }
2468
2469 static struct clk ssi1_clk = {
2470         __INIT_CLK_DEBUG(ssi1_clk)
2471         .parent = &pll3_pfd_508M,
2472         .enable_reg = MXC_CCM_CCGR5,
2473         .enable_shift = MXC_CCM_CCGRx_CG9_OFFSET,
2474         .enable = _clk_enable,
2475         .disable = _clk_disable,
2476         .set_parent = _clk_ssi1_set_parent,
2477         .set_rate = _clk_ssi1_set_rate,
2478         .round_rate = _clk_ssi_round_rate,
2479         .get_rate = _clk_ssi1_get_rate,
2480 #ifdef CONFIG_SND_MXC_SOC_IRAM
2481          .secondary = &ocram_clk,
2482 #else
2483          .secondary = &mmdc_ch0_axi_clk[0],
2484 #endif
2485 };
2486
2487 static unsigned long _clk_ssi2_get_rate(struct clk *clk)
2488 {
2489         u32 reg, prediv, podf;
2490
2491         reg = __raw_readl(MXC_CCM_CS2CDR);
2492
2493         prediv = ((reg & MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK)
2494                 >> MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET) + 1;
2495         podf = ((reg & MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK)
2496                 >> MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET) + 1;
2497
2498         return clk_get_rate(clk->parent) / (prediv * podf);
2499 }
2500
2501 static int _clk_ssi2_set_rate(struct clk *clk, unsigned long rate)
2502 {
2503         u32 reg, div, pre, post;
2504         u32 parent_rate = clk_get_rate(clk->parent);
2505
2506         div = parent_rate / rate;
2507         if (div == 0)
2508                 div++;
2509         if (((parent_rate / div) != rate) || div > 512)
2510                 return -EINVAL;
2511
2512         __calc_pre_post_dividers(1 << 6, div, &pre, &post);
2513
2514         reg = __raw_readl(MXC_CCM_CS2CDR);
2515         reg &= ~(MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK |
2516                  MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK);
2517         reg |= (post - 1) << MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET;
2518         reg |= (pre - 1) << MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET;
2519
2520         __raw_writel(reg, MXC_CCM_CS2CDR);
2521
2522         return 0;
2523 }
2524
2525
2526 static int _clk_ssi2_set_parent(struct clk *clk, struct clk *parent)
2527 {
2528         u32 reg, mux;
2529
2530         reg = __raw_readl(MXC_CCM_CSCMR1)
2531                 & ~MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK;
2532
2533         mux = _get_mux6(parent, &pll3_pfd_508M, &pll3_pfd_454M,
2534                         &pll4_audio_main_clk, NULL, NULL, NULL);
2535         reg |= (mux << MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET);
2536
2537         __raw_writel(reg, MXC_CCM_CSCMR1);
2538
2539         return 0;
2540 }
2541
2542 static struct clk ssi2_clk = {
2543         __INIT_CLK_DEBUG(ssi2_clk)
2544         .parent = &pll3_pfd_508M,
2545         .enable_reg = MXC_CCM_CCGR5,
2546         .enable_shift = MXC_CCM_CCGRx_CG10_OFFSET,
2547         .enable = _clk_enable,
2548         .disable = _clk_disable,
2549         .set_parent = _clk_ssi2_set_parent,
2550         .set_rate = _clk_ssi2_set_rate,
2551         .round_rate = _clk_ssi_round_rate,
2552         .get_rate = _clk_ssi2_get_rate,
2553 #ifdef CONFIG_SND_MXC_SOC_IRAM
2554          .secondary = &ocram_clk,
2555 #else
2556          .secondary = &mmdc_ch0_axi_clk[0],
2557 #endif
2558 };
2559
2560 static unsigned long _clk_ssi3_get_rate(struct clk *clk)
2561 {
2562         u32 reg, prediv, podf;
2563
2564         reg = __raw_readl(MXC_CCM_CS1CDR);
2565
2566         prediv = ((reg & MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK)
2567                 >> MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET) + 1;
2568         podf = ((reg & MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK)
2569                 >> MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET) + 1;
2570
2571         return clk_get_rate(clk->parent) / (prediv * podf);
2572 }
2573
2574 static int _clk_ssi3_set_rate(struct clk *clk, unsigned long rate)
2575 {
2576         u32 reg, div, pre, post;
2577         u32 parent_rate = clk_get_rate(clk->parent);
2578
2579         div = parent_rate / rate;
2580         if (div == 0)
2581                 div++;
2582         if (((parent_rate / div) != rate) || div > 512)
2583                 return -EINVAL;
2584
2585         __calc_pre_post_dividers(1 << 6, div, &pre, &post);
2586
2587         reg = __raw_readl(MXC_CCM_CS1CDR);
2588         reg &= ~(MXC_CCM_CS1CDR_SSI3_CLK_PODF_MASK|
2589                  MXC_CCM_CS1CDR_SSI3_CLK_PRED_MASK);
2590         reg |= (post - 1) << MXC_CCM_CS1CDR_SSI3_CLK_PODF_OFFSET;
2591         reg |= (pre - 1) << MXC_CCM_CS1CDR_SSI3_CLK_PRED_OFFSET;
2592
2593         __raw_writel(reg, MXC_CCM_CS1CDR);
2594
2595         return 0;
2596 }
2597
2598
2599 static int _clk_ssi3_set_parent(struct clk *clk, struct clk *parent)
2600 {
2601         u32 reg, mux;
2602
2603         reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_SSI3_CLK_SEL_MASK;
2604
2605         mux = _get_mux6(parent, &pll3_pfd_508M, &pll3_pfd_454M,
2606                                 &pll4_audio_main_clk, NULL, NULL, NULL);
2607         reg |= (mux << MXC_CCM_CSCMR1_SSI3_CLK_SEL_OFFSET);
2608
2609         __raw_writel(reg, MXC_CCM_CSCMR1);
2610
2611         return 0;
2612 }
2613
2614 static struct clk ssi3_clk = {
2615         __INIT_CLK_DEBUG(ssi3_clk)
2616         .parent = &pll3_pfd_508M,
2617         .enable_reg = MXC_CCM_CCGR5,
2618         .enable_shift = MXC_CCM_CCGRx_CG11_OFFSET,
2619         .enable = _clk_enable,
2620         .disable = _clk_disable,
2621         .set_parent = _clk_ssi3_set_parent,
2622         .set_rate = _clk_ssi3_set_rate,
2623         .round_rate = _clk_ssi_round_rate,
2624         .get_rate = _clk_ssi3_get_rate,
2625 #ifdef CONFIG_SND_MXC_SOC_IRAM
2626          .secondary = &ocram_clk,
2627 #else
2628          .secondary = &mmdc_ch0_axi_clk[0],
2629 #endif
2630 };
2631
2632 static unsigned long _clk_ldb_di_round_rate(struct clk *clk,
2633                                                 unsigned long rate)
2634 {
2635         u32 parent_rate = clk_get_rate(clk->parent);
2636
2637         if (rate * 7 <= parent_rate + parent_rate/20)
2638                 return parent_rate / 7;
2639         else
2640                 return 2 * parent_rate / 7;
2641 }
2642
2643 static unsigned long _clk_ldb_di0_get_rate(struct clk *clk)
2644 {
2645         u32 div;
2646
2647         div = __raw_readl(MXC_CCM_CSCMR2) &
2648                 MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
2649
2650         if (div)
2651                 return clk_get_rate(clk->parent) / 7;
2652
2653         return (2 * clk_get_rate(clk->parent)) / 7;
2654 }
2655
2656 static int _clk_ldb_di0_set_rate(struct clk *clk, unsigned long rate)
2657 {
2658         u32 reg, div = 0;
2659         u32 parent_rate = clk_get_rate(clk->parent);
2660
2661         if (rate * 7 <= parent_rate + parent_rate/20) {
2662                 div = 7;
2663                 rate = parent_rate / 7;
2664         } else
2665                 rate = 2 * parent_rate / 7;
2666
2667         reg = __raw_readl(MXC_CCM_CSCMR2);
2668         if (div == 7)
2669                 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
2670         else
2671                 reg &= ~MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
2672
2673         __raw_writel(reg, MXC_CCM_CSCMR2);
2674
2675         return 0;
2676 }
2677
2678 static int _clk_ldb_di0_set_parent(struct clk *clk, struct clk *parent)
2679 {
2680         u32 reg, mux;
2681
2682         reg = __raw_readl(MXC_CCM_CS2CDR)
2683                 & ~MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK;
2684
2685         mux = _get_mux6(parent, &pll5_video_main_clk,
2686                 &pll2_pfd_352M, &pll2_pfd_400M, &pll3_pfd_540M,
2687                 &pll3_usb_otg_main_clk, NULL);
2688         reg |= (mux << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET);
2689
2690         __raw_writel(reg, MXC_CCM_CS2CDR);
2691
2692         return 0;
2693 }
2694
2695 static struct clk ldb_di0_clk = {
2696          __INIT_CLK_DEBUG(ldb_di0_clk)
2697         .id = 0,
2698         .parent = &pll3_pfd_540M,
2699         .enable_reg = MXC_CCM_CCGR3,
2700         .enable_shift = MXC_CCM_CCGRx_CG6_OFFSET,
2701         .enable = _clk_enable,
2702         .disable = _clk_disable,
2703         .set_parent = _clk_ldb_di0_set_parent,
2704         .set_rate = _clk_ldb_di0_set_rate,
2705         .round_rate = _clk_ldb_di_round_rate,
2706         .get_rate = _clk_ldb_di0_get_rate,
2707         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
2708 };
2709
2710 static unsigned long _clk_ldb_di1_get_rate(struct clk *clk)
2711 {
2712         u32 div;
2713
2714         div = __raw_readl(MXC_CCM_CSCMR2) &
2715                 MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
2716
2717         if (div)
2718                 return clk_get_rate(clk->parent) / 7;
2719
2720         return (2 * clk_get_rate(clk->parent)) / 7;
2721 }
2722
2723 static int _clk_ldb_di1_set_rate(struct clk *clk, unsigned long rate)
2724 {
2725         u32 reg, div = 0;
2726         u32 parent_rate = clk_get_rate(clk->parent);
2727
2728         if (rate * 7 <= parent_rate + parent_rate/20) {
2729                 div = 7;
2730                 rate = parent_rate / 7;
2731         } else
2732                 rate = 2 * parent_rate / 7;
2733
2734         reg = __raw_readl(MXC_CCM_CSCMR2);
2735         if (div == 7)
2736                 reg |= MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
2737         else
2738                 reg &= ~MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
2739
2740         __raw_writel(reg, MXC_CCM_CSCMR2);
2741
2742         return 0;
2743 }
2744
2745 static int _clk_ldb_di1_set_parent(struct clk *clk, struct clk *parent)
2746 {
2747         u32 reg, mux;
2748
2749         reg = __raw_readl(MXC_CCM_CS2CDR)
2750                 & ~MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK;
2751
2752         mux = _get_mux6(parent, &pll5_video_main_clk,
2753                 &pll2_pfd_352M, &pll2_pfd_400M, &pll3_pfd_540M,
2754                 &pll3_usb_otg_main_clk, NULL);
2755         reg |= (mux << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
2756
2757         __raw_writel(reg, MXC_CCM_CS2CDR);
2758
2759         return 0;
2760 }
2761
2762 static struct clk ldb_di1_clk = {
2763          __INIT_CLK_DEBUG(ldb_di1_clk)
2764         .id = 0,
2765         .parent = &pll3_pfd_540M,
2766         .enable_reg = MXC_CCM_CCGR3,
2767         .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
2768         .enable = _clk_enable,
2769         .disable = _clk_disable,
2770         .set_parent = _clk_ldb_di1_set_parent,
2771         .set_rate = _clk_ldb_di1_set_rate,
2772         .round_rate = _clk_ldb_di_round_rate,
2773         .get_rate = _clk_ldb_di1_get_rate,
2774         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
2775 };
2776
2777
2778 static unsigned long _clk_ipu_di_round_rate(struct clk *clk,
2779                                                 unsigned long rate)
2780 {
2781         u32 div;
2782         u32 parent_rate = clk_get_rate(clk->parent);
2783
2784         if ((clk->parent == &ldb_di0_clk) ||
2785                 (clk->parent == &ldb_di1_clk))
2786                 return parent_rate;
2787
2788         div = parent_rate / rate;
2789         /* Round to closest divisor */
2790         if ((parent_rate % rate) > (rate / 2))
2791                 div++;
2792
2793         /* Make sure rate is not greater than the maximum value for the clock.
2794          * Also prevent a div of 0.
2795          */
2796         if (div == 0)
2797                 div++;
2798
2799         if (div > 8)
2800                 div = 8;
2801
2802         return parent_rate / div;
2803 }
2804
2805 static unsigned long _clk_ipu1_di0_get_rate(struct clk *clk)
2806 {
2807         u32 reg, div;
2808
2809         if ((clk->parent == &ldb_di0_clk) ||
2810                 (clk->parent == &ldb_di1_clk))
2811                 return clk_get_rate(clk->parent);
2812
2813         reg = __raw_readl(MXC_CCM_CHSCCDR);
2814
2815         div = ((reg & MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK) >>
2816                          MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET) + 1;
2817
2818         return clk_get_rate(clk->parent) / div;
2819 }
2820
2821 static int _clk_ipu1_di0_set_rate(struct clk *clk, unsigned long rate)
2822 {
2823         u32 reg, div;
2824         u32 parent_rate = clk_get_rate(clk->parent);
2825
2826         if ((clk->parent == &ldb_di0_clk) ||
2827                 (clk->parent == &ldb_di1_clk)) {
2828                 if (parent_rate == rate)
2829                         return 0;
2830                 else
2831                         return -EINVAL;
2832         }
2833
2834         div = parent_rate / rate;
2835         if (div == 0)
2836                 div++;
2837         if (((parent_rate / div) != rate) || (div > 8))
2838                 return -EINVAL;
2839
2840         reg = __raw_readl(MXC_CCM_CHSCCDR);
2841         reg &= ~MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK;
2842         reg |= (div - 1) << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET;
2843         __raw_writel(reg, MXC_CCM_CHSCCDR);
2844
2845         return 0;
2846 }
2847
2848
2849 static int _clk_ipu1_di0_set_parent(struct clk *clk, struct clk *parent)
2850 {
2851         u32 reg, mux;
2852
2853         if (parent == &ldb_di0_clk)
2854                 mux = 0x3;
2855         else if (parent == &ldb_di1_clk)
2856                 mux = 0x4;
2857         else {
2858                 reg = __raw_readl(MXC_CCM_CHSCCDR)
2859                         & ~MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK;
2860
2861                 mux = _get_mux6(parent, &mmdc_ch0_axi_clk[0],
2862                                 &pll3_usb_otg_main_clk, &pll5_video_main_clk,
2863                                 &pll2_pfd_352M, &pll2_pfd_400M, &pll3_pfd_540M);
2864                 reg |= (mux << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
2865
2866                 __raw_writel(reg, MXC_CCM_CHSCCDR);
2867
2868                 /* Derive clock from divided pre-muxed ipu1_di0 clock.*/
2869                 mux = 0;
2870         }
2871
2872         reg = __raw_readl(MXC_CCM_CHSCCDR)
2873                 & ~MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK;
2874         __raw_writel(reg | (mux << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET),
2875                 MXC_CCM_CHSCCDR);
2876
2877         return 0;
2878 }
2879
2880 static unsigned long _clk_ipu1_di1_get_rate(struct clk *clk)
2881 {
2882         u32 reg, div;
2883
2884         if ((clk->parent == &ldb_di0_clk) ||
2885                 (clk->parent == &ldb_di1_clk))
2886                 return clk_get_rate(clk->parent);
2887
2888         reg = __raw_readl(MXC_CCM_CHSCCDR);
2889
2890         div = ((reg & MXC_CCM_CHSCCDR_IPU1_DI1_PODF_MASK)
2891                         >> MXC_CCM_CHSCCDR_IPU1_DI1_PODF_OFFSET) + 1;
2892
2893         return clk_get_rate(clk->parent) / div;
2894 }
2895
2896 static int _clk_ipu1_di1_set_rate(struct clk *clk, unsigned long rate)
2897 {
2898         u32 reg, div;
2899         u32 parent_rate = clk_get_rate(clk->parent);
2900
2901         if ((clk->parent == &ldb_di0_clk) ||
2902                 (clk->parent == &ldb_di1_clk)) {
2903                 if (parent_rate == rate)
2904                         return 0;
2905                 else
2906                         return -EINVAL;
2907         }
2908
2909         div = parent_rate / rate;
2910         if (div == 0)
2911                 div++;
2912         if (((parent_rate / div) != rate) || (div > 8))
2913                 return -EINVAL;
2914
2915         reg = __raw_readl(MXC_CCM_CHSCCDR);
2916         reg &= ~MXC_CCM_CHSCCDR_IPU1_DI1_PODF_MASK;
2917         reg |= (div - 1) << MXC_CCM_CHSCCDR_IPU1_DI1_PODF_OFFSET;
2918         __raw_writel(reg, MXC_CCM_CHSCCDR);
2919
2920         return 0;
2921 }
2922
2923
2924 static int _clk_ipu1_di1_set_parent(struct clk *clk, struct clk *parent)
2925 {
2926         u32 reg, mux;
2927
2928         if (parent == &ldb_di0_clk)
2929                 mux = 0x3;
2930         else if (parent == &ldb_di1_clk)
2931                 mux = 0x4;
2932         else {
2933                 reg = __raw_readl(MXC_CCM_CHSCCDR)
2934                         & ~MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_MASK;
2935
2936                 mux = _get_mux6(parent, &mmdc_ch0_axi_clk[0],
2937                                 &pll3_usb_otg_main_clk, &pll5_video_main_clk,
2938                                 &pll2_pfd_352M, &pll2_pfd_400M, &pll3_pfd_540M);
2939                 reg |= (mux << MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_OFFSET);
2940
2941                 __raw_writel(reg, MXC_CCM_CHSCCDR);
2942
2943                 /* Derive clock from divided pre-muxed ipu1_di0 clock.*/
2944                 mux = 0;
2945         }
2946         reg = __raw_readl(MXC_CCM_CHSCCDR)
2947                 & ~MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_MASK;
2948         __raw_writel(reg | (mux << MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET),
2949                 MXC_CCM_CHSCCDR);
2950
2951         return 0;
2952 }
2953
2954 static struct clk ipu1_di_clk[] = {
2955         {
2956          __INIT_CLK_DEBUG(ipu1_di_clk_0)
2957         .id = 0,
2958         .parent = &pll5_video_main_clk,
2959         .enable_reg = MXC_CCM_CCGR3,
2960         .enable_shift = MXC_CCM_CCGRx_CG1_OFFSET,
2961         .enable = _clk_enable,
2962         .disable = _clk_disable,
2963         .set_parent = _clk_ipu1_di0_set_parent,
2964         .set_rate = _clk_ipu1_di0_set_rate,
2965         .round_rate = _clk_ipu_di_round_rate,
2966         .get_rate = _clk_ipu1_di0_get_rate,
2967         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
2968         },
2969         {
2970          __INIT_CLK_DEBUG(ipu1_di_clk_1)
2971         .id = 1,
2972         .parent = &pll5_video_main_clk,
2973         .enable_reg = MXC_CCM_CCGR3,
2974         .enable_shift = MXC_CCM_CCGRx_CG2_OFFSET,
2975         .enable = _clk_enable,
2976         .disable = _clk_disable,
2977         .set_parent = _clk_ipu1_di1_set_parent,
2978         .set_rate = _clk_ipu1_di1_set_rate,
2979         .round_rate = _clk_ipu_di_round_rate,
2980         .get_rate = _clk_ipu1_di1_get_rate,
2981         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
2982         },
2983 };
2984
2985 static unsigned long _clk_ipu2_di0_get_rate(struct clk *clk)
2986 {
2987         u32 reg, div;
2988
2989         if ((clk->parent == &ldb_di0_clk) ||
2990                 (clk->parent == &ldb_di1_clk))
2991                 return clk_get_rate(clk->parent);
2992
2993         reg = __raw_readl(MXC_CCM_CSCDR2);
2994
2995         div = ((reg & MXC_CCM_CSCDR2_IPU2_DI0_PODF_MASK) >>
2996                         MXC_CCM_CSCDR2_IPU2_DI0_PODF_OFFSET) + 1;
2997
2998         return clk_get_rate(clk->parent) / div;
2999 }
3000
3001 static int _clk_ipu2_di0_set_rate(struct clk *clk, unsigned long rate)
3002 {
3003         u32 reg, div;
3004         u32 parent_rate = clk_get_rate(clk->parent);
3005
3006         if ((clk->parent == &ldb_di0_clk) ||
3007                 (clk->parent == &ldb_di1_clk)) {
3008                 if (parent_rate == rate)
3009                         return 0;
3010                 else
3011                         return -EINVAL;
3012         }
3013
3014         div = parent_rate / rate;
3015         if (div == 0)
3016                 div++;
3017         if (((parent_rate / div) != rate) || (div > 8))
3018                 return -EINVAL;
3019
3020         reg = __raw_readl(MXC_CCM_CSCDR2);
3021         reg &= ~MXC_CCM_CSCDR2_IPU2_DI0_PODF_MASK;
3022         reg |= (div - 1) << MXC_CCM_CSCDR2_IPU2_DI0_PODF_OFFSET;
3023         __raw_writel(reg, MXC_CCM_CSCDR2);
3024
3025         return 0;
3026 }
3027
3028 static int _clk_ipu2_di0_set_parent(struct clk *clk, struct clk *parent)
3029 {
3030         u32 reg, mux;
3031
3032         if (parent == &ldb_di0_clk)
3033                 mux = 0x3;
3034         else if (parent == &ldb_di1_clk)
3035                 mux = 0x4;
3036         else {
3037                 reg = __raw_readl(MXC_CCM_CSCDR2)
3038                         & ~MXC_CCM_CSCDR2_IPU2_DI0_PRE_CLK_SEL_MASK;
3039
3040                 mux = _get_mux6(parent, &mmdc_ch0_axi_clk[0],
3041                                 &pll3_usb_otg_main_clk, &pll5_video_main_clk,
3042                                 &pll2_pfd_352M, &pll2_pfd_400M, &pll3_pfd_540M);
3043                 reg |= (mux << MXC_CCM_CSCDR2_IPU2_DI0_PRE_CLK_SEL_OFFSET);
3044
3045                 __raw_writel(reg, MXC_CCM_CSCDR2);
3046
3047                 /* Derive clock from divided pre-muxed ipu2_di0 clock.*/
3048                 mux = 0;
3049         }
3050         reg = __raw_readl(MXC_CCM_CSCDR2)
3051                 & ~MXC_CCM_CSCDR2_IPU2_DI0_CLK_SEL_MASK;
3052         __raw_writel(reg | (mux << MXC_CCM_CSCDR2_IPU2_DI0_CLK_SEL_OFFSET),
3053                 MXC_CCM_CSCDR2);
3054
3055         return 0;
3056 }
3057
3058 static unsigned long _clk_ipu2_di1_get_rate(struct clk *clk)
3059 {
3060         u32 reg, div;
3061
3062         if ((clk->parent == &ldb_di0_clk) ||
3063                 (clk->parent == &ldb_di1_clk))
3064                 return clk_get_rate(clk->parent);
3065
3066         reg = __raw_readl(MXC_CCM_CSCDR2);
3067
3068         div = ((reg & MXC_CCM_CSCDR2_IPU2_DI1_PODF_MASK)
3069                 >> MXC_CCM_CSCDR2_IPU2_DI1_PODF_OFFSET) + 1;
3070
3071         return clk_get_rate(clk->parent) / div;
3072 }
3073
3074 static int _clk_ipu2_di1_set_rate(struct clk *clk, unsigned long rate)
3075 {
3076         u32 reg, div;
3077         u32 parent_rate = clk_get_rate(clk->parent);
3078
3079         if ((clk->parent == &ldb_di0_clk) ||
3080                 (clk->parent == &ldb_di1_clk)) {
3081                 if (parent_rate == rate)
3082                         return 0;
3083                 else
3084                         return -EINVAL;
3085         }
3086
3087         div = parent_rate / rate;
3088         if (div == 0)
3089                 div++;
3090         if (((parent_rate / div) != rate) || (div > 8))
3091                 return -EINVAL;
3092
3093         reg = __raw_readl(MXC_CCM_CSCDR2);
3094         reg &= ~MXC_CCM_CSCDR2_IPU2_DI1_PODF_MASK;
3095         reg |= (div - 1) << MXC_CCM_CSCDR2_IPU2_DI1_PODF_OFFSET;
3096         __raw_writel(reg, MXC_CCM_CSCDR2);
3097
3098         return 0;
3099 }
3100
3101 static int _clk_ipu2_di1_set_parent(struct clk *clk, struct clk *parent)
3102 {
3103         u32 reg, mux;
3104
3105         if (parent == &ldb_di0_clk)
3106                 mux = 0x3;
3107         else if (parent == &ldb_di1_clk)
3108                 mux = 0x4;
3109         else {
3110                 reg = __raw_readl(MXC_CCM_CSCDR2)
3111                         & ~MXC_CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_MASK;
3112
3113                 mux = _get_mux6(parent, &mmdc_ch0_axi_clk[0],
3114                                 &pll3_usb_otg_main_clk, &pll5_video_main_clk,
3115                                 &pll2_pfd_352M, &pll2_pfd_400M, &pll3_pfd_540M);
3116                 reg |= (mux << MXC_CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_OFFSET);
3117
3118                 __raw_writel(reg, MXC_CCM_CSCDR2);
3119
3120                 /* Derive clock from divided pre-muxed ipu1_di0 clock.*/
3121                 mux = 0;
3122         }
3123         reg = __raw_readl(MXC_CCM_CSCDR2)
3124                 & ~MXC_CCM_CSCDR2_IPU2_DI1_CLK_SEL_MASK;
3125         __raw_writel(reg | (mux << MXC_CCM_CSCDR2_IPU2_DI1_CLK_SEL_OFFSET),
3126                 MXC_CCM_CSCDR2);
3127
3128         return 0;
3129 }
3130
3131 static struct clk ipu2_di_clk[] = {
3132         {
3133          __INIT_CLK_DEBUG(ipu2_di_clk_0)
3134         .id = 0,
3135         .parent = &pll5_video_main_clk,
3136         .enable_reg = MXC_CCM_CCGR3,
3137         .enable_shift = MXC_CCM_CCGRx_CG4_OFFSET,
3138         .enable = _clk_enable,
3139         .disable = _clk_disable,
3140         .set_parent = _clk_ipu2_di0_set_parent,
3141         .set_rate = _clk_ipu2_di0_set_rate,
3142         .round_rate = _clk_ipu_di_round_rate,
3143         .get_rate = _clk_ipu2_di0_get_rate,
3144         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
3145         },
3146         {
3147          __INIT_CLK_DEBUG(ipu2_di_clk_1)
3148         .id = 1,
3149         .parent = &pll5_video_main_clk,
3150         .enable_reg = MXC_CCM_CCGR3,
3151         .enable_shift = MXC_CCM_CCGRx_CG5_OFFSET,
3152         .enable = _clk_enable,
3153         .disable = _clk_disable,
3154         .set_parent = _clk_ipu2_di1_set_parent,
3155         .set_rate = _clk_ipu2_di1_set_rate,
3156         .round_rate = _clk_ipu_di_round_rate,
3157         .get_rate = _clk_ipu2_di1_get_rate,
3158         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
3159         },
3160 };
3161
3162 static unsigned long _clk_can_root_round_rate(struct clk *clk,
3163                                                 unsigned long rate)
3164 {
3165         u32 div;
3166         u32 parent_rate = clk_get_rate(clk->parent);
3167
3168         div = parent_rate / rate;
3169
3170         /* Make sure rate is not greater than the maximum value for the clock.
3171          * Also prevent a div of 0.
3172          */
3173         if (div == 0)
3174                 div++;
3175
3176         if (div > 64)
3177                 div = 64;
3178
3179         return parent_rate / div;
3180 }
3181
3182 static int _clk_can_root_set_rate(struct clk *clk, unsigned long rate)
3183 {
3184         u32 reg, div;
3185         u32 parent_rate = clk_get_rate(clk->parent);
3186
3187         div = parent_rate / rate;
3188         if (div == 0)
3189                 div++;
3190         if (((parent_rate / div) != rate) || (div > 64))
3191                 return -EINVAL;
3192
3193         reg = __raw_readl(MXC_CCM_CSCMR2) & MXC_CCM_CSCMR2_CAN_CLK_PODF_MASK;
3194         reg |= ((div - 1) << MXC_CCM_CSCMR2_CAN_CLK_PODF_OFFSET);
3195
3196         __raw_writel(reg, MXC_CCM_CSCMR2);
3197
3198         return 0;
3199 }
3200
3201 static unsigned long _clk_can_root_get_rate(struct clk *clk)
3202 {
3203         u32 reg, div;
3204         unsigned long val;
3205
3206         reg = __raw_readl(MXC_CCM_CSCMR2) & MXC_CCM_CSCMR2_CAN_CLK_PODF_MASK;
3207         div = (reg >> MXC_CCM_CSCMR2_CAN_CLK_PODF_OFFSET) + 1;
3208         val = clk_get_rate(clk->parent) / div;
3209
3210         return val;
3211 }
3212
3213 static struct clk can_clk_root = {
3214          __INIT_CLK_DEBUG(can_clk_root)
3215         .parent = &pll3_60M,
3216         .set_rate = _clk_can_root_set_rate,
3217         .get_rate = _clk_can_root_get_rate,
3218         .round_rate = _clk_can_root_round_rate,
3219 };
3220
3221 static struct clk can2_clk[] = {
3222         {
3223          __INIT_CLK_DEBUG(can2_module_clk)
3224         .id = 0,
3225         .parent = &can_clk_root,
3226         .enable_reg = MXC_CCM_CCGR0,
3227         .enable_shift = MXC_CCM_CCGRx_CG9_OFFSET,
3228         .enable = _clk_enable,
3229         .disable = _clk_disable,
3230         .secondary = &can2_clk[1],
3231         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
3232         },
3233         {
3234          __INIT_CLK_DEBUG(can2_serial_clk)
3235         .id = 1,
3236         .parent = &can_clk_root,
3237         .enable_reg = MXC_CCM_CCGR0,
3238         .enable_shift = MXC_CCM_CCGRx_CG10_OFFSET,
3239         .enable = _clk_enable,
3240         .disable = _clk_disable,
3241         },
3242 };
3243
3244
3245 static struct clk can1_clk[] = {
3246         {
3247          __INIT_CLK_DEBUG(can1_module_clk)
3248         .id = 0,
3249         .parent = &can_clk_root,
3250         .enable_reg = MXC_CCM_CCGR0,
3251         .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
3252         .enable = _clk_enable,
3253         .disable = _clk_disable,
3254         .secondary = &can1_clk[1],
3255         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
3256         },
3257         {
3258          __INIT_CLK_DEBUG(can1_serial_clk)
3259         .id = 1,
3260         .parent = &can_clk_root,
3261         .enable_reg = MXC_CCM_CCGR0,
3262         .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET,
3263         .enable = _clk_enable,
3264         .disable = _clk_disable,
3265         },
3266 };
3267
3268 static unsigned long _clk_spdif_round_rate(struct clk *clk,
3269                                                 unsigned long rate)
3270 {
3271         u32 pre, post;
3272         u32 parent_rate = clk_get_rate(clk->parent);
3273         u32 div = parent_rate / rate;
3274
3275         if (parent_rate % rate)
3276                 div++;
3277
3278         __calc_pre_post_dividers(1 << 3, div, &pre, &post);
3279
3280         return parent_rate / (pre * post);
3281 }
3282
3283 static int _clk_spdif0_set_parent(struct clk *clk, struct clk *parent)
3284 {
3285         u32 reg, mux;
3286
3287         reg = __raw_readl(MXC_CCM_CDCDR)
3288                 & ~MXC_CCM_CDCDR_SPDIF0_CLK_SEL_MASK;
3289
3290         mux = _get_mux6(parent, &pll4_audio_main_clk,
3291                 &pll3_pfd_508M, &pll3_pfd_454M,
3292                 &pll3_sw_clk, NULL, NULL);
3293         reg |= mux << MXC_CCM_CDCDR_SPDIF0_CLK_SEL_OFFSET;
3294
3295         __raw_writel(reg, MXC_CCM_CDCDR);
3296
3297         return 0;
3298 }
3299
3300 static unsigned long _clk_spdif0_get_rate(struct clk *clk)
3301 {
3302         u32 reg, pred, podf;
3303
3304         reg = __raw_readl(MXC_CCM_CDCDR);
3305
3306         pred = ((reg & MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK)
3307                 >> MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET) + 1;
3308         podf = ((reg & MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK)
3309                 >> MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET) + 1;
3310
3311         return clk_get_rate(clk->parent) / (pred * podf);
3312 }
3313
3314 static int _clk_spdif0_set_rate(struct clk *clk, unsigned long rate)
3315 {
3316         u32 reg, div, pre, post;
3317         u32 parent_rate = clk_get_rate(clk->parent);
3318
3319         div = parent_rate / rate;
3320         if (div == 0)
3321                 div++;
3322         if (((parent_rate / div) != rate) || div > 64)
3323                 return -EINVAL;
3324
3325         __calc_pre_post_dividers(1 << 3, div, &pre, &post);
3326
3327         reg = __raw_readl(MXC_CCM_CDCDR);
3328         reg &= ~(MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK|
3329                  MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK);
3330         reg |= (post - 1) << MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET;
3331         reg |= (pre - 1) << MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET;
3332
3333         __raw_writel(reg, MXC_CCM_CDCDR);
3334
3335         return 0;
3336 }
3337
3338 static struct clk spdif0_clk[] = {
3339         {
3340         __INIT_CLK_DEBUG(spdif0_clk_0)
3341         .id = 0,
3342         .parent = &pll3_sw_clk,
3343          .enable = _clk_enable,
3344          .enable_reg = MXC_CCM_CCGR5,
3345          .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
3346          .disable = _clk_disable,
3347          .secondary = &spdif0_clk[1],
3348          .set_rate = _clk_spdif0_set_rate,
3349          .get_rate = _clk_spdif0_get_rate,
3350          .set_parent = _clk_spdif0_set_parent,
3351          .round_rate = _clk_spdif_round_rate,
3352         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
3353         },
3354         {
3355         __INIT_CLK_DEBUG(spdif0_clk_1)
3356          .id = 1,
3357          .parent = &ipg_clk,
3358          .secondary = &spba_clk,
3359          },
3360 };
3361
3362 static unsigned long _clk_esai_round_rate(struct clk *clk,
3363                                                 unsigned long rate)
3364 {
3365         u32 pre, post;
3366         u32 parent_rate = clk_get_rate(clk->parent);
3367         u32 div = parent_rate / rate;
3368
3369         if (parent_rate % rate)
3370                 div++;
3371
3372         __calc_pre_post_dividers(1 << 3, div, &pre, &post);
3373
3374         return parent_rate / (pre * post);
3375 }
3376
3377 static int _clk_esai_set_parent(struct clk *clk, struct clk *parent)
3378 {
3379         u32 reg, mux;
3380
3381         reg = __raw_readl(MXC_CCM_CSCMR2) & ~MXC_CCM_CSCMR2_ESAI_CLK_SEL_MASK;
3382
3383         mux = _get_mux6(parent, &pll4_audio_main_clk, &pll3_pfd_508M,
3384                         &pll3_pfd_454M, &pll3_sw_clk, NULL, NULL);
3385         reg |= mux << MXC_CCM_CSCMR2_ESAI_CLK_SEL_OFFSET;
3386
3387         __raw_writel(reg, MXC_CCM_CSCMR2);
3388
3389         return 0;
3390 }
3391
3392 static unsigned long _clk_esai_get_rate(struct clk *clk)
3393 {
3394         u32 reg, pred, podf;
3395
3396         reg = __raw_readl(MXC_CCM_CS1CDR);
3397
3398         pred = ((reg & MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK)
3399                 >> MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET) + 1;
3400         podf = ((reg & MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK)
3401                 >> MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET) + 1;
3402
3403         return clk_get_rate(clk->parent) / (pred * podf);
3404 }
3405
3406 static int _clk_esai_set_rate(struct clk *clk, unsigned long rate)
3407 {
3408         u32 reg, div, pre, post;
3409         u32 parent_rate = clk_get_rate(clk->parent);
3410
3411         div = parent_rate / rate;
3412         if (div == 0)
3413                 div++;
3414         if (((parent_rate / div) != rate) || div > 64)
3415                 return -EINVAL;
3416
3417         __calc_pre_post_dividers(1 << 3, div, &pre, &post);
3418
3419         reg = __raw_readl(MXC_CCM_CS1CDR);
3420         reg &= ~(MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK|
3421                  MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK);
3422         reg |= (post - 1) << MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET;
3423         reg |= (pre - 1) << MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET;
3424
3425         __raw_writel(reg, MXC_CCM_CS1CDR);
3426
3427         return 0;
3428 }
3429
3430 static struct clk esai_clk = {
3431         __INIT_CLK_DEBUG(esai_clk)
3432          .id = 0,
3433          .parent = &pll3_sw_clk,
3434          .secondary = &spba_clk,
3435          .enable_reg = MXC_CCM_CCGR1,
3436          .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET,
3437          .enable = _clk_enable,
3438          .disable = _clk_disable,
3439          .set_rate = _clk_esai_set_rate,
3440          .get_rate = _clk_esai_get_rate,
3441          .set_parent = _clk_esai_set_parent,
3442          .round_rate = _clk_esai_round_rate,
3443 };
3444
3445 static int _clk_enet_enable(struct clk *clk)
3446 {
3447         unsigned int reg;
3448
3449         /* Enable ENET ref clock */
3450         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
3451         reg &= ~ANADIG_PLL_BYPASS;
3452         reg |= ANADIG_PLL_ENABLE;
3453         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
3454
3455         _clk_enable(clk);
3456         return 0;
3457 }
3458
3459 static void _clk_enet_disable(struct clk *clk)
3460 {
3461         unsigned int reg;
3462
3463         _clk_disable(clk);
3464
3465         /* Enable ENET ref clock */
3466         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
3467         reg |= ANADIG_PLL_BYPASS;
3468         reg &= ~ANADIG_PLL_ENABLE;
3469         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
3470 }
3471
3472 static int _clk_enet_set_rate(struct clk *clk, unsigned long rate)
3473 {
3474         unsigned int reg, div = 1;
3475
3476         switch (rate) {
3477         case 25000000:
3478                 div = 0;
3479                 break;
3480         case 50000000:
3481                 div = 1;
3482                 break;
3483         case 100000000:
3484                 div = 2;
3485                 break;
3486         case 125000000:
3487                 div = 3;
3488                 break;
3489         default:
3490                 return -EINVAL;
3491         }
3492         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
3493         reg &= ~ANADIG_PLL_ENET_DIV_SELECT_MASK;
3494         reg |= (div << ANADIG_PLL_ENET_DIV_SELECT_OFFSET);
3495         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
3496
3497         return 0;
3498 }
3499
3500 static unsigned long _clk_enet_get_rate(struct clk *clk)
3501 {
3502         unsigned int div;
3503
3504         div = (__raw_readl(PLL8_ENET_BASE_ADDR))
3505                 & ANADIG_PLL_ENET_DIV_SELECT_MASK;
3506
3507         switch (div) {
3508         case 0:
3509                 div = 20;
3510                 break;
3511         case 1:
3512                 div = 10;
3513                 break;
3514         case 3:
3515                 div = 5;
3516                 break;
3517         case 4:
3518                 div = 4;
3519                 break;
3520         }
3521
3522         return 500000000 / div;
3523 }
3524
3525 static struct clk enet_clk[] = {
3526         {
3527         __INIT_CLK_DEBUG(enet_clk)
3528          .id = 0,
3529          .parent = &pll8_enet_main_clk,
3530          .enable_reg = MXC_CCM_CCGR1,
3531          .enable_shift = MXC_CCM_CCGRx_CG5_OFFSET,
3532          .enable = _clk_enet_enable,
3533          .disable = _clk_enet_disable,
3534          .set_rate = _clk_enet_set_rate,
3535          .get_rate = _clk_enet_get_rate,
3536         .secondary = &enet_clk[1],
3537         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
3538         },
3539         {
3540         .parent = &mmdc_ch0_axi_clk[0],
3541         .secondary = &mx6per1_clk,
3542         },
3543 };
3544
3545 static struct clk ecspi_clk[] = {
3546         {
3547         __INIT_CLK_DEBUG(ecspi0_clk)
3548         .id = 0,
3549         .parent = &pll3_60M,
3550         .secondary = &spba_clk,
3551         .enable_reg = MXC_CCM_CCGR1,
3552         .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET,
3553         .enable = _clk_enable,
3554         .disable = _clk_disable,
3555         },
3556         {
3557         __INIT_CLK_DEBUG(ecspi1_clk)
3558         .id = 1,
3559         .parent = &pll3_60M,
3560         .secondary = &spba_clk,
3561         .enable_reg = MXC_CCM_CCGR1,
3562         .enable_shift = MXC_CCM_CCGRx_CG1_OFFSET,
3563         .enable = _clk_enable,
3564         .disable = _clk_disable,
3565         },
3566         {
3567         __INIT_CLK_DEBUG(ecspi2_clk)
3568         .id = 2,
3569         .parent = &pll3_60M,
3570         .secondary = &spba_clk,
3571         .enable_reg = MXC_CCM_CCGR1,
3572         .enable_shift = MXC_CCM_CCGRx_CG2_OFFSET,
3573         .enable = _clk_enable,
3574         .disable = _clk_disable,
3575         },
3576         {
3577         __INIT_CLK_DEBUG(ecspi3_clk)
3578         .id = 3,
3579         .parent = &pll3_60M,
3580         .secondary = &spba_clk,
3581         .enable_reg = MXC_CCM_CCGR1,
3582         .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET,
3583         .enable = _clk_enable,
3584         .disable = _clk_disable,
3585         },
3586         {
3587         __INIT_CLK_DEBUG(ecspi4_clk)
3588         .id = 4,
3589         .parent = &pll3_60M,
3590         .secondary = &spba_clk,
3591         .enable_reg = MXC_CCM_CCGR1,
3592         .enable_shift = MXC_CCM_CCGRx_CG4_OFFSET,
3593         .enable = _clk_enable,
3594         .disable = _clk_disable,
3595         },
3596 };
3597
3598 static unsigned long _clk_emi_slow_round_rate(struct clk *clk,
3599                                                 unsigned long rate)
3600 {
3601         u32 div;
3602         u32 parent_rate = clk_get_rate(clk->parent);
3603
3604         div = parent_rate / rate;
3605
3606         /* Make sure rate is not greater than the maximum value for the clock.
3607          * Also prevent a div of 0.
3608          */
3609         if (div == 0)
3610                 div++;
3611
3612         if (div > 8)
3613                 div = 8;
3614
3615         return parent_rate / div;
3616 }
3617
3618 static int _clk_emi_slow_set_parent(struct clk *clk, struct clk *parent)
3619 {
3620         int mux;
3621         u32 reg = __raw_readl(MXC_CCM_CSCMR1)
3622                 & ~MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK;
3623
3624         mux = _get_mux6(parent, &axi_clk, &pll3_usb_otg_main_clk,
3625                                 &pll2_pfd_400M, &pll2_pfd_352M, NULL, NULL);
3626         reg |= (mux << MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET);
3627         __raw_writel(reg, MXC_CCM_CSCMR1);
3628
3629         return 0;
3630 }
3631
3632 static unsigned long _clk_emi_slow_get_rate(struct clk *clk)
3633 {
3634         u32 reg, div;
3635
3636         reg = __raw_readl(MXC_CCM_CSCMR1);
3637         div = ((reg & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK) >>
3638                         MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET) + 1;
3639
3640         return clk_get_rate(clk->parent) / div;
3641 }
3642
3643 static int _clk_emi_slow_set_rate(struct clk *clk, unsigned long rate)
3644 {
3645         u32 reg, div;
3646         u32 parent_rate = clk_get_rate(clk->parent);
3647
3648         div = parent_rate / rate;
3649         if (div == 0)
3650                 div++;
3651         if (((parent_rate / div) != rate) || (div > 8))
3652                 return -EINVAL;
3653
3654         reg = __raw_readl(MXC_CCM_CSCMR1);
3655         reg &= ~MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK;
3656         reg |= (div - 1) << MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET;
3657         __raw_writel(reg, MXC_CCM_CSCMR1);
3658
3659         return 0;
3660 }
3661
3662 static struct clk emi_slow_clk = {
3663         __INIT_CLK_DEBUG(emi_slow_clk)
3664          .id = 0,
3665          .parent = &axi_clk,
3666          .enable_reg = MXC_CCM_CCGR6,
3667          .enable_shift = MXC_CCM_CCGRx_CG5_OFFSET,
3668          .enable = _clk_enable,
3669          .disable = _clk_disable,
3670          .set_rate = _clk_emi_slow_set_rate,
3671          .get_rate = _clk_emi_slow_get_rate,
3672          .round_rate = _clk_emi_slow_round_rate,
3673          .set_parent = _clk_emi_slow_set_parent,
3674 };
3675
3676 static unsigned long _clk_emi_round_rate(struct clk *clk,
3677                                                 unsigned long rate)
3678 {
3679         u32 div;
3680         u32 parent_rate = clk_get_rate(clk->parent);
3681
3682         div = parent_rate / rate;
3683
3684         /* Make sure rate is not greater than the maximum value for the clock.
3685          * Also prevent a div of 0.
3686          */
3687         if (div == 0)
3688                 div++;
3689
3690         if (div > 8)
3691                 div = 8;
3692
3693         return parent_rate / div;
3694 }
3695
3696 static int _clk_emi_set_parent(struct clk *clk, struct clk *parent)
3697 {
3698         int mux;
3699         u32 reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_ACLK_EMI_MASK;
3700
3701         mux = _get_mux6(parent, &axi_clk, &pll3_usb_otg_main_clk,
3702                         &pll2_pfd_400M, &pll2_pfd_352M, NULL, NULL);
3703         reg |= (mux << MXC_CCM_CSCMR1_ACLK_EMI_OFFSET);
3704         __raw_writel(reg, MXC_CCM_CSCMR1);
3705
3706         return 0;
3707 }
3708
3709 static unsigned long _clk_emi_get_rate(struct clk *clk)
3710 {
3711         u32 reg, div;
3712
3713         reg = __raw_readl(MXC_CCM_CSCMR1);
3714         div = ((reg & MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK) >>
3715                         MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET) + 1;
3716
3717         return clk_get_rate(clk->parent) / div;
3718 }
3719
3720 static int _clk_emi_set_rate(struct clk *clk, unsigned long rate)
3721 {
3722         u32 reg, div;
3723         u32 parent_rate = clk_get_rate(clk->parent);
3724
3725         div = parent_rate / rate;
3726         if (div == 0)
3727                 div++;
3728         if (((parent_rate / div) != rate) || (div > 8))
3729                 return -EINVAL;
3730
3731         reg = __raw_readl(MXC_CCM_CSCMR1);
3732         reg &= ~MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK;
3733         reg |= (div - 1) << MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET;
3734         __raw_writel(reg, MXC_CCM_CSCMR1);
3735
3736         return 0;
3737 }
3738
3739 static struct clk emi_clk = {
3740         __INIT_CLK_DEBUG(emi_clk)
3741          .id = 0,
3742          .parent = &axi_clk,
3743          .set_rate = _clk_emi_set_rate,
3744          .get_rate = _clk_emi_get_rate,
3745          .round_rate = _clk_emi_round_rate,
3746          .set_parent = _clk_emi_set_parent,
3747 };
3748
3749 static unsigned long _clk_enfc_round_rate(struct clk *clk,
3750                                                 unsigned long rate)
3751 {
3752         u32 pre, post;
3753         u32 parent_rate = clk_get_rate(clk->parent);
3754         u32 div = parent_rate / rate;
3755
3756         if (parent_rate % rate)
3757                 div++;
3758
3759         __calc_pre_post_dividers(1 << 6, div, &pre, &post);
3760
3761         return parent_rate / (pre * post);
3762 }
3763
3764 static int _clk_enfc_set_parent(struct clk *clk, struct clk *parent)
3765 {
3766         u32 reg, mux;
3767
3768         reg = __raw_readl(MXC_CCM_CS2CDR)
3769                 & ~MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK;
3770
3771         mux = _get_mux6(parent, &pll2_pfd_352M,
3772                 &pll2_528_bus_main_clk, &pll3_usb_otg_main_clk,
3773                 &pll2_pfd_400M, NULL, NULL);
3774         reg |= mux << MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET;
3775
3776         __raw_writel(reg, MXC_CCM_CS2CDR);
3777
3778         return 0;
3779 }
3780
3781 static unsigned long _clk_enfc_get_rate(struct clk *clk)
3782 {
3783         u32 reg, pred, podf;
3784
3785         reg = __raw_readl(MXC_CCM_CS2CDR);
3786
3787         pred = ((reg & MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK)
3788                 >> MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET) + 1;
3789         podf = ((reg & MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK)
3790                 >> MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET) + 1;
3791
3792         return clk_get_rate(clk->parent) / (pred * podf);
3793 }
3794
3795 static int _clk_enfc_set_rate(struct clk *clk, unsigned long rate)
3796 {
3797         u32 reg, div, pre, post;
3798         u32 parent_rate = clk_get_rate(clk->parent);
3799
3800         div = parent_rate / rate;
3801         if (div == 0)
3802                 div++;
3803         if (((parent_rate / div) != rate) || div > 512)
3804                 return -EINVAL;
3805
3806         __calc_pre_post_dividers(1 << 6, div, &pre, &post);
3807
3808         reg = __raw_readl(MXC_CCM_CS2CDR);
3809         reg &= ~(MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK|
3810                  MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK);
3811         reg |= (post - 1) << MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET;
3812         reg |= (pre - 1) << MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET;
3813
3814         __raw_writel(reg, MXC_CCM_CS2CDR);
3815
3816         return 0;
3817 }
3818
3819 static struct clk enfc_clk = {
3820         __INIT_CLK_DEBUG(enfc_clk)
3821          .id = 0,
3822          .parent = &pll2_pfd_352M,
3823          .enable_reg = MXC_CCM_CCGR2,
3824          .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
3825          .enable = _clk_enable,
3826          .disable = _clk_disable,
3827          .set_rate = _clk_enfc_set_rate,
3828          .get_rate = _clk_enfc_get_rate,
3829          .round_rate = _clk_enfc_round_rate,
3830          .set_parent = _clk_enfc_set_parent,
3831 };
3832
3833 static unsigned long _clk_uart_round_rate(struct clk *clk,
3834                                                 unsigned long rate)
3835 {
3836         u32 div;
3837         u32 parent_rate = clk_get_rate(clk->parent);
3838
3839         div = parent_rate / rate;
3840
3841         /* Make sure rate is not greater than the maximum value for the clock.
3842          * Also prevent a div of 0.
3843          */
3844         if (div == 0)
3845                 div++;
3846
3847         if (div > 64)
3848                 div = 64;
3849
3850         return parent_rate / div;
3851 }
3852
3853 static int _clk_uart_set_rate(struct clk *clk, unsigned long rate)
3854 {
3855         u32 reg, div;
3856         u32 parent_rate = clk_get_rate(clk->parent);
3857
3858         div = parent_rate / rate;
3859         if (div == 0)
3860                 div++;
3861         if (((parent_rate / div) != rate) || (div > 64))
3862                 return -EINVAL;
3863
3864         reg = __raw_readl(MXC_CCM_CSCDR1) & MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
3865         reg |= ((div - 1) << MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET);
3866
3867         __raw_writel(reg, MXC_CCM_CSCDR1);
3868
3869         return 0;
3870 }
3871
3872 static unsigned long _clk_uart_get_rate(struct clk *clk)
3873 {
3874         u32 reg, div;
3875         unsigned long val;
3876
3877         reg = __raw_readl(MXC_CCM_CSCDR1) & MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
3878         div = (reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET) + 1;
3879         val = clk_get_rate(clk->parent) / div;
3880
3881         return val;
3882 }
3883
3884 static struct clk uart_clk[] = {
3885         {
3886         __INIT_CLK_DEBUG(uart_clk)
3887          .id = 0,
3888          .parent = &pll3_80M,
3889          .enable_reg = MXC_CCM_CCGR5,
3890          .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET,
3891          .enable = _clk_enable,
3892          .disable = _clk_disable,
3893          .secondary = &uart_clk[1],
3894          .set_rate = _clk_uart_set_rate,
3895          .get_rate = _clk_uart_get_rate,
3896          .round_rate = _clk_uart_round_rate,
3897         },
3898         {
3899         __INIT_CLK_DEBUG(uart_serial_clk)
3900          .id = 1,
3901          .enable_reg = MXC_CCM_CCGR5,
3902          .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
3903          .enable = _clk_enable,
3904          .disable = _clk_disable,
3905         },
3906 };
3907
3908 static unsigned long _clk_hsi_tx_round_rate(struct clk *clk,
3909                                                 unsigned long rate)
3910 {
3911         u32 div;
3912         u32 parent_rate = clk_get_rate(clk->parent);
3913
3914         div = parent_rate / rate;
3915
3916         /* Make sure rate is not greater than the maximum value for the clock.
3917          * Also prevent a div of 0.
3918          */
3919         if (div == 0)
3920                 div++;
3921
3922         if (div > 8)
3923                 div = 8;
3924
3925         return parent_rate / div;
3926 }
3927
3928 static int _clk_hsi_tx_set_parent(struct clk *clk, struct clk *parent)
3929 {
3930         u32 reg = __raw_readl(MXC_CCM_CDCDR) & ~MXC_CCM_CDCDR_HSI_TX_CLK_SEL;
3931
3932         if (parent == &pll2_pfd_400M)
3933                 reg |= (MXC_CCM_CDCDR_HSI_TX_CLK_SEL);
3934
3935         __raw_writel(reg, MXC_CCM_CDCDR);
3936
3937         return 0;
3938 }
3939
3940 static unsigned long _clk_hsi_tx_get_rate(struct clk *clk)
3941 {
3942         u32 reg, div;
3943
3944         reg = __raw_readl(MXC_CCM_CDCDR);
3945         div = ((reg & MXC_CCM_CDCDR_HSI_TX_PODF_MASK) >>
3946                         MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET) + 1;
3947
3948         return clk_get_rate(clk->parent) / div;
3949 }
3950
3951 static int _clk_hsi_tx_set_rate(struct clk *clk, unsigned long rate)
3952 {
3953         u32 reg, div;
3954         u32 parent_rate = clk_get_rate(clk->parent);
3955
3956         div = parent_rate / rate;
3957         if (div == 0)
3958                 div++;
3959         if (((parent_rate / div) != rate) || (div > 8))
3960                 return -EINVAL;
3961
3962         reg = __raw_readl(MXC_CCM_CDCDR);
3963         reg &= ~MXC_CCM_CDCDR_HSI_TX_PODF_MASK;
3964         reg |= (div - 1) << MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET;
3965         __raw_writel(reg, MXC_CCM_CDCDR);
3966
3967         return 0;
3968 }
3969
3970 static struct clk hsi_tx_clk[] = {
3971         {
3972          __INIT_CLK_DEBUG(hsi_tx_clk)
3973         .id = 0,
3974          .parent = &pll2_pfd_400M,
3975         .enable_reg = MXC_CCM_CCGR3,
3976         .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET,
3977         .enable = _clk_enable,
3978         .disable = _clk_disable,
3979         .set_parent = _clk_hsi_tx_set_parent,
3980         .round_rate = _clk_hsi_tx_round_rate,
3981         .set_rate = _clk_hsi_tx_set_rate,
3982         .get_rate = _clk_hsi_tx_get_rate,
3983          .secondary = &hsi_tx_clk[1],
3984         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
3985         },
3986         {
3987         .parent = &mx6per1_clk,
3988         .secondary = &mx6per2_clk,
3989          },
3990 };
3991
3992 static struct clk mipi_pllref_clk = {
3993          __INIT_CLK_DEBUG(mipi_pllref_clk)
3994         .id = 0,
3995         .parent = &pll3_pfd_540M,
3996         .enable_reg = MXC_CCM_CCGR3,
3997         .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET,
3998         .enable = _clk_enable,
3999         .disable = _clk_disable,
4000 };
4001
4002 static struct clk hdmi_clk[] = {
4003         {
4004          __INIT_CLK_DEBUG(hdmi_isfr_clk)
4005         .id = 0,
4006         .parent = &pll3_pfd_540M,
4007         .enable_reg = MXC_CCM_CCGR2,
4008         .enable_shift = MXC_CCM_CCGRx_CG2_OFFSET,
4009         .enable = _clk_enable,
4010         .disable = _clk_disable,
4011         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
4012         },
4013         {
4014          __INIT_CLK_DEBUG(hdmi_iahb_clk)
4015         .id = 1,
4016          .parent = &ahb_clk,
4017         .enable_reg = MXC_CCM_CCGR2,
4018         .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET,
4019         .enable = _clk_enable,
4020         .disable = _clk_disable,
4021         },
4022 };
4023
4024 static struct clk caam_clk[] = {
4025         {
4026          __INIT_CLK_DEBUG(caam_mem_clk)
4027         .id = 0,
4028         .enable_reg = MXC_CCM_CCGR0,
4029         .enable_shift = MXC_CCM_CCGRx_CG4_OFFSET,
4030         .enable = _clk_enable,
4031         .disable = _clk_disable,
4032         .secondary = &caam_clk[1],
4033         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
4034         },
4035         {
4036          __INIT_CLK_DEBUG(caam_aclk_clk)
4037         .id = 1,
4038         .enable_reg = MXC_CCM_CCGR0,
4039         .enable_shift = MXC_CCM_CCGRx_CG5_OFFSET,
4040         .enable = _clk_enable,
4041         .disable = _clk_disable,
4042         .secondary = &caam_clk[2],
4043         },
4044         {
4045          __INIT_CLK_DEBUG(caam_ipg_clk)
4046         .id = 2,
4047         .enable_reg = MXC_CCM_CCGR0,
4048         .enable_shift = MXC_CCM_CCGRx_CG4_OFFSET,
4049         .enable = _clk_enable,
4050         .disable = _clk_disable,
4051         .parent = &mmdc_ch0_axi_clk[0],
4052         .secondary = &mx6per1_clk,
4053         },
4054 };
4055
4056 static int _clk_asrc_serial_set_parent(struct clk *clk, struct clk *parent)
4057 {
4058         u32 reg, mux;
4059
4060         reg = __raw_readl(MXC_CCM_CDCDR) & ~MXC_CCM_CDCDR_SPDIF1_CLK_SEL_MASK;
4061
4062         mux = _get_mux6(parent, &pll4_audio_main_clk, &pll3_pfd_508M,
4063                         &pll3_pfd_454M, &pll3_sw_clk, NULL, NULL);
4064         reg |= mux << MXC_CCM_CDCDR_SPDIF1_CLK_SEL_OFFSET;
4065
4066         __raw_writel(reg, MXC_CCM_CDCDR);
4067
4068         return 0;
4069 }
4070
4071 static unsigned long _clk_asrc_serial_get_rate(struct clk *clk)
4072 {
4073         u32 reg, pred, podf;
4074
4075         reg = __raw_readl(MXC_CCM_CDCDR);
4076
4077         pred = ((reg & MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK)
4078                 >> MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET) + 1;
4079         podf = ((reg & MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK)
4080                 >> MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET) + 1;
4081
4082         return clk_get_rate(clk->parent) / (pred * podf);
4083 }
4084
4085 static int _clk_asrc_serial_set_rate(struct clk *clk, unsigned long rate)
4086 {
4087         u32 reg, div, pre, post;
4088         u32 parent_rate = clk_get_rate(clk->parent);
4089
4090         div = parent_rate / rate;
4091         if (div == 0)
4092                 div++;
4093         if (((parent_rate / div) != rate) || div > 64)
4094                 return -EINVAL;
4095
4096         __calc_pre_post_dividers(1 << 3, div, &pre, &post);
4097
4098         reg = __raw_readl(MXC_CCM_CDCDR);
4099         reg &= ~(MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK|
4100                  MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK);
4101         reg |= (post - 1) << MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET;
4102         reg |= (pre - 1) << MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET;
4103
4104         __raw_writel(reg, MXC_CCM_CDCDR);
4105
4106         return 0;
4107 }
4108
4109 static unsigned long _clk_asrc_serial_round_rate(struct clk *clk,
4110                                                 unsigned long rate)
4111 {
4112         u32 pre, post;
4113         u32 parent_rate = clk_get_rate(clk->parent);
4114         u32 div = parent_rate / rate;
4115
4116         if (parent_rate % rate)
4117                 div++;
4118
4119         __calc_pre_post_dividers(1 << 3, div, &pre, &post);
4120
4121         return parent_rate / (pre * post);
4122 }
4123
4124 static struct clk asrc_clk[] = {
4125         {
4126         __INIT_CLK_DEBUG(asrc_clk)
4127         .id = 0,
4128         .parent = &pll4_audio_main_clk,
4129         .enable_reg = MXC_CCM_CCGR0,
4130         .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET,
4131         .enable = _clk_enable,
4132         .disable = _clk_disable,
4133         .secondary = &spba_clk,
4134         },
4135         {
4136         /*In the MX6 spec, asrc_serial_clk is listed as SPDIF1 clk
4137          * This clock can never be gated and does  not have any
4138          * CCGR bits associated with it.
4139          */
4140         __INIT_CLK_DEBUG(asrc_serial_clk)
4141         .id = 1,
4142         .parent = &pll3_sw_clk,
4143          .set_rate = _clk_asrc_serial_set_rate,
4144          .get_rate = _clk_asrc_serial_get_rate,
4145          .set_parent = _clk_asrc_serial_set_parent,
4146          .round_rate = _clk_asrc_serial_round_rate,
4147         },
4148 };
4149
4150 static struct clk apbh_dma_clk = {
4151         __INIT_CLK_DEBUG(apbh_dma_clk)
4152         .parent = &usdhc3_clk,
4153         .secondary = &mx6per1_clk,
4154         .enable = _clk_enable,
4155         .disable = _clk_disable_inwait,
4156         .enable_reg = MXC_CCM_CCGR0,
4157         .enable_shift = MXC_CCM_CCGRx_CG2_OFFSET,
4158 };
4159
4160 static struct clk aips_tz2_clk = {
4161         __INIT_CLK_DEBUG(aips_tz2_clk)
4162         .parent = &ahb_clk,
4163         .enable_reg = MXC_CCM_CCGR0,
4164         .enable_shift = MXC_CCM_CCGRx_CG1_OFFSET,
4165         .enable = _clk_enable,
4166         .disable = _clk_disable_inwait,
4167 };
4168
4169 static struct clk aips_tz1_clk = {
4170         __INIT_CLK_DEBUG(aips_tz1_clk)
4171         .parent = &ahb_clk,
4172         .enable_reg = MXC_CCM_CCGR0,
4173         .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET,
4174         .enable = _clk_enable,
4175         .disable = _clk_disable_inwait,
4176 };
4177
4178
4179 static struct clk openvg_axi_clk = {
4180         __INIT_CLK_DEBUG(openvg_axi_clk)
4181         .parent = &gpu2d_axi_clk,
4182         .enable = _clk_enable,
4183         .enable_reg = MXC_CCM_CCGR3,
4184         .enable_shift = MXC_CCM_CCGRx_CG15_OFFSET,
4185         .disable = _clk_disable,
4186         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
4187 };
4188
4189 static unsigned long _clk_gpu3d_core_round_rate(struct clk *clk,
4190                                                 unsigned long rate)
4191 {
4192         u32 div;
4193         u32 parent_rate = clk_get_rate(clk->parent);
4194
4195         div = parent_rate / rate;
4196
4197         /* Make sure rate is not greater than the maximum value for the clock.
4198          * Also prevent a div of 0.
4199          */
4200         if (div == 0)
4201                 div++;
4202
4203         if (div > 8)
4204                 div = 8;
4205
4206         return parent_rate / div;
4207 }
4208
4209 static int _clk_gpu3d_core_set_parent(struct clk *clk, struct clk *parent)
4210 {
4211         int mux;
4212         u32 reg = __raw_readl(MXC_CCM_CBCMR)
4213                 & ~MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK;
4214
4215         mux = _get_mux6(parent, &mmdc_ch0_axi_clk[0],
4216                 &pll3_usb_otg_main_clk,
4217                 &pll2_pfd_594M, &pll2_pfd_400M, NULL, NULL);
4218         reg |= (mux << MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET);
4219         __raw_writel(reg, MXC_CCM_CBCMR);
4220
4221         return 0;
4222 }
4223
4224 static unsigned long _clk_gpu3d_core_get_rate(struct clk *clk)
4225 {
4226         u32 reg, div;
4227
4228         reg = __raw_readl(MXC_CCM_CBCMR);
4229         div = ((reg & MXC_CCM_CBCMR_GPU3D_CORE_PODF_MASK) >>
4230                         MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET) + 1;
4231
4232         return clk_get_rate(clk->parent) / div;
4233 }
4234
4235 static int _clk_gpu3d_core_set_rate(struct clk *clk, unsigned long rate)
4236 {
4237         u32 reg, div;
4238         u32 parent_rate = clk_get_rate(clk->parent);
4239
4240         div = parent_rate / rate;
4241         if (div == 0)
4242                 div++;
4243         if (div > 8)
4244                 div = 8;
4245
4246         reg = __raw_readl(MXC_CCM_CBCMR);
4247         reg &= ~MXC_CCM_CBCMR_GPU3D_CORE_PODF_MASK;
4248         reg |= (div - 1) << MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET;
4249         __raw_writel(reg, MXC_CCM_CBCMR);
4250
4251         return 0;
4252 }
4253
4254 static struct clk gpu3d_core_clk[] = {
4255         {
4256         __INIT_CLK_DEBUG(gpu3d_core_clk)
4257         .parent = &pll2_pfd_594M,
4258         .enable = _clk_enable,
4259         .enable_reg = MXC_CCM_CCGR1,
4260         .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
4261         .disable = _clk_disable,
4262         .set_parent = _clk_gpu3d_core_set_parent,
4263         .set_rate = _clk_gpu3d_core_set_rate,
4264         .get_rate = _clk_gpu3d_core_get_rate,
4265         .round_rate = _clk_gpu3d_core_round_rate,
4266         .secondary = &gpu3d_core_clk[1],
4267         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
4268         },
4269         {
4270         .parent = &gpu3d_axi_clk,
4271         .secondary = &mx6fast1_clk,
4272         },
4273 };
4274
4275 static unsigned long _clk_gpu2d_core_round_rate(struct clk *clk,
4276                                                 unsigned long rate)
4277 {
4278         u32 div;
4279         u32 parent_rate = clk_get_rate(clk->parent);
4280
4281         div = parent_rate / rate;
4282
4283         /* Make sure rate is not greater than the maximum value for the clock.
4284          * Also prevent a div of 0.
4285          */
4286         if (div == 0)
4287                 div++;
4288
4289         if (div > 8)
4290                 div = 8;
4291
4292         return parent_rate / div;
4293 }
4294
4295 static int _clk_gpu2d_core_set_parent(struct clk *clk, struct clk *parent)
4296 {
4297         int mux;
4298         u32 reg = __raw_readl(MXC_CCM_CBCMR) &
4299                                 ~MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK;
4300
4301         /*on mx6dl, 2d core clock sources from 3d shader core clock*/
4302         if (!cpu_is_mx6dl()) {
4303                 mux = _get_mux6(parent, &axi_clk, &pll3_usb_otg_main_clk,
4304                         &pll2_pfd_352M, &pll2_pfd_400M, NULL, NULL);
4305                 reg |= (mux << MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET);
4306                 __raw_writel(reg, MXC_CCM_CBCMR);
4307         }
4308
4309         return 0;
4310 }
4311
4312 static unsigned long _clk_gpu2d_core_get_rate(struct clk *clk)
4313 {
4314         u32 reg, div = 1;
4315
4316         reg = __raw_readl(MXC_CCM_CBCMR);
4317         if (cpu_is_mx6q())
4318                 div = ((reg & MXC_CCM_CBCMR_GPU2D_CORE_PODF_MASK) >>
4319                                 MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET) + 1;
4320         else if (cpu_is_mx6dl())
4321                 /* on i.mx6dl, gpu2d_core_clk source from gpu3d_shader_clk */
4322                 return clk_get_rate(clk->parent);
4323
4324         return clk_get_rate(clk->parent) / div;
4325 }
4326
4327 static int _clk_gpu2d_core_set_rate(struct clk *clk, unsigned long rate)
4328 {
4329         u32 reg, div;
4330         u32 parent_rate = clk_get_rate(clk->parent);
4331
4332         div = parent_rate / rate;
4333         if (div == 0)
4334                 div++;
4335         if (((parent_rate / div) != rate) || (div > 8))
4336                 return -EINVAL;
4337
4338         reg = __raw_readl(MXC_CCM_CBCMR);
4339         reg &= ~MXC_CCM_CBCMR_GPU2D_CORE_PODF_MASK;
4340         reg |= (div - 1) << MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET;
4341         __raw_writel(reg, MXC_CCM_CBCMR);
4342
4343         return 0;
4344 }
4345 static struct clk gpu2d_core_clk[] = {
4346         {
4347         __INIT_CLK_DEBUG(gpu2d_core_clk)
4348         .parent = &pll2_pfd_352M,
4349         .enable = _clk_enable,
4350         .enable_reg = MXC_CCM_CCGR1,
4351         .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET,
4352         .disable = _clk_disable,
4353         .set_parent = _clk_gpu2d_core_set_parent,
4354         .set_rate = _clk_gpu2d_core_set_rate,
4355         .get_rate = _clk_gpu2d_core_get_rate,
4356         .round_rate = _clk_gpu2d_core_round_rate,
4357         .secondary = &gpu2d_core_clk[1],
4358         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
4359         },
4360         {
4361         .parent = &gpu2d_axi_clk,
4362         .secondary = &mx6fast1_clk,
4363         },
4364 };
4365
4366 static unsigned long _clk_gpu3d_shader_round_rate(struct clk *clk,
4367                                                 unsigned long rate)
4368 {
4369         u32 div;
4370         u32 parent_rate = clk_get_rate(clk->parent);
4371
4372         div = parent_rate / rate;
4373
4374         /* Make sure rate is not greater than the maximum value for the clock.
4375          * Also prevent a div of 0.
4376          */
4377         if (div == 0)
4378                 div++;
4379
4380         if (div > 8)
4381                 div = 8;
4382
4383         return parent_rate / div;
4384 }
4385
4386 static int _clk_gpu3d_shader_set_parent(struct clk *clk, struct clk *parent)
4387 {
4388         int mux;
4389         u32 reg = __raw_readl(MXC_CCM_CBCMR)
4390                 & ~MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_MASK;
4391
4392         mux = _get_mux6(parent, &mmdc_ch0_axi_clk[0],
4393                 &pll3_usb_otg_main_clk,
4394                 &pll2_pfd_594M, &pll3_pfd_720M, NULL, NULL);
4395         reg |= (mux << MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET);
4396         __raw_writel(reg, MXC_CCM_CBCMR);
4397
4398         return 0;
4399 }
4400
4401 static unsigned long _clk_gpu3d_shader_get_rate(struct clk *clk)
4402 {
4403         u32 reg, div;
4404
4405         reg = __raw_readl(MXC_CCM_CBCMR);
4406         div = ((reg & MXC_CCM_CBCMR_GPU3D_SHADER_PODF_MASK) >>
4407                         MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET) + 1;
4408
4409         return clk_get_rate(clk->parent) / div;
4410 }
4411
4412 static int _clk_gpu3d_shader_set_rate(struct clk *clk, unsigned long rate)
4413 {
4414         u32 reg, div;
4415         u32 parent_rate = clk_get_rate(clk->parent);
4416
4417         div = parent_rate / rate;
4418         if (div == 0)
4419                 div++;
4420         if (div > 8)
4421                 div = 8;
4422
4423         reg = __raw_readl(MXC_CCM_CBCMR);
4424         reg &= ~MXC_CCM_CBCMR_GPU3D_SHADER_PODF_MASK;
4425         reg |= (div - 1) << MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET;
4426         __raw_writel(reg, MXC_CCM_CBCMR);
4427
4428         return 0;
4429 }
4430
4431
4432 static struct clk gpu3d_shader_clk = {
4433         __INIT_CLK_DEBUG(gpu3d_shader_clk)
4434         .parent = &pll3_pfd_720M,
4435         .secondary = &mmdc_ch0_axi_clk[0],
4436         .enable = _clk_enable,
4437         .enable_reg = MXC_CCM_CCGR1,
4438         .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
4439         .disable = _clk_disable,
4440         .set_parent = _clk_gpu3d_shader_set_parent,
4441         .set_rate = _clk_gpu3d_shader_set_rate,
4442         .get_rate = _clk_gpu3d_shader_get_rate,
4443         .round_rate = _clk_gpu3d_shader_round_rate,
4444         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
4445 };
4446
4447 /* set the parent by the ipcg table */
4448 static struct clk gpmi_nand_clk[] = {
4449         {       /* gpmi_io_clk */
4450         __INIT_CLK_DEBUG(gpmi_io_clk)
4451         .parent = &enfc_clk,
4452         .secondary = &gpmi_nand_clk[1],
4453         .enable = _clk_enable,
4454         .enable_reg = MXC_CCM_CCGR4,
4455         .enable_shift = MXC_CCM_CCGRx_CG14_OFFSET,
4456         .disable = _clk_disable,
4457         },
4458         {       /* gpmi_apb_clk */
4459         __INIT_CLK_DEBUG(gpmi_apb_clk)
4460         .parent = &usdhc3_clk,
4461         .secondary = &gpmi_nand_clk[2],
4462         .enable = _clk_enable,
4463         .enable_reg = MXC_CCM_CCGR4,
4464         .enable_shift = MXC_CCM_CCGRx_CG15_OFFSET,
4465         .disable = _clk_disable,
4466         },
4467         {       /* bch_clk */
4468         __INIT_CLK_DEBUG(gpmi_bch_clk)
4469         .parent = &usdhc4_clk,
4470         .secondary = &gpmi_nand_clk[3],
4471         .enable = _clk_enable,
4472         .enable_reg = MXC_CCM_CCGR4,
4473         .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
4474         .disable = _clk_disable,
4475         },
4476         {       /* bch_apb_clk */
4477         __INIT_CLK_DEBUG(gpmi_bch_apb_clk)
4478         .parent = &usdhc3_clk,
4479         .secondary = &gpmi_nand_clk[4],
4480         .enable = _clk_enable,
4481         .enable_reg = MXC_CCM_CCGR4,
4482         .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET,
4483         .disable = _clk_disable,
4484         },
4485         {       /* bch relative clk */
4486         __INIT_CLK_DEBUG(pl301_mx6qperl_bch)
4487         .parent = &mx6per1_clk,
4488         .secondary = &mmdc_ch0_axi_clk[0],
4489         },
4490 };
4491
4492 static struct clk pwm_clk[] = {
4493         {
4494         __INIT_CLK_DEBUG(pwm_clk_0)
4495          .parent = &ipg_perclk,
4496          .id = 0,
4497          .enable_reg = MXC_CCM_CCGR4,
4498          .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET,
4499          .enable = _clk_enable,
4500          .disable = _clk_disable,
4501          },
4502         {
4503         __INIT_CLK_DEBUG(pwm_clk_1)
4504          .parent = &ipg_perclk,
4505          .id = 1,
4506          .enable_reg = MXC_CCM_CCGR4,
4507          .enable_shift = MXC_CCM_CCGRx_CG9_OFFSET,
4508          .enable = _clk_enable,
4509          .disable = _clk_disable,
4510          },
4511         {
4512         __INIT_CLK_DEBUG(pwm_clk_2)
4513          .parent = &ipg_perclk,
4514          .id = 2,
4515          .enable_reg = MXC_CCM_CCGR4,
4516          .enable_shift = MXC_CCM_CCGRx_CG10_OFFSET,
4517          .enable = _clk_enable,
4518          .disable = _clk_disable,
4519          },
4520         {
4521         __INIT_CLK_DEBUG(pwm_clk_3)
4522          .parent = &ipg_perclk,
4523          .id = 3,
4524          .enable_reg = MXC_CCM_CCGR4,
4525          .enable_shift = MXC_CCM_CCGRx_CG11_OFFSET,
4526          .enable = _clk_enable,
4527          .disable = _clk_disable,
4528          },
4529 };
4530
4531 static int _clk_pcie_enable(struct clk *clk)
4532 {
4533         unsigned int reg;
4534
4535         /* Clear Power Down and Enable PLLs */
4536         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
4537         reg &= ~ANADIG_PLL_ENET_POWER_DOWN;
4538         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
4539
4540         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
4541         reg |= ANADIG_PLL_ENET_EN;
4542         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
4543
4544         /* Waiting for the PLL is locked */
4545         if (!WAIT(ANADIG_PLL_ENET_LOCK & __raw_readl(PLL8_ENET_BASE_ADDR),
4546                                 SPIN_DELAY))
4547                 panic("pll8 lock failed\n");
4548
4549         /* Disable the bypass */
4550         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
4551         reg &= ~ANADIG_PLL_ENET_BYPASS;
4552         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
4553
4554         /*
4555          * Enable SATA ref clock.
4556          * PCIe needs both sides to have the same source of refernce clock,
4557          * The SATA reference clock is taken out on clk out
4558          */
4559         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
4560         reg |= ANADIG_PLL_ENET_EN_SATA;
4561         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
4562
4563         /* Activate LVDS CLK1 (the MiniPCIe slot clock input) */
4564         reg = __raw_readl(ANADIG_MISC1_REG);
4565         reg &= ~ANATOP_LVDS_CLK1_IBEN_MASK;
4566         __raw_writel(reg, ANADIG_MISC1_REG);
4567
4568         reg = __raw_readl(ANADIG_MISC1_REG);
4569         reg |= ANATOP_LVDS_CLK1_SRC_SATA;
4570         __raw_writel(reg, ANADIG_MISC1_REG);
4571
4572         reg = __raw_readl(ANADIG_MISC1_REG);
4573         reg |= ANATOP_LVDS_CLK1_OBEN_MASK;
4574         __raw_writel(reg, ANADIG_MISC1_REG);
4575
4576         /* Enable PCIE ref clock */
4577         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
4578         reg |= ANADIG_PLL_ENET_EN_PCIE;
4579         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
4580
4581         _clk_enable(clk);
4582
4583         return 0;
4584 }
4585
4586 static void _clk_pcie_disable(struct clk *clk)
4587 {
4588         unsigned int reg;
4589
4590         _clk_disable(clk);
4591
4592         /* Disable SATA ref clock */
4593         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
4594         reg &= ~ANADIG_PLL_ENET_EN_PCIE;
4595         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
4596 }
4597
4598 static struct clk pcie_clk[] = {
4599         {
4600         __INIT_CLK_DEBUG(pcie_clk)
4601         .parent = &pcie_axi_clk,
4602         .enable = _clk_pcie_enable,
4603         .disable = _clk_pcie_disable,
4604         .enable_reg = MXC_CCM_CCGR4,
4605         .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET,
4606         .secondary = &pcie_clk[1],
4607         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
4608         },
4609         {
4610         .parent = &mmdc_ch0_axi_clk[0],
4611         .secondary = &mx6fast1_clk,
4612         },
4613 };
4614
4615 static int _clk_sata_enable(struct clk *clk)
4616 {
4617         unsigned int reg;
4618
4619         /* Clear Power Down and Enable PLLs */
4620         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
4621         reg &= ~ANADIG_PLL_ENET_POWER_DOWN;
4622         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
4623
4624         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
4625         reg |= ANADIG_PLL_ENET_EN;
4626         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
4627
4628         /* Waiting for the PLL is locked */
4629         if (!WAIT(ANADIG_PLL_ENET_LOCK & __raw_readl(PLL8_ENET_BASE_ADDR),
4630                                 SPIN_DELAY))
4631                 panic("pll8 lock failed\n");
4632
4633         /* Disable the bypass */
4634         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
4635         reg &= ~ANADIG_PLL_ENET_BYPASS;
4636         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
4637
4638         /* Enable SATA ref clock */
4639         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
4640         reg |= ANADIG_PLL_ENET_EN_SATA;
4641         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
4642
4643         _clk_enable(clk);
4644
4645         return 0;
4646 }
4647
4648 static void _clk_sata_disable(struct clk *clk)
4649 {
4650         unsigned int reg;
4651
4652         _clk_disable(clk);
4653
4654         /* Disable SATA ref clock */
4655         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
4656         reg &= ~ANADIG_PLL_ENET_EN_SATA;
4657         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
4658 }
4659
4660 static struct clk sata_clk[] = {
4661         {
4662         __INIT_CLK_DEBUG(sata_clk)
4663         .parent = &ipg_clk,
4664         .enable = _clk_sata_enable,
4665         .enable_reg = MXC_CCM_CCGR5,
4666         .enable_shift = MXC_CCM_CCGRx_CG2_OFFSET,
4667         .disable = _clk_sata_disable,
4668         .secondary = &sata_clk[1],
4669         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
4670         },
4671         {
4672         .parent = &mmdc_ch0_axi_clk[0],
4673         .secondary = &mx6per1_clk,
4674         }
4675 };
4676
4677 static struct clk usboh3_clk[] = {
4678         {
4679         __INIT_CLK_DEBUG(usboh3_clk)
4680         .parent = &ahb_clk,
4681         .enable = _clk_enable,
4682         .enable_reg = MXC_CCM_CCGR6,
4683         .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET,
4684         .disable = _clk_disable,
4685         .secondary = &usboh3_clk[1],
4686         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
4687         },
4688         {
4689         .parent = &mmdc_ch0_axi_clk[0],
4690         .secondary = &mx6per1_clk,
4691         },
4692 };
4693
4694 static struct clk mlb150_clk = {
4695         __INIT_CLK_DEBUG(mlb150_clk)
4696         .id = 0,
4697         .parent = &ipg_clk,
4698         .enable_reg = MXC_CCM_CCGR3,
4699         .enable_shift = MXC_CCM_CCGRx_CG9_OFFSET,
4700         .enable = _clk_enable,
4701         .disable = _clk_disable,
4702 };
4703
4704 static int _clk_enable1(struct clk *clk)
4705 {
4706         u32 reg;
4707         reg = __raw_readl(clk->enable_reg);
4708         reg |= 1 << clk->enable_shift;
4709         __raw_writel(reg, clk->enable_reg);
4710
4711         return 0;
4712 }
4713
4714 static void _clk_disable1(struct clk *clk)
4715 {
4716         u32 reg;
4717         reg = __raw_readl(clk->enable_reg);
4718         reg &= ~(1 << clk->enable_shift);
4719         __raw_writel(reg, clk->enable_reg);
4720 }
4721
4722 static int _clk_clko_set_parent(struct clk *clk, struct clk *parent)
4723 {
4724         u32 sel, reg;
4725
4726         if (parent == &pll3_usb_otg_main_clk)
4727                 sel = 0;
4728         else if (parent == &pll2_528_bus_main_clk)
4729                 sel = 1;
4730         else if (parent == &pll1_sys_main_clk)
4731                 sel = 2;
4732         else if (parent == &pll5_video_main_clk)
4733                 sel = 3;
4734         else if (parent == &axi_clk)
4735                 sel = 5;
4736         else if (parent == &enfc_clk)
4737                 sel = 6;
4738         else if (parent == &ipu1_di_clk[0])
4739                 sel = 7;
4740         else if (parent == &ipu1_di_clk[1])
4741                 sel = 8;
4742         else if (parent == &ipu2_di_clk[0])
4743                 sel = 9;
4744         else if (parent == &ipu2_di_clk[1])
4745                 sel = 10;
4746         else if (parent == &ahb_clk)
4747                 sel = 11;
4748         else if (parent == &ipg_clk)
4749                 sel = 12;
4750         else if (parent == &ipg_perclk)
4751                 sel = 13;
4752         else if (parent == &ckil_clk)
4753                 sel = 14;
4754         else if (parent == &pll4_audio_main_clk)
4755                 sel = 15;
4756         else
4757                 return -EINVAL;
4758
4759         reg = __raw_readl(MXC_CCM_CCOSR);
4760         reg &= ~MXC_CCM_CCOSR_CKOL_SEL_MASK;
4761         reg |= sel << MXC_CCM_CCOSR_CKOL_SEL_OFFSET;
4762         __raw_writel(reg, MXC_CCM_CCOSR);
4763         return 0;
4764 }
4765
4766 static unsigned long _clk_clko_get_rate(struct clk *clk)
4767 {
4768         u32 reg = __raw_readl(MXC_CCM_CCOSR);
4769         u32 div = ((reg & MXC_CCM_CCOSR_CKOL_DIV_MASK) >>
4770                         MXC_CCM_CCOSR_CKOL_DIV_OFFSET) + 1;
4771         return clk_get_rate(clk->parent) / div;
4772 }
4773
4774 static int _clk_clko_set_rate(struct clk *clk, unsigned long rate)
4775 {
4776         u32 reg;
4777         u32 parent_rate = clk_get_rate(clk->parent);
4778         u32 div = parent_rate / rate;
4779
4780         if (div == 0)
4781                 div++;
4782         if (((parent_rate / div) != rate) || (div > 8))
4783                 return -EINVAL;
4784
4785         reg = __raw_readl(MXC_CCM_CCOSR);
4786         reg &= ~MXC_CCM_CCOSR_CKOL_DIV_MASK;
4787         reg |= (div - 1) << MXC_CCM_CCOSR_CKOL_DIV_OFFSET;
4788         __raw_writel(reg, MXC_CCM_CCOSR);
4789         return 0;
4790 }
4791
4792 static unsigned long _clk_clko_round_rate(struct clk *clk,
4793                                                 unsigned long rate)
4794 {
4795         u32 parent_rate = clk_get_rate(clk->parent);
4796         u32 div = parent_rate / rate;
4797
4798         /* Make sure rate is not greater than the maximum value for the clock.
4799          * Also prevent a div of 0.
4800          */
4801         if (div == 0)
4802                 div++;
4803         if (div > 8)
4804                 div = 8;
4805         return parent_rate / div;
4806 }
4807
4808 static int _clk_clko2_set_parent(struct clk *clk, struct clk *parent)
4809 {
4810         u32 sel, reg;
4811
4812         if (parent == &mmdc_ch0_axi_clk[0])
4813                 sel = 0;
4814         else if (parent == &mmdc_ch1_axi_clk[0])
4815                 sel = 1;
4816         else if (parent == &usdhc4_clk)
4817                 sel = 2;
4818         else if (parent == &usdhc1_clk)
4819                 sel = 3;
4820         else if (parent == &gpu2d_axi_clk)
4821                 sel = 4;
4822         else if (parent == &ecspi_clk[0])
4823                 sel = 6;
4824         else if (parent == &gpu3d_axi_clk)
4825                 sel = 7;
4826         else if (parent == &usdhc3_clk)
4827                 sel = 8;
4828         else if (parent == &pcie_clk[0])
4829                 sel = 9;
4830         else if (parent == &ipu1_clk)
4831                 sel = 11;
4832         else if (parent == &ipu2_clk)
4833                 sel = 12;
4834         else if (parent == &vdo_axi_clk)
4835                 sel = 13;
4836         else if (parent == &osc_clk)
4837                 sel = 14;
4838         else if (parent == &gpu2d_core_clk[0])
4839                 sel = 15;
4840         else if (parent == &gpu3d_core_clk[0])
4841                 sel = 16;
4842         else if (parent == &usdhc2_clk)
4843                 sel = 17;
4844         else if (parent == &ssi1_clk)
4845                 sel = 18;
4846         else if (parent == &ssi2_clk)
4847                 sel = 19;
4848         else if (parent == &ssi3_clk)
4849                 sel = 20;
4850         else if (parent == &gpu3d_shader_clk)
4851                 sel = 21;
4852         else if (parent == &can_clk_root)
4853                 sel = 23;
4854         else if (parent == &ldb_di0_clk)
4855                 sel = 24;
4856         else if (parent == &ldb_di1_clk)
4857                 sel = 25;
4858         else if (parent == &esai_clk)
4859                 sel = 26;
4860         else if (parent == &uart_clk[0])
4861                 sel = 28;
4862         else if (parent == &spdif0_clk[0])
4863                 sel = 29;
4864         else if (parent == &hsi_tx_clk[0])
4865                 sel = 31;
4866         else
4867                 return -EINVAL;
4868
4869         reg = __raw_readl(MXC_CCM_CCOSR);
4870         reg &= ~MXC_CCM_CCOSR_CKO2_SEL_MASK;
4871         reg |= sel << MXC_CCM_CCOSR_CKO2_SEL_OFFSET;
4872         __raw_writel(reg, MXC_CCM_CCOSR);
4873         return 0;
4874 }
4875
4876 static unsigned long _clk_clko2_get_rate(struct clk *clk)
4877 {
4878         u32 reg = __raw_readl(MXC_CCM_CCOSR);
4879         u32 div = ((reg & MXC_CCM_CCOSR_CKO2_DIV_MASK) >>
4880                         MXC_CCM_CCOSR_CKO2_DIV_OFFSET) + 1;
4881         return clk_get_rate(clk->parent) / div;
4882 }
4883
4884 static int _clk_clko2_set_rate(struct clk *clk, unsigned long rate)
4885 {
4886         u32 reg;
4887         u32 parent_rate = clk_get_rate(clk->parent);
4888         u32 div = parent_rate / rate;
4889
4890         if (div == 0)
4891                 div++;
4892         if (((parent_rate / div) != rate) || (div > 8))
4893                 return -EINVAL;
4894
4895         reg = __raw_readl(MXC_CCM_CCOSR);
4896         reg &= ~MXC_CCM_CCOSR_CKO2_DIV_MASK;
4897         reg |= (div - 1) << MXC_CCM_CCOSR_CKO2_DIV_OFFSET;
4898         __raw_writel(reg, MXC_CCM_CCOSR);
4899         return 0;
4900 }
4901
4902 static struct clk clko_clk = {
4903         __INIT_CLK_DEBUG(clko_clk)
4904         .parent = &pll2_528_bus_main_clk,
4905         .enable = _clk_enable1,
4906         .enable_reg = MXC_CCM_CCOSR,
4907         .enable_shift = MXC_CCM_CCOSR_CKOL_EN_OFFSET,
4908         .disable = _clk_disable1,
4909         .set_parent = _clk_clko_set_parent,
4910         .set_rate = _clk_clko_set_rate,
4911         .get_rate = _clk_clko_get_rate,
4912         .round_rate = _clk_clko_round_rate,
4913 };
4914
4915 static struct clk clko2_clk = {
4916         __INIT_CLK_DEBUG(clko2_clk)
4917         .parent = &usdhc4_clk,
4918         .enable = _clk_enable1,
4919         .enable_reg = MXC_CCM_CCOSR,
4920         .enable_shift = MXC_CCM_CCOSR_CKO2_EN_OFFSET,
4921         .disable = _clk_disable1,
4922         .set_parent = _clk_clko2_set_parent,
4923         .set_rate = _clk_clko2_set_rate,
4924         .get_rate = _clk_clko2_get_rate,
4925         .round_rate = _clk_clko_round_rate,
4926 };
4927
4928 static struct clk perfmon0_clk = {
4929         __INIT_CLK_DEBUG(perfmon0_clk)
4930         .parent = &mmdc_ch0_axi_clk[0],
4931         .enable = _clk_enable1,
4932         .enable_reg = MXC_CCM_CCGR4,
4933         .enable_shift = MXC_CCM_CCGRx_CG1_OFFSET,
4934         .disable = _clk_disable1,
4935 };
4936
4937 static struct clk perfmon1_clk = {
4938         __INIT_CLK_DEBUG(perfmon1_clk)
4939         .parent = &ipu1_clk,
4940         .enable = _clk_enable1,
4941         .enable_reg = MXC_CCM_CCGR4,
4942         .enable_shift = MXC_CCM_CCGRx_CG2_OFFSET,
4943         .disable = _clk_disable1,
4944 };
4945
4946 static struct clk perfmon2_clk = {
4947         __INIT_CLK_DEBUG(perfmon2_clk)
4948         .parent = &mmdc_ch0_axi_clk[0],
4949         .enable = _clk_enable1,
4950         .enable_reg = MXC_CCM_CCGR4,
4951         .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET,
4952         .disable = _clk_disable1,
4953 };
4954
4955 static struct clk dummy_clk = {
4956         .id = 0,
4957 };
4958
4959 #define _REGISTER_CLOCK(d, n, c) \
4960         { \
4961                 .dev_id = d, \
4962                 .con_id = n, \
4963                 .clk = &c, \
4964         }
4965
4966
4967 static struct clk_lookup lookups[] = {
4968         _REGISTER_CLOCK(NULL, "osc", osc_clk),
4969         _REGISTER_CLOCK(NULL, "ckih", ckih_clk),
4970         _REGISTER_CLOCK(NULL, "ckih2", ckih2_clk),
4971         _REGISTER_CLOCK(NULL, "ckil", ckil_clk),
4972         _REGISTER_CLOCK(NULL, "pll1_main_clk", pll1_sys_main_clk),
4973         _REGISTER_CLOCK(NULL, "pll1_sw_clk", pll1_sw_clk),
4974         _REGISTER_CLOCK(NULL, "pll2", pll2_528_bus_main_clk),
4975         _REGISTER_CLOCK(NULL, "pll2_pfd_400M", pll2_pfd_400M),
4976         _REGISTER_CLOCK(NULL, "pll2_pfd_352M", pll2_pfd_352M),
4977         _REGISTER_CLOCK(NULL, "pll2_pfd_594M", pll2_pfd_594M),
4978         _REGISTER_CLOCK(NULL, "pll2_200M", pll2_200M),
4979         _REGISTER_CLOCK(NULL, "pll3_main_clk", pll3_usb_otg_main_clk),
4980         _REGISTER_CLOCK(NULL, "pll3_pfd_508M", pll3_pfd_508M),
4981         _REGISTER_CLOCK(NULL, "pll3_pfd_454M", pll3_pfd_454M),
4982         _REGISTER_CLOCK(NULL, "pll3_pfd_720M", pll3_pfd_720M),
4983         _REGISTER_CLOCK(NULL, "pll3_pfd_540M", pll3_pfd_540M),
4984         _REGISTER_CLOCK(NULL, "pll3_sw_clk", pll3_sw_clk),
4985         _REGISTER_CLOCK(NULL, "pll3_120M", pll3_120M),
4986         _REGISTER_CLOCK(NULL, "pll3_120M", pll3_80M),
4987         _REGISTER_CLOCK(NULL, "pll3_120M", pll3_60M),
4988         _REGISTER_CLOCK(NULL, "pll4", pll4_audio_main_clk),
4989         _REGISTER_CLOCK(NULL, "pll5", pll5_video_main_clk),
4990         _REGISTER_CLOCK(NULL, "pll6", pll6_mlb150_main_clk),
4991         _REGISTER_CLOCK(NULL, "pll3", pll7_usb_host_main_clk),
4992         _REGISTER_CLOCK(NULL, "pll4", pll8_enet_main_clk),
4993         _REGISTER_CLOCK(NULL, "cpu_clk", cpu_clk),
4994         _REGISTER_CLOCK(NULL, "periph_clk", periph_clk),
4995         _REGISTER_CLOCK(NULL, "axi_clk", axi_clk),
4996         _REGISTER_CLOCK(NULL, "mmdc_ch0_axi", mmdc_ch0_axi_clk[0]),
4997         _REGISTER_CLOCK(NULL, "mmdc_ch1_axi", mmdc_ch1_axi_clk[0]),
4998         _REGISTER_CLOCK(NULL, "ahb", ahb_clk),
4999         _REGISTER_CLOCK(NULL, "ipg_clk", ipg_clk),
5000         _REGISTER_CLOCK(NULL, "ipg_perclk", ipg_perclk),
5001         _REGISTER_CLOCK(NULL, "spba", spba_clk),
5002         _REGISTER_CLOCK("imx-sdma", NULL, sdma_clk[0]),
5003         _REGISTER_CLOCK(NULL, "gpu2d_axi_clk", gpu2d_axi_clk),
5004         _REGISTER_CLOCK(NULL, "gpu3d_axi_clk", gpu3d_axi_clk),
5005         _REGISTER_CLOCK(NULL, "pcie_axi_clk", pcie_axi_clk),
5006         _REGISTER_CLOCK(NULL, "vdo_axi_clk", vdo_axi_clk),
5007         _REGISTER_CLOCK(NULL, "iim_clk", iim_clk),
5008         _REGISTER_CLOCK(NULL, "i2c_clk", i2c_clk[0]),
5009         _REGISTER_CLOCK("imx-i2c.1", NULL, i2c_clk[1]),
5010         _REGISTER_CLOCK("imx-i2c.2", NULL, i2c_clk[2]),
5011         _REGISTER_CLOCK(NULL, "vpu_clk", vpu_clk[0]),
5012         _REGISTER_CLOCK(NULL, "ipu1_clk", ipu1_clk),
5013         _REGISTER_CLOCK(NULL, "ipu2_clk", ipu2_clk),
5014         _REGISTER_CLOCK("sdhci-esdhc-imx.0", NULL, usdhc1_clk),
5015         _REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL, usdhc2_clk),
5016         _REGISTER_CLOCK("sdhci-esdhc-imx.2", NULL, usdhc3_clk),
5017         _REGISTER_CLOCK("sdhci-esdhc-imx.3", NULL, usdhc4_clk),
5018         _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk),
5019         _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk),
5020         _REGISTER_CLOCK("imx-ssi.2", NULL, ssi3_clk),
5021         _REGISTER_CLOCK(NULL, "ipu1_di0_clk", ipu1_di_clk[0]),
5022         _REGISTER_CLOCK(NULL, "ipu1_di1_clk", ipu1_di_clk[1]),
5023         _REGISTER_CLOCK(NULL, "ipu2_di0_clk", ipu2_di_clk[0]),
5024         _REGISTER_CLOCK(NULL, "ipu2_di1_clk", ipu2_di_clk[1]),
5025         _REGISTER_CLOCK(NULL, "can_root_clk", can_clk_root),
5026         _REGISTER_CLOCK("imx6q-flexcan.0", NULL, can1_clk[0]),
5027         _REGISTER_CLOCK("imx6q-flexcan.1", NULL, can2_clk[0]),
5028         _REGISTER_CLOCK(NULL, "ldb_di0_clk", ldb_di0_clk),
5029         _REGISTER_CLOCK(NULL, "ldb_di1_clk", ldb_di1_clk),
5030         _REGISTER_CLOCK("mxc_spdif.0", NULL, spdif0_clk[0]),
5031         _REGISTER_CLOCK(NULL, "esai_clk", esai_clk),
5032         _REGISTER_CLOCK("imx6q-ecspi.0", NULL, ecspi_clk[0]),
5033         _REGISTER_CLOCK("imx6q-ecspi.1", NULL, ecspi_clk[1]),
5034         _REGISTER_CLOCK("imx6q-ecspi.2", NULL, ecspi_clk[2]),
5035         _REGISTER_CLOCK("imx6q-ecspi.3", NULL, ecspi_clk[3]),
5036         _REGISTER_CLOCK("imx6q-ecspi.4", NULL, ecspi_clk[4]),
5037         _REGISTER_CLOCK(NULL, "emi_slow_clk", emi_slow_clk),
5038         _REGISTER_CLOCK(NULL, "emi_clk", emi_clk),
5039         _REGISTER_CLOCK(NULL, "enfc_clk", enfc_clk),
5040         _REGISTER_CLOCK("imx-uart.0", NULL, uart_clk[0]),
5041         _REGISTER_CLOCK("imx-uart.1", NULL, uart_clk[0]),
5042         _REGISTER_CLOCK("imx-uart.2", NULL, uart_clk[0]),
5043         _REGISTER_CLOCK("imx-uart.3", NULL, uart_clk[0]),
5044         _REGISTER_CLOCK(NULL, "hsi_tx", hsi_tx_clk[0]),
5045         _REGISTER_CLOCK(NULL, "caam_clk", caam_clk[0]),
5046         _REGISTER_CLOCK(NULL, "asrc_clk", asrc_clk[0]),
5047         _REGISTER_CLOCK(NULL, "asrc_serial_clk", asrc_clk[1]),
5048         _REGISTER_CLOCK("mxs-dma-apbh", NULL, apbh_dma_clk),
5049         _REGISTER_CLOCK(NULL, "openvg_axi_clk", openvg_axi_clk),
5050         _REGISTER_CLOCK(NULL, "gpu3d_clk", gpu3d_core_clk[0]),
5051         _REGISTER_CLOCK(NULL, "gpu2d_clk", gpu2d_core_clk[0]),
5052         _REGISTER_CLOCK(NULL, "gpu3d_shader_clk", gpu3d_shader_clk),
5053         _REGISTER_CLOCK(NULL, "gpt", gpt_clk[0]),
5054         _REGISTER_CLOCK("imx6q-gpmi-nand.0", NULL, gpmi_nand_clk[0]),
5055         _REGISTER_CLOCK(NULL, "gpmi-apb", gpmi_nand_clk[1]),
5056         _REGISTER_CLOCK(NULL, "bch", gpmi_nand_clk[2]),
5057         _REGISTER_CLOCK(NULL, "bch-apb", gpmi_nand_clk[3]),
5058         _REGISTER_CLOCK(NULL, "pl301_mx6qperl-bch", gpmi_nand_clk[4]),
5059         _REGISTER_CLOCK("mxc_pwm.0", NULL, pwm_clk[0]),
5060         _REGISTER_CLOCK("mxc_pwm.1", NULL, pwm_clk[1]),
5061         _REGISTER_CLOCK("mxc_pwm.2", NULL, pwm_clk[2]),
5062         _REGISTER_CLOCK("mxc_pwm.3", NULL, pwm_clk[3]),
5063         _REGISTER_CLOCK(NULL, "pcie_clk", pcie_clk[0]),
5064         _REGISTER_CLOCK("fec.0", NULL, enet_clk[0]),
5065         _REGISTER_CLOCK(NULL, "imx_sata_clk", sata_clk[0]),
5066         _REGISTER_CLOCK(NULL, "usboh3_clk", usboh3_clk[0]),
5067         _REGISTER_CLOCK(NULL, "usb_phy1_clk", usb_phy1_clk),
5068         _REGISTER_CLOCK(NULL, "usb_phy3_clk", usb_phy3_clk),
5069         _REGISTER_CLOCK(NULL, "usb_phy4_clk", usb_phy4_clk),
5070         _REGISTER_CLOCK("imx2-wdt.0", NULL, dummy_clk),
5071         _REGISTER_CLOCK("imx2-wdt.1", NULL, dummy_clk),
5072         _REGISTER_CLOCK(NULL, "hdmi_isfr_clk", hdmi_clk[0]),
5073         _REGISTER_CLOCK(NULL, "hdmi_iahb_clk", hdmi_clk[1]),
5074         _REGISTER_CLOCK(NULL, "mipi_pllref_clk", mipi_pllref_clk),
5075         _REGISTER_CLOCK(NULL, NULL, vdoa_clk),
5076         _REGISTER_CLOCK(NULL, NULL, aips_tz2_clk),
5077         _REGISTER_CLOCK(NULL, NULL, aips_tz1_clk),
5078         _REGISTER_CLOCK(NULL, "clko_clk", clko_clk),
5079         _REGISTER_CLOCK(NULL, "clko2_clk", clko2_clk),
5080         _REGISTER_CLOCK(NULL, "pxp_axi", ipu2_clk),
5081         _REGISTER_CLOCK(NULL, "epdc_axi", ipu2_clk),
5082         _REGISTER_CLOCK(NULL, "epdc_pix", ipu2_di_clk[1]),
5083         _REGISTER_CLOCK("mxs-perfmon.0", "perfmon", perfmon0_clk),
5084         _REGISTER_CLOCK("mxs-perfmon.1", "perfmon", perfmon1_clk),
5085         _REGISTER_CLOCK("mxs-perfmon.2", "perfmon", perfmon2_clk),
5086         _REGISTER_CLOCK(NULL, "mlb150_clk", mlb150_clk),
5087         _REGISTER_CLOCK(NULL, "anaclk_1", anaclk_1),
5088         _REGISTER_CLOCK(NULL, "anaclk_2", anaclk_2),
5089 };
5090
5091 static void clk_tree_init(void)
5092
5093 {
5094         unsigned int reg;
5095
5096         reg = __raw_readl(MMDC_MDMISC_OFFSET);
5097         if ((reg & MMDC_MDMISC_DDR_TYPE_MASK) ==
5098                 (0x1 << MMDC_MDMISC_DDR_TYPE_OFFSET) ||
5099                 cpu_is_mx6dl()) {
5100                 clk_set_parent(&periph_clk, &pll2_pfd_400M);
5101                 printk(KERN_INFO "Set periph_clk's parent to pll2_pfd_400M!\n");
5102         }
5103 }
5104
5105
5106 int __init mx6_clocks_init(unsigned long ckil, unsigned long osc,
5107         unsigned long ckih1, unsigned long ckih2)
5108 {
5109         __iomem void *base;
5110         int i;
5111
5112         external_low_reference = ckil;
5113         external_high_reference = ckih1;
5114         ckih2_reference = ckih2;
5115         oscillator_reference = osc;
5116
5117         apll_base = ioremap(ANATOP_BASE_ADDR, SZ_4K);
5118
5119         for (i = 0; i < ARRAY_SIZE(lookups); i++) {
5120                 clkdev_add(&lookups[i]);
5121                 clk_debug_register(lookups[i].clk);
5122         }
5123
5124         /* Disable un-necessary PFDs & PLLs */
5125
5126         /* keep correct count. */
5127         clk_enable(&cpu_clk);
5128         clk_enable(&periph_clk);
5129
5130         clk_tree_init();
5131
5132         if (pll2_pfd_400M.usecount == 0 && cpu_is_mx6q())
5133                 pll2_pfd_400M.disable(&pll2_pfd_400M);
5134         pll2_pfd_352M.disable(&pll2_pfd_352M);
5135         pll2_pfd_594M.disable(&pll2_pfd_594M);
5136
5137 #if !defined(CONFIG_FEC_1588)
5138         pll3_pfd_454M.disable(&pll3_pfd_454M);
5139         pll3_pfd_508M.disable(&pll3_pfd_508M);
5140         pll3_pfd_540M.disable(&pll3_pfd_540M);
5141         pll3_pfd_720M.disable(&pll3_pfd_720M);
5142
5143         pll3_usb_otg_main_clk.disable(&pll3_usb_otg_main_clk);
5144 #endif
5145         pll4_audio_main_clk.disable(&pll4_audio_main_clk);
5146         pll5_video_main_clk.disable(&pll5_video_main_clk);
5147         pll6_mlb150_main_clk.disable(&pll6_mlb150_main_clk);
5148         pll7_usb_host_main_clk.disable(&pll7_usb_host_main_clk);
5149         pll8_enet_main_clk.disable(&pll8_enet_main_clk);
5150
5151         sata_clk[0].disable(&sata_clk[0]);
5152         pcie_clk[0].disable(&pcie_clk[0]);
5153
5154         /* Initialize Audio and Video PLLs to valid frequency (650MHz). */
5155         clk_set_rate(&pll4_audio_main_clk, 650000000);
5156         clk_set_rate(&pll5_video_main_clk, 650000000);
5157
5158         clk_set_parent(&ipu1_di_clk[0], &pll5_video_main_clk);
5159         clk_set_parent(&ipu1_di_clk[1], &pll5_video_main_clk);
5160         clk_set_parent(&ipu2_di_clk[0], &pll5_video_main_clk);
5161         clk_set_parent(&ipu2_di_clk[1], &pll5_video_main_clk);
5162
5163         clk_set_parent(&emi_clk, &pll2_pfd_400M);
5164         clk_set_rate(&emi_clk, 200000000);
5165
5166         clk_set_parent(&gpu3d_shader_clk, &pll2_pfd_594M);
5167         clk_set_rate(&gpu3d_shader_clk, 594000000);
5168         clk_set_parent(&gpu3d_core_clk[0], &mmdc_ch0_axi_clk[0]);
5169         clk_set_rate(&gpu3d_core_clk[0], 528000000);
5170         if (cpu_is_mx6dl()) {
5171                 /*on mx6dl, 2d core clock sources from 3d shader core clock*/
5172                 clk_set_parent(&gpu2d_core_clk[0], &gpu3d_shader_clk);
5173                 /* on mx6dl gpu3d_axi_clk source from mmdc0 directly */
5174                 clk_set_parent(&gpu3d_axi_clk, &mmdc_ch0_axi_clk[0]);
5175                 /* on mx6dl gpu2d_axi_clk source from mmdc0 directly */
5176                 clk_set_parent(&gpu2d_axi_clk, &mmdc_ch0_axi_clk[0]);
5177                 gpu2d_axi_clk.secondary = NULL;
5178
5179                 /* set axi_clk parent to pll3_pfd_540M */
5180                 clk_set_parent(&axi_clk, &pll3_pfd_540M);
5181
5182                 /* on mx6dl, max ipu clock is 274M */
5183                 clk_set_parent(&ipu1_clk, &pll3_pfd_540M);
5184                 clk_set_parent(&ldb_di0_clk, &pll2_pfd_352M);
5185                 clk_set_parent(&ldb_di1_clk, &pll2_pfd_352M);
5186         }
5187         if (cpu_is_mx6q())
5188                 clk_set_parent(&gpu2d_core_clk[0], &pll3_usb_otg_main_clk);
5189
5190         /* PCLK camera - J5 */
5191         clk_set_parent(&clko2_clk, &osc_clk);
5192         clk_set_rate(&clko2_clk, 2400000);
5193
5194         clk_set_parent(&clko_clk, &ipg_clk);
5195         /*
5196          * FIXME: asrc needs to use asrc_serial(spdif1) clock to do sample
5197          * rate convertion and this clock frequency can not be too high, set
5198          * it to the minimum value 7.5Mhz to make asrc work properly.
5199          */
5200         clk_set_parent(&asrc_clk[1], &pll3_sw_clk);
5201         clk_set_rate(&asrc_clk[1], 7500000);
5202
5203         /* set the GPMI clock to default frequency : 20MHz */
5204         clk_set_rate(&enfc_clk, enfc_clk.round_rate(&enfc_clk, 20000000));
5205
5206         mx6_cpu_op_init();
5207         cpu_op_tbl = get_cpu_op(&cpu_op_nr);
5208
5209         /* Gate off all possible clocks */
5210         if (mxc_jtag_enabled) {
5211                 __raw_writel(3 << MXC_CCM_CCGRx_CG11_OFFSET |
5212                              3 << MXC_CCM_CCGRx_CG2_OFFSET |
5213                              3 << MXC_CCM_CCGRx_CG1_OFFSET |
5214                              3 << MXC_CCM_CCGRx_CG0_OFFSET, MXC_CCM_CCGR0);
5215         } else {
5216                 __raw_writel(1 << MXC_CCM_CCGRx_CG11_OFFSET |
5217                              3 << MXC_CCM_CCGRx_CG2_OFFSET |
5218                              3 << MXC_CCM_CCGRx_CG1_OFFSET |
5219                              3 << MXC_CCM_CCGRx_CG0_OFFSET, MXC_CCM_CCGR0);
5220         }
5221         __raw_writel(3 << MXC_CCM_CCGRx_CG10_OFFSET, MXC_CCM_CCGR1);
5222         __raw_writel(1 << MXC_CCM_CCGRx_CG12_OFFSET |
5223                      1 << MXC_CCM_CCGRx_CG11_OFFSET |
5224                      3 << MXC_CCM_CCGRx_CG10_OFFSET |
5225                      3 << MXC_CCM_CCGRx_CG9_OFFSET |
5226                      3 << MXC_CCM_CCGRx_CG8_OFFSET, MXC_CCM_CCGR2);
5227         __raw_writel(1 << MXC_CCM_CCGRx_CG14_OFFSET |
5228                      3 << MXC_CCM_CCGRx_CG13_OFFSET |
5229                      3 << MXC_CCM_CCGRx_CG12_OFFSET |
5230                      3 << MXC_CCM_CCGRx_CG11_OFFSET |
5231                      3 << MXC_CCM_CCGRx_CG10_OFFSET, MXC_CCM_CCGR3);
5232         __raw_writel(3 << MXC_CCM_CCGRx_CG7_OFFSET |
5233                         1 << MXC_CCM_CCGRx_CG6_OFFSET |
5234                         1 << MXC_CCM_CCGRx_CG4_OFFSET, MXC_CCM_CCGR4);
5235         __raw_writel(1 << MXC_CCM_CCGRx_CG0_OFFSET, MXC_CCM_CCGR5);
5236
5237         __raw_writel(0, MXC_CCM_CCGR6);
5238
5239         /* Lower the ipg_perclk frequency to 8.25MHz. */
5240         clk_set_rate(&ipg_perclk, 8250000);
5241
5242         /* S/PDIF */
5243         clk_set_parent(&spdif0_clk[0], &pll3_pfd_454M);
5244
5245         /* pxp & epdc */
5246         clk_set_parent(&ipu2_clk, &pll2_pfd_400M);
5247         clk_set_rate(&ipu2_clk, 200000000);
5248
5249         if (mx6q_revision() == IMX_CHIP_REVISION_1_0) {
5250                 gpt_clk[0].parent = &ipg_perclk;
5251                 gpt_clk[0].get_rate = NULL;
5252         } else {
5253                 /* Here we use OSC 24M as GPT's clock source, no need to
5254                 enable gpt serial clock*/
5255                 gpt_clk[0].secondary = NULL;
5256         }
5257
5258         if (cpu_is_mx6dl()) {
5259                 if (epdc_enabled)
5260                         clk_set_parent(&ipu2_di_clk[1], &pll5_video_main_clk);
5261                 else
5262                         clk_set_parent(&ipu2_di_clk[1], &pll3_pfd_540M);
5263         }
5264
5265         base = ioremap(GPT_BASE_ADDR, SZ_4K);
5266         mxc_timer_init(&gpt_clk[0], base, MXC_INT_GPT);
5267
5268         lp_high_freq = 0;
5269         lp_med_freq = 0;
5270
5271         return 0;
5272
5273 }