arch/arm/mach-mx6/clock.c

   1
   2 /*
   3  * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved.
   4  */
   5
   6 /*
   7  * The code contained herein is licensed under the GNU General Public
   8  * License. You may obtain a copy of the GNU General Public License
   9  * Version 2 or later at the following locations:
  10  *
  11  * http://www.opensource.org/licenses/gpl-license.html
  12  * http://www.gnu.org/copyleft/gpl.html
  13  */
  14
  15 #include <linux/kernel.h>
  16 #include <linux/init.h>
  17 #include <linux/types.h>
  18 #include <linux/time.h>
  19 #include <linux/hrtimer.h>
  20 #include <linux/mm.h>
  21 #include <linux/errno.h>
  22 #include <linux/delay.h>
  23 #include <linux/clk.h>
  24 #include <linux/io.h>
  25 #include <linux/clkdev.h>
  26 #include <linux/regulator/consumer.h>
  27 #include <asm/div64.h>
  28 #include <mach/hardware.h>
  29 #include <mach/common.h>
  30 #include <mach/clock.h>
  31 #include <mach/mxc_dvfs.h>
  32 #include "crm_regs.h"
  33 #include "cpu_op-mx6.h"
  34 #include "regs-anadig.h"
  35
  36 #ifdef CONFIG_CLK_DEBUG
  37 #define __INIT_CLK_DEBUG(n)     .name = #n,
  38 #else
  39 #define __INIT_CLK_DEBUG(n)
  40 #endif
  41
  42 extern u32 arm_max_freq;
  43 extern int mxc_jtag_enabled;
  44 extern struct regulator *cpu_regulator;
  45 extern struct cpu_op *(*get_cpu_op)(int *op);
  46 extern int lp_high_freq;
  47 extern int lp_med_freq;
  48 extern int mx6q_revision(void);
  49
  50 void __iomem *apll_base;
  51 static struct clk pll1_sys_main_clk;
  52 static struct clk pll2_528_bus_main_clk;
  53 static struct clk pll2_pfd_400M;
  54 static struct clk pll3_usb_otg_main_clk;
  55 static struct clk pll4_audio_main_clk;
  56 static struct clk pll5_video_main_clk;
  57 static struct clk pll6_mlb150_main_clk;
  58 static struct clk pll7_usb_host_main_clk;
  59 static struct clk pll8_enet_main_clk;
  60 static struct clk apbh_dma_clk;
  61 static struct clk openvg_axi_clk;
  62 static struct clk enfc_clk;
  63 static struct clk ipu1_di_clk_root;
  64 static struct clk ipu2_di_clk_root;
  65 static struct clk usdhc3_clk;
  66
  67 static struct cpu_op *cpu_op_tbl;
  68 static int cpu_op_nr;
  69
  70 #define SPIN_DELAY      1200000 /* in nanoseconds */
  71
  72 #define AUDIO_VIDEO_MIN_CLK_FREQ        650000000
  73 #define AUDIO_VIDEO_MAX_CLK_FREQ        1300000000
  74
  75 /* We need to check the exp status again after timer expiration,
  76  * as there might be interrupt coming between the first time exp
  77  * and the time reading, then the time reading may be several ms
  78  * after the exp checking due to the irq handle, so we need to
  79  * check it to make sure the exp return the right value after
  80  * timer expiration. */
  81 #define WAIT(exp, timeout) \
  82 ({ \
  83         struct timespec nstimeofday; \
  84         struct timespec curtime; \
  85         int result = 1; \
  86         getnstimeofday(&nstimeofday); \
  87         while (!(exp)) { \
  88                 getnstimeofday(&curtime); \
  89                 if ((curtime.tv_nsec - nstimeofday.tv_nsec) > (timeout)) { \
  90                         if (!(exp)) \
  91                                 result = 0; \
  92                         break; \
  93                 } \
  94         } \
  95         result; \
  96 })
  97
  98 /* External clock values passed-in by the board code */
  99 static unsigned long external_high_reference, external_low_reference;
 100 static unsigned long oscillator_reference, ckih2_reference;
 101
 102 /* For MX 6DL/S, Video PLL may be used by synchronous display devices,
 103  * such as HDMI or LVDS, and also by the EPDC.  If EPDC is in use,
 104  * it must use the Video PLL to achieve the clock frequencies it needs.
 105  * So if EPDC is in use, the "epdc" string should be added to kernel
 106  * parameters, in order to set the EPDC parent clock to the Video PLL.
 107  * This will have an impact on the behavior of HDMI and LVDS.
 108  */
 109 static int epdc_use_video_pll;
 110 static int __init epdc_clk_setup(char *__unused)
 111 {
 112         epdc_use_video_pll = 1;
 113         return 1;
 114 }
 115 __setup("epdc", epdc_clk_setup);
 116
 117 static void __calc_pre_post_dividers(u32 max_podf, u32 div, u32 *pre, u32 *post)
 118 {
 119         u32 min_pre, temp_pre, old_err, err;
 120
 121         /* Some of the podfs are 3 bits while others are 6 bits.
 122           * Handle both cases here.
 123           */
 124         if (div >= 512 && (max_podf == 64)) {
 125                 /* For pre = 3bits and podf = 6 bits, max divider is 512. */
 126                 *pre = 8;
 127                 *post = 64;
 128         } else if (div >= 64 && (max_podf == 8)) {
 129                 /* For pre = 3bits and podf = 3 bits, max divider is 64. */
 130                 *pre = 8;
 131                 *post = 8;
 132         } else if (div >= 8) {
 133                 /* Find the minimum pre-divider for a max podf */
 134                 if (max_podf == 64)
 135                         min_pre = (div - 1) / (1 << 6) + 1;
 136                 else
 137                         min_pre = (div - 1) / (1 << 3) + 1;
 138                 old_err = 8;
 139                 /* Now loop through to find the max pre-divider. */
 140                 for (temp_pre = 8; temp_pre >= min_pre; temp_pre--) {
 141                         err = div % temp_pre;
 142                         if (err == 0) {
 143                                 *pre = temp_pre;
 144                                 break;
 145                         }
 146                         err = temp_pre - err;
 147                         if (err < old_err) {
 148                                 old_err = err;
 149                                 *pre = temp_pre;
 150                         }
 151                 }
 152                 *post = (div + *pre - 1) / *pre;
 153         } else if (div < 8) {
 154                 *pre = div;
 155                 *post = 1;
 156         }
 157 }
 158
 159 static int _clk_enable(struct clk *clk)
 160 {
 161         u32 reg;
 162         reg = __raw_readl(clk->enable_reg);
 163         reg |= MXC_CCM_CCGRx_CG_MASK << clk->enable_shift;
 164         __raw_writel(reg, clk->enable_reg);
 165
 166         if (clk->flags & AHB_HIGH_SET_POINT)
 167                 lp_high_freq++;
 168         else if (clk->flags & AHB_MED_SET_POINT)
 169                 lp_med_freq++;
 170
 171         return 0;
 172 }
 173
 174 static void _clk_disable(struct clk *clk)
 175 {
 176         u32 reg;
 177         reg = __raw_readl(clk->enable_reg);
 178         reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift);
 179         __raw_writel(reg, clk->enable_reg);
 180
 181         if (clk->flags & AHB_HIGH_SET_POINT)
 182                 lp_high_freq--;
 183         else if (clk->flags & AHB_MED_SET_POINT)
 184                 lp_med_freq--;
 185 }
 186
 187 static void _clk_disable_inwait(struct clk *clk)
 188 {
 189         u32 reg;
 190         reg = __raw_readl(clk->enable_reg);
 191         reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift);
 192         reg |= 1 << clk->enable_shift;
 193         __raw_writel(reg, clk->enable_reg);
 194 }
 195
 196 /*
 197  * For the 4-to-1 muxed input clock
 198  */
 199 static inline u32 _get_mux(struct clk *parent, struct clk *m0,
 200                            struct clk *m1, struct clk *m2, struct clk *m3)
 201 {
 202         if (parent == m0)
 203                 return 0;
 204         else if (parent == m1)
 205                 return 1;
 206         else if (parent == m2)
 207                 return 2;
 208         else if (parent == m3)
 209                 return 3;
 210         else
 211                 BUG();
 212
 213         return 0;
 214 }
 215
 216 static inline void __iomem *_get_pll_base(struct clk *pll)
 217 {
 218         if (pll == &pll1_sys_main_clk)
 219                 return PLL1_SYS_BASE_ADDR;
 220         else if (pll == &pll2_528_bus_main_clk)
 221                 return PLL2_528_BASE_ADDR;
 222         else if (pll == &pll3_usb_otg_main_clk)
 223                 return PLL3_480_USB1_BASE_ADDR;
 224         else if (pll == &pll4_audio_main_clk)
 225                 return PLL4_AUDIO_BASE_ADDR;
 226         else if (pll == &pll5_video_main_clk)
 227                 return PLL5_VIDEO_BASE_ADDR;
 228         else if (pll == &pll6_mlb150_main_clk)
 229                 return PLL6_MLB_BASE_ADDR;
 230         else if (pll == &pll7_usb_host_main_clk)
 231                 return PLL7_480_USB2_BASE_ADDR;
 232         else if (pll == &pll8_enet_main_clk)
 233                 return PLL8_ENET_BASE_ADDR;
 234         else
 235                 BUG();
 236         return NULL;
 237 }
 238
 239
 240 /*
 241  * For the 6-to-1 muxed input clock
 242  */
 243 static inline u32 _get_mux6(struct clk *parent, struct clk *m0, struct clk *m1,
 244                             struct clk *m2, struct clk *m3, struct clk *m4,
 245                             struct clk *m5)
 246 {
 247         if (parent == m0)
 248                 return 0;
 249         else if (parent == m1)
 250                 return 1;
 251         else if (parent == m2)
 252                 return 2;
 253         else if (parent == m3)
 254                 return 3;
 255         else if (parent == m4)
 256                 return 4;
 257         else if (parent == m5)
 258                 return 5;
 259         else
 260                 BUG();
 261
 262         return 0;
 263 }
 264 static unsigned long get_high_reference_clock_rate(struct clk *clk)
 265 {
 266         return external_high_reference;
 267 }
 268
 269 static unsigned long get_low_reference_clock_rate(struct clk *clk)
 270 {
 271         return external_low_reference;
 272 }
 273
 274 static unsigned long get_oscillator_reference_clock_rate(struct clk *clk)
 275 {
 276         return oscillator_reference;
 277 }
 278
 279 static unsigned long get_ckih2_reference_clock_rate(struct clk *clk)
 280 {
 281         return ckih2_reference;
 282 }
 283
 284 /* External high frequency clock */
 285 static struct clk ckih_clk = {
 286         __INIT_CLK_DEBUG(ckih_clk)
 287         .get_rate = get_high_reference_clock_rate,
 288 };
 289
 290 static struct clk ckih2_clk = {
 291         __INIT_CLK_DEBUG(ckih2_clk)
 292         .get_rate = get_ckih2_reference_clock_rate,
 293 };
 294
 295 static struct clk osc_clk = {
 296         __INIT_CLK_DEBUG(osc_clk)
 297         .get_rate = get_oscillator_reference_clock_rate,
 298 };
 299
 300 /* External low frequency (32kHz) clock */
 301 static struct clk ckil_clk = {
 302         __INIT_CLK_DEBUG(ckil_clk)
 303         .get_rate = get_low_reference_clock_rate,
 304 };
 305
 306 static unsigned long pfd_round_rate(struct clk *clk, unsigned long rate)
 307 {
 308         u32 frac;
 309         u64 tmp;
 310
 311         tmp = (u64)clk_get_rate(clk->parent) * 18;
 312         tmp += rate/2;
 313         do_div(tmp, rate);
 314         frac = tmp;
 315         frac = frac < 12 ? 12 : frac;
 316         frac = frac > 35 ? 35 : frac;
 317         tmp = (u64)clk_get_rate(clk->parent) * 18;
 318         do_div(tmp, frac);
 319         return tmp;
 320 }
 321
 322 static unsigned long pfd_get_rate(struct clk *clk)
 323 {
 324         u32 frac;
 325         u64 tmp;
 326         tmp = (u64)clk_get_rate(clk->parent) * 18;
 327
 328         if (apbh_dma_clk.usecount == 0)
 329                 apbh_dma_clk.enable(&apbh_dma_clk);
 330
 331         frac = (__raw_readl(clk->enable_reg) >> clk->enable_shift) &
 332                         ANADIG_PFD_FRAC_MASK;
 333
 334         do_div(tmp, frac);
 335
 336         return tmp;
 337 }
 338
 339 static int pfd_set_rate(struct clk *clk, unsigned long rate)
 340 {
 341         u32 frac;
 342         u64 tmp;
 343         tmp = (u64)clk_get_rate(clk->parent) * 18;
 344
 345         if (apbh_dma_clk.usecount == 0)
 346                 apbh_dma_clk.enable(&apbh_dma_clk);
 347
 348         /* Round up the divider so that we don't set a rate
 349           * higher than what is requested. */
 350         tmp += rate/2;
 351         do_div(tmp, rate);
 352         frac = tmp;
 353         frac = frac < 12 ? 12 : frac;
 354         frac = frac > 35 ? 35 : frac;
 355         /* clear clk frac bits */
 356         __raw_writel(ANADIG_PFD_FRAC_MASK << clk->enable_shift,
 357                         (int)clk->enable_reg + 8);
 358         /* set clk frac bits */
 359         __raw_writel(frac << clk->enable_shift,
 360                         (int)clk->enable_reg + 4);
 361
 362         if (apbh_dma_clk.usecount == 0)
 363                 apbh_dma_clk.disable(&apbh_dma_clk);
 364         return 0;
 365 }
 366
 367 static int _clk_pfd_enable(struct clk *clk)
 368 {
 369         if (apbh_dma_clk.usecount == 0)
 370                 apbh_dma_clk.enable(&apbh_dma_clk);
 371
 372         /* clear clk gate bit */
 373         __raw_writel((1 << (clk->enable_shift + 7)),
 374                         (int)clk->enable_reg + 8);
 375
 376         if (apbh_dma_clk.usecount == 0)
 377                 apbh_dma_clk.disable(&apbh_dma_clk);
 378
 379         return 0;
 380 }
 381
 382 static void _clk_pfd_disable(struct clk *clk)
 383 {
 384         if (apbh_dma_clk.usecount == 0)
 385                 apbh_dma_clk.enable(&apbh_dma_clk);
 386
 387         /* set clk gate bit */
 388         __raw_writel((1 << (clk->enable_shift + 7)),
 389                         (int)clk->enable_reg + 4);
 390
 391         if (apbh_dma_clk.usecount == 0)
 392                 apbh_dma_clk.disable(&apbh_dma_clk);
 393 }
 394
 395 static int _clk_pll_enable(struct clk *clk)
 396 {
 397         unsigned int reg;
 398         void __iomem *pllbase;
 399
 400         pllbase = _get_pll_base(clk);
 401
 402         reg = __raw_readl(pllbase);
 403         reg &= ~ANADIG_PLL_BYPASS;
 404         reg &= ~ANADIG_PLL_POWER_DOWN;
 405
 406         /* The 480MHz PLLs have the opposite definition for power bit. */
 407         if (clk == &pll3_usb_otg_main_clk || clk == &pll7_usb_host_main_clk)
 408                 reg |= ANADIG_PLL_POWER_DOWN;
 409
 410         __raw_writel(reg, pllbase);
 411
 412         /* It will power on pll3 */
 413         if (clk == &pll3_usb_otg_main_clk)
 414                 __raw_writel(BM_ANADIG_ANA_MISC2_CONTROL0, apll_base + HW_ANADIG_ANA_MISC2_CLR);
 415
 416         /* Wait for PLL to lock */
 417         if (!WAIT(__raw_readl(pllbase) & ANADIG_PLL_LOCK,
 418                                 SPIN_DELAY))
 419                 panic("pll enable failed\n");
 420
 421         /* Enable the PLL output now*/
 422         reg = __raw_readl(pllbase);
 423         reg |= ANADIG_PLL_ENABLE;
 424         __raw_writel(reg, pllbase);
 425
 426         return 0;
 427 }
 428
 429 static void _clk_pll_disable(struct clk *clk)
 430 {
 431         unsigned int reg;
 432         void __iomem *pllbase;
 433
 434         pllbase = _get_pll_base(clk);
 435
 436         reg = __raw_readl(pllbase);
 437         reg |= ANADIG_PLL_BYPASS;
 438         reg &= ~ANADIG_PLL_ENABLE;
 439
 440         __raw_writel(reg, pllbase);
 441
 442         /*
 443          * It will power off PLL3's power, it is the TO1.1 fix
 444          * Please see TKT064178 for detail.
 445          */
 446         if (clk == &pll3_usb_otg_main_clk)
 447                 __raw_writel(BM_ANADIG_ANA_MISC2_CONTROL0, apll_base + HW_ANADIG_ANA_MISC2_SET);
 448 }
 449
 450 static unsigned long  _clk_pll1_main_get_rate(struct clk *clk)
 451 {
 452         unsigned int div;
 453         unsigned long val;
 454
 455         div = __raw_readl(PLL1_SYS_BASE_ADDR) & ANADIG_PLL_SYS_DIV_SELECT_MASK;
 456         val = (clk_get_rate(clk->parent) * div) / 2;
 457         return val;
 458 }
 459
 460 static int _clk_pll1_main_set_rate(struct clk *clk, unsigned long rate)
 461 {
 462         unsigned int reg,  div;
 463
 464         if (rate < AUDIO_VIDEO_MIN_CLK_FREQ || rate > AUDIO_VIDEO_MAX_CLK_FREQ)
 465                 return -EINVAL;
 466
 467         div = (rate * 2) / clk_get_rate(clk->parent) ;
 468
 469         reg = __raw_readl(PLL1_SYS_BASE_ADDR) & ~ANADIG_PLL_SYS_DIV_SELECT_MASK;
 470         reg |= div;
 471         __raw_writel(reg, PLL1_SYS_BASE_ADDR);
 472
 473         return 0;
 474 }
 475
 476 static struct clk pll1_sys_main_clk = {
 477         __INIT_CLK_DEBUG(pll1_sys_main_clk)
 478         .parent = &osc_clk,
 479         .get_rate = _clk_pll1_main_get_rate,
 480         .set_rate = _clk_pll1_main_set_rate,
 481         .enable = _clk_pll_enable,
 482         .disable = _clk_pll_disable,
 483 };
 484
 485 static int _clk_pll1_sw_set_parent(struct clk *clk, struct clk *parent)
 486 {
 487         u32 reg;
 488
 489         reg = __raw_readl(MXC_CCM_CCSR);
 490
 491         if (parent == &pll1_sys_main_clk) {
 492                 reg &= ~MXC_CCM_CCSR_PLL1_SW_CLK_SEL;
 493                 __raw_writel(reg, MXC_CCM_CCSR);
 494                 /* Set the step_clk parent to be lp_apm, to save power. */
 495                 reg = __raw_readl(MXC_CCM_CCSR);
 496                 reg = (reg & ~MXC_CCM_CCSR_STEP_SEL);
 497         } else {
 498                 /* Set STEP_CLK to be the parent*/
 499                 if (parent == &osc_clk) {
 500                         /* Set STEP_CLK to be sourced from LPAPM. */
 501                         reg = __raw_readl(MXC_CCM_CCSR);
 502                         reg = (reg & ~MXC_CCM_CCSR_STEP_SEL);
 503                         __raw_writel(reg, MXC_CCM_CCSR);
 504                 } else {
 505                         /* Set STEP_CLK to be sourced from PLL2-PDF (400MHz). */
 506                         reg = __raw_readl(MXC_CCM_CCSR);
 507                         reg |= MXC_CCM_CCSR_STEP_SEL;
 508                         __raw_writel(reg, MXC_CCM_CCSR);
 509
 510                 }
 511                 reg = __raw_readl(MXC_CCM_CCSR);
 512                 reg |= MXC_CCM_CCSR_PLL1_SW_CLK_SEL;
 513         }
 514         __raw_writel(reg, MXC_CCM_CCSR);
 515         return 0;
 516 }
 517
 518 static unsigned long _clk_pll1_sw_get_rate(struct clk *clk)
 519 {
 520         return clk_get_rate(clk->parent);
 521 }
 522
 523 static struct clk pll1_sw_clk = {
 524         __INIT_CLK_DEBUG(pll1_sw_clk)
 525         .parent = &pll1_sys_main_clk,
 526         .set_parent = _clk_pll1_sw_set_parent,
 527         .get_rate = _clk_pll1_sw_get_rate,
 528 };
 529
 530 static unsigned long _clk_pll2_main_get_rate(struct clk *clk)
 531 {
 532         unsigned int div;
 533         unsigned long val;
 534
 535         div = __raw_readl(PLL2_528_BASE_ADDR) & ANADIG_PLL_528_DIV_SELECT;
 536
 537         if (div == 1)
 538                 val = clk_get_rate(clk->parent) * 22;
 539
 540         else
 541                 val = clk_get_rate(clk->parent) * 20;
 542
 543         return val;
 544 }
 545
 546 static int _clk_pll2_main_set_rate(struct clk *clk, unsigned long rate)
 547 {
 548         unsigned int reg,  div;
 549
 550         if (rate == 528000000)
 551                 div = 1;
 552         else if (rate == 480000000)
 553                 div = 0;
 554         else
 555                 return -EINVAL;
 556
 557         reg = __raw_readl(PLL2_528_BASE_ADDR);
 558         reg &= ~ANADIG_PLL_528_DIV_SELECT;
 559         reg |= div;
 560         __raw_writel(reg, PLL2_528_BASE_ADDR);
 561
 562         return 0;
 563 }
 564
 565 static struct clk pll2_528_bus_main_clk = {
 566         __INIT_CLK_DEBUG(pll2_528_bus_main_clk)
 567         .parent = &osc_clk,
 568         .get_rate = _clk_pll2_main_get_rate,
 569         .set_rate = _clk_pll2_main_set_rate,
 570         .enable = _clk_pll_enable,
 571         .disable = _clk_pll_disable,
 572 };
 573
 574 static struct clk pll2_pfd_400M = {
 575         __INIT_CLK_DEBUG(pll2_pfd_400M)
 576         .parent = &pll2_528_bus_main_clk,
 577         .enable_reg = (void *)PFD_528_BASE_ADDR,
 578         .enable_shift = ANADIG_PFD2_FRAC_OFFSET,
 579         .enable = _clk_pfd_enable,
 580         .disable = _clk_pfd_disable,
 581         .get_rate = pfd_get_rate,
 582         .set_rate = pfd_set_rate,
 583         .get_rate = pfd_get_rate,
 584         .round_rate = pfd_round_rate,
 585 };
 586
 587 static struct clk pll2_pfd_352M = {
 588         __INIT_CLK_DEBUG(pll2_pfd_352M)
 589         .parent = &pll2_528_bus_main_clk,
 590         .enable_reg = (void *)PFD_528_BASE_ADDR,
 591         .enable_shift = ANADIG_PFD0_FRAC_OFFSET,
 592         .enable = _clk_pfd_enable,
 593         .disable = _clk_pfd_disable,
 594         .set_rate = pfd_set_rate,
 595         .get_rate = pfd_get_rate,
 596         .round_rate = pfd_round_rate,
 597 };
 598
 599 static struct clk pll2_pfd_594M = {
 600         __INIT_CLK_DEBUG(pll2_pfd_594M)
 601         .parent = &pll2_528_bus_main_clk,
 602         .enable_reg = (void *)PFD_528_BASE_ADDR,
 603         .enable_shift = ANADIG_PFD1_FRAC_OFFSET,
 604         .enable = _clk_pfd_enable,
 605         .disable = _clk_pfd_disable,
 606         .set_rate = pfd_set_rate,
 607         .get_rate = pfd_get_rate,
 608         .round_rate = pfd_round_rate,
 609 };
 610
 611 static unsigned long _clk_pll2_200M_get_rate(struct clk *clk)
 612 {
 613         return clk_get_rate(clk->parent) / 2;
 614 }
 615
 616 static struct clk pll2_200M = {
 617         __INIT_CLK_DEBUG(pll2_200M)
 618         .parent = &pll2_pfd_400M,
 619         .get_rate = _clk_pll2_200M_get_rate,
 620 };
 621
 622 static unsigned long _clk_pll3_usb_otg_get_rate(struct clk *clk)
 623 {
 624         unsigned int div;
 625         unsigned long val;
 626
 627         div = __raw_readl(PLL3_480_USB1_BASE_ADDR)
 628                 & ANADIG_PLL_480_DIV_SELECT_MASK;
 629
 630         if (div == 1)
 631                 val = clk_get_rate(clk->parent) * 22;
 632         else
 633                 val = clk_get_rate(clk->parent) * 20;
 634         return val;
 635 }
 636
 637 static int _clk_pll3_usb_otg_set_rate(struct clk *clk, unsigned long rate)
 638 {
 639         unsigned int reg,  div;
 640
 641         if (rate == 528000000)
 642                 div = 1;
 643         else if (rate == 480000000)
 644                 div = 0;
 645         else
 646                 return -EINVAL;
 647
 648         reg = __raw_readl(PLL3_480_USB1_BASE_ADDR);
 649         reg &= ~ANADIG_PLL_480_DIV_SELECT_MASK;
 650         reg |= div;
 651         __raw_writel(reg, PLL3_480_USB1_BASE_ADDR);
 652
 653         return 0;
 654 }
 655
 656
 657 /* same as pll3_main_clk. These two clocks should always be the same */
 658 static struct clk pll3_usb_otg_main_clk = {
 659         __INIT_CLK_DEBUG(pll3_usb_otg_main_clk)
 660         .parent = &osc_clk,
 661         .enable = _clk_pll_enable,
 662         .disable = _clk_pll_disable,
 663         .set_rate = _clk_pll3_usb_otg_set_rate,
 664         .get_rate = _clk_pll3_usb_otg_get_rate,
 665 };
 666
 667 /* for USB OTG */
 668 static struct clk usb_phy1_clk = {
 669         __INIT_CLK_DEBUG(usb_phy1_clk)
 670         .parent = &pll3_usb_otg_main_clk,
 671         .set_rate = _clk_pll3_usb_otg_set_rate,
 672         .get_rate = _clk_pll3_usb_otg_get_rate,
 673 };
 674
 675 /* For HSIC port 1 */
 676 static struct clk usb_phy3_clk = {
 677         __INIT_CLK_DEBUG(usb_phy3_clk)
 678         .parent = &pll3_usb_otg_main_clk,
 679         .set_rate = _clk_pll3_usb_otg_set_rate,
 680         .get_rate = _clk_pll3_usb_otg_get_rate,
 681 };
 682
 683 /* For HSIC port 2 */
 684 static struct clk usb_phy4_clk = {
 685         __INIT_CLK_DEBUG(usb_phy4_clk)
 686         .parent = &pll3_usb_otg_main_clk,
 687         .set_rate = _clk_pll3_usb_otg_set_rate,
 688         .get_rate = _clk_pll3_usb_otg_get_rate,
 689 };
 690
 691 static struct clk pll3_pfd_508M = {
 692         __INIT_CLK_DEBUG(pll3_pfd_508M)
 693         .parent = &pll3_usb_otg_main_clk,
 694         .enable_reg = (void *)PFD_480_BASE_ADDR,
 695         .enable_shift = ANADIG_PFD2_FRAC_OFFSET,
 696         .enable = _clk_pfd_enable,
 697         .disable = _clk_pfd_disable,
 698         .set_rate = pfd_set_rate,
 699         .get_rate = pfd_get_rate,
 700         .round_rate = pfd_round_rate,
 701 };
 702
 703 static struct clk pll3_pfd_454M = {
 704         __INIT_CLK_DEBUG(pll3_pfd_454M)
 705         .parent = &pll3_usb_otg_main_clk,
 706         .enable_reg = (void *)PFD_480_BASE_ADDR,
 707         .enable_shift = ANADIG_PFD3_FRAC_OFFSET,
 708         .enable = _clk_pfd_enable,
 709         .disable = _clk_pfd_disable,
 710         .set_rate = pfd_set_rate,
 711         .get_rate = pfd_get_rate,
 712         .round_rate = pfd_round_rate,
 713 };
 714
 715 static struct clk pll3_pfd_720M = {
 716         __INIT_CLK_DEBUG(pll3_pfd_720M)
 717         .parent = &pll3_usb_otg_main_clk,
 718         .enable_reg = (void *)PFD_480_BASE_ADDR,
 719         .enable_shift = ANADIG_PFD0_FRAC_OFFSET,
 720         .enable = _clk_pfd_enable,
 721         .disable = _clk_pfd_disable,
 722         .set_rate = pfd_set_rate,
 723         .get_rate = pfd_get_rate,
 724         .round_rate = pfd_round_rate,
 725 };
 726
 727 static struct clk pll3_pfd_540M = {
 728         __INIT_CLK_DEBUG(pll3_pfd_540M)
 729         .parent = &pll3_usb_otg_main_clk,
 730         .enable_reg = (void *)PFD_480_BASE_ADDR,
 731         .enable_shift = ANADIG_PFD1_FRAC_OFFSET,
 732         .enable = _clk_pfd_enable,
 733         .disable = _clk_pfd_disable,
 734         .set_rate = pfd_set_rate,
 735         .get_rate = pfd_get_rate,
 736         .round_rate = pfd_round_rate,
 737         .get_rate = pfd_get_rate,
 738 };
 739
 740 static unsigned long _clk_pll3_sw_get_rate(struct clk *clk)
 741 {
 742         return clk_get_rate(clk->parent);
 743 }
 744
 745 /* same as pll3_main_clk. These two clocks should always be the same */
 746 static struct clk pll3_sw_clk = {
 747         __INIT_CLK_DEBUG(pll3_sw_clk)
 748         .parent = &pll3_usb_otg_main_clk,
 749         .get_rate = _clk_pll3_sw_get_rate,
 750 };
 751
 752 static unsigned long _clk_pll3_120M_get_rate(struct clk *clk)
 753 {
 754         return clk_get_rate(clk->parent) / 4;
 755 }
 756
 757 static struct clk pll3_120M = {
 758         __INIT_CLK_DEBUG(pll3_120M)
 759         .parent = &pll3_sw_clk,
 760         .get_rate = _clk_pll3_120M_get_rate,
 761 };
 762
 763 static unsigned long _clk_pll3_80M_get_rate(struct clk *clk)
 764 {
 765         return clk_get_rate(clk->parent) / 6;
 766 }
 767
 768 static struct clk pll3_80M = {
 769         __INIT_CLK_DEBUG(pll3_80M)
 770         .parent = &pll3_sw_clk,
 771         .get_rate = _clk_pll3_80M_get_rate,
 772 };
 773
 774 static unsigned long _clk_pll3_60M_get_rate(struct clk *clk)
 775 {
 776         return clk_get_rate(clk->parent) / 8;
 777 }
 778
 779 static struct clk pll3_60M = {
 780         __INIT_CLK_DEBUG(pll3_60M)
 781         .parent = &pll3_sw_clk,
 782         .get_rate = _clk_pll3_60M_get_rate,
 783 };
 784
 785 static unsigned long  _clk_audio_video_get_rate(struct clk *clk)
 786 {
 787         unsigned int div, mfn, mfd;
 788         unsigned long rate;
 789         unsigned int parent_rate = clk_get_rate(clk->parent);
 790         void __iomem *pllbase;
 791         int rev = mx6q_revision();
 792         unsigned int test_div_sel, control3, post_div = 1;
 793
 794         if (clk == &pll4_audio_main_clk)
 795                 pllbase = PLL4_AUDIO_BASE_ADDR;
 796         else
 797                 pllbase = PLL5_VIDEO_BASE_ADDR;
 798
 799         if ((rev >= IMX_CHIP_REVISION_1_1) || cpu_is_mx6dl()) {
 800                 test_div_sel = (__raw_readl(pllbase)
 801                         & ANADIG_PLL_AV_TEST_DIV_SEL_MASK)
 802                         >> ANADIG_PLL_AV_TEST_DIV_SEL_OFFSET;
 803                 if (test_div_sel == 0)
 804                         post_div = 4;
 805                 else if (test_div_sel == 1)
 806                         post_div = 2;
 807
 808                 if (clk == &pll5_video_main_clk) {
 809                         control3 = (__raw_readl(ANA_MISC2_BASE_ADDR)
 810                                 & ANADIG_ANA_MISC2_CONTROL3_MASK)
 811                                 >> ANADIG_ANA_MISC2_CONTROL3_OFFSET;
 812                         if (control3 == 1)
 813                                 post_div *= 2;
 814                         else if (control3 == 3)
 815                                 post_div *= 4;
 816                 }
 817         }
 818
 819         div = __raw_readl(pllbase) & ANADIG_PLL_SYS_DIV_SELECT_MASK;
 820         mfn = __raw_readl(pllbase + PLL_NUM_DIV_OFFSET);
 821         mfd = __raw_readl(pllbase + PLL_DENOM_DIV_OFFSET);
 822
 823         rate = (parent_rate * div) + ((parent_rate / mfd) * mfn);
 824         rate = rate / post_div;
 825
 826         return rate;
 827 }
 828
 829 static int _clk_audio_video_set_rate(struct clk *clk, unsigned long rate)
 830 {
 831         unsigned int reg,  div;
 832         unsigned int mfn, mfd = 1000000;
 833         s64 temp64;
 834         unsigned int parent_rate = clk_get_rate(clk->parent);
 835         void __iomem *pllbase;
 836         unsigned long min_clk_rate, pre_div_rate;
 837         int rev = mx6q_revision();
 838         u32 test_div_sel = 2;
 839         u32 control3 = 0;
 840
 841         if ((rev < IMX_CHIP_REVISION_1_1) && !cpu_is_mx6dl())
 842                 min_clk_rate = AUDIO_VIDEO_MIN_CLK_FREQ;
 843         else if (clk == &pll4_audio_main_clk)
 844                 min_clk_rate = AUDIO_VIDEO_MIN_CLK_FREQ / 4;
 845         else
 846                 min_clk_rate = AUDIO_VIDEO_MIN_CLK_FREQ / 16;
 847
 848         if ((rate < min_clk_rate) || (rate > AUDIO_VIDEO_MAX_CLK_FREQ))
 849                 return -EINVAL;
 850
 851         if (clk == &pll4_audio_main_clk)
 852                 pllbase = PLL4_AUDIO_BASE_ADDR;
 853         else
 854                 pllbase = PLL5_VIDEO_BASE_ADDR;
 855
 856         pre_div_rate = rate;
 857         if ((rev >= IMX_CHIP_REVISION_1_1) || cpu_is_mx6dl()) {
 858                 while (pre_div_rate < AUDIO_VIDEO_MIN_CLK_FREQ) {
 859                         pre_div_rate *= 2;
 860                         /*
 861                          * test_div_sel field values:
 862                          * 2 -> Divide by 1
 863                          * 1 -> Divide by 2
 864                          * 0 -> Divide by 4
 865                          *
 866                          * control3 field values:
 867                          * 0 -> Divide by 1
 868                          * 1 -> Divide by 2
 869                          * 3 -> Divide by 4
 870                          */
 871                         if (test_div_sel != 0)
 872                                 test_div_sel--;
 873                         else {
 874                                 control3++;
 875                                 if (control3 == 2)
 876                                         control3++;
 877                         }
 878                 }
 879         }
 880
 881         div = pre_div_rate / parent_rate;
 882         temp64 = (u64) (pre_div_rate - (div * parent_rate));
 883         temp64 *= mfd;
 884         do_div(temp64, parent_rate);
 885         mfn = temp64;
 886
 887         reg = __raw_readl(pllbase)
 888                         & ~ANADIG_PLL_SYS_DIV_SELECT_MASK
 889                         & ~ANADIG_PLL_AV_TEST_DIV_SEL_MASK;
 890         reg |= div |
 891                 (test_div_sel << ANADIG_PLL_AV_TEST_DIV_SEL_OFFSET);
 892         __raw_writel(reg, pllbase);
 893         __raw_writel(mfn, pllbase + PLL_NUM_DIV_OFFSET);
 894         __raw_writel(mfd, pllbase + PLL_DENOM_DIV_OFFSET);
 895
 896         if (rev >= IMX_CHIP_REVISION_1_1) {
 897                 reg = __raw_readl(ANA_MISC2_BASE_ADDR)
 898                         & ~ANADIG_ANA_MISC2_CONTROL3_MASK;
 899                 reg |= control3 << ANADIG_ANA_MISC2_CONTROL3_OFFSET;
 900                 __raw_writel(reg, ANA_MISC2_BASE_ADDR);
 901         }
 902
 903         return 0;
 904 }
 905
 906 static unsigned long _clk_audio_video_round_rate(struct clk *clk,
 907                                                 unsigned long rate)
 908 {
 909         unsigned long min_clk_rate;
 910         unsigned int div, post_div = 1;
 911         unsigned int mfn, mfd = 1000000;
 912         s64 temp64;
 913         unsigned int parent_rate = clk_get_rate(clk->parent);
 914         unsigned long pre_div_rate;
 915         u32 test_div_sel = 2;
 916         u32 control3 = 0;
 917         unsigned long final_rate;
 918         int rev = mx6q_revision();
 919
 920         if ((rev < IMX_CHIP_REVISION_1_1) && !cpu_is_mx6dl())
 921                 min_clk_rate = AUDIO_VIDEO_MIN_CLK_FREQ;
 922         else if (clk == &pll4_audio_main_clk)
 923                 min_clk_rate = AUDIO_VIDEO_MIN_CLK_FREQ / 4;
 924         else
 925                 min_clk_rate = AUDIO_VIDEO_MIN_CLK_FREQ / 16;
 926
 927         if (rate < min_clk_rate)
 928                 return min_clk_rate;
 929
 930         if (rate > AUDIO_VIDEO_MAX_CLK_FREQ)
 931                 return AUDIO_VIDEO_MAX_CLK_FREQ;
 932
 933         pre_div_rate = rate;
 934         if ((rev >= IMX_CHIP_REVISION_1_1) || cpu_is_mx6dl()) {
 935                 while (pre_div_rate < AUDIO_VIDEO_MIN_CLK_FREQ) {
 936                         pre_div_rate *= 2;
 937                         post_div *= 2;
 938                         if (test_div_sel != 0)
 939                                 test_div_sel--;
 940                         else {
 941                                 control3++;
 942                                 if (control3 == 2)
 943                                         control3++;
 944                         }
 945                 }
 946         }
 947
 948         div = pre_div_rate / parent_rate;
 949         temp64 = (u64) (pre_div_rate - (div * parent_rate));
 950         temp64 *= mfd;
 951         do_div(temp64, parent_rate);
 952         mfn = temp64;
 953
 954         final_rate = (parent_rate * div) + ((parent_rate / mfd) * mfn);
 955         final_rate = final_rate / post_div;
 956
 957         return final_rate;
 958 }
 959
 960
 961 static struct clk pll4_audio_main_clk = {
 962         __INIT_CLK_DEBUG(pll4_audio_main_clk)
 963         .parent = &osc_clk,
 964         .enable = _clk_pll_enable,
 965         .disable = _clk_pll_disable,
 966         .set_rate = _clk_audio_video_set_rate,
 967         .get_rate = _clk_audio_video_get_rate,
 968         .round_rate = _clk_audio_video_round_rate,
 969 };
 970
 971
 972 static struct clk pll5_video_main_clk = {
 973         __INIT_CLK_DEBUG(pll5_video_main_clk)
 974         .parent = &osc_clk,
 975         .enable = _clk_pll_enable,
 976         .disable = _clk_pll_disable,
 977         .set_rate = _clk_audio_video_set_rate,
 978         .get_rate = _clk_audio_video_get_rate,
 979         .round_rate = _clk_audio_video_round_rate,
 980 };
 981
 982 static int _clk_pll_mlb_main_enable(struct clk *clk)
 983 {
 984         unsigned int reg;
 985         void __iomem *pllbase;
 986
 987         pllbase = _get_pll_base(clk);
 988
 989         reg = __raw_readl(pllbase);
 990         reg &= ~ANADIG_PLL_BYPASS;
 991
 992         reg = 0x0da20000;
 993         __raw_writel(reg, pllbase);
 994
 995         /* Wait for PLL to lock */
 996         if (!WAIT(__raw_readl(pllbase) & ANADIG_PLL_LOCK,
 997                 SPIN_DELAY))
 998                 panic("pll enable failed\n");
 999
1000         return 0;
1001 }
1002
1003 static struct clk pll6_mlb150_main_clk = {
1004         __INIT_CLK_DEBUG(pll6_mlb150_main_clk)
1005         .parent = &osc_clk,
1006         .enable = _clk_pll_mlb_main_enable,
1007         .disable = _clk_pll_disable,
1008 };
1009
1010 static unsigned long _clk_pll7_usb_otg_get_rate(struct clk *clk)
1011 {
1012         unsigned int div;
1013         unsigned long val;
1014
1015         div = __raw_readl(PLL7_480_USB2_BASE_ADDR)
1016                 & ANADIG_PLL_480_DIV_SELECT_MASK;
1017
1018         if (div == 1)
1019                 val = clk_get_rate(clk->parent) * 22;
1020         else
1021                 val = clk_get_rate(clk->parent) * 20;
1022         return val;
1023 }
1024
1025 static int _clk_pll7_usb_otg_set_rate(struct clk *clk, unsigned long rate)
1026 {
1027         unsigned int reg,  div;
1028
1029         if (rate == 528000000)
1030                 div = 1;
1031         else if (rate == 480000000)
1032                 div = 0;
1033         else
1034                 return -EINVAL;
1035
1036         reg = __raw_readl(PLL7_480_USB2_BASE_ADDR);
1037         reg &= ~ANADIG_PLL_480_DIV_SELECT_MASK;
1038         reg |= div;
1039         __raw_writel(reg, PLL7_480_USB2_BASE_ADDR);
1040
1041         return 0;
1042 }
1043
1044 static struct clk pll7_usb_host_main_clk = {
1045         __INIT_CLK_DEBUG(pll7_usb_host_main_clk)
1046         .parent = &osc_clk,
1047         .enable = _clk_pll_enable,
1048         .disable = _clk_pll_disable,
1049         .set_rate = _clk_pll7_usb_otg_set_rate,
1050         .get_rate = _clk_pll7_usb_otg_get_rate,
1051
1052 };
1053
1054 static struct clk pll8_enet_main_clk = {
1055         __INIT_CLK_DEBUG(pll8_enet_main_clk)
1056         .parent = &osc_clk,
1057         .enable = _clk_pll_enable,
1058         .disable = _clk_pll_disable,
1059 };
1060
1061 static unsigned long _clk_arm_get_rate(struct clk *clk)
1062 {
1063         u32 cacrr, div;
1064
1065         cacrr = __raw_readl(MXC_CCM_CACRR);
1066         div = (cacrr & MXC_CCM_CACRR_ARM_PODF_MASK) + 1;
1067         return clk_get_rate(clk->parent) / div;
1068 }
1069
1070 static int _clk_arm_set_rate(struct clk *clk, unsigned long rate)
1071 {
1072         int i;
1073         u32 div;
1074         u32 parent_rate;
1075
1076
1077         for (i = 0; i < cpu_op_nr; i++) {
1078                 if (rate == cpu_op_tbl[i].cpu_rate)
1079                         break;
1080         }
1081         if (i >= cpu_op_nr)
1082                 return -EINVAL;
1083
1084         if (cpu_op_tbl[i].pll_rate != clk_get_rate(&pll1_sys_main_clk)) {
1085                 /* Change the PLL1 rate. */
1086                 if (pll2_pfd_400M.usecount != 0)
1087                         pll1_sw_clk.set_parent(&pll1_sw_clk, &pll2_pfd_400M);
1088                 else
1089                         pll1_sw_clk.set_parent(&pll1_sw_clk, &osc_clk);
1090                 pll1_sys_main_clk.set_rate(&pll1_sys_main_clk, cpu_op_tbl[i].pll_rate);
1091                 pll1_sw_clk.set_parent(&pll1_sw_clk, &pll1_sys_main_clk);
1092         }
1093
1094         parent_rate = clk_get_rate(clk->parent);
1095         div = parent_rate / rate;
1096
1097         if (div == 0)
1098                 div = 1;
1099
1100         if ((parent_rate / div) > rate)
1101                 div++;
1102
1103         if (div > 8)
1104                 return -1;
1105
1106         __raw_writel(div - 1, MXC_CCM_CACRR);
1107
1108         return 0;
1109 }
1110
1111 static struct clk cpu_clk = {
1112         __INIT_CLK_DEBUG(cpu_clk)
1113         .parent = &pll1_sw_clk,
1114         .set_rate = _clk_arm_set_rate,
1115         .get_rate = _clk_arm_get_rate,
1116 };
1117
1118 static int _clk_periph_set_parent(struct clk *clk, struct clk *parent)
1119 {
1120         u32 reg;
1121         int mux;
1122
1123         mux = _get_mux6(parent, &pll2_528_bus_main_clk, &pll2_pfd_400M,
1124                 &pll2_pfd_352M, &pll2_200M, &pll3_sw_clk, &osc_clk);
1125
1126         if (mux <= 3) {
1127                 /* Set the pre_periph_clk multiplexer */
1128                 reg = __raw_readl(MXC_CCM_CBCMR);
1129                 reg &= ~MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK;
1130                 reg |= mux << MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET;
1131                 __raw_writel(reg, MXC_CCM_CBCMR);
1132
1133                 /* Set the periph_clk_sel multiplexer. */
1134                 reg = __raw_readl(MXC_CCM_CBCDR);
1135                 reg &= ~MXC_CCM_CBCDR_PERIPH_CLK_SEL;
1136                 __raw_writel(reg, MXC_CCM_CBCDR);
1137         } else {
1138                 reg = __raw_readl(MXC_CCM_CBCDR);
1139                 /* Set the periph_clk2_podf divider to divide by 1. */
1140                 reg &= ~MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK;
1141                 __raw_writel(reg, MXC_CCM_CBCDR);
1142
1143                 /* Set the periph_clk2_sel mux. */
1144                 reg = __raw_readl(MXC_CCM_CBCMR);
1145                 reg &= ~MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK;
1146                 reg |= ((mux - 4) << MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET);
1147                 __raw_writel(reg, MXC_CCM_CBCMR);
1148
1149                 while (__raw_readl(MXC_CCM_CDHIPR))
1150                         ;
1151
1152                 reg = __raw_readl(MXC_CCM_CBCDR);
1153                 /* Set periph_clk_sel to select periph_clk2. */
1154                 reg |= MXC_CCM_CBCDR_PERIPH_CLK_SEL;
1155                 __raw_writel(reg, MXC_CCM_CBCDR);
1156         }
1157
1158         if (!WAIT(!(__raw_readl(MXC_CCM_CDHIPR)
1159              & MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY), SPIN_DELAY))
1160                 panic("_clk_periph_set_parent failed\n");
1161
1162         return 0;
1163 }
1164
1165 static unsigned long _clk_periph_get_rate(struct clk *clk)
1166 {
1167         u32 div = 1;
1168         u32 reg;
1169         unsigned long val;
1170
1171         if ((clk->parent == &pll3_sw_clk) || (clk->parent == &osc_clk)) {
1172                 reg = __raw_readl(MXC_CCM_CBCDR)
1173                         & MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK;
1174                 div = (reg >> MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET) + 1;
1175         }
1176         val = clk_get_rate(clk->parent) / div;
1177         return val;
1178 }
1179
1180 static struct clk periph_clk = {
1181         __INIT_CLK_DEBUG(periph_clk)
1182         .parent = &pll2_528_bus_main_clk,
1183         .set_parent = _clk_periph_set_parent,
1184         .get_rate = _clk_periph_get_rate,
1185 };
1186
1187 static unsigned long _clk_axi_get_rate(struct clk *clk)
1188 {
1189         u32 div, reg;
1190         unsigned long val;
1191
1192         reg = __raw_readl(MXC_CCM_CBCDR) & MXC_CCM_CBCDR_AXI_PODF_MASK;
1193         div = (reg >> MXC_CCM_CBCDR_AXI_PODF_OFFSET);
1194
1195         val = clk_get_rate(clk->parent) / (div + 1);
1196         return val;
1197 }
1198
1199 static int _clk_axi_set_rate(struct clk *clk, unsigned long rate)
1200 {
1201         u32 reg, div;
1202         u32 parent_rate = clk_get_rate(clk->parent);
1203
1204         div = parent_rate / rate;
1205
1206         if (div == 0)
1207                 div++;
1208         if (((parent_rate / div) != rate) || (div > 8))
1209                 return -EINVAL;
1210
1211         reg = __raw_readl(MXC_CCM_CBCDR);
1212         reg &= ~MXC_CCM_CBCDR_AXI_PODF_MASK;
1213         reg |= (div - 1) << MXC_CCM_CBCDR_AXI_PODF_OFFSET;
1214         __raw_writel(reg, MXC_CCM_CBCDR);
1215
1216         if (!WAIT(!(__raw_readl(MXC_CCM_CDHIPR)
1217              & MXC_CCM_CDHIPR_AXI_PODF_BUSY), SPIN_DELAY))
1218                 panic("pll _clk_axi_a_set_rate failed\n");
1219
1220         return 0;
1221 }
1222
1223 static unsigned long _clk_axi_round_rate(struct clk *clk,
1224                                                 unsigned long rate)
1225 {
1226         u32 div;
1227         u32 parent_rate = clk_get_rate(clk->parent);
1228
1229         div = parent_rate / rate;
1230
1231         /* Make sure rate is not greater than the maximum
1232          * value for the clock.
1233          * Also prevent a div of 0.
1234          */
1235
1236         if (div > 8)
1237                 div = 8;
1238         else if (div == 0)
1239                 div++;
1240
1241         return parent_rate / div;
1242 }
1243
1244 static int _clk_axi_set_parent(struct clk *clk, struct clk *parent)
1245 {
1246         u32 reg;
1247         int mux;
1248
1249         mux = _get_mux6(parent, &periph_clk, &pll2_pfd_400M,
1250                                 &pll3_pfd_540M, NULL, NULL, NULL);
1251
1252         if (mux == 0) {
1253                 /* Set the AXI_SEL mux */
1254                 reg = __raw_readl(MXC_CCM_CBCDR) & ~MXC_CCM_CBCDR_AXI_SEL;
1255                 __raw_writel(reg, MXC_CCM_CBCDR);
1256         } else {
1257                 /* Set the AXI_ALT_SEL mux. */
1258                 reg = __raw_readl(MXC_CCM_CBCDR)
1259                         & ~MXC_CCM_CBCDR_AXI_ALT_SEL_MASK;
1260                 reg = ((mux - 1) << MXC_CCM_CBCDR_AXI_ALT_SEL_OFFSET);
1261                 __raw_writel(reg, MXC_CCM_CBCDR);
1262
1263                 /* Set the AXI_SEL mux */
1264                 reg = __raw_readl(MXC_CCM_CBCDR) & ~MXC_CCM_CBCDR_AXI_SEL;
1265                 reg |= MXC_CCM_CBCDR_AXI_SEL;
1266                 __raw_writel(reg, MXC_CCM_CBCDR);
1267         }
1268         return 0;
1269 }
1270
1271 static struct clk axi_clk = {
1272         __INIT_CLK_DEBUG(axi_clk)
1273         .parent = &periph_clk,
1274         .set_parent = _clk_axi_set_parent,
1275         .set_rate = _clk_axi_set_rate,
1276         .get_rate = _clk_axi_get_rate,
1277         .round_rate = _clk_axi_round_rate,
1278 };
1279
1280 static unsigned long _clk_ahb_get_rate(struct clk *clk)
1281 {
1282         u32 reg, div;
1283
1284         reg = __raw_readl(MXC_CCM_CBCDR);
1285         div = ((reg & MXC_CCM_CBCDR_AHB_PODF_MASK) >>
1286                MXC_CCM_CBCDR_AHB_PODF_OFFSET) + 1;
1287
1288         return clk_get_rate(clk->parent) / div;
1289 }
1290
1291 static int _clk_ahb_set_rate(struct clk *clk, unsigned long rate)
1292 {
1293         u32 reg, div;
1294         u32 parent_rate = clk_get_rate(clk->parent);
1295
1296         div = parent_rate / rate;
1297         if (div == 0)
1298                 div++;
1299         if (((parent_rate / div) != rate) || (div > 8))
1300                 return -EINVAL;
1301
1302         reg = __raw_readl(MXC_CCM_CBCDR);
1303         reg &= ~MXC_CCM_CBCDR_AHB_PODF_MASK;
1304         reg |= (div - 1) << MXC_CCM_CBCDR_AHB_PODF_OFFSET;
1305         __raw_writel(reg, MXC_CCM_CBCDR);
1306
1307         if (!WAIT(!(__raw_readl(MXC_CCM_CDHIPR) & MXC_CCM_CDHIPR_AHB_PODF_BUSY),
1308                                 SPIN_DELAY))
1309                         panic("_clk_ahb_set_rate failed\n");
1310
1311         return 0;
1312 }
1313
1314 static unsigned long _clk_ahb_round_rate(struct clk *clk,
1315                                                 unsigned long rate)
1316 {
1317         u32 div;
1318         u32 parent_rate = clk_get_rate(clk->parent);
1319
1320         div = parent_rate / rate;
1321
1322         /* Make sure rate is not greater than the maximum value for the clock.
1323          * Also prevent a div of 0.
1324          */
1325         if (div == 0)
1326                 div++;
1327
1328         if (div > 8)
1329                 div = 8;
1330
1331         return parent_rate / div;
1332 }
1333
1334 static struct clk ahb_clk = {
1335         __INIT_CLK_DEBUG(ahb_clk)
1336         .parent = &periph_clk,
1337         .get_rate = _clk_ahb_get_rate,
1338         .set_rate = _clk_ahb_set_rate,
1339         .round_rate = _clk_ahb_round_rate,
1340 };
1341
1342 static unsigned long _clk_ipg_get_rate(struct clk *clk)
1343 {
1344         u32 reg, div;
1345
1346         reg = __raw_readl(MXC_CCM_CBCDR);
1347         div = ((reg & MXC_CCM_CBCDR_IPG_PODF_MASK) >>
1348                 MXC_CCM_CBCDR_IPG_PODF_OFFSET) + 1;
1349
1350         return clk_get_rate(clk->parent) / div;
1351 }
1352
1353
1354 static struct clk ipg_clk = {
1355         __INIT_CLK_DEBUG(ipg_clk)
1356         .parent = &ahb_clk,
1357         .get_rate = _clk_ipg_get_rate,
1358 };
1359
1360 static struct clk tzasc1_clk = {
1361         __INIT_CLK_DEBUG(tzasc1_clk)
1362         .id = 0,
1363         .parent = &ipg_clk,
1364         .enable_reg = MXC_CCM_CCGR2,
1365         .enable_shift = MXC_CCM_CCGRx_CG11_OFFSET,
1366         .enable = _clk_enable,
1367         .disable = _clk_disable_inwait,
1368 };
1369
1370 static struct clk tzasc2_clk = {
1371         __INIT_CLK_DEBUG(tzasc2_clk)
1372         .id = 0,
1373         .parent = &ipg_clk,
1374         .enable_reg = MXC_CCM_CCGR2,
1375         .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET,
1376         .enable = _clk_enable,
1377         .disable = _clk_disable_inwait,
1378 };
1379
1380 static struct clk mx6fast1_clk = {
1381         __INIT_CLK_DEBUG(mx6fast1_clk)
1382         .id = 0,
1383         .parent = &ahb_clk,
1384         .enable_reg = MXC_CCM_CCGR4,
1385         .enable_shift = MXC_CCM_CCGRx_CG4_OFFSET,
1386         .enable = _clk_enable,
1387         .disable = _clk_disable_inwait,
1388 };
1389
1390 static struct clk mx6per1_clk = {
1391         __INIT_CLK_DEBUG(mx6per1_clk)
1392         .id = 0,
1393         .parent = &ahb_clk,
1394         .secondary = &mx6fast1_clk,
1395         .enable_reg = MXC_CCM_CCGR4,
1396         .enable_shift = MXC_CCM_CCGRx_CG6_OFFSET,
1397         .enable = _clk_enable,
1398         .disable = _clk_disable_inwait,
1399 };
1400
1401 static struct clk mx6per2_clk = {
1402         __INIT_CLK_DEBUG(mx6per2_clk)
1403         .id = 0,
1404         .parent = &ahb_clk,
1405         .enable_reg = MXC_CCM_CCGR4,
1406         .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
1407         .enable = _clk_enable,
1408         .disable = _clk_disable_inwait,
1409 };
1410
1411 static unsigned long _clk_mmdc_ch0_axi_get_rate(struct clk *clk)
1412 {
1413         u32 reg, div;
1414
1415         reg = __raw_readl(MXC_CCM_CBCDR);
1416         div = ((reg & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
1417                         MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET) + 1;
1418
1419         return clk_get_rate(clk->parent) / div;
1420 }
1421
1422 static int _clk_mmdc_ch0_axi_set_rate(struct clk *clk, unsigned long rate)
1423 {
1424         u32 reg, div;
1425         u32 parent_rate = clk_get_rate(clk->parent);
1426
1427         div = parent_rate / rate;
1428         if (div == 0)
1429                 div++;
1430         if (((parent_rate / div) != rate) || (div > 8))
1431                 return -EINVAL;
1432
1433         reg = __raw_readl(MXC_CCM_CBCDR);
1434         reg &= ~MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK;
1435         reg |= (div - 1) << MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
1436         __raw_writel(reg, MXC_CCM_CBCDR);
1437
1438         if (!WAIT(!(__raw_readl(MXC_CCM_CDHIPR)
1439                 & MXC_CCM_CDHIPR_MMDC_CH0_PODF_BUSY),
1440                                 SPIN_DELAY))
1441                         panic("_clk_mmdc_ch0_axi_set_rate failed\n");
1442
1443         return 0;
1444 }
1445
1446 static unsigned long _clk_mmdc_ch0_axi_round_rate(struct clk *clk,
1447                                                 unsigned long rate)
1448 {
1449         u32 div;
1450         u32 parent_rate = clk_get_rate(clk->parent);
1451
1452         div = parent_rate / rate;
1453
1454         /* Make sure rate is not greater than the maximum value for the clock.
1455          * Also prevent a div of 0.
1456          */
1457         if (div == 0)
1458                 div++;
1459
1460         if (div > 8)
1461                 div = 8;
1462
1463         return parent_rate / div;
1464 }
1465
1466 static struct clk mmdc_ch0_axi_clk[] = {
1467         {
1468         __INIT_CLK_DEBUG(mmdc_ch0_axi_clk)
1469         .id = 0,
1470         .parent = &periph_clk,
1471         .enable = _clk_enable,
1472         .disable = _clk_disable_inwait,
1473         .enable_reg = MXC_CCM_CCGR3,
1474         .enable_shift = MXC_CCM_CCGRx_CG10_OFFSET,
1475         .secondary = &mmdc_ch0_axi_clk[1],
1476         .get_rate = _clk_mmdc_ch0_axi_get_rate,
1477         .set_rate = _clk_mmdc_ch0_axi_set_rate,
1478         .round_rate = _clk_mmdc_ch0_axi_round_rate,
1479         },
1480         {
1481         __INIT_CLK_DEBUG(mmdc_ch0_ipg_clk)
1482         .id = 0,
1483         .parent = &ipg_clk,
1484         .enable = _clk_enable,
1485         .disable = _clk_disable_inwait,
1486         .enable_reg = MXC_CCM_CCGR3,
1487         .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET,
1488         .secondary = &tzasc1_clk,
1489         },
1490 };
1491
1492 static unsigned long _clk_mmdc_ch1_axi_get_rate(struct clk *clk)
1493 {
1494         u32 reg, div;
1495
1496         reg = __raw_readl(MXC_CCM_CBCDR);
1497         div = ((reg & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) >>
1498                         MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET) + 1;
1499
1500         return clk_get_rate(clk->parent) / div;
1501 }
1502
1503 static int _clk_mmdc_ch1_axi_set_rate(struct clk *clk, unsigned long rate)
1504 {
1505         u32 reg, div;
1506         u32 parent_rate = clk_get_rate(clk->parent);
1507
1508         div = parent_rate / rate;
1509         if (div == 0)
1510                 div++;
1511         if (((parent_rate / div) != rate) || (div > 8))
1512                 return -EINVAL;
1513
1514         reg = __raw_readl(MXC_CCM_CBCDR);
1515         reg &= ~MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK;
1516         reg |= (div - 1) << MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
1517         __raw_writel(reg, MXC_CCM_CBCDR);
1518
1519         if (!WAIT(!(__raw_readl(MXC_CCM_CDHIPR)
1520                 & MXC_CCM_CDHIPR_MMDC_CH1_PODF_BUSY), SPIN_DELAY))
1521                         panic("_clk_mmdc_ch1_axi_set_rate failed\n");
1522
1523         return 0;
1524 }
1525
1526 static unsigned long _clk_mmdc_ch1_axi_round_rate(struct clk *clk,
1527                                                 unsigned long rate)
1528 {
1529         u32 div;
1530         u32 parent_rate = clk_get_rate(clk->parent);
1531
1532         div = parent_rate / rate;
1533
1534         /* Make sure rate is not greater than the maximum value for the clock.
1535          * Also prevent a div of 0.
1536          */
1537         if (div == 0)
1538                 div++;
1539
1540         if (div > 8)
1541                 div = 8;
1542
1543         return parent_rate / div;
1544 }
1545
1546 static struct clk mmdc_ch1_axi_clk[] = {
1547         {
1548         __INIT_CLK_DEBUG(mmdc_ch1_axi_clk)
1549         .id = 0,
1550         .parent = &pll2_pfd_400M,
1551         .enable = _clk_enable,
1552         .disable = _clk_disable,
1553         .enable_reg = MXC_CCM_CCGR3,
1554         .enable_shift = MXC_CCM_CCGRx_CG11_OFFSET,
1555         .secondary = &mmdc_ch1_axi_clk[1],
1556         .get_rate = _clk_mmdc_ch1_axi_get_rate,
1557         .set_rate = _clk_mmdc_ch1_axi_set_rate,
1558         .round_rate = _clk_mmdc_ch1_axi_round_rate,
1559         },
1560         {
1561         .id = 1,
1562         __INIT_CLK_DEBUG(mmdc_ch1_ipg_clk)
1563         .parent = &ipg_clk,
1564         .enable = _clk_enable,
1565         .disable = _clk_disable,
1566         .enable_reg = MXC_CCM_CCGR3,
1567         .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
1568         .secondary = &tzasc2_clk,
1569         },
1570 };
1571
1572 static struct clk ocram_clk = {
1573         __INIT_CLK_DEBUG(ocram_clk)
1574         .id = 0,
1575         .parent = &ahb_clk,
1576         .enable_reg = MXC_CCM_CCGR3,
1577         .enable_shift = MXC_CCM_CCGRx_CG14_OFFSET,
1578         .enable = _clk_enable,
1579         .disable = _clk_disable_inwait,
1580 };
1581
1582 static unsigned long _clk_ipg_perclk_get_rate(struct clk *clk)
1583 {
1584         u32 reg, div;
1585
1586         reg = __raw_readl(MXC_CCM_CSCMR1);
1587         div = ((reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK) >>
1588                         MXC_CCM_CSCMR1_PERCLK_PODF_OFFSET) + 1;
1589
1590         return clk_get_rate(clk->parent) / div;
1591 }
1592
1593 static int _clk_ipg_perclk_set_rate(struct clk *clk, unsigned long rate)
1594 {
1595         u32 reg, div;
1596         u32 parent_rate = clk_get_rate(clk->parent);
1597
1598         div = parent_rate / rate;
1599         if (div == 0)
1600                 div++;
1601         if (((parent_rate / div) != rate) || (div > 64))
1602                 return -EINVAL;
1603
1604         reg = __raw_readl(MXC_CCM_CSCMR1);
1605         reg &= ~MXC_CCM_CSCMR1_PERCLK_PODF_MASK;
1606         reg |= (div - 1) << MXC_CCM_CSCMR1_PERCLK_PODF_OFFSET;
1607         __raw_writel(reg, MXC_CCM_CSCMR1);
1608
1609         return 0;
1610 }
1611
1612
1613 static unsigned long _clk_ipg_perclk_round_rate(struct clk *clk,
1614                                                 unsigned long rate)
1615 {
1616         u32 div;
1617         u32 parent_rate = clk_get_rate(clk->parent);
1618
1619         div = parent_rate / rate;
1620
1621         /* Make sure rate is not greater than the maximum value for the clock.
1622          * Also prevent a div of 0.
1623          */
1624         if (div == 0)
1625                 div++;
1626
1627         if (div > 64)
1628                 div = 64;
1629
1630         return parent_rate / div;
1631 }
1632
1633 static struct clk ipg_perclk = {
1634         __INIT_CLK_DEBUG(ipg_perclk)
1635         .parent = &ipg_clk,
1636         .get_rate = _clk_ipg_perclk_get_rate,
1637         .set_rate = _clk_ipg_perclk_set_rate,
1638         .round_rate = _clk_ipg_perclk_round_rate,
1639 };
1640
1641 static struct clk spba_clk = {
1642         __INIT_CLK_DEBUG(spba_clk)
1643         .parent = &ipg_clk,
1644         .enable_reg = MXC_CCM_CCGR5,
1645         .enable_shift = MXC_CCM_CCGRx_CG6_OFFSET,
1646         .enable = _clk_enable,
1647         .disable = _clk_disable,
1648 };
1649
1650 static struct clk sdma_clk[] = {
1651         {
1652          __INIT_CLK_DEBUG(sdma_clk)
1653          .parent = &ahb_clk,
1654          .enable_reg = MXC_CCM_CCGR5,
1655          .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET,
1656          .enable = _clk_enable,
1657          .disable = _clk_disable,
1658          .secondary = &sdma_clk[1],
1659         },
1660         {
1661          .parent = &mx6per1_clk,
1662 #ifdef CONFIG_SDMA_IRAM
1663          .secondary = &ocram_clk,
1664 #else
1665         .secondary = &mmdc_ch0_axi_clk[0],
1666 #endif
1667         },
1668 };
1669
1670 static int _clk_gpu2d_axi_set_parent(struct clk *clk, struct clk *parent)
1671 {
1672         u32 reg = __raw_readl(MXC_CCM_CBCMR) & ~MXC_CCM_CBCMR_GPU2D_AXI_CLK_SEL;
1673
1674         if (parent == &ahb_clk)
1675                 reg |= MXC_CCM_CBCMR_GPU2D_AXI_CLK_SEL;
1676
1677         __raw_writel(reg, MXC_CCM_CBCMR);
1678
1679         return 0;
1680 }
1681
1682 static struct clk gpu2d_axi_clk = {
1683         __INIT_CLK_DEBUG(gpu2d_axi_clk)
1684         .parent = &axi_clk,
1685         .secondary = &openvg_axi_clk,
1686         .set_parent = _clk_gpu2d_axi_set_parent,
1687 };
1688
1689 static int _clk_gpu3d_axi_set_parent(struct clk *clk, struct clk *parent)
1690 {
1691         u32 reg = __raw_readl(MXC_CCM_CBCMR) & ~MXC_CCM_CBCMR_GPU3D_AXI_CLK_SEL;
1692
1693         if (parent == &ahb_clk)
1694                 reg |= MXC_CCM_CBCMR_GPU3D_AXI_CLK_SEL;
1695
1696         __raw_writel(reg, MXC_CCM_CBCMR);
1697
1698         return 0;
1699 }
1700
1701 static struct clk gpu3d_axi_clk = {
1702         __INIT_CLK_DEBUG(gpu3d_axi_clk)
1703         .parent = &axi_clk,
1704         .secondary = &mmdc_ch0_axi_clk[0],
1705         .set_parent = _clk_gpu3d_axi_set_parent,
1706 };
1707
1708 static int _clk_pcie_axi_set_parent(struct clk *clk, struct clk *parent)
1709 {
1710         u32 reg = __raw_readl(MXC_CCM_CBCMR) & ~MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL;
1711
1712         if (parent == &ahb_clk)
1713                 reg |= MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL;
1714
1715         __raw_writel(reg, MXC_CCM_CBCMR);
1716
1717         return 0;
1718 }
1719
1720 static struct clk pcie_axi_clk = {
1721         __INIT_CLK_DEBUG(pcie_axi_clk)
1722         .parent = &axi_clk,
1723         .set_parent = _clk_pcie_axi_set_parent,
1724 };
1725
1726 static int _clk_vdo_axi_set_parent(struct clk *clk, struct clk *parent)
1727 {
1728         u32 reg = __raw_readl(MXC_CCM_CBCMR) & ~MXC_CCM_CBCMR_VDOAXI_CLK_SEL;
1729
1730         if (parent == &ahb_clk)
1731                 reg |= MXC_CCM_CBCMR_VDOAXI_CLK_SEL;
1732
1733         __raw_writel(reg, MXC_CCM_CBCMR);
1734
1735         return 0;
1736 }
1737
1738 static struct clk vdo_axi_clk = {
1739         __INIT_CLK_DEBUG(vdo_axi_clk)
1740         .parent = &axi_clk,
1741         .enable_reg = MXC_CCM_CCGR6,
1742         .enable_shift = MXC_CCM_CCGRx_CG6_OFFSET,
1743         .enable = _clk_enable,
1744         .disable = _clk_disable,
1745         .set_parent = _clk_vdo_axi_set_parent,
1746 };
1747
1748 static struct clk vdoa_clk = {
1749         __INIT_CLK_DEBUG(vdoa_clk)
1750         .id = 0,
1751         .parent = &axi_clk,
1752         .secondary = &mx6fast1_clk,
1753         .enable_reg = MXC_CCM_CCGR2,
1754         .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
1755         .enable = _clk_enable,
1756         .disable = _clk_disable,
1757 };
1758
1759 static unsigned long _clk_gpt_get_rate(struct clk *clk)
1760 {
1761         unsigned long rate;
1762
1763         if (mx6q_revision() == IMX_CHIP_REVISION_1_0)
1764                 return clk_get_rate(clk->parent);
1765
1766         rate = mx6_timer_rate();
1767         if (!rate)
1768                 return clk_get_rate(clk->parent);
1769
1770         return rate;
1771 }
1772
1773 static struct clk gpt_clk[] = {
1774         {
1775         __INIT_CLK_DEBUG(gpt_clk)
1776          .parent = &osc_clk,
1777          .id = 0,
1778          .enable_reg = MXC_CCM_CCGR1,
1779          .enable_shift = MXC_CCM_CCGRx_CG10_OFFSET,
1780          .enable = _clk_enable,
1781          .disable = _clk_disable,
1782          .get_rate = _clk_gpt_get_rate,
1783          .secondary = &gpt_clk[1],
1784          },
1785         {
1786         __INIT_CLK_DEBUG(gpt_serial_clk)
1787          .id = 0,
1788          .enable_reg = MXC_CCM_CCGR1,
1789          .enable_shift = MXC_CCM_CCGRx_CG11_OFFSET,
1790          .enable = _clk_enable,
1791          .disable = _clk_disable,
1792          },
1793 };
1794
1795 static unsigned long _clk_iim_get_rate(struct clk *clk)
1796 {
1797         return clk_get_rate(clk->parent);
1798 }
1799
1800 static struct clk iim_clk = {
1801         __INIT_CLK_DEBUG(iim_clk)
1802         .parent = &ipg_clk,
1803         .enable = _clk_enable,
1804         .enable_reg = MXC_CCM_CCGR2,
1805         .enable_shift = MXC_CCM_CCGRx_CG6_OFFSET,
1806         .disable = _clk_disable,
1807         .get_rate = _clk_iim_get_rate,
1808 };
1809
1810 static struct clk i2c_clk[] = {
1811         {
1812         __INIT_CLK_DEBUG(i2c_clk_0)
1813          .id = 0,
1814          .parent = &ipg_perclk,
1815          .enable_reg = MXC_CCM_CCGR2,
1816          .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET,
1817          .enable = _clk_enable,
1818          .disable = _clk_disable,
1819          },
1820         {
1821         __INIT_CLK_DEBUG(i2c_clk_1)
1822          .id = 1,
1823          .parent = &ipg_perclk,
1824          .enable_reg = MXC_CCM_CCGR2,
1825          .enable_shift = MXC_CCM_CCGRx_CG4_OFFSET,
1826          .enable = _clk_enable,
1827          .disable = _clk_disable,
1828          },
1829         {
1830         __INIT_CLK_DEBUG(i2c_clk_2)
1831          .id = 2,
1832          .parent = &ipg_perclk,
1833          .enable_reg = MXC_CCM_CCGR2,
1834          .enable_shift = MXC_CCM_CCGRx_CG5_OFFSET,
1835          .enable = _clk_enable,
1836          .disable = _clk_disable,
1837          },
1838 };
1839
1840 static int _clk_vpu_axi_set_parent(struct clk *clk, struct clk *parent)
1841 {
1842         int mux;
1843         u32 reg = __raw_readl(MXC_CCM_CBCMR)
1844                 & ~MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK;
1845
1846         mux = _get_mux6(parent, &axi_clk, &pll2_pfd_400M,
1847                 &pll2_pfd_352M, NULL, NULL, NULL);
1848
1849         reg |= (mux << MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET);
1850
1851         __raw_writel(reg, MXC_CCM_CBCMR);
1852
1853         return 0;
1854 }
1855
1856 static unsigned long _clk_vpu_axi_get_rate(struct clk *clk)
1857 {
1858         u32 reg, div;
1859
1860         reg = __raw_readl(MXC_CCM_CSCDR1);
1861         div = ((reg & MXC_CCM_CSCDR1_VPU_AXI_PODF_MASK) >>
1862                         MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET) + 1;
1863
1864         return clk_get_rate(clk->parent) / div;
1865 }
1866
1867 static int _clk_vpu_axi_set_rate(struct clk *clk, unsigned long rate)
1868 {
1869         u32 reg, div;
1870         u32 parent_rate = clk_get_rate(clk->parent);
1871
1872         div = parent_rate / rate;
1873         if (div == 0)
1874                 div++;
1875         if (((parent_rate / div) != rate) || (div > 8))
1876                 return -EINVAL;
1877
1878         reg = __raw_readl(MXC_CCM_CSCDR1);
1879         reg &= ~MXC_CCM_CSCDR1_VPU_AXI_PODF_MASK;
1880         reg |= (div - 1) << MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET;
1881         __raw_writel(reg, MXC_CCM_CSCDR1);
1882
1883         return 0;
1884 }
1885
1886 static unsigned long _clk_vpu_axi_round_rate(struct clk *clk,
1887                                                 unsigned long rate)
1888 {
1889         u32 div;
1890         u32 parent_rate = clk_get_rate(clk->parent);
1891
1892         div = parent_rate / rate;
1893
1894         /* Make sure rate is not greater than the maximum value for the clock.
1895          * Also prevent a div of 0.
1896          */
1897         if (div == 0)
1898                 div++;
1899
1900         if (div > 8)
1901                 div = 8;
1902
1903         return parent_rate / div;
1904 }
1905
1906 static struct clk vpu_clk[] = {
1907         {
1908         __INIT_CLK_DEBUG(vpu_clk)
1909         .parent = &axi_clk,
1910         .enable_reg = MXC_CCM_CCGR6,
1911         .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
1912         .enable = _clk_enable,
1913         .disable = _clk_disable,
1914         .set_parent = _clk_vpu_axi_set_parent,
1915         .round_rate = _clk_vpu_axi_round_rate,
1916         .set_rate = _clk_vpu_axi_set_rate,
1917         .get_rate = _clk_vpu_axi_get_rate,
1918         .secondary = &vpu_clk[1],
1919         },
1920         {
1921         .parent =  &mmdc_ch0_axi_clk[0],
1922         .secondary = &vpu_clk[2],
1923         },
1924         {
1925         .parent =  &mx6fast1_clk,
1926         .secondary = &ocram_clk,
1927         },
1928
1929 };
1930
1931 static int _clk_ipu1_set_parent(struct clk *clk, struct clk *parent)
1932 {
1933         int mux;
1934         u32 reg = __raw_readl(MXC_CCM_CSCDR3)
1935                 & ~MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_MASK;
1936
1937         mux = _get_mux6(parent, &mmdc_ch0_axi_clk[0],
1938                 &pll2_pfd_400M, &pll3_120M, &pll3_pfd_540M, NULL, NULL);
1939
1940         reg |= (mux << MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_OFFSET);
1941
1942         __raw_writel(reg, MXC_CCM_CSCDR3);
1943
1944         return 0;
1945 }
1946
1947 static unsigned long _clk_ipu1_get_rate(struct clk *clk)
1948 {
1949         u32 reg, div;
1950
1951         reg = __raw_readl(MXC_CCM_CSCDR3);
1952         div = ((reg & MXC_CCM_CSCDR3_IPU1_HSP_PODF_MASK) >>
1953                         MXC_CCM_CSCDR3_IPU1_HSP_PODF_OFFSET) + 1;
1954
1955         return clk_get_rate(clk->parent) / div;
1956 }
1957
1958 static int _clk_ipu1_set_rate(struct clk *clk, unsigned long rate)
1959 {
1960         u32 reg, div;
1961         u32 parent_rate = clk_get_rate(clk->parent);
1962
1963         div = parent_rate / rate;
1964         if (div == 0)
1965                 div++;
1966         if (((parent_rate / div) != rate) || (div > 8))
1967                 return -EINVAL;
1968
1969         reg = __raw_readl(MXC_CCM_CSCDR3);
1970         reg &= ~MXC_CCM_CSCDR3_IPU1_HSP_PODF_MASK;
1971         reg |= (div - 1) << MXC_CCM_CSCDR3_IPU1_HSP_PODF_OFFSET;
1972         __raw_writel(reg, MXC_CCM_CSCDR3);
1973
1974         return 0;
1975 }
1976
1977 static unsigned long _clk_ipu_round_rate(struct clk *clk,
1978                                                 unsigned long rate)
1979 {
1980         u32 div;
1981         u32 parent_rate = clk_get_rate(clk->parent);
1982
1983         div = parent_rate / rate;
1984
1985         /* Make sure rate is not greater than the maximum value for the clock.
1986          * Also prevent a div of 0.
1987          */
1988         if (div == 0)
1989                 div++;
1990
1991         if (div > 8)
1992                 div = 8;
1993
1994         return parent_rate / div;
1995 }
1996
1997 static struct clk ipu1_clk = {
1998         __INIT_CLK_DEBUG(ipu1_clk)
1999         .parent = &mmdc_ch0_axi_clk[0],
2000         .secondary = &mmdc_ch0_axi_clk[0],
2001         .enable_reg = MXC_CCM_CCGR3,
2002         .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET,
2003         .enable = _clk_enable,
2004         .disable = _clk_disable,
2005         .set_parent = _clk_ipu1_set_parent,
2006         .round_rate = _clk_ipu_round_rate,
2007         .set_rate = _clk_ipu1_set_rate,
2008         .get_rate = _clk_ipu1_get_rate,
2009         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
2010 };
2011
2012 static int _clk_cko1_clk0_set_parent(struct clk *clk, struct clk *parent)
2013 {
2014         u32 sel, reg;
2015
2016         if (parent == &pll3_sw_clk)
2017                 sel = 0;
2018         else if (parent == &pll2_528_bus_main_clk)
2019                 sel = 1;
2020         else if (parent == &pll1_sys_main_clk)
2021                 sel = 2;
2022         else if (parent == &pll5_video_main_clk)
2023                 sel = 3;
2024         else if (parent == &axi_clk)
2025                 sel = 5;
2026         else if (parent == &enfc_clk)
2027                 sel = 6;
2028         else if (parent == &ipu1_di_clk_root)
2029                 sel = 7;
2030         else if (parent == &ipu1_di_clk_root)
2031                 sel = 8;
2032         else if (parent == &ipu2_di_clk_root)
2033                 sel = 9;
2034         else if (parent == &ipu2_di_clk_root)
2035                 sel = 10;
2036         else if (parent == &ahb_clk)
2037                 sel = 11;
2038         else if (parent == &ipg_clk)
2039                 sel = 12;
2040         else if (parent == &ipg_perclk)
2041                 sel = 13;
2042         else if (parent == &ckil_clk)
2043                 sel = 14;
2044         else if (parent == &pll4_audio_main_clk)
2045                 sel = 15;
2046         else
2047                 return -EINVAL;
2048
2049         reg = __raw_readl(MXC_CCM_CCOSR);
2050         reg &= ~MXC_CCM_CCOSR_CKOL_SEL_MASK;
2051         reg |= sel << MXC_CCM_CCOSR_CKOL_SEL_OFFSET;
2052         __raw_writel(reg, MXC_CCM_CCOSR);
2053         return 0;
2054 }
2055
2056 static unsigned long _clk_cko1_round_rate(struct clk *clk,
2057                                                 unsigned long rate)
2058 {
2059         u32 div;
2060         u32 parent_rate = clk_get_rate(clk->parent);
2061
2062         div = parent_rate / rate;
2063
2064         /* Make sure rate is not greater than the maximum value for the clock.
2065          * Also prevent a div of 0.
2066          */
2067         if (div == 0)
2068                 div++;
2069
2070         if (div > 8)
2071                 div = 8;
2072
2073         return parent_rate / div;
2074 }
2075
2076 static int _clk_cko1_set_rate(struct clk *clk, unsigned long rate)
2077 {
2078         u32 reg, div;
2079         u32 parent_rate = clk_get_rate(clk->parent);
2080
2081         div = parent_rate / rate;
2082         if (div == 0)
2083                 div++;
2084         if (((parent_rate / div) != rate) || (div > 8))
2085                 return -EINVAL;
2086
2087         reg = __raw_readl(MXC_CCM_CCOSR);
2088         reg &= ~MXC_CCM_CCOSR_CKOL_DIV_MASK;
2089         reg |= div << MXC_CCM_CCOSR_CKOL_DIV_OFFSET;
2090         __raw_writel(reg, MXC_CCM_CCOSR);
2091
2092         return 0;
2093 }
2094
2095 static unsigned long _clk_cko1_get_rate(struct clk *clk)
2096 {
2097         u32 reg, div;
2098
2099         reg = __raw_readl(MXC_CCM_CCOSR);
2100         div = ((reg & MXC_CCM_CCOSR_CKOL_DIV_MASK) >>
2101                         MXC_CCM_CCOSR_CKOL_DIV_OFFSET) + 1;
2102
2103         return clk_get_rate(clk->parent) / div;
2104 }
2105
2106 static int cko1_clk_enable(struct clk *clk)
2107 {
2108         u32 reg;
2109         reg = __raw_readl(clk->enable_reg);
2110         reg |= clk->enable_shift;
2111         __raw_writel(reg, clk->enable_reg);
2112
2113         return 0;
2114 }
2115
2116 static struct clk cko1_clk0 = {
2117         __INIT_CLK_DEBUG(cko1_clk0)
2118         .parent = &ipg_clk,
2119         .enable_reg = MXC_CCM_CCOSR,
2120         .enable_shift = MXC_CCM_CCOSR_CKOL_EN,
2121         .enable = cko1_clk_enable,
2122         .disable = _clk_disable,
2123         .set_parent = _clk_cko1_clk0_set_parent,
2124         .round_rate = _clk_cko1_round_rate,
2125         .set_rate = _clk_cko1_set_rate,
2126         .get_rate = _clk_cko1_get_rate,
2127 };
2128
2129 static int _clk_ipu2_set_parent(struct clk *clk, struct clk *parent)
2130 {
2131         int mux;
2132         u32 reg = __raw_readl(MXC_CCM_CSCDR3)
2133                 & ~MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_MASK;
2134
2135         mux = _get_mux6(parent, &mmdc_ch0_axi_clk[0],
2136                 &pll2_pfd_400M, &pll3_120M, &pll3_pfd_540M, NULL, NULL);
2137
2138         reg |= (mux << MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_OFFSET);
2139
2140         __raw_writel(reg, MXC_CCM_CSCDR3);
2141
2142         return 0;
2143 }
2144
2145 static unsigned long _clk_ipu2_get_rate(struct clk *clk)
2146 {
2147         u32 reg, div;
2148
2149         reg = __raw_readl(MXC_CCM_CSCDR3);
2150         div = ((reg & MXC_CCM_CSCDR3_IPU2_HSP_PODF_MASK) >>
2151                         MXC_CCM_CSCDR3_IPU2_HSP_PODF_OFFSET) + 1;
2152
2153         return clk_get_rate(clk->parent) / div;
2154 }
2155
2156 static int _clk_ipu2_set_rate(struct clk *clk, unsigned long rate)
2157 {
2158         u32 reg, div;
2159         u32 parent_rate = clk_get_rate(clk->parent);
2160
2161         div = parent_rate / rate;
2162         if (div == 0)
2163                 div++;
2164         if (((parent_rate / div) != rate) || (div > 8))
2165                 return -EINVAL;
2166
2167         reg = __raw_readl(MXC_CCM_CSCDR3);
2168         reg &= ~MXC_CCM_CSCDR3_IPU2_HSP_PODF_MASK;
2169         reg |= (div - 1) << MXC_CCM_CSCDR3_IPU2_HSP_PODF_OFFSET;
2170         __raw_writel(reg, MXC_CCM_CSCDR3);
2171
2172         return 0;
2173 }
2174
2175 static struct clk ipu2_clk = {
2176         __INIT_CLK_DEBUG(ipu2_clk)
2177         .parent = &mmdc_ch0_axi_clk[0],
2178         .secondary = &mmdc_ch0_axi_clk[0],
2179         .enable_reg = MXC_CCM_CCGR3,
2180         .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET,
2181         .enable = _clk_enable,
2182         .disable = _clk_disable,
2183         .set_parent = _clk_ipu2_set_parent,
2184         .round_rate = _clk_ipu_round_rate,
2185         .set_rate = _clk_ipu2_set_rate,
2186         .get_rate = _clk_ipu2_get_rate,
2187         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
2188 };
2189
2190 static struct clk usdhc_dep_clk = {
2191         .parent = &mmdc_ch0_axi_clk[0],
2192         .secondary = &mx6per1_clk,
2193         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
2194         };
2195
2196 static unsigned long _clk_usdhc_round_rate(struct clk *clk,
2197                                                 unsigned long rate)
2198 {
2199         u32 div;
2200         u32 parent_rate = clk_get_rate(clk->parent);
2201
2202         div = parent_rate / rate;
2203
2204         /* Make sure rate is not greater than the maximum value for the clock.
2205          * Also prevent a div of 0.
2206          */
2207         if (div == 0)
2208                 div++;
2209
2210         if (div > 8)
2211                 div = 8;
2212
2213         return parent_rate / div;
2214 }
2215
2216 static int _clk_usdhc1_set_parent(struct clk *clk, struct clk *parent)
2217 {
2218         u32 reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_USDHC1_CLK_SEL;
2219
2220         if (parent == &pll2_pfd_352M)
2221                 reg |= (MXC_CCM_CSCMR1_USDHC1_CLK_SEL);
2222
2223         __raw_writel(reg, MXC_CCM_CSCMR1);
2224
2225         return 0;
2226 }
2227
2228 static unsigned long _clk_usdhc1_get_rate(struct clk *clk)
2229 {
2230         u32 reg, div;
2231
2232         reg = __raw_readl(MXC_CCM_CSCDR1);
2233         div = ((reg & MXC_CCM_CSCDR1_USDHC1_PODF_MASK) >>
2234                         MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET) + 1;
2235
2236         return clk_get_rate(clk->parent) / div;
2237 }
2238
2239 static int _clk_usdhc1_set_rate(struct clk *clk, unsigned long rate)
2240 {
2241         u32 reg, div;
2242         u32 parent_rate = clk_get_rate(clk->parent);
2243
2244         div = parent_rate / rate;
2245         if (div == 0)
2246                 div++;
2247         if (((parent_rate / div) != rate) || (div > 8))
2248                 return -EINVAL;
2249
2250         reg = __raw_readl(MXC_CCM_CSCDR1);
2251         reg &= ~MXC_CCM_CSCDR1_USDHC1_PODF_MASK;
2252         reg |= (div - 1) << MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET;
2253         __raw_writel(reg, MXC_CCM_CSCDR1);
2254
2255         return 0;
2256 }
2257
2258 static struct clk usdhc1_clk = {
2259         __INIT_CLK_DEBUG(usdhc1_clk)
2260         .id = 0,
2261         .parent = &pll2_pfd_400M,
2262         .secondary = &usdhc_dep_clk,
2263         .enable_reg = MXC_CCM_CCGR6,
2264         .enable_shift = MXC_CCM_CCGRx_CG1_OFFSET,
2265         .enable = _clk_enable,
2266         .disable = _clk_disable,
2267         .set_parent = _clk_usdhc1_set_parent,
2268         .round_rate = _clk_usdhc_round_rate,
2269         .set_rate = _clk_usdhc1_set_rate,
2270         .get_rate = _clk_usdhc1_get_rate,
2271         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
2272 };
2273
2274 static int _clk_usdhc2_set_parent(struct clk *clk, struct clk *parent)
2275 {
2276         u32 reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_USDHC2_CLK_SEL;
2277
2278         if (parent == &pll2_pfd_352M)
2279                 reg |= (MXC_CCM_CSCMR1_USDHC2_CLK_SEL);
2280
2281         __raw_writel(reg, MXC_CCM_CSCMR1);
2282
2283         return 0;
2284 }
2285
2286 static unsigned long _clk_usdhc2_get_rate(struct clk *clk)
2287 {
2288         u32 reg, div;
2289
2290         reg = __raw_readl(MXC_CCM_CSCDR1);
2291         div = ((reg & MXC_CCM_CSCDR1_USDHC2_PODF_MASK) >>
2292                         MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET) + 1;
2293
2294         return clk_get_rate(clk->parent) / div;
2295 }
2296
2297 static int _clk_usdhc2_set_rate(struct clk *clk, unsigned long rate)
2298 {
2299         u32 reg, div;
2300         u32 parent_rate = clk_get_rate(clk->parent);
2301
2302         div = parent_rate / rate;
2303         if (div == 0)
2304                 div++;
2305         if (((parent_rate / div) != rate) || (div > 8))
2306                 return -EINVAL;
2307
2308         reg = __raw_readl(MXC_CCM_CSCDR1);
2309         reg &= ~MXC_CCM_CSCDR1_USDHC2_PODF_MASK;
2310         reg |= (div - 1) << MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET;
2311         __raw_writel(reg, MXC_CCM_CSCDR1);
2312
2313         return 0;
2314 }
2315
2316 static struct clk usdhc2_clk = {
2317         __INIT_CLK_DEBUG(usdhc2_clk)
2318         .id = 1,
2319         .parent = &pll2_pfd_400M,
2320         .secondary = &usdhc_dep_clk,
2321         .enable_reg = MXC_CCM_CCGR6,
2322         .enable_shift = MXC_CCM_CCGRx_CG2_OFFSET,
2323         .enable = _clk_enable,
2324         .disable = _clk_disable,
2325         .set_parent = _clk_usdhc2_set_parent,
2326         .round_rate = _clk_usdhc_round_rate,
2327         .set_rate = _clk_usdhc2_set_rate,
2328         .get_rate = _clk_usdhc2_get_rate,
2329         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
2330 };
2331
2332 static int _clk_usdhc3_set_parent(struct clk *clk, struct clk *parent)
2333 {
2334         u32 reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_USDHC3_CLK_SEL;
2335
2336         if (parent == &pll2_pfd_352M)
2337                 reg |= (MXC_CCM_CSCMR1_USDHC3_CLK_SEL);
2338
2339         __raw_writel(reg, MXC_CCM_CSCMR1);
2340
2341         return 0;
2342 }
2343
2344 static unsigned long _clk_usdhc3_get_rate(struct clk *clk)
2345 {
2346         u32 reg, div;
2347
2348         reg = __raw_readl(MXC_CCM_CSCDR1);
2349         div = ((reg & MXC_CCM_CSCDR1_USDHC3_PODF_MASK) >>
2350                         MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET) + 1;
2351
2352         return clk_get_rate(clk->parent) / div;
2353 }
2354
2355 static int _clk_usdhc3_set_rate(struct clk *clk, unsigned long rate)
2356 {
2357         u32 reg, div;
2358         u32 parent_rate = clk_get_rate(clk->parent);
2359
2360         div = parent_rate / rate;
2361         if (div == 0)
2362                 div++;
2363         if (((parent_rate / div) != rate) || (div > 8))
2364                 return -EINVAL;
2365
2366         reg = __raw_readl(MXC_CCM_CSCDR1);
2367         reg &= ~MXC_CCM_CSCDR1_USDHC3_PODF_MASK;
2368         reg |= (div - 1) << MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET;
2369         __raw_writel(reg, MXC_CCM_CSCDR1);
2370
2371         return 0;
2372 }
2373
2374
2375 static struct clk usdhc3_clk = {
2376         __INIT_CLK_DEBUG(usdhc3_clk)
2377         .id = 2,
2378         .parent = &pll2_pfd_400M,
2379         .secondary = &usdhc_dep_clk,
2380         .enable_reg = MXC_CCM_CCGR6,
2381         .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET,
2382         .enable = _clk_enable,
2383         .disable = _clk_disable,
2384         .set_parent = _clk_usdhc3_set_parent,
2385         .round_rate = _clk_usdhc_round_rate,
2386         .set_rate = _clk_usdhc3_set_rate,
2387         .get_rate = _clk_usdhc3_get_rate,
2388         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
2389 };
2390
2391 static int _clk_usdhc4_set_parent(struct clk *clk, struct clk *parent)
2392 {
2393         u32 reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_USDHC4_CLK_SEL;
2394
2395         if (parent == &pll2_pfd_352M)
2396                 reg |= (MXC_CCM_CSCMR1_USDHC4_CLK_SEL);
2397
2398         __raw_writel(reg, MXC_CCM_CSCMR1);
2399
2400         return 0;
2401 }
2402
2403 static unsigned long _clk_usdhc4_get_rate(struct clk *clk)
2404 {
2405         u32 reg, div;
2406
2407         reg = __raw_readl(MXC_CCM_CSCDR1);
2408         div = ((reg & MXC_CCM_CSCDR1_USDHC4_PODF_MASK) >>
2409                         MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET) + 1;
2410
2411         return clk_get_rate(clk->parent) / div;
2412 }
2413
2414 static int _clk_usdhc4_set_rate(struct clk *clk, unsigned long rate)
2415 {
2416         u32 reg, div;
2417         u32 parent_rate = clk_get_rate(clk->parent);
2418
2419         div = parent_rate / rate;
2420         if (div == 0)
2421                 div++;
2422         if (((parent_rate / div) != rate) || (div > 8))
2423                 return -EINVAL;
2424
2425         reg = __raw_readl(MXC_CCM_CSCDR1);
2426         reg &= ~MXC_CCM_CSCDR1_USDHC4_PODF_MASK;
2427         reg |= (div - 1) << MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET;
2428         __raw_writel(reg, MXC_CCM_CSCDR1);
2429
2430         return 0;
2431 }
2432
2433
2434 static struct clk usdhc4_clk = {
2435         __INIT_CLK_DEBUG(usdhc4_clk)
2436         .id = 3,
2437         .parent = &pll2_pfd_400M,
2438         .secondary = &usdhc_dep_clk,
2439         .enable_reg = MXC_CCM_CCGR6,
2440         .enable_shift = MXC_CCM_CCGRx_CG4_OFFSET,
2441         .enable = _clk_enable,
2442         .disable = _clk_disable,
2443         .set_parent = _clk_usdhc4_set_parent,
2444         .round_rate = _clk_usdhc_round_rate,
2445         .set_rate = _clk_usdhc4_set_rate,
2446         .get_rate = _clk_usdhc4_get_rate,
2447         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
2448 };
2449
2450 static unsigned long _clk_ssi_round_rate(struct clk *clk,
2451                                                 unsigned long rate)
2452 {
2453         u32 pre, post;
2454         u32 parent_rate = clk_get_rate(clk->parent);
2455         u32 div = parent_rate / rate;
2456
2457         if (parent_rate % rate)
2458                 div++;
2459
2460         __calc_pre_post_dividers(1 << 6, div, &pre, &post);
2461
2462         return parent_rate / (pre * post);
2463 }
2464
2465 static unsigned long _clk_ssi1_get_rate(struct clk *clk)
2466 {
2467         u32 reg, prediv, podf;
2468
2469         reg = __raw_readl(MXC_CCM_CS1CDR);
2470
2471         prediv = ((reg & MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK)
2472                 >> MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET) + 1;
2473         podf = ((reg & MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK)
2474                 >> MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET) + 1;
2475
2476         return clk_get_rate(clk->parent) / (prediv * podf);
2477 }
2478
2479 static int _clk_ssi1_set_rate(struct clk *clk, unsigned long rate)
2480 {
2481         u32 reg, div, pre, post;
2482         u32 parent_rate = clk_get_rate(clk->parent);
2483
2484         div = parent_rate / rate;
2485         if (div == 0)
2486                 div++;
2487         if (((parent_rate / div) != rate) || div > 512)
2488                 return -EINVAL;
2489
2490         __calc_pre_post_dividers(1 << 6, div, &pre, &post);
2491
2492         reg = __raw_readl(MXC_CCM_CS1CDR);
2493         reg &= ~(MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK |
2494                  MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK);
2495         reg |= (post - 1) << MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET;
2496         reg |= (pre - 1) << MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET;
2497
2498         __raw_writel(reg, MXC_CCM_CS1CDR);
2499
2500         return 0;
2501 }
2502
2503
2504 static int _clk_ssi1_set_parent(struct clk *clk, struct clk *parent)
2505 {
2506         u32 reg, mux;
2507
2508         reg = __raw_readl(MXC_CCM_CSCMR1)
2509                 & ~MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK;
2510
2511         mux = _get_mux6(parent, &pll3_pfd_508M, &pll3_pfd_454M,
2512                         &pll4_audio_main_clk, NULL, NULL, NULL);
2513         reg |= (mux << MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET);
2514
2515         __raw_writel(reg, MXC_CCM_CSCMR1);
2516
2517         return 0;
2518 }
2519
2520 static struct clk ssi1_clk = {
2521         __INIT_CLK_DEBUG(ssi1_clk)
2522         .parent = &pll3_pfd_508M,
2523         .enable_reg = MXC_CCM_CCGR5,
2524         .enable_shift = MXC_CCM_CCGRx_CG9_OFFSET,
2525         .enable = _clk_enable,
2526         .disable = _clk_disable,
2527         .set_parent = _clk_ssi1_set_parent,
2528         .set_rate = _clk_ssi1_set_rate,
2529         .round_rate = _clk_ssi_round_rate,
2530         .get_rate = _clk_ssi1_get_rate,
2531 #ifdef CONFIG_SND_MXC_SOC_IRAM
2532          .secondary = &ocram_clk,
2533 #else
2534          .secondary = &mmdc_ch0_axi_clk[0],
2535 #endif
2536 };
2537
2538 static unsigned long _clk_ssi2_get_rate(struct clk *clk)
2539 {
2540         u32 reg, prediv, podf;
2541
2542         reg = __raw_readl(MXC_CCM_CS2CDR);
2543
2544         prediv = ((reg & MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK)
2545                 >> MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET) + 1;
2546         podf = ((reg & MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK)
2547                 >> MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET) + 1;
2548
2549         return clk_get_rate(clk->parent) / (prediv * podf);
2550 }
2551
2552 static int _clk_ssi2_set_rate(struct clk *clk, unsigned long rate)
2553 {
2554         u32 reg, div, pre, post;
2555         u32 parent_rate = clk_get_rate(clk->parent);
2556
2557         div = parent_rate / rate;
2558         if (div == 0)
2559                 div++;
2560         if (((parent_rate / div) != rate) || div > 512)
2561                 return -EINVAL;
2562
2563         __calc_pre_post_dividers(1 << 6, div, &pre, &post);
2564
2565         reg = __raw_readl(MXC_CCM_CS2CDR);
2566         reg &= ~(MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK |
2567                  MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK);
2568         reg |= (post - 1) << MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET;
2569         reg |= (pre - 1) << MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET;
2570
2571         __raw_writel(reg, MXC_CCM_CS2CDR);
2572
2573         return 0;
2574 }
2575
2576
2577 static int _clk_ssi2_set_parent(struct clk *clk, struct clk *parent)
2578 {
2579         u32 reg, mux;
2580
2581         reg = __raw_readl(MXC_CCM_CSCMR1)
2582                 & ~MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK;
2583
2584         mux = _get_mux6(parent, &pll3_pfd_508M, &pll3_pfd_454M,
2585                         &pll4_audio_main_clk, NULL, NULL, NULL);
2586         reg |= (mux << MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET);
2587
2588         __raw_writel(reg, MXC_CCM_CSCMR1);
2589
2590         return 0;
2591 }
2592
2593 static struct clk ssi2_clk = {
2594         __INIT_CLK_DEBUG(ssi2_clk)
2595         .parent = &pll3_pfd_508M,
2596         .enable_reg = MXC_CCM_CCGR5,
2597         .enable_shift = MXC_CCM_CCGRx_CG10_OFFSET,
2598         .enable = _clk_enable,
2599         .disable = _clk_disable,
2600         .set_parent = _clk_ssi2_set_parent,
2601         .set_rate = _clk_ssi2_set_rate,
2602         .round_rate = _clk_ssi_round_rate,
2603         .get_rate = _clk_ssi2_get_rate,
2604 #ifdef CONFIG_SND_MXC_SOC_IRAM
2605          .secondary = &ocram_clk,
2606 #else
2607          .secondary = &mmdc_ch0_axi_clk[0],
2608 #endif
2609 };
2610
2611 static unsigned long _clk_ssi3_get_rate(struct clk *clk)
2612 {
2613         u32 reg, prediv, podf;
2614
2615         reg = __raw_readl(MXC_CCM_CS1CDR);
2616
2617         prediv = ((reg & MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK)
2618                 >> MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET) + 1;
2619         podf = ((reg & MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK)
2620                 >> MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET) + 1;
2621
2622         return clk_get_rate(clk->parent) / (prediv * podf);
2623 }
2624
2625 static int _clk_ssi3_set_rate(struct clk *clk, unsigned long rate)
2626 {
2627         u32 reg, div, pre, post;
2628         u32 parent_rate = clk_get_rate(clk->parent);
2629
2630         div = parent_rate / rate;
2631         if (div == 0)
2632                 div++;
2633         if (((parent_rate / div) != rate) || div > 512)
2634                 return -EINVAL;
2635
2636         __calc_pre_post_dividers(1 << 6, div, &pre, &post);
2637
2638         reg = __raw_readl(MXC_CCM_CS1CDR);
2639         reg &= ~(MXC_CCM_CS1CDR_SSI3_CLK_PODF_MASK|
2640                  MXC_CCM_CS1CDR_SSI3_CLK_PRED_MASK);
2641         reg |= (post - 1) << MXC_CCM_CS1CDR_SSI3_CLK_PODF_OFFSET;
2642         reg |= (pre - 1) << MXC_CCM_CS1CDR_SSI3_CLK_PRED_OFFSET;
2643
2644         __raw_writel(reg, MXC_CCM_CS1CDR);
2645
2646         return 0;
2647 }
2648
2649
2650 static int _clk_ssi3_set_parent(struct clk *clk, struct clk *parent)
2651 {
2652         u32 reg, mux;
2653
2654         reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_SSI3_CLK_SEL_MASK;
2655
2656         mux = _get_mux6(parent, &pll3_pfd_508M, &pll3_pfd_454M,
2657                                 &pll4_audio_main_clk, NULL, NULL, NULL);
2658         reg |= (mux << MXC_CCM_CSCMR1_SSI3_CLK_SEL_OFFSET);
2659
2660         __raw_writel(reg, MXC_CCM_CSCMR1);
2661
2662         return 0;
2663 }
2664
2665 static struct clk ssi3_clk = {
2666         __INIT_CLK_DEBUG(ssi3_clk)
2667         .parent = &pll3_pfd_508M,
2668         .enable_reg = MXC_CCM_CCGR5,
2669         .enable_shift = MXC_CCM_CCGRx_CG11_OFFSET,
2670         .enable = _clk_enable,
2671         .disable = _clk_disable,
2672         .set_parent = _clk_ssi3_set_parent,
2673         .set_rate = _clk_ssi3_set_rate,
2674         .round_rate = _clk_ssi_round_rate,
2675         .get_rate = _clk_ssi3_get_rate,
2676 #ifdef CONFIG_SND_MXC_SOC_IRAM
2677          .secondary = &ocram_clk,
2678 #else
2679          .secondary = &mmdc_ch0_axi_clk[0],
2680 #endif
2681 };
2682
2683 static unsigned long _clk_ldb_di_round_rate(struct clk *clk,
2684                                                 unsigned long rate)
2685 {
2686         u32 parent_rate = clk_get_rate(clk->parent);
2687
2688         if (rate * 7 <= parent_rate + parent_rate/20)
2689                 return parent_rate / 7;
2690         else
2691                 return 2 * parent_rate / 7;
2692 }
2693
2694 static unsigned long _clk_ldb_di0_get_rate(struct clk *clk)
2695 {
2696         u32 div;
2697
2698         div = __raw_readl(MXC_CCM_CSCMR2) &
2699                 MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
2700
2701         if (div)
2702                 return clk_get_rate(clk->parent) / 7;
2703
2704         return (2 * clk_get_rate(clk->parent)) / 7;
2705 }
2706
2707 static int _clk_ldb_di0_set_rate(struct clk *clk, unsigned long rate)
2708 {
2709         u32 reg, div = 0;
2710         u32 parent_rate = clk_get_rate(clk->parent);
2711
2712         if (rate * 7 <= parent_rate + parent_rate/20) {
2713                 div = 7;
2714                 rate = parent_rate / 7;
2715         } else
2716                 rate = 2 * parent_rate / 7;
2717
2718         reg = __raw_readl(MXC_CCM_CSCMR2);
2719         if (div == 7)
2720                 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
2721         else
2722                 reg &= ~MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
2723
2724         __raw_writel(reg, MXC_CCM_CSCMR2);
2725
2726         return 0;
2727 }
2728
2729 static int _clk_ldb_di0_set_parent(struct clk *clk, struct clk *parent)
2730 {
2731         u32 reg, mux;
2732
2733         reg = __raw_readl(MXC_CCM_CS2CDR)
2734                 & ~MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK;
2735
2736         mux = _get_mux6(parent, &pll5_video_main_clk,
2737                 &pll2_pfd_352M, &pll2_pfd_400M, &pll3_pfd_540M,
2738                 &pll3_usb_otg_main_clk, NULL);
2739         reg |= (mux << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET);
2740
2741         __raw_writel(reg, MXC_CCM_CS2CDR);
2742
2743         return 0;
2744 }
2745
2746 static struct clk ldb_di0_clk = {
2747          __INIT_CLK_DEBUG(ldb_di0_clk)
2748         .id = 0,
2749         .parent = &pll3_pfd_540M,
2750         .enable_reg = MXC_CCM_CCGR3,
2751         .enable_shift = MXC_CCM_CCGRx_CG6_OFFSET,
2752         .enable = _clk_enable,
2753         .disable = _clk_disable,
2754         .set_parent = _clk_ldb_di0_set_parent,
2755         .set_rate = _clk_ldb_di0_set_rate,
2756         .round_rate = _clk_ldb_di_round_rate,
2757         .get_rate = _clk_ldb_di0_get_rate,
2758         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
2759 };
2760
2761 static unsigned long _clk_ldb_di1_get_rate(struct clk *clk)
2762 {
2763         u32 div;
2764
2765         div = __raw_readl(MXC_CCM_CSCMR2) &
2766                 MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
2767
2768         if (div)
2769                 return clk_get_rate(clk->parent) / 7;
2770
2771         return (2 * clk_get_rate(clk->parent)) / 7;
2772 }
2773
2774 static int _clk_ldb_di1_set_rate(struct clk *clk, unsigned long rate)
2775 {
2776         u32 reg, div = 0;
2777         u32 parent_rate = clk_get_rate(clk->parent);
2778
2779         if (rate * 7 <= parent_rate + parent_rate/20) {
2780                 div = 7;
2781                 rate = parent_rate / 7;
2782         } else
2783                 rate = 2 * parent_rate / 7;
2784
2785         reg = __raw_readl(MXC_CCM_CSCMR2);
2786         if (div == 7)
2787                 reg |= MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
2788         else
2789                 reg &= ~MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
2790
2791         __raw_writel(reg, MXC_CCM_CSCMR2);
2792
2793         return 0;
2794 }
2795
2796 static int _clk_ldb_di1_set_parent(struct clk *clk, struct clk *parent)
2797 {
2798         u32 reg, mux;
2799
2800         reg = __raw_readl(MXC_CCM_CS2CDR)
2801                 & ~MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK;
2802
2803         mux = _get_mux6(parent, &pll5_video_main_clk,
2804                 &pll2_pfd_352M, &pll2_pfd_400M, &pll3_pfd_540M,
2805                 &pll3_usb_otg_main_clk, NULL);
2806         reg |= (mux << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
2807
2808         __raw_writel(reg, MXC_CCM_CS2CDR);
2809
2810         return 0;
2811 }
2812
2813 static struct clk ldb_di1_clk = {
2814          __INIT_CLK_DEBUG(ldb_di1_clk)
2815         .id = 0,
2816         .parent = &pll3_pfd_540M,
2817         .enable_reg = MXC_CCM_CCGR3,
2818         .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
2819         .enable = _clk_enable,
2820         .disable = _clk_disable,
2821         .set_parent = _clk_ldb_di1_set_parent,
2822         .set_rate = _clk_ldb_di1_set_rate,
2823         .round_rate = _clk_ldb_di_round_rate,
2824         .get_rate = _clk_ldb_di1_get_rate,
2825         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
2826 };
2827
2828
2829 static unsigned long _clk_ipu_di_round_rate(struct clk *clk,
2830                                                 unsigned long rate)
2831 {
2832         u32 div;
2833         u32 parent_rate = clk_get_rate(clk->parent);
2834
2835         if ((clk->parent == &ldb_di0_clk) ||
2836                 (clk->parent == &ldb_di1_clk))
2837                 return parent_rate;
2838
2839         div = parent_rate / rate;
2840         /* Round to closest divisor */
2841         if ((parent_rate % rate) > (rate / 2))
2842                 div++;
2843
2844         /* Make sure rate is not greater than the maximum value for the clock.
2845          * Also prevent a div of 0.
2846          */
2847         if (div == 0)
2848                 div++;
2849
2850         if (div > 8)
2851                 div = 8;
2852
2853         return parent_rate / div;
2854 }
2855
2856 static unsigned long _clk_ipu1_di0_get_rate(struct clk *clk)
2857 {
2858         u32 reg, div;
2859
2860         if ((clk->parent == &ldb_di0_clk) ||
2861                 (clk->parent == &ldb_di1_clk))
2862                 return clk_get_rate(clk->parent);
2863
2864         reg = __raw_readl(MXC_CCM_CHSCCDR);
2865
2866         div = ((reg & MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK) >>
2867                          MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET) + 1;
2868
2869         return clk_get_rate(clk->parent) / div;
2870 }
2871
2872 static int _clk_ipu1_di0_set_rate(struct clk *clk, unsigned long rate)
2873 {
2874         u32 reg, div;
2875         u32 parent_rate = clk_get_rate(clk->parent);
2876
2877         if ((clk->parent == &ldb_di0_clk) ||
2878                 (clk->parent == &ldb_di1_clk)) {
2879                 if (parent_rate == rate)
2880                         return 0;
2881                 else
2882                         return -EINVAL;
2883         }
2884
2885         div = parent_rate / rate;
2886         if (div == 0)
2887                 div++;
2888         if (((parent_rate / div) != rate) || (div > 8))
2889                 return -EINVAL;
2890
2891         reg = __raw_readl(MXC_CCM_CHSCCDR);
2892         reg &= ~MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK;
2893         reg |= (div - 1) << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET;
2894         __raw_writel(reg, MXC_CCM_CHSCCDR);
2895
2896         return 0;
2897 }
2898
2899
2900 static int _clk_ipu1_di0_set_parent(struct clk *clk, struct clk *parent)
2901 {
2902         u32 reg, mux;
2903
2904         if (parent == &ldb_di0_clk)
2905                 mux = 0x3;
2906         else if (parent == &ldb_di1_clk)
2907                 mux = 0x4;
2908         else {
2909                 reg = __raw_readl(MXC_CCM_CHSCCDR)
2910                         & ~MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK;
2911
2912                 mux = _get_mux6(parent, &mmdc_ch0_axi_clk[0],
2913                                 &pll3_usb_otg_main_clk, &pll5_video_main_clk,
2914                                 &pll2_pfd_352M, &pll2_pfd_400M, &pll3_pfd_540M);
2915                 reg |= (mux << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
2916
2917                 __raw_writel(reg, MXC_CCM_CHSCCDR);
2918
2919                 /* Derive clock from divided pre-muxed ipu1_di0 clock.*/
2920                 mux = 0;
2921         }
2922
2923         reg = __raw_readl(MXC_CCM_CHSCCDR)
2924                 & ~MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK;
2925         __raw_writel(reg | (mux << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET),
2926                 MXC_CCM_CHSCCDR);
2927
2928         return 0;
2929 }
2930
2931 static unsigned long _clk_ipu1_di1_get_rate(struct clk *clk)
2932 {
2933         u32 reg, div;
2934
2935         if ((clk->parent == &ldb_di0_clk) ||
2936                 (clk->parent == &ldb_di1_clk))
2937                 return clk_get_rate(clk->parent);
2938
2939         reg = __raw_readl(MXC_CCM_CHSCCDR);
2940
2941         div = ((reg & MXC_CCM_CHSCCDR_IPU1_DI1_PODF_MASK)
2942                         >> MXC_CCM_CHSCCDR_IPU1_DI1_PODF_OFFSET) + 1;
2943
2944         return clk_get_rate(clk->parent) / div;
2945 }
2946
2947 static int _clk_ipu1_di1_set_rate(struct clk *clk, unsigned long rate)
2948 {
2949         u32 reg, div;
2950         u32 parent_rate = clk_get_rate(clk->parent);
2951
2952         if ((clk->parent == &ldb_di0_clk) ||
2953                 (clk->parent == &ldb_di1_clk)) {
2954                 if (parent_rate == rate)
2955                         return 0;
2956                 else
2957                         return -EINVAL;
2958         }
2959
2960         div = parent_rate / rate;
2961         if (div == 0)
2962                 div++;
2963         if (((parent_rate / div) != rate) || (div > 8))
2964                 return -EINVAL;
2965
2966         reg = __raw_readl(MXC_CCM_CHSCCDR);
2967         reg &= ~MXC_CCM_CHSCCDR_IPU1_DI1_PODF_MASK;
2968         reg |= (div - 1) << MXC_CCM_CHSCCDR_IPU1_DI1_PODF_OFFSET;
2969         __raw_writel(reg, MXC_CCM_CHSCCDR);
2970
2971         return 0;
2972 }
2973
2974
2975 static int _clk_ipu1_di1_set_parent(struct clk *clk, struct clk *parent)
2976 {
2977         u32 reg, mux;
2978
2979         if (parent == &ldb_di0_clk)
2980                 mux = 0x3;
2981         else if (parent == &ldb_di1_clk)
2982                 mux = 0x4;
2983         else {
2984                 reg = __raw_readl(MXC_CCM_CHSCCDR)
2985                         & ~MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_MASK;
2986
2987                 mux = _get_mux6(parent, &mmdc_ch0_axi_clk[0],
2988                                 &pll3_usb_otg_main_clk, &pll5_video_main_clk,
2989                                 &pll2_pfd_352M, &pll2_pfd_400M, &pll3_pfd_540M);
2990                 reg |= (mux << MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_OFFSET);
2991
2992                 __raw_writel(reg, MXC_CCM_CHSCCDR);
2993
2994                 /* Derive clock from divided pre-muxed ipu1_di0 clock.*/
2995                 mux = 0;
2996         }
2997         reg = __raw_readl(MXC_CCM_CHSCCDR)
2998                 & ~MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_MASK;
2999         __raw_writel(reg | (mux << MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET),
3000                 MXC_CCM_CHSCCDR);
3001
3002         return 0;
3003 }
3004
3005 static struct clk ipu1_di_clk[] = {
3006         {
3007          __INIT_CLK_DEBUG(ipu1_di_clk_0)
3008         .id = 0,
3009         .parent = &pll5_video_main_clk,
3010         .enable_reg = MXC_CCM_CCGR3,
3011         .enable_shift = MXC_CCM_CCGRx_CG1_OFFSET,
3012         .enable = _clk_enable,
3013         .disable = _clk_disable,
3014         .set_parent = _clk_ipu1_di0_set_parent,
3015         .set_rate = _clk_ipu1_di0_set_rate,
3016         .round_rate = _clk_ipu_di_round_rate,
3017         .get_rate = _clk_ipu1_di0_get_rate,
3018         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
3019         },
3020         {
3021          __INIT_CLK_DEBUG(ipu1_di_clk_1)
3022         .id = 1,
3023         .parent = &pll5_video_main_clk,
3024         .enable_reg = MXC_CCM_CCGR3,
3025         .enable_shift = MXC_CCM_CCGRx_CG2_OFFSET,
3026         .enable = _clk_enable,
3027         .disable = _clk_disable,
3028         .set_parent = _clk_ipu1_di1_set_parent,
3029         .set_rate = _clk_ipu1_di1_set_rate,
3030         .round_rate = _clk_ipu_di_round_rate,
3031         .get_rate = _clk_ipu1_di1_get_rate,
3032         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
3033         },
3034 };
3035
3036 static unsigned long _clk_ipu2_di0_get_rate(struct clk *clk)
3037 {
3038         u32 reg, div;
3039
3040         if ((clk->parent == &ldb_di0_clk) ||
3041                 (clk->parent == &ldb_di1_clk))
3042                 return clk_get_rate(clk->parent);
3043
3044         reg = __raw_readl(MXC_CCM_CSCDR2);
3045
3046         div = ((reg & MXC_CCM_CSCDR2_IPU2_DI0_PODF_MASK) >>
3047                         MXC_CCM_CSCDR2_IPU2_DI0_PODF_OFFSET) + 1;
3048
3049         return clk_get_rate(clk->parent) / div;
3050 }
3051
3052 static int _clk_ipu2_di0_set_rate(struct clk *clk, unsigned long rate)
3053 {
3054         u32 reg, div;
3055         u32 parent_rate = clk_get_rate(clk->parent);
3056
3057         if ((clk->parent == &ldb_di0_clk) ||
3058                 (clk->parent == &ldb_di1_clk)) {
3059                 if (parent_rate == rate)
3060                         return 0;
3061                 else
3062                         return -EINVAL;
3063         }
3064
3065         div = parent_rate / rate;
3066         if (div == 0)
3067                 div++;
3068         if (((parent_rate / div) != rate) || (div > 8))
3069                 return -EINVAL;
3070
3071         reg = __raw_readl(MXC_CCM_CSCDR2);
3072         reg &= ~MXC_CCM_CSCDR2_IPU2_DI0_PODF_MASK;
3073         reg |= (div - 1) << MXC_CCM_CSCDR2_IPU2_DI0_PODF_OFFSET;
3074         __raw_writel(reg, MXC_CCM_CSCDR2);
3075
3076         return 0;
3077 }
3078
3079 static int _clk_ipu2_di0_set_parent(struct clk *clk, struct clk *parent)
3080 {
3081         u32 reg, mux;
3082
3083         if (parent == &ldb_di0_clk)
3084                 mux = 0x3;
3085         else if (parent == &ldb_di1_clk)
3086                 mux = 0x4;
3087         else {
3088                 reg = __raw_readl(MXC_CCM_CSCDR2)
3089                         & ~MXC_CCM_CSCDR2_IPU2_DI0_PRE_CLK_SEL_MASK;
3090
3091                 mux = _get_mux6(parent, &mmdc_ch0_axi_clk[0],
3092                                 &pll3_usb_otg_main_clk, &pll5_video_main_clk,
3093                                 &pll2_pfd_352M, &pll2_pfd_400M, &pll3_pfd_540M);
3094                 reg |= (mux << MXC_CCM_CSCDR2_IPU2_DI0_PRE_CLK_SEL_OFFSET);
3095
3096                 __raw_writel(reg, MXC_CCM_CSCDR2);
3097
3098                 /* Derive clock from divided pre-muxed ipu2_di0 clock.*/
3099                 mux = 0;
3100         }
3101         reg = __raw_readl(MXC_CCM_CSCDR2)
3102                 & ~MXC_CCM_CSCDR2_IPU2_DI0_CLK_SEL_MASK;
3103         __raw_writel(reg | (mux << MXC_CCM_CSCDR2_IPU2_DI0_CLK_SEL_OFFSET),
3104                 MXC_CCM_CSCDR2);
3105
3106         return 0;
3107 }
3108
3109 static unsigned long _clk_ipu2_di1_get_rate(struct clk *clk)
3110 {
3111         u32 reg, div;
3112
3113         if ((clk->parent == &ldb_di0_clk) ||
3114                 (clk->parent == &ldb_di1_clk))
3115                 return clk_get_rate(clk->parent);
3116
3117         reg = __raw_readl(MXC_CCM_CSCDR2);
3118
3119         div = ((reg & MXC_CCM_CSCDR2_IPU2_DI1_PODF_MASK)
3120                 >> MXC_CCM_CSCDR2_IPU2_DI1_PODF_OFFSET) + 1;
3121
3122         return clk_get_rate(clk->parent) / div;
3123 }
3124
3125 static int _clk_ipu2_di1_set_rate(struct clk *clk, unsigned long rate)
3126 {
3127         u32 reg, div;
3128         u32 parent_rate = clk_get_rate(clk->parent);
3129
3130         if ((clk->parent == &ldb_di0_clk) ||
3131                 (clk->parent == &ldb_di1_clk)) {
3132                 if (parent_rate == rate)
3133                         return 0;
3134                 else
3135                         return -EINVAL;
3136         }
3137
3138         div = parent_rate / rate;
3139         if (div == 0)
3140                 div++;
3141         if (((parent_rate / div) != rate) || (div > 8))
3142                 return -EINVAL;
3143
3144         reg = __raw_readl(MXC_CCM_CSCDR2);
3145         reg &= ~MXC_CCM_CSCDR2_IPU2_DI1_PODF_MASK;
3146         reg |= (div - 1) << MXC_CCM_CSCDR2_IPU2_DI1_PODF_OFFSET;
3147         __raw_writel(reg, MXC_CCM_CSCDR2);
3148
3149         return 0;
3150 }
3151
3152 static int _clk_ipu2_di1_set_parent(struct clk *clk, struct clk *parent)
3153 {
3154         u32 reg, mux;
3155
3156         if (parent == &ldb_di0_clk)
3157                 mux = 0x3;
3158         else if (parent == &ldb_di1_clk)
3159                 mux = 0x4;
3160         else {
3161                 reg = __raw_readl(MXC_CCM_CSCDR2)
3162                         & ~MXC_CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_MASK;
3163
3164                 mux = _get_mux6(parent, &mmdc_ch0_axi_clk[0],
3165                                 &pll3_usb_otg_main_clk, &pll5_video_main_clk,
3166                                 &pll2_pfd_352M, &pll2_pfd_400M, &pll3_pfd_540M);
3167                 reg |= (mux << MXC_CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_OFFSET);
3168
3169                 __raw_writel(reg, MXC_CCM_CSCDR2);
3170
3171                 /* Derive clock from divided pre-muxed ipu1_di0 clock.*/
3172                 mux = 0;
3173         }
3174         reg = __raw_readl(MXC_CCM_CSCDR2)
3175                 & ~MXC_CCM_CSCDR2_IPU2_DI1_CLK_SEL_MASK;
3176         __raw_writel(reg | (mux << MXC_CCM_CSCDR2_IPU2_DI1_CLK_SEL_OFFSET),
3177                 MXC_CCM_CSCDR2);
3178
3179         return 0;
3180 }
3181
3182 static struct clk ipu2_di_clk[] = {
3183         {
3184          __INIT_CLK_DEBUG(ipu2_di_clk_0)
3185         .id = 0,
3186         .parent = &pll5_video_main_clk,
3187         .enable_reg = MXC_CCM_CCGR3,
3188         .enable_shift = MXC_CCM_CCGRx_CG4_OFFSET,
3189         .enable = _clk_enable,
3190         .disable = _clk_disable,
3191         .set_parent = _clk_ipu2_di0_set_parent,
3192         .set_rate = _clk_ipu2_di0_set_rate,
3193         .round_rate = _clk_ipu_di_round_rate,
3194         .get_rate = _clk_ipu2_di0_get_rate,
3195         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
3196         },
3197         {
3198          __INIT_CLK_DEBUG(ipu2_di_clk_1)
3199         .id = 1,
3200         .parent = &pll5_video_main_clk,
3201         .enable_reg = MXC_CCM_CCGR3,
3202         .enable_shift = MXC_CCM_CCGRx_CG5_OFFSET,
3203         .enable = _clk_enable,
3204         .disable = _clk_disable,
3205         .set_parent = _clk_ipu2_di1_set_parent,
3206         .set_rate = _clk_ipu2_di1_set_rate,
3207         .round_rate = _clk_ipu_di_round_rate,
3208         .get_rate = _clk_ipu2_di1_get_rate,
3209         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
3210         },
3211 };
3212
3213 static unsigned long _clk_can_root_round_rate(struct clk *clk,
3214                                                 unsigned long rate)
3215 {
3216         u32 div;
3217         u32 parent_rate = clk_get_rate(clk->parent);
3218
3219         div = parent_rate / rate;
3220
3221         /* Make sure rate is not greater than the maximum value for the clock.
3222          * Also prevent a div of 0.
3223          */
3224         if (div == 0)
3225                 div++;
3226
3227         if (div > 64)
3228                 div = 64;
3229
3230         return parent_rate / div;
3231 }
3232
3233 static int _clk_can_root_set_rate(struct clk *clk, unsigned long rate)
3234 {
3235         u32 reg, div;
3236         u32 parent_rate = clk_get_rate(clk->parent);
3237
3238         div = parent_rate / rate;
3239         if (div == 0)
3240                 div++;
3241         if (((parent_rate / div) != rate) || (div > 64))
3242                 return -EINVAL;
3243
3244         reg = __raw_readl(MXC_CCM_CSCMR2) & MXC_CCM_CSCMR2_CAN_CLK_PODF_MASK;
3245         reg |= ((div - 1) << MXC_CCM_CSCMR2_CAN_CLK_PODF_OFFSET);
3246
3247         __raw_writel(reg, MXC_CCM_CSCMR2);
3248
3249         return 0;
3250 }
3251
3252 static unsigned long _clk_can_root_get_rate(struct clk *clk)
3253 {
3254         u32 reg, div;
3255         unsigned long val;
3256
3257         reg = __raw_readl(MXC_CCM_CSCMR2) & MXC_CCM_CSCMR2_CAN_CLK_PODF_MASK;
3258         div = (reg >> MXC_CCM_CSCMR2_CAN_CLK_PODF_OFFSET) + 1;
3259         val = clk_get_rate(clk->parent) / div;
3260
3261         return val;
3262 }
3263
3264 static struct clk can_clk_root = {
3265          __INIT_CLK_DEBUG(can_clk_root)
3266         .parent = &pll3_60M,
3267         .set_rate = _clk_can_root_set_rate,
3268         .get_rate = _clk_can_root_get_rate,
3269         .round_rate = _clk_can_root_round_rate,
3270 };
3271
3272 static struct clk can2_clk[] = {
3273         {
3274          __INIT_CLK_DEBUG(can2_module_clk)
3275         .id = 0,
3276         .parent = &can_clk_root,
3277         .enable_reg = MXC_CCM_CCGR0,
3278         .enable_shift = MXC_CCM_CCGRx_CG9_OFFSET,
3279         .enable = _clk_enable,
3280         .disable = _clk_disable,
3281         .secondary = &can2_clk[1],
3282         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
3283         },
3284         {
3285          __INIT_CLK_DEBUG(can2_serial_clk)
3286         .id = 1,
3287         .parent = &can_clk_root,
3288         .enable_reg = MXC_CCM_CCGR0,
3289         .enable_shift = MXC_CCM_CCGRx_CG10_OFFSET,
3290         .enable = _clk_enable,
3291         .disable = _clk_disable,
3292         },
3293 };
3294
3295
3296 static struct clk can1_clk[] = {
3297         {
3298          __INIT_CLK_DEBUG(can1_module_clk)
3299         .id = 0,
3300         .parent = &can_clk_root,
3301         .enable_reg = MXC_CCM_CCGR0,
3302         .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
3303         .enable = _clk_enable,
3304         .disable = _clk_disable,
3305         .secondary = &can1_clk[1],
3306         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
3307         },
3308         {
3309          __INIT_CLK_DEBUG(can1_serial_clk)
3310         .id = 1,
3311         .parent = &can_clk_root,
3312         .enable_reg = MXC_CCM_CCGR0,
3313         .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET,
3314         .enable = _clk_enable,
3315         .disable = _clk_disable,
3316         },
3317 };
3318
3319 static unsigned long _clk_spdif_round_rate(struct clk *clk,
3320                                                 unsigned long rate)
3321 {
3322         u32 pre, post;
3323         u32 parent_rate = clk_get_rate(clk->parent);
3324         u32 div = parent_rate / rate;
3325
3326         if (parent_rate % rate)
3327                 div++;
3328
3329         __calc_pre_post_dividers(1 << 3, div, &pre, &post);
3330
3331         return parent_rate / (pre * post);
3332 }
3333
3334 static int _clk_spdif0_set_parent(struct clk *clk, struct clk *parent)
3335 {
3336         u32 reg, mux;
3337
3338         reg = __raw_readl(MXC_CCM_CDCDR)
3339                 & ~MXC_CCM_CDCDR_SPDIF0_CLK_SEL_MASK;
3340
3341         mux = _get_mux6(parent, &pll4_audio_main_clk,
3342                 &pll3_pfd_508M, &pll3_pfd_454M,
3343                 &pll3_sw_clk, NULL, NULL);
3344         reg |= mux << MXC_CCM_CDCDR_SPDIF0_CLK_SEL_OFFSET;
3345
3346         __raw_writel(reg, MXC_CCM_CDCDR);
3347
3348         return 0;
3349 }
3350
3351 static unsigned long _clk_spdif0_get_rate(struct clk *clk)
3352 {
3353         u32 reg, pred, podf;
3354
3355         reg = __raw_readl(MXC_CCM_CDCDR);
3356
3357         pred = ((reg & MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK)
3358                 >> MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET) + 1;
3359         podf = ((reg & MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK)
3360                 >> MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET) + 1;
3361
3362         return clk_get_rate(clk->parent) / (pred * podf);
3363 }
3364
3365 static int _clk_spdif0_set_rate(struct clk *clk, unsigned long rate)
3366 {
3367         u32 reg, div, pre, post;
3368         u32 parent_rate = clk_get_rate(clk->parent);
3369
3370         div = parent_rate / rate;
3371         if (div == 0)
3372                 div++;
3373         if (((parent_rate / div) != rate) || div > 64)
3374                 return -EINVAL;
3375
3376         __calc_pre_post_dividers(1 << 3, div, &pre, &post);
3377
3378         reg = __raw_readl(MXC_CCM_CDCDR);
3379         reg &= ~(MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK|
3380                  MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK);
3381         reg |= (post - 1) << MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET;
3382         reg |= (pre - 1) << MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET;
3383
3384         __raw_writel(reg, MXC_CCM_CDCDR);
3385
3386         return 0;
3387 }
3388
3389 static struct clk spdif0_clk[] = {
3390         {
3391         __INIT_CLK_DEBUG(spdif0_clk_0)
3392         .id = 0,
3393         .parent = &pll3_sw_clk,
3394          .enable = _clk_enable,
3395          .enable_reg = MXC_CCM_CCGR5,
3396          .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
3397          .disable = _clk_disable,
3398          .secondary = &spdif0_clk[1],
3399          .set_rate = _clk_spdif0_set_rate,
3400          .get_rate = _clk_spdif0_get_rate,
3401          .set_parent = _clk_spdif0_set_parent,
3402          .round_rate = _clk_spdif_round_rate,
3403         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
3404         },
3405         {
3406         __INIT_CLK_DEBUG(spdif0_clk_1)
3407          .id = 1,
3408          .parent = &ipg_clk,
3409          .secondary = &spba_clk,
3410          },
3411 };
3412
3413 static unsigned long _clk_esai_round_rate(struct clk *clk,
3414                                                 unsigned long rate)
3415 {
3416         u32 pre, post;
3417         u32 parent_rate = clk_get_rate(clk->parent);
3418         u32 div = parent_rate / rate;
3419
3420         if (parent_rate % rate)
3421                 div++;
3422
3423         __calc_pre_post_dividers(1 << 3, div, &pre, &post);
3424
3425         return parent_rate / (pre * post);
3426 }
3427
3428 static int _clk_esai_set_parent(struct clk *clk, struct clk *parent)
3429 {
3430         u32 reg, mux;
3431
3432         reg = __raw_readl(MXC_CCM_CSCMR2) & ~MXC_CCM_CSCMR2_ESAI_CLK_SEL_MASK;
3433
3434         mux = _get_mux6(parent, &pll4_audio_main_clk, &pll3_pfd_508M,
3435                         &pll3_pfd_454M, &pll3_sw_clk, NULL, NULL);
3436         reg |= mux << MXC_CCM_CSCMR2_ESAI_CLK_SEL_OFFSET;
3437
3438         __raw_writel(reg, MXC_CCM_CSCMR2);
3439
3440         return 0;
3441 }
3442
3443 static unsigned long _clk_esai_get_rate(struct clk *clk)
3444 {
3445         u32 reg, pred, podf;
3446
3447         reg = __raw_readl(MXC_CCM_CS1CDR);
3448
3449         pred = ((reg & MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK)
3450                 >> MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET) + 1;
3451         podf = ((reg & MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK)
3452                 >> MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET) + 1;
3453
3454         return clk_get_rate(clk->parent) / (pred * podf);
3455 }
3456
3457 static int _clk_esai_set_rate(struct clk *clk, unsigned long rate)
3458 {
3459         u32 reg, div, pre, post;
3460         u32 parent_rate = clk_get_rate(clk->parent);
3461
3462         div = parent_rate / rate;
3463         if (div == 0)
3464                 div++;
3465         if (((parent_rate / div) != rate) || div > 64)
3466                 return -EINVAL;
3467
3468         __calc_pre_post_dividers(1 << 3, div, &pre, &post);
3469
3470         reg = __raw_readl(MXC_CCM_CS1CDR);
3471         reg &= ~(MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK|
3472                  MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK);
3473         reg |= (post - 1) << MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET;
3474         reg |= (pre - 1) << MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET;
3475
3476         __raw_writel(reg, MXC_CCM_CS1CDR);
3477
3478         return 0;
3479 }
3480
3481 static struct clk esai_clk = {
3482         __INIT_CLK_DEBUG(esai_clk)
3483          .id = 0,
3484          .parent = &pll3_sw_clk,
3485          .secondary = &spba_clk,
3486          .enable_reg = MXC_CCM_CCGR1,
3487          .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET,
3488          .enable = _clk_enable,
3489          .disable = _clk_disable,
3490          .set_rate = _clk_esai_set_rate,
3491          .get_rate = _clk_esai_get_rate,
3492          .set_parent = _clk_esai_set_parent,
3493          .round_rate = _clk_esai_round_rate,
3494 };
3495
3496 static int _clk_enet_enable(struct clk *clk)
3497 {
3498         unsigned int reg;
3499
3500         /* Enable ENET ref clock */
3501         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
3502         reg &= ~ANADIG_PLL_BYPASS;
3503         reg |= ANADIG_PLL_ENABLE;
3504         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
3505
3506         _clk_enable(clk);
3507         return 0;
3508 }
3509
3510 static void _clk_enet_disable(struct clk *clk)
3511 {
3512         unsigned int reg;
3513
3514         _clk_disable(clk);
3515
3516         /* Enable ENET ref clock */
3517         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
3518         reg |= ANADIG_PLL_BYPASS;
3519         reg &= ~ANADIG_PLL_ENABLE;
3520         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
3521 }
3522
3523 static int _clk_enet_set_rate(struct clk *clk, unsigned long rate)
3524 {
3525         unsigned int reg, div = 1;
3526
3527         switch (rate) {
3528         case 25000000:
3529                 div = 0;
3530                 break;
3531         case 50000000:
3532                 div = 1;
3533                 break;
3534         case 100000000:
3535                 div = 2;
3536                 break;
3537         case 125000000:
3538                 div = 3;
3539                 break;
3540         default:
3541                 return -EINVAL;
3542         }
3543         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
3544         reg &= ~ANADIG_PLL_ENET_DIV_SELECT_MASK;
3545         reg |= (div << ANADIG_PLL_ENET_DIV_SELECT_OFFSET);
3546         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
3547
3548         return 0;
3549 }
3550
3551 static unsigned long _clk_enet_get_rate(struct clk *clk)
3552 {
3553         unsigned int div;
3554
3555         div = (__raw_readl(PLL8_ENET_BASE_ADDR))
3556                 & ANADIG_PLL_ENET_DIV_SELECT_MASK;
3557
3558         switch (div) {
3559         case 0:
3560                 div = 20;
3561                 break;
3562         case 1:
3563                 div = 10;
3564                 break;
3565         case 3:
3566                 div = 5;
3567                 break;
3568         case 4:
3569                 div = 4;
3570                 break;
3571         }
3572
3573         return 500000000 / div;
3574 }
3575
3576 static struct clk enet_clk[] = {
3577         {
3578         __INIT_CLK_DEBUG(enet_clk)
3579          .id = 0,
3580          .parent = &pll8_enet_main_clk,
3581          .enable_reg = MXC_CCM_CCGR1,
3582          .enable_shift = MXC_CCM_CCGRx_CG5_OFFSET,
3583          .enable = _clk_enet_enable,
3584          .disable = _clk_enet_disable,
3585          .set_rate = _clk_enet_set_rate,
3586          .get_rate = _clk_enet_get_rate,
3587         .secondary = &enet_clk[1],
3588         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
3589         },
3590         {
3591         .parent = &mmdc_ch0_axi_clk[0],
3592         .secondary = &mx6per1_clk,
3593         },
3594 };
3595
3596 static struct clk ecspi_clk[] = {
3597         {
3598         __INIT_CLK_DEBUG(ecspi0_clk)
3599         .id = 0,
3600         .parent = &pll3_60M,
3601         .secondary = &spba_clk,
3602         .enable_reg = MXC_CCM_CCGR1,
3603         .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET,
3604         .enable = _clk_enable,
3605         .disable = _clk_disable,
3606         },
3607         {
3608         __INIT_CLK_DEBUG(ecspi1_clk)
3609         .id = 1,
3610         .parent = &pll3_60M,
3611         .secondary = &spba_clk,
3612         .enable_reg = MXC_CCM_CCGR1,
3613         .enable_shift = MXC_CCM_CCGRx_CG1_OFFSET,
3614         .enable = _clk_enable,
3615         .disable = _clk_disable,
3616         },
3617         {
3618         __INIT_CLK_DEBUG(ecspi2_clk)
3619         .id = 2,
3620         .parent = &pll3_60M,
3621         .secondary = &spba_clk,
3622         .enable_reg = MXC_CCM_CCGR1,
3623         .enable_shift = MXC_CCM_CCGRx_CG2_OFFSET,
3624         .enable = _clk_enable,
3625         .disable = _clk_disable,
3626         },
3627         {
3628         __INIT_CLK_DEBUG(ecspi3_clk)
3629         .id = 3,
3630         .parent = &pll3_60M,
3631         .secondary = &spba_clk,
3632         .enable_reg = MXC_CCM_CCGR1,
3633         .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET,
3634         .enable = _clk_enable,
3635         .disable = _clk_disable,
3636         },
3637         {
3638         __INIT_CLK_DEBUG(ecspi4_clk)
3639         .id = 4,
3640         .parent = &pll3_60M,
3641         .secondary = &spba_clk,
3642         .enable_reg = MXC_CCM_CCGR1,
3643         .enable_shift = MXC_CCM_CCGRx_CG4_OFFSET,
3644         .enable = _clk_enable,
3645         .disable = _clk_disable,
3646         },
3647 };
3648
3649 static unsigned long _clk_emi_slow_round_rate(struct clk *clk,
3650                                                 unsigned long rate)
3651 {
3652         u32 div;
3653         u32 parent_rate = clk_get_rate(clk->parent);
3654
3655         div = parent_rate / rate;
3656
3657         /* Make sure rate is not greater than the maximum value for the clock.
3658          * Also prevent a div of 0.
3659          */
3660         if (div == 0)
3661                 div++;
3662
3663         if (div > 8)
3664                 div = 8;
3665
3666         return parent_rate / div;
3667 }
3668
3669 static int _clk_emi_slow_set_parent(struct clk *clk, struct clk *parent)
3670 {
3671         int mux;
3672         u32 reg = __raw_readl(MXC_CCM_CSCMR1)
3673                 & ~MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK;
3674
3675         mux = _get_mux6(parent, &axi_clk, &pll3_usb_otg_main_clk,
3676                                 &pll2_pfd_400M, &pll2_pfd_352M, NULL, NULL);
3677         reg |= (mux << MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET);
3678         __raw_writel(reg, MXC_CCM_CSCMR1);
3679
3680         return 0;
3681 }
3682
3683 static unsigned long _clk_emi_slow_get_rate(struct clk *clk)
3684 {
3685         u32 reg, div;
3686
3687         reg = __raw_readl(MXC_CCM_CSCMR1);
3688         div = ((reg & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK) >>
3689                         MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET) + 1;
3690
3691         return clk_get_rate(clk->parent) / div;
3692 }
3693
3694 static int _clk_emi_slow_set_rate(struct clk *clk, unsigned long rate)
3695 {
3696         u32 reg, div;
3697         u32 parent_rate = clk_get_rate(clk->parent);
3698
3699         div = parent_rate / rate;
3700         if (div == 0)
3701                 div++;
3702         if (((parent_rate / div) != rate) || (div > 8))
3703                 return -EINVAL;
3704
3705         reg = __raw_readl(MXC_CCM_CSCMR1);
3706         reg &= ~MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK;
3707         reg |= (div - 1) << MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET;
3708         __raw_writel(reg, MXC_CCM_CSCMR1);
3709
3710         return 0;
3711 }
3712
3713 static struct clk emi_slow_clk = {
3714         __INIT_CLK_DEBUG(emi_slow_clk)
3715          .id = 0,
3716          .parent = &axi_clk,
3717          .enable_reg = MXC_CCM_CCGR6,
3718          .enable_shift = MXC_CCM_CCGRx_CG5_OFFSET,
3719          .enable = _clk_enable,
3720          .disable = _clk_disable,
3721          .set_rate = _clk_emi_slow_set_rate,
3722          .get_rate = _clk_emi_slow_get_rate,
3723          .round_rate = _clk_emi_slow_round_rate,
3724          .set_parent = _clk_emi_slow_set_parent,
3725 };
3726
3727 static unsigned long _clk_emi_round_rate(struct clk *clk,
3728                                                 unsigned long rate)
3729 {
3730         u32 div;
3731         u32 parent_rate = clk_get_rate(clk->parent);
3732
3733         div = parent_rate / rate;
3734
3735         /* Make sure rate is not greater than the maximum value for the clock.
3736          * Also prevent a div of 0.
3737          */
3738         if (div == 0)
3739                 div++;
3740
3741         if (div > 8)
3742                 div = 8;
3743
3744         return parent_rate / div;
3745 }
3746
3747 static int _clk_emi_set_parent(struct clk *clk, struct clk *parent)
3748 {
3749         int mux;
3750         u32 reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_ACLK_EMI_MASK;
3751
3752         mux = _get_mux6(parent, &axi_clk, &pll3_usb_otg_main_clk,
3753                         &pll2_pfd_400M, &pll2_pfd_352M, NULL, NULL);
3754         reg |= (mux << MXC_CCM_CSCMR1_ACLK_EMI_OFFSET);
3755         __raw_writel(reg, MXC_CCM_CSCMR1);
3756
3757         return 0;
3758 }
3759
3760 static unsigned long _clk_emi_get_rate(struct clk *clk)
3761 {
3762         u32 reg, div;
3763
3764         reg = __raw_readl(MXC_CCM_CSCMR1);
3765         div = ((reg & MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK) >>
3766                         MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET) + 1;
3767
3768         return clk_get_rate(clk->parent) / div;
3769 }
3770
3771 static int _clk_emi_set_rate(struct clk *clk, unsigned long rate)
3772 {
3773         u32 reg, div;
3774         u32 parent_rate = clk_get_rate(clk->parent);
3775
3776         div = parent_rate / rate;
3777         if (div == 0)
3778                 div++;
3779         if (((parent_rate / div) != rate) || (div > 8))
3780                 return -EINVAL;
3781
3782         reg = __raw_readl(MXC_CCM_CSCMR1);
3783         reg &= ~MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK;
3784         reg |= (div - 1) << MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET;
3785         __raw_writel(reg, MXC_CCM_CSCMR1);
3786
3787         return 0;
3788 }
3789
3790 static struct clk emi_clk = {
3791         __INIT_CLK_DEBUG(emi_clk)
3792          .id = 0,
3793          .parent = &axi_clk,
3794          .set_rate = _clk_emi_set_rate,
3795          .get_rate = _clk_emi_get_rate,
3796          .round_rate = _clk_emi_round_rate,
3797          .set_parent = _clk_emi_set_parent,
3798 };
3799
3800 static unsigned long _clk_enfc_round_rate(struct clk *clk,
3801                                                 unsigned long rate)
3802 {
3803         u32 pre, post;
3804         u32 parent_rate = clk_get_rate(clk->parent);
3805         u32 div = parent_rate / rate;
3806
3807         if (parent_rate % rate)
3808                 div++;
3809
3810         __calc_pre_post_dividers(1 << 6, div, &pre, &post);
3811
3812         return parent_rate / (pre * post);
3813 }
3814
3815 static int _clk_enfc_set_parent(struct clk *clk, struct clk *parent)
3816 {
3817         u32 reg, mux;
3818
3819         reg = __raw_readl(MXC_CCM_CS2CDR)
3820                 & ~MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK;
3821
3822         mux = _get_mux6(parent, &pll2_pfd_352M,
3823                 &pll2_528_bus_main_clk, &pll3_usb_otg_main_clk,
3824                 &pll2_pfd_400M, NULL, NULL);
3825         reg |= mux << MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET;
3826
3827         __raw_writel(reg, MXC_CCM_CS2CDR);
3828
3829         return 0;
3830 }
3831
3832 static unsigned long _clk_enfc_get_rate(struct clk *clk)
3833 {
3834         u32 reg, pred, podf;
3835
3836         reg = __raw_readl(MXC_CCM_CS2CDR);
3837
3838         pred = ((reg & MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK)
3839                 >> MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET) + 1;
3840         podf = ((reg & MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK)
3841                 >> MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET) + 1;
3842
3843         return clk_get_rate(clk->parent) / (pred * podf);
3844 }
3845
3846 static int _clk_enfc_set_rate(struct clk *clk, unsigned long rate)
3847 {
3848         u32 reg, div, pre, post;
3849         u32 parent_rate = clk_get_rate(clk->parent);
3850
3851         div = parent_rate / rate;
3852         if (div == 0)
3853                 div++;
3854         if (((parent_rate / div) != rate) || div > 512)
3855                 return -EINVAL;
3856
3857         __calc_pre_post_dividers(1 << 6, div, &pre, &post);
3858
3859         reg = __raw_readl(MXC_CCM_CS2CDR);
3860         reg &= ~(MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK|
3861                  MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK);
3862         reg |= (post - 1) << MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET;
3863         reg |= (pre - 1) << MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET;
3864
3865         __raw_writel(reg, MXC_CCM_CS2CDR);
3866
3867         return 0;
3868 }
3869
3870 static struct clk enfc_clk = {
3871         __INIT_CLK_DEBUG(enfc_clk)
3872          .id = 0,
3873          .parent = &pll2_pfd_352M,
3874          .enable_reg = MXC_CCM_CCGR2,
3875          .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
3876          .enable = _clk_enable,
3877          .disable = _clk_disable,
3878          .set_rate = _clk_enfc_set_rate,
3879          .get_rate = _clk_enfc_get_rate,
3880          .round_rate = _clk_enfc_round_rate,
3881          .set_parent = _clk_enfc_set_parent,
3882 };
3883
3884 static unsigned long _clk_uart_round_rate(struct clk *clk,
3885                                                 unsigned long rate)
3886 {
3887         u32 div;
3888         u32 parent_rate = clk_get_rate(clk->parent);
3889
3890         div = parent_rate / rate;
3891
3892         /* Make sure rate is not greater than the maximum value for the clock.
3893          * Also prevent a div of 0.
3894          */
3895         if (div == 0)
3896                 div++;
3897
3898         if (div > 64)
3899                 div = 64;
3900
3901         return parent_rate / div;
3902 }
3903
3904 static int _clk_uart_set_rate(struct clk *clk, unsigned long rate)
3905 {
3906         u32 reg, div;
3907         u32 parent_rate = clk_get_rate(clk->parent);
3908
3909         div = parent_rate / rate;
3910         if (div == 0)
3911                 div++;
3912         if (((parent_rate / div) != rate) || (div > 64))
3913                 return -EINVAL;
3914
3915         reg = __raw_readl(MXC_CCM_CSCDR1) & MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
3916         reg |= ((div - 1) << MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET);
3917
3918         __raw_writel(reg, MXC_CCM_CSCDR1);
3919
3920         return 0;
3921 }
3922
3923 static unsigned long _clk_uart_get_rate(struct clk *clk)
3924 {
3925         u32 reg, div;
3926         unsigned long val;
3927
3928         reg = __raw_readl(MXC_CCM_CSCDR1) & MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
3929         div = (reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET) + 1;
3930         val = clk_get_rate(clk->parent) / div;
3931
3932         return val;
3933 }
3934
3935 static struct clk uart_clk[] = {
3936         {
3937         __INIT_CLK_DEBUG(uart_clk)
3938          .id = 0,
3939          .parent = &pll3_80M,
3940          .enable_reg = MXC_CCM_CCGR5,
3941          .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET,
3942          .enable = _clk_enable,
3943          .disable = _clk_disable,
3944          .secondary = &uart_clk[1],
3945          .set_rate = _clk_uart_set_rate,
3946          .get_rate = _clk_uart_get_rate,
3947          .round_rate = _clk_uart_round_rate,
3948         },
3949         {
3950         __INIT_CLK_DEBUG(uart_serial_clk)
3951          .id = 1,
3952          .enable_reg = MXC_CCM_CCGR5,
3953          .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
3954          .enable = _clk_enable,
3955          .disable = _clk_disable,
3956         },
3957 };
3958
3959 static unsigned long _clk_hsi_tx_round_rate(struct clk *clk,
3960                                                 unsigned long rate)
3961 {
3962         u32 div;
3963         u32 parent_rate = clk_get_rate(clk->parent);
3964
3965         div = parent_rate / rate;
3966
3967         /* Make sure rate is not greater than the maximum value for the clock.
3968          * Also prevent a div of 0.
3969          */
3970         if (div == 0)
3971                 div++;
3972
3973         if (div > 8)
3974                 div = 8;
3975
3976         return parent_rate / div;
3977 }
3978
3979 static int _clk_hsi_tx_set_parent(struct clk *clk, struct clk *parent)
3980 {
3981         u32 reg = __raw_readl(MXC_CCM_CDCDR) & ~MXC_CCM_CDCDR_HSI_TX_CLK_SEL;
3982
3983         if (parent == &pll2_pfd_400M)
3984                 reg |= (MXC_CCM_CDCDR_HSI_TX_CLK_SEL);
3985
3986         __raw_writel(reg, MXC_CCM_CDCDR);
3987
3988         return 0;
3989 }
3990
3991 static unsigned long _clk_hsi_tx_get_rate(struct clk *clk)
3992 {
3993         u32 reg, div;
3994
3995         reg = __raw_readl(MXC_CCM_CDCDR);
3996         div = ((reg & MXC_CCM_CDCDR_HSI_TX_PODF_MASK) >>
3997                         MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET) + 1;
3998
3999         return clk_get_rate(clk->parent) / div;
4000 }
4001
4002 static int _clk_hsi_tx_set_rate(struct clk *clk, unsigned long rate)
4003 {
4004         u32 reg, div;
4005         u32 parent_rate = clk_get_rate(clk->parent);
4006
4007         div = parent_rate / rate;
4008         if (div == 0)
4009                 div++;
4010         if (((parent_rate / div) != rate) || (div > 8))
4011                 return -EINVAL;
4012
4013         reg = __raw_readl(MXC_CCM_CDCDR);
4014         reg &= ~MXC_CCM_CDCDR_HSI_TX_PODF_MASK;
4015         reg |= (div - 1) << MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET;
4016         __raw_writel(reg, MXC_CCM_CDCDR);
4017
4018         return 0;
4019 }
4020
4021 static struct clk hsi_tx_clk[] = {
4022         {
4023          __INIT_CLK_DEBUG(hsi_tx_clk)
4024         .id = 0,
4025          .parent = &pll2_pfd_400M,
4026         .enable_reg = MXC_CCM_CCGR3,
4027         .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET,
4028         .enable = _clk_enable,
4029         .disable = _clk_disable,
4030         .set_parent = _clk_hsi_tx_set_parent,
4031         .round_rate = _clk_hsi_tx_round_rate,
4032         .set_rate = _clk_hsi_tx_set_rate,
4033         .get_rate = _clk_hsi_tx_get_rate,
4034          .secondary = &hsi_tx_clk[1],
4035         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
4036         },
4037         {
4038         .parent = &mx6per1_clk,
4039         .secondary = &mx6per2_clk,
4040          },
4041 };
4042
4043 static struct clk mipi_pllref_clk = {
4044          __INIT_CLK_DEBUG(mipi_pllref_clk)
4045         .id = 0,
4046         .parent = &pll3_pfd_540M,
4047         .enable_reg = MXC_CCM_CCGR3,
4048         .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET,
4049         .enable = _clk_enable,
4050         .disable = _clk_disable,
4051 };
4052
4053 static struct clk hdmi_clk[] = {
4054         {
4055          __INIT_CLK_DEBUG(hdmi_isfr_clk)
4056         .id = 0,
4057         .parent = &pll3_pfd_540M,
4058         .enable_reg = MXC_CCM_CCGR2,
4059         .enable_shift = MXC_CCM_CCGRx_CG2_OFFSET,
4060         .enable = _clk_enable,
4061         .disable = _clk_disable,
4062         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
4063         },
4064         {
4065          __INIT_CLK_DEBUG(hdmi_iahb_clk)
4066         .id = 1,
4067          .parent = &ahb_clk,
4068         .enable_reg = MXC_CCM_CCGR2,
4069         .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET,
4070         .enable = _clk_enable,
4071         .disable = _clk_disable,
4072         },
4073 };
4074
4075 static struct clk caam_clk[] = {
4076         {
4077          __INIT_CLK_DEBUG(caam_mem_clk)
4078         .id = 0,
4079         .enable_reg = MXC_CCM_CCGR0,
4080         .enable_shift = MXC_CCM_CCGRx_CG4_OFFSET,
4081         .enable = _clk_enable,
4082         .disable = _clk_disable,
4083         .secondary = &caam_clk[1],
4084         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
4085         },
4086         {
4087          __INIT_CLK_DEBUG(caam_aclk_clk)
4088         .id = 1,
4089         .enable_reg = MXC_CCM_CCGR0,
4090         .enable_shift = MXC_CCM_CCGRx_CG5_OFFSET,
4091         .enable = _clk_enable,
4092         .disable = _clk_disable,
4093         .secondary = &caam_clk[2],
4094         },
4095         {
4096          __INIT_CLK_DEBUG(caam_ipg_clk)
4097         .id = 2,
4098         .enable_reg = MXC_CCM_CCGR0,
4099         .enable_shift = MXC_CCM_CCGRx_CG4_OFFSET,
4100         .enable = _clk_enable,
4101         .disable = _clk_disable,
4102         .parent = &mmdc_ch0_axi_clk[0],
4103         .secondary = &mx6per1_clk,
4104         },
4105 };
4106
4107 static int _clk_asrc_serial_set_parent(struct clk *clk, struct clk *parent)
4108 {
4109         u32 reg, mux;
4110
4111         reg = __raw_readl(MXC_CCM_CDCDR) & ~MXC_CCM_CDCDR_SPDIF1_CLK_SEL_MASK;
4112
4113         mux = _get_mux6(parent, &pll4_audio_main_clk, &pll3_pfd_508M,
4114                         &pll3_pfd_454M, &pll3_sw_clk, NULL, NULL);
4115         reg |= mux << MXC_CCM_CDCDR_SPDIF1_CLK_SEL_OFFSET;
4116
4117         __raw_writel(reg, MXC_CCM_CDCDR);
4118
4119         return 0;
4120 }
4121
4122 static unsigned long _clk_asrc_serial_get_rate(struct clk *clk)
4123 {
4124         u32 reg, pred, podf;
4125
4126         reg = __raw_readl(MXC_CCM_CDCDR);
4127
4128         pred = ((reg & MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK)
4129                 >> MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET) + 1;
4130         podf = ((reg & MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK)
4131                 >> MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET) + 1;
4132
4133         return clk_get_rate(clk->parent) / (pred * podf);
4134 }
4135
4136 static int _clk_asrc_serial_set_rate(struct clk *clk, unsigned long rate)
4137 {
4138         u32 reg, div, pre, post;
4139         u32 parent_rate = clk_get_rate(clk->parent);
4140
4141         div = parent_rate / rate;
4142         if (div == 0)
4143                 div++;
4144         if (((parent_rate / div) != rate) || div > 64)
4145                 return -EINVAL;
4146
4147         __calc_pre_post_dividers(1 << 3, div, &pre, &post);
4148
4149         reg = __raw_readl(MXC_CCM_CDCDR);
4150         reg &= ~(MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK|
4151                  MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK);
4152         reg |= (post - 1) << MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET;
4153         reg |= (pre - 1) << MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET;
4154
4155         __raw_writel(reg, MXC_CCM_CDCDR);
4156
4157         return 0;
4158 }
4159
4160 static unsigned long _clk_asrc_serial_round_rate(struct clk *clk,
4161                                                 unsigned long rate)
4162 {
4163         u32 pre, post;
4164         u32 parent_rate = clk_get_rate(clk->parent);
4165         u32 div = parent_rate / rate;
4166
4167         if (parent_rate % rate)
4168                 div++;
4169
4170         __calc_pre_post_dividers(1 << 3, div, &pre, &post);
4171
4172         return parent_rate / (pre * post);
4173 }
4174
4175 static struct clk asrc_clk[] = {
4176         {
4177         __INIT_CLK_DEBUG(asrc_clk)
4178         .id = 0,
4179         .parent = &pll4_audio_main_clk,
4180         .enable_reg = MXC_CCM_CCGR0,
4181         .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET,
4182         .enable = _clk_enable,
4183         .disable = _clk_disable,
4184         .secondary = &spba_clk,
4185         },
4186         {
4187         /*In the MX6 spec, asrc_serial_clk is listed as SPDIF1 clk
4188          * This clock can never be gated and does  not have any
4189          * CCGR bits associated with it.
4190          */
4191         __INIT_CLK_DEBUG(asrc_serial_clk)
4192         .id = 1,
4193         .parent = &pll3_sw_clk,
4194          .set_rate = _clk_asrc_serial_set_rate,
4195          .get_rate = _clk_asrc_serial_get_rate,
4196          .set_parent = _clk_asrc_serial_set_parent,
4197          .round_rate = _clk_asrc_serial_round_rate,
4198         },
4199 };
4200
4201 static struct clk apbh_dma_clk = {
4202         __INIT_CLK_DEBUG(apbh_dma_clk)
4203         .parent = &usdhc3_clk,
4204         .secondary = &mx6per1_clk,
4205         .enable = _clk_enable,
4206         .disable = _clk_disable_inwait,
4207         .enable_reg = MXC_CCM_CCGR0,
4208         .enable_shift = MXC_CCM_CCGRx_CG2_OFFSET,
4209 };
4210
4211 static struct clk aips_tz2_clk = {
4212         __INIT_CLK_DEBUG(aips_tz2_clk)
4213         .parent = &ahb_clk,
4214         .enable_reg = MXC_CCM_CCGR0,
4215         .enable_shift = MXC_CCM_CCGRx_CG1_OFFSET,
4216         .enable = _clk_enable,
4217         .disable = _clk_disable_inwait,
4218 };
4219
4220 static struct clk aips_tz1_clk = {
4221         __INIT_CLK_DEBUG(aips_tz1_clk)
4222         .parent = &ahb_clk,
4223         .enable_reg = MXC_CCM_CCGR0,
4224         .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET,
4225         .enable = _clk_enable,
4226         .disable = _clk_disable_inwait,
4227 };
4228
4229
4230 static struct clk openvg_axi_clk = {
4231         __INIT_CLK_DEBUG(openvg_axi_clk)
4232         .parent = &gpu2d_axi_clk,
4233         .enable = _clk_enable,
4234         .enable_reg = MXC_CCM_CCGR3,
4235         .enable_shift = MXC_CCM_CCGRx_CG15_OFFSET,
4236         .disable = _clk_disable,
4237         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
4238 };
4239
4240 static unsigned long _clk_gpu3d_core_round_rate(struct clk *clk,
4241                                                 unsigned long rate)
4242 {
4243         u32 div;
4244         u32 parent_rate = clk_get_rate(clk->parent);
4245
4246         div = parent_rate / rate;
4247
4248         /* Make sure rate is not greater than the maximum value for the clock.
4249          * Also prevent a div of 0.
4250          */
4251         if (div == 0)
4252                 div++;
4253
4254         if (div > 8)
4255                 div = 8;
4256
4257         return parent_rate / div;
4258 }
4259
4260 static int _clk_gpu3d_core_set_parent(struct clk *clk, struct clk *parent)
4261 {
4262         int mux;
4263         u32 reg = __raw_readl(MXC_CCM_CBCMR)
4264                 & ~MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK;
4265
4266         mux = _get_mux6(parent, &mmdc_ch0_axi_clk[0],
4267                 &pll3_usb_otg_main_clk,
4268                 &pll2_pfd_594M, &pll2_pfd_400M, NULL, NULL);
4269         reg |= (mux << MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET);
4270         __raw_writel(reg, MXC_CCM_CBCMR);
4271
4272         return 0;
4273 }
4274
4275 static unsigned long _clk_gpu3d_core_get_rate(struct clk *clk)
4276 {
4277         u32 reg, div;
4278
4279         reg = __raw_readl(MXC_CCM_CBCMR);
4280         div = ((reg & MXC_CCM_CBCMR_GPU3D_CORE_PODF_MASK) >>
4281                         MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET) + 1;
4282
4283         return clk_get_rate(clk->parent) / div;
4284 }
4285
4286 static int _clk_gpu3d_core_set_rate(struct clk *clk, unsigned long rate)
4287 {
4288         u32 reg, div;
4289         u32 parent_rate = clk_get_rate(clk->parent);
4290
4291         div = parent_rate / rate;
4292         if (div == 0)
4293                 div++;
4294         if (div > 8)
4295                 div = 8;
4296
4297         reg = __raw_readl(MXC_CCM_CBCMR);
4298         reg &= ~MXC_CCM_CBCMR_GPU3D_CORE_PODF_MASK;
4299         reg |= (div - 1) << MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET;
4300         __raw_writel(reg, MXC_CCM_CBCMR);
4301
4302         return 0;
4303 }
4304
4305 static struct clk gpu3d_core_clk[] = {
4306         {
4307         __INIT_CLK_DEBUG(gpu3d_core_clk)
4308         .parent = &pll2_pfd_594M,
4309         .enable = _clk_enable,
4310         .enable_reg = MXC_CCM_CCGR1,
4311         .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
4312         .disable = _clk_disable,
4313         .set_parent = _clk_gpu3d_core_set_parent,
4314         .set_rate = _clk_gpu3d_core_set_rate,
4315         .get_rate = _clk_gpu3d_core_get_rate,
4316         .round_rate = _clk_gpu3d_core_round_rate,
4317         .secondary = &gpu3d_core_clk[1],
4318         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
4319         },
4320         {
4321         .parent = &gpu3d_axi_clk,
4322         .secondary = &mx6fast1_clk,
4323         },
4324 };
4325
4326 static unsigned long _clk_gpu2d_core_round_rate(struct clk *clk,
4327                                                 unsigned long rate)
4328 {
4329         u32 div;
4330         u32 parent_rate = clk_get_rate(clk->parent);
4331
4332         div = parent_rate / rate;
4333
4334         /* Make sure rate is not greater than the maximum value for the clock.
4335          * Also prevent a div of 0.
4336          */
4337         if (div == 0)
4338                 div++;
4339
4340         if (div > 8)
4341                 div = 8;
4342
4343         return parent_rate / div;
4344 }
4345
4346 static int _clk_gpu2d_core_set_parent(struct clk *clk, struct clk *parent)
4347 {
4348         int mux;
4349         u32 reg = __raw_readl(MXC_CCM_CBCMR) &
4350                                 ~MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK;
4351
4352         /*on mx6dl, 2d core clock sources from 3d shader core clock*/
4353         if (!cpu_is_mx6dl()) {
4354                 mux = _get_mux6(parent, &axi_clk, &pll3_usb_otg_main_clk,
4355                         &pll2_pfd_352M, &pll2_pfd_400M, NULL, NULL);
4356                 reg |= (mux << MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET);
4357                 __raw_writel(reg, MXC_CCM_CBCMR);
4358         }
4359
4360         return 0;
4361 }
4362
4363 static unsigned long _clk_gpu2d_core_get_rate(struct clk *clk)
4364 {
4365         u32 reg, div;
4366
4367         reg = __raw_readl(MXC_CCM_CBCMR);
4368         div = ((reg & MXC_CCM_CBCMR_GPU2D_CORE_PODF_MASK) >>
4369                         MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET) + 1;
4370
4371         return clk_get_rate(clk->parent) / div;
4372 }
4373
4374 static int _clk_gpu2d_core_set_rate(struct clk *clk, unsigned long rate)
4375 {
4376         u32 reg, div;
4377         u32 parent_rate = clk_get_rate(clk->parent);
4378
4379         div = parent_rate / rate;
4380         if (div == 0)
4381                 div++;
4382         if (((parent_rate / div) != rate) || (div > 8))
4383                 return -EINVAL;
4384
4385         reg = __raw_readl(MXC_CCM_CBCMR);
4386         reg &= ~MXC_CCM_CBCMR_GPU2D_CORE_PODF_MASK;
4387         reg |= (div - 1) << MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET;
4388         __raw_writel(reg, MXC_CCM_CBCMR);
4389
4390         return 0;
4391 }
4392 static struct clk gpu2d_core_clk[] = {
4393         {
4394         __INIT_CLK_DEBUG(gpu2d_core_clk)
4395         .parent = &pll2_pfd_352M,
4396         .enable = _clk_enable,
4397         .enable_reg = MXC_CCM_CCGR1,
4398         .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET,
4399         .disable = _clk_disable,
4400         .set_parent = _clk_gpu2d_core_set_parent,
4401         .set_rate = _clk_gpu2d_core_set_rate,
4402         .get_rate = _clk_gpu2d_core_get_rate,
4403         .round_rate = _clk_gpu2d_core_round_rate,
4404         .secondary = &gpu2d_core_clk[1],
4405         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
4406         },
4407         {
4408         .parent = &gpu2d_axi_clk,
4409         .secondary = &mx6fast1_clk,
4410         },
4411 };
4412
4413 static unsigned long _clk_gpu3d_shader_round_rate(struct clk *clk,
4414                                                 unsigned long rate)
4415 {
4416         u32 div;
4417         u32 parent_rate = clk_get_rate(clk->parent);
4418
4419         div = parent_rate / rate;
4420
4421         /* Make sure rate is not greater than the maximum value for the clock.
4422          * Also prevent a div of 0.
4423          */
4424         if (div == 0)
4425                 div++;
4426
4427         if (div > 8)
4428                 div = 8;
4429
4430         return parent_rate / div;
4431 }
4432
4433 static int _clk_gpu3d_shader_set_parent(struct clk *clk, struct clk *parent)
4434 {
4435         int mux;
4436         u32 reg = __raw_readl(MXC_CCM_CBCMR)
4437                 & ~MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_MASK;
4438
4439         mux = _get_mux6(parent, &mmdc_ch0_axi_clk[0],
4440                 &pll3_usb_otg_main_clk,
4441                 &pll2_pfd_594M, &pll3_pfd_720M, NULL, NULL);
4442         reg |= (mux << MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET);
4443         __raw_writel(reg, MXC_CCM_CBCMR);
4444
4445         return 0;
4446 }
4447
4448 static unsigned long _clk_gpu3d_shader_get_rate(struct clk *clk)
4449 {
4450         u32 reg, div;
4451
4452         reg = __raw_readl(MXC_CCM_CBCMR);
4453         div = ((reg & MXC_CCM_CBCMR_GPU3D_SHADER_PODF_MASK) >>
4454                         MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET) + 1;
4455
4456         return clk_get_rate(clk->parent) / div;
4457 }
4458
4459 static int _clk_gpu3d_shader_set_rate(struct clk *clk, unsigned long rate)
4460 {
4461         u32 reg, div;
4462         u32 parent_rate = clk_get_rate(clk->parent);
4463
4464         div = parent_rate / rate;
4465         if (div == 0)
4466                 div++;
4467         if (div > 8)
4468                 div = 8;
4469
4470         reg = __raw_readl(MXC_CCM_CBCMR);
4471         reg &= ~MXC_CCM_CBCMR_GPU3D_SHADER_PODF_MASK;
4472         reg |= (div - 1) << MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET;
4473         __raw_writel(reg, MXC_CCM_CBCMR);
4474
4475         return 0;
4476 }
4477
4478
4479 static struct clk gpu3d_shader_clk = {
4480         __INIT_CLK_DEBUG(gpu3d_shader_clk)
4481         .parent = &pll3_pfd_720M,
4482         .secondary = &mmdc_ch0_axi_clk[0],
4483         .enable = _clk_enable,
4484         .enable_reg = MXC_CCM_CCGR1,
4485         .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
4486         .disable = _clk_disable,
4487         .set_parent = _clk_gpu3d_shader_set_parent,
4488         .set_rate = _clk_gpu3d_shader_set_rate,
4489         .get_rate = _clk_gpu3d_shader_get_rate,
4490         .round_rate = _clk_gpu3d_shader_round_rate,
4491         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
4492 };
4493
4494 /* set the parent by the ipcg table */
4495 static struct clk gpmi_nand_clk[] = {
4496         {       /* gpmi_io_clk */
4497         __INIT_CLK_DEBUG(gpmi_io_clk)
4498         .parent = &enfc_clk,
4499         .secondary = &gpmi_nand_clk[1],
4500         .enable = _clk_enable,
4501         .enable_reg = MXC_CCM_CCGR4,
4502         .enable_shift = MXC_CCM_CCGRx_CG14_OFFSET,
4503         .disable = _clk_disable,
4504         },
4505         {       /* gpmi_apb_clk */
4506         __INIT_CLK_DEBUG(gpmi_apb_clk)
4507         .parent = &usdhc3_clk,
4508         .secondary = &gpmi_nand_clk[2],
4509         .enable = _clk_enable,
4510         .enable_reg = MXC_CCM_CCGR4,
4511         .enable_shift = MXC_CCM_CCGRx_CG15_OFFSET,
4512         .disable = _clk_disable,
4513         },
4514         {       /* bch_clk */
4515         __INIT_CLK_DEBUG(gpmi_bch_clk)
4516         .parent = &usdhc4_clk,
4517         .secondary = &gpmi_nand_clk[3],
4518         .enable = _clk_enable,
4519         .enable_reg = MXC_CCM_CCGR4,
4520         .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
4521         .disable = _clk_disable,
4522         },
4523         {       /* bch_apb_clk */
4524         __INIT_CLK_DEBUG(gpmi_bch_apb_clk)
4525         .parent = &usdhc3_clk,
4526         .secondary = &gpmi_nand_clk[4],
4527         .enable = _clk_enable,
4528         .enable_reg = MXC_CCM_CCGR4,
4529         .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET,
4530         .disable = _clk_disable,
4531         },
4532         {       /* bch relative clk */
4533         __INIT_CLK_DEBUG(pl301_mx6qperl_bch)
4534         .parent = &mx6per1_clk,
4535         .secondary = &mmdc_ch0_axi_clk[0],
4536         },
4537 };
4538
4539 static struct clk pwm_clk[] = {
4540         {
4541         __INIT_CLK_DEBUG(pwm_clk_0)
4542          .parent = &ipg_perclk,
4543          .id = 0,
4544          .enable_reg = MXC_CCM_CCGR4,
4545          .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET,
4546          .enable = _clk_enable,
4547          .disable = _clk_disable,
4548          },
4549         {
4550         __INIT_CLK_DEBUG(pwm_clk_1)
4551          .parent = &ipg_perclk,
4552          .id = 1,
4553          .enable_reg = MXC_CCM_CCGR4,
4554          .enable_shift = MXC_CCM_CCGRx_CG9_OFFSET,
4555          .enable = _clk_enable,
4556          .disable = _clk_disable,
4557          },
4558         {
4559         __INIT_CLK_DEBUG(pwm_clk_2)
4560          .parent = &ipg_perclk,
4561          .id = 2,
4562          .enable_reg = MXC_CCM_CCGR4,
4563          .enable_shift = MXC_CCM_CCGRx_CG10_OFFSET,
4564          .enable = _clk_enable,
4565          .disable = _clk_disable,
4566          },
4567         {
4568         __INIT_CLK_DEBUG(pwm_clk_3)
4569          .parent = &ipg_perclk,
4570          .id = 3,
4571          .enable_reg = MXC_CCM_CCGR4,
4572          .enable_shift = MXC_CCM_CCGRx_CG11_OFFSET,
4573          .enable = _clk_enable,
4574          .disable = _clk_disable,
4575          },
4576 };
4577
4578 static int _clk_pcie_enable(struct clk *clk)
4579 {
4580         unsigned int reg;
4581
4582         /* Clear Power Down and Enable PLLs */
4583         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
4584         reg &= ~ANADIG_PLL_ENET_POWER_DOWN;
4585         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
4586
4587         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
4588         reg |= ANADIG_PLL_ENET_EN;
4589         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
4590
4591         /* Waiting for the PLL is locked */
4592         if (!WAIT(ANADIG_PLL_ENET_LOCK & __raw_readl(PLL8_ENET_BASE_ADDR),
4593                                 SPIN_DELAY))
4594                 panic("pll8 lock failed\n");
4595
4596         /* Disable the bypass */
4597         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
4598         reg &= ~ANADIG_PLL_ENET_BYPASS;
4599         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
4600
4601         /*
4602          * Enable SATA ref clock.
4603          * PCIe needs both sides to have the same source of refernce clock,
4604          * The SATA reference clock is taken out on clk out
4605          */
4606         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
4607         reg |= ANADIG_PLL_ENET_EN_SATA;
4608         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
4609
4610         /* Activate LVDS CLK1 (the MiniPCIe slot clock input) */
4611         reg = __raw_readl(ANADIG_MISC1_REG);
4612         reg &= ~ANATOP_LVDS_CLK1_IBEN_MASK;
4613         __raw_writel(reg, ANADIG_MISC1_REG);
4614
4615         reg = __raw_readl(ANADIG_MISC1_REG);
4616         reg |= ANATOP_LVDS_CLK1_SRC_SATA;
4617         __raw_writel(reg, ANADIG_MISC1_REG);
4618
4619         reg = __raw_readl(ANADIG_MISC1_REG);
4620         reg |= ANATOP_LVDS_CLK1_OBEN_MASK;
4621         __raw_writel(reg, ANADIG_MISC1_REG);
4622
4623         /* Enable PCIE ref clock */
4624         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
4625         reg |= ANADIG_PLL_ENET_EN_PCIE;
4626         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
4627
4628         _clk_enable(clk);
4629
4630         return 0;
4631 }
4632
4633 static void _clk_pcie_disable(struct clk *clk)
4634 {
4635         unsigned int reg;
4636
4637         _clk_disable(clk);
4638
4639         /* Disable SATA ref clock */
4640         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
4641         reg &= ~ANADIG_PLL_ENET_EN_PCIE;
4642         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
4643 }
4644
4645 static struct clk pcie_clk[] = {
4646         {
4647         __INIT_CLK_DEBUG(pcie_clk)
4648         .parent = &pcie_axi_clk,
4649         .enable = _clk_pcie_enable,
4650         .disable = _clk_pcie_disable,
4651         .enable_reg = MXC_CCM_CCGR4,
4652         .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET,
4653         .secondary = &pcie_clk[1],
4654         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
4655         },
4656         {
4657         .parent = &mmdc_ch0_axi_clk[0],
4658         .secondary = &mx6fast1_clk,
4659         },
4660 };
4661
4662 static int _clk_sata_enable(struct clk *clk)
4663 {
4664         unsigned int reg;
4665
4666         /* Clear Power Down and Enable PLLs */
4667         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
4668         reg &= ~ANADIG_PLL_ENET_POWER_DOWN;
4669         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
4670
4671         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
4672         reg |= ANADIG_PLL_ENET_EN;
4673         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
4674
4675         /* Waiting for the PLL is locked */
4676         if (!WAIT(ANADIG_PLL_ENET_LOCK & __raw_readl(PLL8_ENET_BASE_ADDR),
4677                                 SPIN_DELAY))
4678                 panic("pll8 lock failed\n");
4679
4680         /* Disable the bypass */
4681         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
4682         reg &= ~ANADIG_PLL_ENET_BYPASS;
4683         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
4684
4685         /* Enable SATA ref clock */
4686         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
4687         reg |= ANADIG_PLL_ENET_EN_SATA;
4688         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
4689
4690         _clk_enable(clk);
4691
4692         return 0;
4693 }
4694
4695 static void _clk_sata_disable(struct clk *clk)
4696 {
4697         unsigned int reg;
4698
4699         _clk_disable(clk);
4700
4701         /* Disable SATA ref clock */
4702         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
4703         reg &= ~ANADIG_PLL_ENET_EN_SATA;
4704         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
4705 }
4706
4707 static struct clk sata_clk[] = {
4708         {
4709         __INIT_CLK_DEBUG(sata_clk)
4710         .parent = &ipg_clk,
4711         .enable = _clk_sata_enable,
4712         .enable_reg = MXC_CCM_CCGR5,
4713         .enable_shift = MXC_CCM_CCGRx_CG2_OFFSET,
4714         .disable = _clk_sata_disable,
4715         .secondary = &sata_clk[1],
4716         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
4717         },
4718         {
4719         .parent = &mmdc_ch0_axi_clk[0],
4720         .secondary = &mx6per1_clk,
4721         }
4722 };
4723
4724 static struct clk usboh3_clk[] = {
4725         {
4726         __INIT_CLK_DEBUG(usboh3_clk)
4727         .parent = &ahb_clk,
4728         .enable = _clk_enable,
4729         .enable_reg = MXC_CCM_CCGR6,
4730         .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET,
4731         .disable = _clk_disable,
4732         .secondary = &usboh3_clk[1],
4733         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
4734         },
4735         {
4736         .parent = &mmdc_ch0_axi_clk[0],
4737         .secondary = &mx6per1_clk,
4738         },
4739 };
4740
4741 static struct clk mlb150_clk = {
4742         __INIT_CLK_DEBUG(mlb150_clk)
4743         .id = 0,
4744         .parent = &ipg_clk,
4745         .enable_reg = MXC_CCM_CCGR3,
4746         .enable_shift = MXC_CCM_CCGRx_CG9_OFFSET,
4747         .enable = _clk_enable,
4748         .disable = _clk_disable,
4749 };
4750
4751 static int _clk_enable1(struct clk *clk)
4752 {
4753         u32 reg;
4754         reg = __raw_readl(clk->enable_reg);
4755         reg |= 1 << clk->enable_shift;
4756         __raw_writel(reg, clk->enable_reg);
4757
4758         return 0;
4759 }
4760
4761 static void _clk_disable1(struct clk *clk)
4762 {
4763         u32 reg;
4764         reg = __raw_readl(clk->enable_reg);
4765         reg &= ~(1 << clk->enable_shift);
4766         __raw_writel(reg, clk->enable_reg);
4767 }
4768
4769 static int _clk_clko_set_parent(struct clk *clk, struct clk *parent)
4770 {
4771         u32 sel, reg;
4772
4773         if (parent == &pll3_usb_otg_main_clk)
4774                 sel = 0;
4775         else if (parent == &pll2_528_bus_main_clk)
4776                 sel = 1;
4777         else if (parent == &pll1_sys_main_clk)
4778                 sel = 2;
4779         else if (parent == &pll5_video_main_clk)
4780                 sel = 3;
4781         else if (parent == &axi_clk)
4782                 sel = 5;
4783         else if (parent == &enfc_clk)
4784                 sel = 6;
4785         else if (parent == &ipu1_di_clk[0])
4786                 sel = 7;
4787         else if (parent == &ipu1_di_clk[1])
4788                 sel = 8;
4789         else if (parent == &ipu2_di_clk[0])
4790                 sel = 9;
4791         else if (parent == &ipu2_di_clk[1])
4792                 sel = 10;
4793         else if (parent == &ahb_clk)
4794                 sel = 11;
4795         else if (parent == &ipg_clk)
4796                 sel = 12;
4797         else if (parent == &ipg_perclk)
4798                 sel = 13;
4799         else if (parent == &ckil_clk)
4800                 sel = 14;
4801         else if (parent == &pll4_audio_main_clk)
4802                 sel = 15;
4803         else
4804                 return -EINVAL;
4805
4806         reg = __raw_readl(MXC_CCM_CCOSR);
4807         reg &= ~MXC_CCM_CCOSR_CKOL_SEL_MASK;
4808         reg |= sel << MXC_CCM_CCOSR_CKOL_SEL_OFFSET;
4809         __raw_writel(reg, MXC_CCM_CCOSR);
4810         return 0;
4811 }
4812
4813 static unsigned long _clk_clko_get_rate(struct clk *clk)
4814 {
4815         u32 reg = __raw_readl(MXC_CCM_CCOSR);
4816         u32 div = ((reg & MXC_CCM_CCOSR_CKOL_DIV_MASK) >>
4817                         MXC_CCM_CCOSR_CKOL_DIV_OFFSET) + 1;
4818         return clk_get_rate(clk->parent) / div;
4819 }
4820
4821 static int _clk_clko_set_rate(struct clk *clk, unsigned long rate)
4822 {
4823         u32 reg;
4824         u32 parent_rate = clk_get_rate(clk->parent);
4825         u32 div = parent_rate / rate;
4826
4827         if (div == 0)
4828                 div++;
4829         if (((parent_rate / div) != rate) || (div > 8))
4830                 return -EINVAL;
4831
4832         reg = __raw_readl(MXC_CCM_CCOSR);
4833         reg &= ~MXC_CCM_CCOSR_CKOL_DIV_MASK;
4834         reg |= (div - 1) << MXC_CCM_CCOSR_CKOL_DIV_OFFSET;
4835         __raw_writel(reg, MXC_CCM_CCOSR);
4836         return 0;
4837 }
4838
4839 static unsigned long _clk_clko_round_rate(struct clk *clk,
4840                                                 unsigned long rate)
4841 {
4842         u32 parent_rate = clk_get_rate(clk->parent);
4843         u32 div = parent_rate / rate;
4844
4845         /* Make sure rate is not greater than the maximum value for the clock.
4846          * Also prevent a div of 0.
4847          */
4848         if (div == 0)
4849                 div++;
4850         if (div > 8)
4851                 div = 8;
4852         return parent_rate / div;
4853 }
4854
4855 static int _clk_clko2_set_parent(struct clk *clk, struct clk *parent)
4856 {
4857         u32 sel, reg;
4858
4859         if (parent == &mmdc_ch0_axi_clk[0])
4860                 sel = 0;
4861         else if (parent == &mmdc_ch1_axi_clk[0])
4862                 sel = 1;
4863         else if (parent == &usdhc4_clk)
4864                 sel = 2;
4865         else if (parent == &usdhc1_clk)
4866                 sel = 3;
4867         else if (parent == &gpu2d_axi_clk)
4868                 sel = 4;
4869         else if (parent == &ecspi_clk[0])
4870                 sel = 6;
4871         else if (parent == &gpu3d_axi_clk)
4872                 sel = 7;
4873         else if (parent == &usdhc3_clk)
4874                 sel = 8;
4875         else if (parent == &pcie_clk[0])
4876                 sel = 9;
4877         else if (parent == &ipu1_clk)
4878                 sel = 11;
4879         else if (parent == &ipu2_clk)
4880                 sel = 12;
4881         else if (parent == &vdo_axi_clk)
4882                 sel = 13;
4883         else if (parent == &osc_clk)
4884                 sel = 14;
4885         else if (parent == &gpu2d_core_clk[0])
4886                 sel = 15;
4887         else if (parent == &gpu3d_core_clk[0])
4888                 sel = 16;
4889         else if (parent == &usdhc2_clk)
4890                 sel = 17;
4891         else if (parent == &ssi1_clk)
4892                 sel = 18;
4893         else if (parent == &ssi2_clk)
4894                 sel = 19;
4895         else if (parent == &ssi3_clk)
4896                 sel = 20;
4897         else if (parent == &gpu3d_shader_clk)
4898                 sel = 21;
4899         else if (parent == &can_clk_root)
4900                 sel = 23;
4901         else if (parent == &ldb_di0_clk)
4902                 sel = 24;
4903         else if (parent == &ldb_di1_clk)
4904                 sel = 25;
4905         else if (parent == &esai_clk)
4906                 sel = 26;
4907         else if (parent == &uart_clk[0])
4908                 sel = 28;
4909         else if (parent == &spdif0_clk[0])
4910                 sel = 29;
4911         else if (parent == &hsi_tx_clk[0])
4912                 sel = 31;
4913         else
4914                 return -EINVAL;
4915
4916         reg = __raw_readl(MXC_CCM_CCOSR);
4917         reg &= ~MXC_CCM_CCOSR_CKO2_SEL_MASK;
4918         reg |= sel << MXC_CCM_CCOSR_CKO2_SEL_OFFSET;
4919         __raw_writel(reg, MXC_CCM_CCOSR);
4920         return 0;
4921 }
4922
4923 static unsigned long _clk_clko2_get_rate(struct clk *clk)
4924 {
4925         u32 reg = __raw_readl(MXC_CCM_CCOSR);
4926         u32 div = ((reg & MXC_CCM_CCOSR_CKO2_DIV_MASK) >>
4927                         MXC_CCM_CCOSR_CKO2_DIV_OFFSET) + 1;
4928         return clk_get_rate(clk->parent) / div;
4929 }
4930
4931 static int _clk_clko2_set_rate(struct clk *clk, unsigned long rate)
4932 {
4933         u32 reg;
4934         u32 parent_rate = clk_get_rate(clk->parent);
4935         u32 div = parent_rate / rate;
4936
4937         if (div == 0)
4938                 div++;
4939         if (((parent_rate / div) != rate) || (div > 8))
4940                 return -EINVAL;
4941
4942         reg = __raw_readl(MXC_CCM_CCOSR);
4943         reg &= ~MXC_CCM_CCOSR_CKO2_DIV_MASK;
4944         reg |= (div - 1) << MXC_CCM_CCOSR_CKO2_DIV_OFFSET;
4945         __raw_writel(reg, MXC_CCM_CCOSR);
4946         return 0;
4947 }
4948
4949 static struct clk clko_clk = {
4950         __INIT_CLK_DEBUG(clko_clk)
4951         .parent = &pll2_528_bus_main_clk,
4952         .enable = _clk_enable1,
4953         .enable_reg = MXC_CCM_CCOSR,
4954         .enable_shift = MXC_CCM_CCOSR_CKOL_EN_OFFSET,
4955         .disable = _clk_disable1,
4956         .set_parent = _clk_clko_set_parent,
4957         .set_rate = _clk_clko_set_rate,
4958         .get_rate = _clk_clko_get_rate,
4959         .round_rate = _clk_clko_round_rate,
4960 };
4961
4962 static struct clk clko2_clk = {
4963         __INIT_CLK_DEBUG(clko2_clk)
4964         .parent = &usdhc4_clk,
4965         .enable = _clk_enable1,
4966         .enable_reg = MXC_CCM_CCOSR,
4967         .enable_shift = MXC_CCM_CCOSR_CKO2_EN_OFFSET,
4968         .disable = _clk_disable1,
4969         .set_parent = _clk_clko2_set_parent,
4970         .set_rate = _clk_clko2_set_rate,
4971         .get_rate = _clk_clko2_get_rate,
4972         .round_rate = _clk_clko_round_rate,
4973 };
4974
4975 static struct clk perfmon0_clk = {
4976         __INIT_CLK_DEBUG(perfmon0_clk)
4977         .parent = &mmdc_ch0_axi_clk[0],
4978         .enable = _clk_enable1,
4979         .enable_reg = MXC_CCM_CCGR4,
4980         .enable_shift = MXC_CCM_CCGRx_CG1_OFFSET,
4981         .disable = _clk_disable1,
4982 };
4983
4984 static struct clk perfmon1_clk = {
4985         __INIT_CLK_DEBUG(perfmon1_clk)
4986         .parent = &ipu1_clk,
4987         .enable = _clk_enable1,
4988         .enable_reg = MXC_CCM_CCGR4,
4989         .enable_shift = MXC_CCM_CCGRx_CG2_OFFSET,
4990         .disable = _clk_disable1,
4991 };
4992
4993 static struct clk perfmon2_clk = {
4994         __INIT_CLK_DEBUG(perfmon2_clk)
4995         .parent = &mmdc_ch0_axi_clk[0],
4996         .enable = _clk_enable1,
4997         .enable_reg = MXC_CCM_CCGR4,
4998         .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET,
4999         .disable = _clk_disable1,
5000 };
5001
5002 static struct clk dummy_clk = {
5003         .id = 0,
5004 };
5005
5006 #define _REGISTER_CLOCK(d, n, c) \
5007         { \
5008                 .dev_id = d, \
5009                 .con_id = n, \
5010                 .clk = &c, \
5011         }
5012
5013
5014 static struct clk_lookup lookups[] = {
5015         _REGISTER_CLOCK(NULL, "osc", osc_clk),
5016         _REGISTER_CLOCK(NULL, "ckih", ckih_clk),
5017         _REGISTER_CLOCK(NULL, "ckih2", ckih2_clk),
5018         _REGISTER_CLOCK(NULL, "ckil", ckil_clk),
5019         _REGISTER_CLOCK(NULL, "pll1_main_clk", pll1_sys_main_clk),
5020         _REGISTER_CLOCK(NULL, "pll1_sw_clk", pll1_sw_clk),
5021         _REGISTER_CLOCK(NULL, "pll2", pll2_528_bus_main_clk),
5022         _REGISTER_CLOCK(NULL, "pll2_pfd_400M", pll2_pfd_400M),
5023         _REGISTER_CLOCK(NULL, "pll2_pfd_352M", pll2_pfd_352M),
5024         _REGISTER_CLOCK(NULL, "pll2_pfd_594M", pll2_pfd_594M),
5025         _REGISTER_CLOCK(NULL, "pll2_200M", pll2_200M),
5026         _REGISTER_CLOCK(NULL, "pll3_main_clk", pll3_usb_otg_main_clk),
5027         _REGISTER_CLOCK(NULL, "pll3_pfd_508M", pll3_pfd_508M),
5028         _REGISTER_CLOCK(NULL, "pll3_pfd_454M", pll3_pfd_454M),
5029         _REGISTER_CLOCK(NULL, "pll3_pfd_720M", pll3_pfd_720M),
5030         _REGISTER_CLOCK(NULL, "pll3_pfd_540M", pll3_pfd_540M),
5031         _REGISTER_CLOCK(NULL, "pll3_sw_clk", pll3_sw_clk),
5032         _REGISTER_CLOCK(NULL, "pll3_120M", pll3_120M),
5033         _REGISTER_CLOCK(NULL, "pll3_120M", pll3_80M),
5034         _REGISTER_CLOCK(NULL, "pll3_120M", pll3_60M),
5035         _REGISTER_CLOCK(NULL, "pll4", pll4_audio_main_clk),
5036         _REGISTER_CLOCK(NULL, "pll5", pll5_video_main_clk),
5037         _REGISTER_CLOCK(NULL, "pll6", pll6_mlb150_main_clk),
5038         _REGISTER_CLOCK(NULL, "pll3", pll7_usb_host_main_clk),
5039         _REGISTER_CLOCK(NULL, "pll4", pll8_enet_main_clk),
5040         _REGISTER_CLOCK(NULL, "cpu_clk", cpu_clk),
5041         _REGISTER_CLOCK(NULL, "periph_clk", periph_clk),
5042         _REGISTER_CLOCK(NULL, "axi_clk", axi_clk),
5043         _REGISTER_CLOCK(NULL, "mmdc_ch0_axi", mmdc_ch0_axi_clk[0]),
5044         _REGISTER_CLOCK(NULL, "mmdc_ch1_axi", mmdc_ch1_axi_clk[0]),
5045         _REGISTER_CLOCK(NULL, "ahb", ahb_clk),
5046         _REGISTER_CLOCK(NULL, "ipg_clk", ipg_clk),
5047         _REGISTER_CLOCK(NULL, "ipg_perclk", ipg_perclk),
5048         _REGISTER_CLOCK(NULL, "spba", spba_clk),
5049         _REGISTER_CLOCK("imx-sdma", NULL, sdma_clk[0]),
5050         _REGISTER_CLOCK(NULL, "gpu2d_axi_clk", gpu2d_axi_clk),
5051         _REGISTER_CLOCK(NULL, "gpu3d_axi_clk", gpu3d_axi_clk),
5052         _REGISTER_CLOCK(NULL, "pcie_axi_clk", pcie_axi_clk),
5053         _REGISTER_CLOCK(NULL, "vdo_axi_clk", vdo_axi_clk),
5054         _REGISTER_CLOCK(NULL, "iim_clk", iim_clk),
5055         _REGISTER_CLOCK(NULL, "i2c_clk", i2c_clk[0]),
5056         _REGISTER_CLOCK("imx-i2c.1", NULL, i2c_clk[1]),
5057         _REGISTER_CLOCK("imx-i2c.2", NULL, i2c_clk[2]),
5058         _REGISTER_CLOCK(NULL, "vpu_clk", vpu_clk[0]),
5059         _REGISTER_CLOCK(NULL, "ipu1_clk", ipu1_clk),
5060         _REGISTER_CLOCK(NULL, "ipu2_clk", ipu2_clk),
5061         _REGISTER_CLOCK(NULL, "cko1_clk0", cko1_clk0),
5062         _REGISTER_CLOCK("sdhci-esdhc-imx.0", NULL, usdhc1_clk),
5063         _REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL, usdhc2_clk),
5064         _REGISTER_CLOCK("sdhci-esdhc-imx.2", NULL, usdhc3_clk),
5065         _REGISTER_CLOCK("sdhci-esdhc-imx.3", NULL, usdhc4_clk),
5066         _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk),
5067         _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk),
5068         _REGISTER_CLOCK("imx-ssi.2", NULL, ssi3_clk),
5069         _REGISTER_CLOCK(NULL, "ipu1_di0_clk", ipu1_di_clk[0]),
5070         _REGISTER_CLOCK(NULL, "ipu1_di1_clk", ipu1_di_clk[1]),
5071         _REGISTER_CLOCK(NULL, "ipu2_di0_clk", ipu2_di_clk[0]),
5072         _REGISTER_CLOCK(NULL, "ipu2_di1_clk", ipu2_di_clk[1]),
5073         _REGISTER_CLOCK(NULL, "can_root_clk", can_clk_root),
5074         _REGISTER_CLOCK("imx6q-flexcan.0", NULL, can1_clk[0]),
5075         _REGISTER_CLOCK("imx6q-flexcan.1", NULL, can2_clk[0]),
5076         _REGISTER_CLOCK(NULL, "ldb_di0_clk", ldb_di0_clk),
5077         _REGISTER_CLOCK(NULL, "ldb_di1_clk", ldb_di1_clk),
5078         _REGISTER_CLOCK("mxc_spdif.0", NULL, spdif0_clk[0]),
5079         _REGISTER_CLOCK(NULL, "esai_clk", esai_clk),
5080         _REGISTER_CLOCK("imx6q-ecspi.0", NULL, ecspi_clk[0]),
5081         _REGISTER_CLOCK("imx6q-ecspi.1", NULL, ecspi_clk[1]),
5082         _REGISTER_CLOCK("imx6q-ecspi.2", NULL, ecspi_clk[2]),
5083         _REGISTER_CLOCK("imx6q-ecspi.3", NULL, ecspi_clk[3]),
5084         _REGISTER_CLOCK("imx6q-ecspi.4", NULL, ecspi_clk[4]),
5085         _REGISTER_CLOCK(NULL, "emi_slow_clk", emi_slow_clk),
5086         _REGISTER_CLOCK(NULL, "emi_clk", emi_clk),
5087         _REGISTER_CLOCK(NULL, "enfc_clk", enfc_clk),
5088         _REGISTER_CLOCK("imx-uart.0", NULL, uart_clk[0]),
5089         _REGISTER_CLOCK("imx-uart.1", NULL, uart_clk[0]),
5090         _REGISTER_CLOCK("imx-uart.2", NULL, uart_clk[0]),
5091         _REGISTER_CLOCK("imx-uart.3", NULL, uart_clk[0]),
5092         _REGISTER_CLOCK(NULL, "hsi_tx", hsi_tx_clk[0]),
5093         _REGISTER_CLOCK(NULL, "caam_clk", caam_clk[0]),
5094         _REGISTER_CLOCK(NULL, "asrc_clk", asrc_clk[0]),
5095         _REGISTER_CLOCK(NULL, "asrc_serial_clk", asrc_clk[1]),
5096         _REGISTER_CLOCK("mxs-dma-apbh", NULL, apbh_dma_clk),
5097         _REGISTER_CLOCK(NULL, "openvg_axi_clk", openvg_axi_clk),
5098         _REGISTER_CLOCK(NULL, "gpu3d_clk", gpu3d_core_clk[0]),
5099         _REGISTER_CLOCK(NULL, "gpu2d_clk", gpu2d_core_clk[0]),
5100         _REGISTER_CLOCK(NULL, "gpu3d_shader_clk", gpu3d_shader_clk),
5101         _REGISTER_CLOCK(NULL, "gpt", gpt_clk[0]),
5102         _REGISTER_CLOCK("imx6q-gpmi-nand.0", NULL, gpmi_nand_clk[0]),
5103         _REGISTER_CLOCK(NULL, "gpmi-apb", gpmi_nand_clk[1]),
5104         _REGISTER_CLOCK(NULL, "bch", gpmi_nand_clk[2]),
5105         _REGISTER_CLOCK(NULL, "bch-apb", gpmi_nand_clk[3]),
5106         _REGISTER_CLOCK(NULL, "pl301_mx6qperl-bch", gpmi_nand_clk[4]),
5107         _REGISTER_CLOCK("mxc_pwm.0", NULL, pwm_clk[0]),
5108         _REGISTER_CLOCK("mxc_pwm.1", NULL, pwm_clk[1]),
5109         _REGISTER_CLOCK("mxc_pwm.2", NULL, pwm_clk[2]),
5110         _REGISTER_CLOCK("mxc_pwm.3", NULL, pwm_clk[3]),
5111         _REGISTER_CLOCK(NULL, "pcie_clk", pcie_clk[0]),
5112         _REGISTER_CLOCK("fec.0", NULL, enet_clk[0]),
5113         _REGISTER_CLOCK(NULL, "imx_sata_clk", sata_clk[0]),
5114         _REGISTER_CLOCK(NULL, "usboh3_clk", usboh3_clk[0]),
5115         _REGISTER_CLOCK(NULL, "usb_phy1_clk", usb_phy1_clk),
5116         _REGISTER_CLOCK(NULL, "usb_phy3_clk", usb_phy3_clk),
5117         _REGISTER_CLOCK(NULL, "usb_phy4_clk", usb_phy4_clk),
5118         _REGISTER_CLOCK("imx2-wdt.0", NULL, dummy_clk),
5119         _REGISTER_CLOCK("imx2-wdt.1", NULL, dummy_clk),
5120         _REGISTER_CLOCK(NULL, "hdmi_isfr_clk", hdmi_clk[0]),
5121         _REGISTER_CLOCK(NULL, "hdmi_iahb_clk", hdmi_clk[1]),
5122         _REGISTER_CLOCK(NULL, "mipi_pllref_clk", mipi_pllref_clk),
5123         _REGISTER_CLOCK(NULL, NULL, vdoa_clk),
5124         _REGISTER_CLOCK(NULL, NULL, aips_tz2_clk),
5125         _REGISTER_CLOCK(NULL, NULL, aips_tz1_clk),
5126         _REGISTER_CLOCK(NULL, "clko_clk", clko_clk),
5127         _REGISTER_CLOCK(NULL, "clko2_clk", clko2_clk),
5128         _REGISTER_CLOCK(NULL, "pxp_axi", ipu2_clk),
5129         _REGISTER_CLOCK(NULL, "epdc_axi", ipu2_clk),
5130         _REGISTER_CLOCK(NULL, "epdc_pix", ipu2_di_clk[1]),
5131         _REGISTER_CLOCK("mxs-perfmon.0", "perfmon", perfmon0_clk),
5132         _REGISTER_CLOCK("mxs-perfmon.1", "perfmon", perfmon1_clk),
5133         _REGISTER_CLOCK("mxs-perfmon.2", "perfmon", perfmon2_clk),
5134         _REGISTER_CLOCK(NULL, "mlb150_clk", mlb150_clk),
5135 };
5136
5137 static void clk_tree_init(void)
5138
5139 {
5140         unsigned int reg;
5141
5142         reg = __raw_readl(MMDC_MDMISC_OFFSET);
5143         if ((reg & MMDC_MDMISC_DDR_TYPE_MASK) ==
5144                 (0x1 << MMDC_MDMISC_DDR_TYPE_OFFSET) ||
5145                 cpu_is_mx6dl()) {
5146                 clk_set_parent(&periph_clk, &pll2_pfd_400M);
5147                 printk(KERN_INFO "Set periph_clk's parent to pll2_pfd_400M!\n");
5148         }
5149 }
5150
5151
5152 int __init mx6_clocks_init(unsigned long ckil, unsigned long osc,
5153         unsigned long ckih1, unsigned long ckih2)
5154 {
5155         __iomem void *base;
5156         int i;
5157
5158         external_low_reference = ckil;
5159         external_high_reference = ckih1;
5160         ckih2_reference = ckih2;
5161         oscillator_reference = osc;
5162
5163         apll_base = ioremap(ANATOP_BASE_ADDR, SZ_4K);
5164
5165         for (i = 0; i < ARRAY_SIZE(lookups); i++) {
5166                 clkdev_add(&lookups[i]);
5167                 clk_debug_register(lookups[i].clk);
5168         }
5169
5170         /* Disable un-necessary PFDs & PLLs */
5171
5172         /* keep correct count. */
5173         clk_enable(&cpu_clk);
5174         clk_enable(&periph_clk);
5175
5176         clk_tree_init();
5177
5178         if (pll2_pfd_400M.usecount == 0 && cpu_is_mx6q())
5179                 pll2_pfd_400M.disable(&pll2_pfd_400M);
5180         pll2_pfd_352M.disable(&pll2_pfd_352M);
5181         pll2_pfd_594M.disable(&pll2_pfd_594M);
5182
5183 #if !defined(CONFIG_FEC_1588)
5184         pll3_pfd_454M.disable(&pll3_pfd_454M);
5185         pll3_pfd_508M.disable(&pll3_pfd_508M);
5186         pll3_pfd_540M.disable(&pll3_pfd_540M);
5187         pll3_pfd_720M.disable(&pll3_pfd_720M);
5188
5189         pll3_usb_otg_main_clk.disable(&pll3_usb_otg_main_clk);
5190 #endif
5191         pll4_audio_main_clk.disable(&pll4_audio_main_clk);
5192         pll5_video_main_clk.disable(&pll5_video_main_clk);
5193         pll6_mlb150_main_clk.disable(&pll6_mlb150_main_clk);
5194         pll7_usb_host_main_clk.disable(&pll7_usb_host_main_clk);
5195         pll8_enet_main_clk.disable(&pll8_enet_main_clk);
5196
5197         sata_clk[0].disable(&sata_clk[0]);
5198         pcie_clk[0].disable(&pcie_clk[0]);
5199
5200         /* Initialize Audio and Video PLLs to valid frequency (650MHz). */
5201         clk_set_rate(&pll4_audio_main_clk, 650000000);
5202         clk_set_rate(&pll5_video_main_clk, 650000000);
5203
5204         clk_set_parent(&ipu1_di_clk[0], &pll5_video_main_clk);
5205         clk_set_parent(&ipu1_di_clk[1], &pll5_video_main_clk);
5206         clk_set_parent(&ipu2_di_clk[0], &pll5_video_main_clk);
5207         clk_set_parent(&ipu2_di_clk[1], &pll5_video_main_clk);
5208
5209         clk_set_parent(&cko1_clk0, &ipg_clk);
5210         clk_set_rate(&cko1_clk0, 22000000);
5211         clk_enable(&cko1_clk0);
5212
5213         clk_set_parent(&emi_clk, &pll2_pfd_400M);
5214         clk_set_rate(&emi_clk, 200000000);
5215
5216         clk_set_parent(&gpu3d_shader_clk, &pll2_pfd_594M);
5217         clk_set_rate(&gpu3d_shader_clk, 594000000);
5218         clk_set_parent(&gpu3d_core_clk[0], &mmdc_ch0_axi_clk[0]);
5219         clk_set_rate(&gpu3d_core_clk[0], 528000000);
5220         if (cpu_is_mx6dl()) {
5221                 /*on mx6dl, 2d core clock sources from 3d shader core clock*/
5222                 clk_set_parent(&gpu2d_core_clk[0], &gpu3d_shader_clk);
5223                 /* on mx6dl gpu2d_axi_clk source from mmdc0 directly */
5224                 clk_set_parent(&gpu2d_axi_clk, &mmdc_ch0_axi_clk[0]);
5225                 gpu2d_axi_clk.secondary = NULL;
5226
5227                 /* on mx6dl, max ipu clock is 274M */
5228                 clk_set_parent(&ipu1_clk, &pll3_pfd_540M);
5229                 clk_set_parent(&ldb_di0_clk, &pll2_pfd_352M);
5230                 clk_set_parent(&ldb_di1_clk, &pll2_pfd_352M);
5231         }
5232         if (cpu_is_mx6q())
5233                 clk_set_parent(&gpu2d_core_clk[0], &pll3_usb_otg_main_clk);
5234
5235         /* PCLK camera - J5 */
5236         clk_set_parent(&clko2_clk, &osc_clk);
5237         clk_set_rate(&clko2_clk, 2400000);
5238
5239         /*
5240          * FIXME: asrc needs to use asrc_serial(spdif1) clock to do sample
5241          * rate convertion and this clock frequency can not be too high, set
5242          * it to the minimum value 7.5Mhz to make asrc work properly.
5243          */
5244         clk_set_parent(&asrc_clk[1], &pll3_sw_clk);
5245         clk_set_rate(&asrc_clk[1], 7500000);
5246
5247         /* set the GPMI clock to default frequency : 20MHz */
5248         clk_set_rate(&enfc_clk, enfc_clk.round_rate(&enfc_clk, 20000000));
5249
5250         mx6_cpu_op_init();
5251         cpu_op_tbl = get_cpu_op(&cpu_op_nr);
5252
5253         /* Gate off all possible clocks */
5254         if (mxc_jtag_enabled) {
5255                 __raw_writel(3 << MXC_CCM_CCGRx_CG11_OFFSET |
5256                              3 << MXC_CCM_CCGRx_CG2_OFFSET |
5257                              3 << MXC_CCM_CCGRx_CG1_OFFSET |
5258                              3 << MXC_CCM_CCGRx_CG0_OFFSET, MXC_CCM_CCGR0);
5259         } else {
5260                 __raw_writel(1 << MXC_CCM_CCGRx_CG11_OFFSET |
5261                              3 << MXC_CCM_CCGRx_CG2_OFFSET |
5262                              3 << MXC_CCM_CCGRx_CG1_OFFSET |
5263                              3 << MXC_CCM_CCGRx_CG0_OFFSET, MXC_CCM_CCGR0);
5264         }
5265         __raw_writel(3 << MXC_CCM_CCGRx_CG10_OFFSET, MXC_CCM_CCGR1);
5266         __raw_writel(1 << MXC_CCM_CCGRx_CG12_OFFSET |
5267                      1 << MXC_CCM_CCGRx_CG11_OFFSET |
5268                      3 << MXC_CCM_CCGRx_CG10_OFFSET |
5269                      3 << MXC_CCM_CCGRx_CG9_OFFSET |
5270                      3 << MXC_CCM_CCGRx_CG8_OFFSET, MXC_CCM_CCGR2);
5271         __raw_writel(1 << MXC_CCM_CCGRx_CG14_OFFSET |
5272                      3 << MXC_CCM_CCGRx_CG13_OFFSET |
5273                      3 << MXC_CCM_CCGRx_CG12_OFFSET |
5274                      3 << MXC_CCM_CCGRx_CG11_OFFSET |
5275                      3 << MXC_CCM_CCGRx_CG10_OFFSET, MXC_CCM_CCGR3);
5276         __raw_writel(3 << MXC_CCM_CCGRx_CG7_OFFSET |
5277                         1 << MXC_CCM_CCGRx_CG6_OFFSET |
5278                         1 << MXC_CCM_CCGRx_CG4_OFFSET, MXC_CCM_CCGR4);
5279         __raw_writel(1 << MXC_CCM_CCGRx_CG0_OFFSET, MXC_CCM_CCGR5);
5280
5281         __raw_writel(0, MXC_CCM_CCGR6);
5282
5283         /* Lower the ipg_perclk frequency to 8.25MHz. */
5284         clk_set_rate(&ipg_perclk, 8250000);
5285
5286         /* S/PDIF */
5287         clk_set_parent(&spdif0_clk[0], &pll3_pfd_454M);
5288
5289         /* pxp & epdc */
5290         clk_set_parent(&ipu2_clk, &pll2_pfd_400M);
5291         clk_set_rate(&ipu2_clk, 200000000);
5292
5293         if (mx6q_revision() == IMX_CHIP_REVISION_1_0) {
5294                 gpt_clk[0].parent = &ipg_perclk;
5295                 gpt_clk[0].get_rate = NULL;
5296         } else {
5297                 /* Here we use OSC 24M as GPT's clock source, no need to
5298                 enable gpt serial clock*/
5299                 gpt_clk[0].secondary = NULL;
5300         }
5301
5302         if (cpu_is_mx6dl()) {
5303                 if (epdc_use_video_pll)
5304                         clk_set_parent(&ipu2_di_clk[1], &pll5_video_main_clk);
5305                 else
5306                         clk_set_parent(&ipu2_di_clk[1], &pll3_pfd_540M);
5307         }
5308
5309         base = ioremap(GPT_BASE_ADDR, SZ_4K);
5310         mxc_timer_init(&gpt_clk[0], base, MXC_INT_GPT);
5311
5312         lp_high_freq = 0;
5313         lp_med_freq = 0;
5314
5315         return 0;
5316
5317 }