arch/arm/mach-mx6/clock.c

   1
   2 /*
   3  * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
   4  */
   5
   6 /*
   7  * The code contained herein is licensed under the GNU General Public
   8  * License. You may obtain a copy of the GNU General Public License
   9  * Version 2 or later at the following locations:
  10  *
  11  * http://www.opensource.org/licenses/gpl-license.html
  12  * http://www.gnu.org/copyleft/gpl.html
  13  */
  14
  15 #include <linux/kernel.h>
  16 #include <linux/init.h>
  17 #include <linux/types.h>
  18 #include <linux/time.h>
  19 #include <linux/hrtimer.h>
  20 #include <linux/mm.h>
  21 #include <linux/errno.h>
  22 #include <linux/delay.h>
  23 #include <linux/clk.h>
  24 #include <linux/io.h>
  25 #include <linux/clkdev.h>
  26 #include <asm/div64.h>
  27 #include <mach/hardware.h>
  28 #include <mach/common.h>
  29 #include <mach/clock.h>
  30 #include <mach/mxc_dvfs.h>
  31 #include "crm_regs.h"
  32 #include "cpu_op-mx6.h"
  33
  34 #ifdef CONFIG_CLK_DEBUG
  35 #define __INIT_CLK_DEBUG(n)     .name = #n,
  36 #else
  37 #define __INIT_CLK_DEBUG(n)
  38 #endif
  39
  40 extern int mxc_jtag_enabled;
  41 extern struct cpu_op *(*get_cpu_op)(int *op);
  42 extern int lp_high_freq;
  43 extern int lp_med_freq;
  44
  45 void __iomem *apll_base;
  46 static struct clk pll1_sys_main_clk;
  47 static struct clk pll2_528_bus_main_clk;
  48 static struct clk pll2_pfd_400M;
  49 static struct clk pll3_usb_otg_main_clk;
  50 static struct clk pll4_audio_main_clk;
  51 static struct clk pll5_video_main_clk;
  52 static struct clk pll6_MLB_main_clk;
  53 static struct clk pll7_usb_host_main_clk;
  54 static struct clk pll8_enet_main_clk;
  55 static struct clk apbh_dma_clk;
  56 static struct clk openvg_axi_clk;
  57 static struct clk enfc_clk;
  58 static struct clk ipu1_di_clk_root;
  59 static struct clk ipu2_di_clk_root;
  60 static struct clk usdhc3_clk;
  61
  62 static struct cpu_op *cpu_op_tbl;
  63 static int cpu_op_nr;
  64
  65 #define SPIN_DELAY      1000000 /* in nanoseconds */
  66
  67 #define AUDIO_VIDEO_MIN_CLK_FREQ        650000000
  68 #define AUDIO_VIDEO_MAX_CLK_FREQ        1300000000
  69
  70 #define WAIT(exp, timeout) \
  71 ({ \
  72         struct timespec nstimeofday; \
  73         struct timespec curtime; \
  74         int result = 1; \
  75         getnstimeofday(&nstimeofday); \
  76         while (!(exp)) { \
  77                 getnstimeofday(&curtime); \
  78                 if ((curtime.tv_nsec - nstimeofday.tv_nsec) > (timeout)) { \
  79                         result = 0; \
  80                         break; \
  81                 } \
  82         } \
  83         result; \
  84 })
  85
  86 /* External clock values passed-in by the board code */
  87 static unsigned long external_high_reference, external_low_reference;
  88 static unsigned long oscillator_reference, ckih2_reference;
  89
  90 static void __calc_pre_post_dividers(u32 max_podf, u32 div, u32 *pre, u32 *post)
  91 {
  92         u32 min_pre, temp_pre, old_err, err;
  93
  94         /* Some of the podfs are 3 bits while others are 6 bits.
  95           * Handle both cases here.
  96           */
  97         if (div >= 512 && (max_podf == 64)) {
  98                 /* For pre = 3bits and podf = 6 bits, max divider is 512. */
  99                 *pre = 8;
 100                 *post = 64;
 101         } else if (div >= 64 && (max_podf == 8)) {
 102                 /* For pre = 3bits and podf = 3 bits, max divider is 64. */
 103                 *pre = 8;
 104                 *post = 8;
 105         } else if (div >= 8) {
 106                 /* Find the minimum pre-divider for a max podf */
 107                 if (max_podf == 64)
 108                         min_pre = (div - 1) / (1 << 6) + 1;
 109                 else
 110                         min_pre = (div - 1) / (1 << 3) + 1;
 111                 old_err = 8;
 112                 /* Now loop through to find the max pre-divider. */
 113                 for (temp_pre = 8; temp_pre >= min_pre; temp_pre--) {
 114                         err = div % temp_pre;
 115                         if (err == 0) {
 116                                 *pre = temp_pre;
 117                                 break;
 118                         }
 119                         err = temp_pre - err;
 120                         if (err < old_err) {
 121                                 old_err = err;
 122                                 *pre = temp_pre;
 123                         }
 124                 }
 125                 *post = (div + *pre - 1) / *pre;
 126         } else if (div < 8) {
 127                 *pre = div;
 128                 *post = 1;
 129         }
 130 }
 131
 132 static int _clk_enable(struct clk *clk)
 133 {
 134         u32 reg;
 135         reg = __raw_readl(clk->enable_reg);
 136         reg |= MXC_CCM_CCGRx_CG_MASK << clk->enable_shift;
 137         __raw_writel(reg, clk->enable_reg);
 138
 139         if (clk->flags & AHB_HIGH_SET_POINT)
 140                 lp_high_freq++;
 141         else if (clk->flags & AHB_MED_SET_POINT)
 142                 lp_med_freq++;
 143
 144         return 0;
 145 }
 146
 147 static void _clk_disable(struct clk *clk)
 148 {
 149         u32 reg;
 150         reg = __raw_readl(clk->enable_reg);
 151         reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift);
 152         __raw_writel(reg, clk->enable_reg);
 153
 154         if (clk->flags & AHB_HIGH_SET_POINT)
 155                 lp_high_freq--;
 156         else if (clk->flags & AHB_MED_SET_POINT)
 157                 lp_med_freq--;
 158 }
 159
 160 static void _clk_disable_inwait(struct clk *clk)
 161 {
 162         u32 reg;
 163         reg = __raw_readl(clk->enable_reg);
 164         reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift);
 165         reg |= 1 << clk->enable_shift;
 166         __raw_writel(reg, clk->enable_reg);
 167 }
 168
 169 /*
 170  * For the 4-to-1 muxed input clock
 171  */
 172 static inline u32 _get_mux(struct clk *parent, struct clk *m0,
 173                            struct clk *m1, struct clk *m2, struct clk *m3)
 174 {
 175         if (parent == m0)
 176                 return 0;
 177         else if (parent == m1)
 178                 return 1;
 179         else if (parent == m2)
 180                 return 2;
 181         else if (parent == m3)
 182                 return 3;
 183         else
 184                 BUG();
 185
 186         return 0;
 187 }
 188
 189 static inline void __iomem *_get_pll_base(struct clk *pll)
 190 {
 191         if (pll == &pll1_sys_main_clk)
 192                 return PLL1_SYS_BASE_ADDR;
 193         else if (pll == &pll2_528_bus_main_clk)
 194                 return PLL2_528_BASE_ADDR;
 195         else if (pll == &pll3_usb_otg_main_clk)
 196                 return PLL3_480_USB1_BASE_ADDR;
 197         else if (pll == &pll4_audio_main_clk)
 198                 return PLL4_AUDIO_BASE_ADDR;
 199         else if (pll == &pll5_video_main_clk)
 200                 return PLL5_VIDEO_BASE_ADDR;
 201         else if (pll == &pll6_MLB_main_clk)
 202                 return PLL6_MLB_BASE_ADDR;
 203         else if (pll == &pll7_usb_host_main_clk)
 204                 return PLL7_480_USB2_BASE_ADDR;
 205         else if (pll == &pll8_enet_main_clk)
 206                 return PLL8_ENET_BASE_ADDR;
 207         else
 208                 BUG();
 209         return NULL;
 210 }
 211
 212
 213 /*
 214  * For the 6-to-1 muxed input clock
 215  */
 216 static inline u32 _get_mux6(struct clk *parent, struct clk *m0, struct clk *m1,
 217                             struct clk *m2, struct clk *m3, struct clk *m4,
 218                             struct clk *m5)
 219 {
 220         if (parent == m0)
 221                 return 0;
 222         else if (parent == m1)
 223                 return 1;
 224         else if (parent == m2)
 225                 return 2;
 226         else if (parent == m3)
 227                 return 3;
 228         else if (parent == m4)
 229                 return 4;
 230         else if (parent == m5)
 231                 return 5;
 232         else
 233                 BUG();
 234
 235         return 0;
 236 }
 237 static unsigned long get_high_reference_clock_rate(struct clk *clk)
 238 {
 239         return external_high_reference;
 240 }
 241
 242 static unsigned long get_low_reference_clock_rate(struct clk *clk)
 243 {
 244         return external_low_reference;
 245 }
 246
 247 static unsigned long get_oscillator_reference_clock_rate(struct clk *clk)
 248 {
 249         return oscillator_reference;
 250 }
 251
 252 static unsigned long get_ckih2_reference_clock_rate(struct clk *clk)
 253 {
 254         return ckih2_reference;
 255 }
 256
 257 /* External high frequency clock */
 258 static struct clk ckih_clk = {
 259         __INIT_CLK_DEBUG(ckih_clk)
 260         .get_rate = get_high_reference_clock_rate,
 261 };
 262
 263 static struct clk ckih2_clk = {
 264         __INIT_CLK_DEBUG(ckih2_clk)
 265         .get_rate = get_ckih2_reference_clock_rate,
 266 };
 267
 268 static struct clk osc_clk = {
 269         __INIT_CLK_DEBUG(osc_clk)
 270         .get_rate = get_oscillator_reference_clock_rate,
 271 };
 272
 273 /* External low frequency (32kHz) clock */
 274 static struct clk ckil_clk = {
 275         __INIT_CLK_DEBUG(ckil_clk)
 276         .get_rate = get_low_reference_clock_rate,
 277 };
 278
 279 static unsigned long pfd_round_rate(struct clk *clk, unsigned long rate)
 280 {
 281         u32 frac;
 282         u64 tmp;
 283
 284         tmp = (u64)clk_get_rate(clk->parent) * 18;
 285         tmp += rate/2;
 286         do_div(tmp, rate);
 287         frac = tmp;
 288         frac = frac < 12 ? 12 : frac;
 289         frac = frac > 35 ? 35 : frac;
 290         tmp = (u64)clk_get_rate(clk->parent) * 18;
 291         do_div(tmp, frac);
 292         return tmp;
 293 }
 294
 295 static unsigned long pfd_get_rate(struct clk *clk)
 296 {
 297         u32 frac;
 298         u64 tmp;
 299         tmp = (u64)clk_get_rate(clk->parent) * 18;
 300
 301         if (apbh_dma_clk.usecount == 0)
 302                 apbh_dma_clk.enable(&apbh_dma_clk);
 303
 304         frac = (__raw_readl(clk->enable_reg) >> clk->enable_shift) &
 305                         ANADIG_PFD_FRAC_MASK;
 306
 307         do_div(tmp, frac);
 308
 309         return tmp;
 310 }
 311
 312 static int pfd_set_rate(struct clk *clk, unsigned long rate)
 313 {
 314         u32 frac;
 315         u64 tmp;
 316         tmp = (u64)clk_get_rate(clk->parent) * 18;
 317
 318         if (apbh_dma_clk.usecount == 0)
 319                 apbh_dma_clk.enable(&apbh_dma_clk);
 320
 321         /* Round up the divider so that we don't set a rate
 322           * higher than what is requested. */
 323         tmp += rate/2;
 324         do_div(tmp, rate);
 325         frac = tmp;
 326         frac = frac < 12 ? 12 : frac;
 327         frac = frac > 35 ? 35 : frac;
 328         /* clear clk frac bits */
 329         __raw_writel(ANADIG_PFD_FRAC_MASK << clk->enable_shift,
 330                         (int)clk->enable_reg + 8);
 331         /* set clk frac bits */
 332         __raw_writel(frac << clk->enable_shift,
 333                         (int)clk->enable_reg + 4);
 334
 335         tmp = (u64)clk_get_rate(clk->parent) * 18;
 336         do_div(tmp, frac);
 337
 338         if (apbh_dma_clk.usecount == 0)
 339                 apbh_dma_clk.disable(&apbh_dma_clk);
 340         return 0;
 341 }
 342
 343 static int _clk_pfd_enable(struct clk *clk)
 344 {
 345         if (apbh_dma_clk.usecount == 0)
 346                 apbh_dma_clk.enable(&apbh_dma_clk);
 347
 348         /* clear clk gate bit */
 349         __raw_writel((1 << (clk->enable_shift + 7)),
 350                         (int)clk->enable_reg + 8);
 351
 352         if (apbh_dma_clk.usecount == 0)
 353                 apbh_dma_clk.disable(&apbh_dma_clk);
 354
 355         return 0;
 356 }
 357
 358 static void _clk_pfd_disable(struct clk *clk)
 359 {
 360         if (apbh_dma_clk.usecount == 0)
 361                 apbh_dma_clk.enable(&apbh_dma_clk);
 362
 363         /* set clk gate bit */
 364         __raw_writel((1 << (clk->enable_shift + 7)),
 365                         (int)clk->enable_reg + 4);
 366
 367         if (apbh_dma_clk.usecount == 0)
 368                 apbh_dma_clk.disable(&apbh_dma_clk);
 369 }
 370
 371 static int _clk_pll_enable(struct clk *clk)
 372 {
 373         unsigned int reg;
 374         void __iomem *pllbase;
 375
 376         pllbase = _get_pll_base(clk);
 377
 378         reg = __raw_readl(pllbase);
 379         reg &= ~ANADIG_PLL_BYPASS;
 380         reg &= ~ANADIG_PLL_POWER_DOWN;
 381
 382         /* The 480MHz PLLs have the opposite definition for power bit. */
 383         if (clk == &pll3_usb_otg_main_clk || clk == &pll7_usb_host_main_clk)
 384                 reg |= ANADIG_PLL_POWER_DOWN;
 385
 386         __raw_writel(reg, pllbase);
 387
 388         /* Wait for PLL to lock */
 389         if (!WAIT(__raw_readl(pllbase) & ANADIG_PLL_LOCK,
 390                                 SPIN_DELAY))
 391                 panic("pll enable failed\n");
 392
 393         /* Enable the PLL output now*/
 394         reg = __raw_readl(pllbase);
 395         reg |= ANADIG_PLL_ENABLE;
 396         __raw_writel(reg, pllbase);
 397
 398         return 0;
 399 }
 400
 401 static void _clk_pll_disable(struct clk *clk)
 402 {
 403         unsigned int reg;
 404         void __iomem *pllbase;
 405
 406         pllbase = _get_pll_base(clk);
 407
 408         reg = __raw_readl(pllbase);
 409         reg |= ANADIG_PLL_BYPASS;
 410         reg |= ANADIG_PLL_POWER_DOWN;
 411
 412         /* The 480MHz PLLs, pll3 & pll7, have the opposite
 413          * definition for power bit.
 414          */
 415         if (clk == &pll3_usb_otg_main_clk || clk == &pll7_usb_host_main_clk)
 416                 reg &= ~ANADIG_PLL_POWER_DOWN;
 417         __raw_writel(reg, pllbase);
 418 }
 419
 420 static unsigned long  _clk_pll1_main_get_rate(struct clk *clk)
 421 {
 422         unsigned int div;
 423         unsigned long val;
 424
 425         div = __raw_readl(PLL1_SYS_BASE_ADDR) & ANADIG_PLL_SYS_DIV_SELECT_MASK;
 426         val = (clk_get_rate(clk->parent) * div) / 2;
 427         return val;
 428 }
 429
 430 static int _clk_pll1_main_set_rate(struct clk *clk, unsigned long rate)
 431 {
 432         unsigned int reg,  div;
 433
 434         if (rate < AUDIO_VIDEO_MIN_CLK_FREQ || rate > AUDIO_VIDEO_MAX_CLK_FREQ)
 435                 return -EINVAL;
 436
 437         div = (rate * 2) / clk_get_rate(clk->parent) ;
 438
 439         reg = __raw_readl(PLL1_SYS_BASE_ADDR) & ~ANADIG_PLL_SYS_DIV_SELECT_MASK;
 440         reg |= div;
 441         __raw_writel(reg, PLL1_SYS_BASE_ADDR);
 442
 443         return 0;
 444 }
 445
 446 static struct clk pll1_sys_main_clk = {
 447         __INIT_CLK_DEBUG(pll1_sys_main_clk)
 448         .parent = &osc_clk,
 449         .get_rate = _clk_pll1_main_get_rate,
 450         .set_rate = _clk_pll1_main_set_rate,
 451         .enable = _clk_pll_enable,
 452         .disable = _clk_pll_disable,
 453 };
 454
 455 static int _clk_pll1_sw_set_parent(struct clk *clk, struct clk *parent)
 456 {
 457         u32 reg;
 458
 459         reg = __raw_readl(MXC_CCM_CCSR);
 460
 461         if (parent == &pll1_sys_main_clk) {
 462                 reg &= ~MXC_CCM_CCSR_PLL1_SW_CLK_SEL;
 463                 __raw_writel(reg, MXC_CCM_CCSR);
 464                 /* Set the step_clk parent to be lp_apm, to save power. */
 465                 reg = __raw_readl(MXC_CCM_CCSR);
 466                 reg = (reg & ~MXC_CCM_CCSR_STEP_SEL);
 467         } else {
 468                 /* Set STEP_CLK to be the parent*/
 469                 if (parent == &osc_clk) {
 470                         /* Set STEP_CLK to be sourced from LPAPM. */
 471                         reg = __raw_readl(MXC_CCM_CCSR);
 472                         reg = (reg & ~MXC_CCM_CCSR_STEP_SEL);
 473                         __raw_writel(reg, MXC_CCM_CCSR);
 474                 } else {
 475                         /* Set STEP_CLK to be sourced from PLL2-PDF (400MHz). */
 476                         reg = __raw_readl(MXC_CCM_CCSR);
 477                         reg |= MXC_CCM_CCSR_STEP_SEL;
 478                         __raw_writel(reg, MXC_CCM_CCSR);
 479
 480                 }
 481                 reg = __raw_readl(MXC_CCM_CCSR);
 482                 reg |= MXC_CCM_CCSR_PLL1_SW_CLK_SEL;
 483         }
 484         __raw_writel(reg, MXC_CCM_CCSR);
 485         return 0;
 486 }
 487
 488 static unsigned long _clk_pll1_sw_get_rate(struct clk *clk)
 489 {
 490         return clk_get_rate(clk->parent);
 491 }
 492
 493 static struct clk pll1_sw_clk = {
 494         __INIT_CLK_DEBUG(pll1_sw_clk)
 495         .parent = &pll1_sys_main_clk,
 496         .set_parent = _clk_pll1_sw_set_parent,
 497         .get_rate = _clk_pll1_sw_get_rate,
 498 };
 499
 500 static unsigned long _clk_pll2_main_get_rate(struct clk *clk)
 501 {
 502         unsigned int div;
 503         unsigned long val;
 504
 505         div = __raw_readl(PLL2_528_BASE_ADDR) & ANADIG_PLL_528_DIV_SELECT;
 506
 507         if (div == 1)
 508                 val = clk_get_rate(clk->parent) * 22;
 509
 510         else
 511                 val = clk_get_rate(clk->parent) * 20;
 512
 513         return val;
 514 }
 515
 516 static int _clk_pll2_main_set_rate(struct clk *clk, unsigned long rate)
 517 {
 518         unsigned int reg,  div;
 519
 520         if (rate == 528000000)
 521                 div = 1;
 522         else if (rate == 480000000)
 523                 div = 0;
 524         else
 525                 return -EINVAL;
 526
 527         reg = __raw_readl(PLL2_528_BASE_ADDR);
 528         reg &= ~ANADIG_PLL_528_DIV_SELECT;
 529         reg |= div;
 530         __raw_writel(reg, PLL2_528_BASE_ADDR);
 531
 532         return 0;
 533 }
 534
 535 static struct clk pll2_528_bus_main_clk = {
 536         __INIT_CLK_DEBUG(pll2_528_bus_main_clk)
 537         .parent = &osc_clk,
 538         .get_rate = _clk_pll2_main_get_rate,
 539         .set_rate = _clk_pll2_main_set_rate,
 540         .enable = _clk_pll_enable,
 541         .disable = _clk_pll_disable,
 542 };
 543
 544 static struct clk pll2_pfd_400M = {
 545         __INIT_CLK_DEBUG(pll2_pfd_400M)
 546         .parent = &pll2_528_bus_main_clk,
 547         .enable_reg = (void *)PFD_528_BASE_ADDR,
 548         .enable_shift = ANADIG_PFD2_FRAC_OFFSET,
 549         .enable = _clk_pfd_enable,
 550         .disable = _clk_pfd_disable,
 551         .get_rate = pfd_get_rate,
 552         .set_rate = pfd_set_rate,
 553         .get_rate = pfd_get_rate,
 554         .round_rate = pfd_round_rate,
 555 };
 556
 557 static struct clk pll2_pfd_352M = {
 558         __INIT_CLK_DEBUG(pll2_pfd_352M)
 559         .parent = &pll2_528_bus_main_clk,
 560         .enable_reg = (void *)PFD_528_BASE_ADDR,
 561         .enable_shift = ANADIG_PFD0_FRAC_OFFSET,
 562         .enable = _clk_pfd_enable,
 563         .disable = _clk_pfd_disable,
 564         .set_rate = pfd_set_rate,
 565         .get_rate = pfd_get_rate,
 566         .round_rate = pfd_round_rate,
 567 };
 568
 569 static struct clk pll2_pfd_594M = {
 570         __INIT_CLK_DEBUG(pll2_pfd_594M)
 571         .parent = &pll2_528_bus_main_clk,
 572         .enable_reg = (void *)PFD_528_BASE_ADDR,
 573         .enable_shift = ANADIG_PFD1_FRAC_OFFSET,
 574         .enable = _clk_pfd_enable,
 575         .disable = _clk_pfd_disable,
 576         .set_rate = pfd_set_rate,
 577         .get_rate = pfd_get_rate,
 578         .round_rate = pfd_round_rate,
 579 };
 580
 581 static unsigned long _clk_pll2_200M_get_rate(struct clk *clk)
 582 {
 583         return clk_get_rate(clk->parent) / 2;
 584 }
 585
 586 static struct clk pll2_200M = {
 587         __INIT_CLK_DEBUG(pll2_200M)
 588         .parent = &pll2_pfd_400M,
 589         .get_rate = _clk_pll2_200M_get_rate,
 590 };
 591
 592 static unsigned long _clk_pll3_usb_otg_get_rate(struct clk *clk)
 593 {
 594         unsigned int div;
 595         unsigned long val;
 596
 597         div = __raw_readl(PLL3_480_USB1_BASE_ADDR)
 598                 & ANADIG_PLL_480_DIV_SELECT_MASK;
 599
 600         if (div == 1)
 601                 val = clk_get_rate(clk->parent) * 22;
 602         else
 603                 val = clk_get_rate(clk->parent) * 20;
 604         return val;
 605 }
 606
 607 static int _clk_pll3_usb_otg_set_rate(struct clk *clk, unsigned long rate)
 608 {
 609         unsigned int reg,  div;
 610
 611         if (rate == 528000000)
 612                 div = 1;
 613         else if (rate == 480000000)
 614                 div = 0;
 615         else
 616                 return -EINVAL;
 617
 618         reg = __raw_readl(PLL3_480_USB1_BASE_ADDR);
 619         reg &= ~ANADIG_PLL_480_DIV_SELECT_MASK;
 620         reg |= div;
 621         __raw_writel(reg, PLL3_480_USB1_BASE_ADDR);
 622
 623         return 0;
 624 }
 625
 626
 627 /* same as pll3_main_clk. These two clocks should always be the same */
 628 static struct clk pll3_usb_otg_main_clk = {
 629         __INIT_CLK_DEBUG(pll3_usb_otg_main_clk)
 630         .parent = &osc_clk,
 631         .enable = _clk_pll_enable,
 632         .disable = _clk_pll_disable,
 633         .set_rate = _clk_pll3_usb_otg_set_rate,
 634         .get_rate = _clk_pll3_usb_otg_get_rate,
 635 };
 636
 637 static struct clk usb_phy1_clk = {
 638         __INIT_CLK_DEBUG(usb_phy1_clk)
 639         .parent = &pll3_usb_otg_main_clk,
 640         .set_rate = _clk_pll3_usb_otg_set_rate,
 641         .get_rate = _clk_pll3_usb_otg_get_rate,
 642 };
 643
 644 static struct clk pll3_pfd_508M = {
 645         __INIT_CLK_DEBUG(pll3_pfd_508M)
 646         .parent = &pll3_usb_otg_main_clk,
 647         .enable_reg = (void *)PFD_480_BASE_ADDR,
 648         .enable_shift = ANADIG_PFD2_FRAC_OFFSET,
 649         .enable = _clk_pfd_enable,
 650         .disable = _clk_pfd_disable,
 651         .set_rate = pfd_set_rate,
 652         .get_rate = pfd_get_rate,
 653         .round_rate = pfd_round_rate,
 654 };
 655
 656 static struct clk pll3_pfd_454M = {
 657         __INIT_CLK_DEBUG(pll3_pfd_454M)
 658         .parent = &pll3_usb_otg_main_clk,
 659         .enable_reg = (void *)PFD_480_BASE_ADDR,
 660         .enable_shift = ANADIG_PFD3_FRAC_OFFSET,
 661         .enable = _clk_pfd_enable,
 662         .disable = _clk_pfd_disable,
 663         .set_rate = pfd_set_rate,
 664         .get_rate = pfd_get_rate,
 665         .round_rate = pfd_round_rate,
 666 };
 667
 668 static struct clk pll3_pfd_720M = {
 669         __INIT_CLK_DEBUG(pll3_pfd_720M)
 670         .parent = &pll3_usb_otg_main_clk,
 671         .enable_reg = (void *)PFD_480_BASE_ADDR,
 672         .enable_shift = ANADIG_PFD0_FRAC_OFFSET,
 673         .enable = _clk_pfd_enable,
 674         .disable = _clk_pfd_disable,
 675         .set_rate = pfd_set_rate,
 676         .get_rate = pfd_get_rate,
 677         .round_rate = pfd_round_rate,
 678 };
 679
 680 static struct clk pll3_pfd_540M = {
 681         __INIT_CLK_DEBUG(pll3_pfd_540M)
 682         .parent = &pll3_usb_otg_main_clk,
 683         .enable_reg = (void *)PFD_480_BASE_ADDR,
 684         .enable_shift = ANADIG_PFD1_FRAC_OFFSET,
 685         .enable = _clk_pfd_enable,
 686         .disable = _clk_pfd_disable,
 687         .set_rate = pfd_set_rate,
 688         .get_rate = pfd_get_rate,
 689         .round_rate = pfd_round_rate,
 690         .get_rate = pfd_get_rate,
 691 };
 692
 693 static unsigned long _clk_pll3_sw_get_rate(struct clk *clk)
 694 {
 695         return clk_get_rate(clk->parent);
 696 }
 697
 698 /* same as pll3_main_clk. These two clocks should always be the same */
 699 static struct clk pll3_sw_clk = {
 700         __INIT_CLK_DEBUG(pll3_sw_clk)
 701         .parent = &pll3_usb_otg_main_clk,
 702         .get_rate = _clk_pll3_sw_get_rate,
 703 };
 704
 705 static unsigned long _clk_pll3_120M_get_rate(struct clk *clk)
 706 {
 707         return clk_get_rate(clk->parent) / 4;
 708 }
 709
 710 static struct clk pll3_120M = {
 711         __INIT_CLK_DEBUG(pll3_120M)
 712         .parent = &pll3_sw_clk,
 713         .get_rate = _clk_pll3_120M_get_rate,
 714 };
 715
 716 static unsigned long _clk_pll3_80M_get_rate(struct clk *clk)
 717 {
 718         return clk_get_rate(clk->parent) / 6;
 719 }
 720
 721 static struct clk pll3_80M = {
 722         __INIT_CLK_DEBUG(pll3_80M)
 723         .parent = &pll3_sw_clk,
 724         .get_rate = _clk_pll3_80M_get_rate,
 725 };
 726
 727 static unsigned long _clk_pll3_60M_get_rate(struct clk *clk)
 728 {
 729         return clk_get_rate(clk->parent) / 8;
 730 }
 731
 732 static struct clk pll3_60M = {
 733         __INIT_CLK_DEBUG(pll3_60M)
 734         .parent = &pll3_sw_clk,
 735         .get_rate = _clk_pll3_60M_get_rate,
 736 };
 737
 738 static unsigned long  _clk_audio_video_get_rate(struct clk *clk)
 739 {
 740         unsigned int div, mfn, mfd;
 741         unsigned long rate;
 742         unsigned int parent_rate = clk_get_rate(clk->parent);
 743         void __iomem *pllbase;
 744
 745         if (clk == &pll4_audio_main_clk)
 746                 pllbase = PLL4_AUDIO_BASE_ADDR;
 747         else
 748                 pllbase = PLL5_VIDEO_BASE_ADDR;
 749
 750         div = __raw_readl(pllbase) & ANADIG_PLL_SYS_DIV_SELECT_MASK;
 751         mfn = __raw_readl(pllbase + PLL_NUM_DIV_OFFSET);
 752         mfd = __raw_readl(pllbase + PLL_DENOM_DIV_OFFSET);
 753
 754         rate = (parent_rate * div) + ((parent_rate / mfd) * mfn);
 755
 756         return rate;
 757 }
 758
 759 static int _clk_audio_video_set_rate(struct clk *clk, unsigned long rate)
 760 {
 761         unsigned int reg,  div;
 762         unsigned int mfn, mfd = 1000000;
 763         s64 temp64;
 764         unsigned int parent_rate = clk_get_rate(clk->parent);
 765         void __iomem *pllbase;
 766
 767         if ((rate < AUDIO_VIDEO_MIN_CLK_FREQ) ||
 768                 (rate > AUDIO_VIDEO_MAX_CLK_FREQ))
 769                 return -EINVAL;
 770
 771         if (clk == &pll4_audio_main_clk)
 772                 pllbase = PLL4_AUDIO_BASE_ADDR;
 773         else
 774                 pllbase = PLL5_VIDEO_BASE_ADDR;
 775
 776         div = rate / parent_rate ;
 777         temp64 = (u64) (rate - (div * parent_rate));
 778         temp64 *= mfd;
 779         do_div(temp64, parent_rate);
 780         mfn = temp64;
 781
 782         reg = __raw_readl(pllbase) & ~ANADIG_PLL_SYS_DIV_SELECT_MASK;
 783         reg |= div;
 784         __raw_writel(reg, pllbase);
 785         __raw_writel(mfn, pllbase + PLL_NUM_DIV_OFFSET);
 786         __raw_writel(mfd, pllbase + PLL_DENOM_DIV_OFFSET);
 787
 788         return 0;
 789 }
 790
 791 static unsigned long _clk_audio_video_round_rate(struct clk *clk,
 792                                                 unsigned long rate)
 793 {
 794         if (rate < AUDIO_VIDEO_MIN_CLK_FREQ)
 795                 return AUDIO_VIDEO_MIN_CLK_FREQ;
 796
 797         if (rate > AUDIO_VIDEO_MAX_CLK_FREQ)
 798                 return AUDIO_VIDEO_MAX_CLK_FREQ;
 799
 800         return rate;
 801 }
 802
 803
 804 static struct clk pll4_audio_main_clk = {
 805         __INIT_CLK_DEBUG(pll4_audio_main_clk)
 806         .parent = &osc_clk,
 807         .enable = _clk_pll_enable,
 808         .disable = _clk_pll_disable,
 809         .set_rate = _clk_audio_video_set_rate,
 810         .get_rate = _clk_audio_video_get_rate,
 811         .round_rate = _clk_audio_video_round_rate,
 812 };
 813
 814
 815 static struct clk pll5_video_main_clk = {
 816         __INIT_CLK_DEBUG(pll5_video_main_clk)
 817         .parent = &osc_clk,
 818         .enable = _clk_pll_enable,
 819         .disable = _clk_pll_disable,
 820         .set_rate = _clk_audio_video_set_rate,
 821         .get_rate = _clk_audio_video_get_rate,
 822         .round_rate = _clk_audio_video_round_rate,
 823 };
 824
 825 static struct clk pll6_MLB_main_clk = {
 826         __INIT_CLK_DEBUG(pll6_MLB_main_clk)
 827         .parent = &osc_clk,
 828         .enable = _clk_pll_enable,
 829         .disable = _clk_pll_disable,
 830 };
 831
 832 static unsigned long _clk_pll7_usb_otg_get_rate(struct clk *clk)
 833 {
 834         unsigned int div;
 835         unsigned long val;
 836
 837         div = __raw_readl(PLL7_480_USB2_BASE_ADDR)
 838                 & ANADIG_PLL_480_DIV_SELECT_MASK;
 839
 840         if (div == 1)
 841                 val = clk_get_rate(clk->parent) * 22;
 842         else
 843                 val = clk_get_rate(clk->parent) * 20;
 844         return val;
 845 }
 846
 847 static int _clk_pll7_usb_otg_set_rate(struct clk *clk, unsigned long rate)
 848 {
 849         unsigned int reg,  div;
 850
 851         if (rate == 528000000)
 852                 div = 1;
 853         else if (rate == 480000000)
 854                 div = 0;
 855         else
 856                 return -EINVAL;
 857
 858         reg = __raw_readl(PLL7_480_USB2_BASE_ADDR);
 859         reg &= ~ANADIG_PLL_480_DIV_SELECT_MASK;
 860         reg |= div;
 861         __raw_writel(reg, PLL7_480_USB2_BASE_ADDR);
 862
 863         return 0;
 864 }
 865
 866 static struct clk pll7_usb_host_main_clk = {
 867         __INIT_CLK_DEBUG(pll7_usb_host_main_clk)
 868         .parent = &osc_clk,
 869         .enable = _clk_pll_enable,
 870         .disable = _clk_pll_disable,
 871         .set_rate = _clk_pll7_usb_otg_set_rate,
 872         .get_rate = _clk_pll7_usb_otg_get_rate,
 873
 874 };
 875
 876 static struct clk pll8_enet_main_clk = {
 877         __INIT_CLK_DEBUG(pll8_enet_main_clk)
 878         .parent = &osc_clk,
 879         .enable = _clk_pll_enable,
 880         .disable = _clk_pll_disable,
 881 };
 882
 883 static unsigned long _clk_arm_get_rate(struct clk *clk)
 884 {
 885         u32 cacrr, div;
 886
 887         cacrr = __raw_readl(MXC_CCM_CACRR);
 888         div = (cacrr & MXC_CCM_CACRR_ARM_PODF_MASK) + 1;
 889         return clk_get_rate(clk->parent) / div;
 890 }
 891
 892 static int _clk_arm_set_rate(struct clk *clk, unsigned long rate)
 893 {
 894         int i;
 895         u32 div;
 896         u32 parent_rate;
 897
 898
 899         for (i = 0; i < cpu_op_nr; i++) {
 900                 if (rate == cpu_op_tbl[i].cpu_rate)
 901                         break;
 902         }
 903         if (i >= cpu_op_nr)
 904                 return -EINVAL;
 905
 906         if (cpu_op_tbl[i].pll_rate != clk_get_rate(&pll1_sys_main_clk)) {
 907                 /* Change the PLL1 rate. */
 908                 if (pll2_pfd_400M.usecount != 0)
 909                         pll1_sw_clk.set_parent(&pll1_sw_clk, &pll2_pfd_400M);
 910                 else
 911                         pll1_sw_clk.set_parent(&pll1_sw_clk, &osc_clk);
 912                 pll1_sys_main_clk.set_rate(&pll1_sys_main_clk, cpu_op_tbl[i].pll_rate);
 913                 pll1_sw_clk.set_parent(&pll1_sw_clk, &pll1_sys_main_clk);
 914         }
 915
 916         parent_rate = clk_get_rate(clk->parent);
 917         div = parent_rate / rate;
 918
 919         if (div == 0)
 920                 div = 1;
 921
 922         if ((parent_rate / div) > rate)
 923                 div++;
 924
 925         if (div > 8)
 926                 return -1;
 927
 928         __raw_writel(div - 1, MXC_CCM_CACRR);
 929
 930         return 0;
 931 }
 932
 933 static struct clk cpu_clk = {
 934         __INIT_CLK_DEBUG(cpu_clk)
 935         .parent = &pll1_sw_clk,
 936         .set_rate = _clk_arm_set_rate,
 937         .get_rate = _clk_arm_get_rate,
 938 };
 939
 940 static int _clk_periph_set_parent(struct clk *clk, struct clk *parent)
 941 {
 942         u32 reg;
 943         int mux;
 944
 945         mux = _get_mux6(parent, &pll2_528_bus_main_clk, &pll2_pfd_400M,
 946                 &pll2_pfd_352M, &pll2_200M, &pll3_sw_clk, &osc_clk);
 947
 948         if (mux <= 3) {
 949                 /* Set the pre_periph_clk multiplexer */
 950                 reg = __raw_readl(MXC_CCM_CBCMR);
 951                 reg &= ~MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK;
 952                 reg |= mux << MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET;
 953                 __raw_writel(reg, MXC_CCM_CBCMR);
 954
 955                 /* Set the periph_clk_sel multiplexer. */
 956                 reg = __raw_readl(MXC_CCM_CBCDR);
 957                 reg &= ~MXC_CCM_CBCDR_PERIPH_CLK_SEL;
 958                 __raw_writel(reg, MXC_CCM_CBCDR);
 959         } else {
 960                 reg = __raw_readl(MXC_CCM_CBCDR);
 961                 /* Set the periph_clk2_podf divider to divide by 1. */
 962                 reg &= ~MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK;
 963                 __raw_writel(reg, MXC_CCM_CBCDR);
 964
 965                 /* Set the periph_clk2_sel mux. */
 966                 reg = __raw_readl(MXC_CCM_CBCMR);
 967                 reg &= ~MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK;
 968                 reg |= ((mux - 4) << MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET);
 969                 __raw_writel(reg, MXC_CCM_CBCMR);
 970
 971                 while (__raw_readl(MXC_CCM_CDHIPR))
 972                         ;
 973
 974                 reg = __raw_readl(MXC_CCM_CBCDR);
 975                 /* Set periph_clk_sel to select periph_clk2. */
 976                 reg |= MXC_CCM_CBCDR_PERIPH_CLK_SEL;
 977                 __raw_writel(reg, MXC_CCM_CBCDR);
 978         }
 979
 980         if (!WAIT(!(__raw_readl(MXC_CCM_CDHIPR)
 981              & MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY), SPIN_DELAY))
 982                 panic("_clk_periph_set_parent failed\n");
 983
 984         return 0;
 985 }
 986
 987 static unsigned long _clk_periph_get_rate(struct clk *clk)
 988 {
 989         u32 div = 1;
 990         u32 reg;
 991         unsigned long val;
 992
 993         if ((clk->parent == &pll3_sw_clk) || (clk->parent == &osc_clk)) {
 994                 reg = __raw_readl(MXC_CCM_CBCDR)
 995                         & MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK;
 996                 div = (reg >> MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET) + 1;
 997         }
 998         val = clk_get_rate(clk->parent) / div;
 999         return val;
1000 }
1001
1002 static struct clk periph_clk = {
1003         __INIT_CLK_DEBUG(periph_clk)
1004         .parent = &pll2_528_bus_main_clk,
1005         .set_parent = _clk_periph_set_parent,
1006         .get_rate = _clk_periph_get_rate,
1007 };
1008
1009 static unsigned long _clk_axi_get_rate(struct clk *clk)
1010 {
1011         u32 div, reg;
1012         unsigned long val;
1013
1014         reg = __raw_readl(MXC_CCM_CBCDR) & MXC_CCM_CBCDR_AXI_PODF_MASK;
1015         div = (reg >> MXC_CCM_CBCDR_AXI_PODF_OFFSET);
1016
1017         val = clk_get_rate(clk->parent) / (div + 1);
1018         return val;
1019 }
1020
1021 static int _clk_axi_set_rate(struct clk *clk, unsigned long rate)
1022 {
1023         u32 reg, div;
1024         u32 parent_rate = clk_get_rate(clk->parent);
1025
1026         div = parent_rate / rate;
1027
1028         if (div == 0)
1029                 div++;
1030         if (((parent_rate / div) != rate) || (div > 8))
1031                 return -EINVAL;
1032
1033         reg = __raw_readl(MXC_CCM_CBCDR);
1034         reg &= ~MXC_CCM_CBCDR_AXI_PODF_MASK;
1035         reg |= (div - 1) << MXC_CCM_CBCDR_AXI_PODF_OFFSET;
1036         __raw_writel(reg, MXC_CCM_CBCDR);
1037
1038         if (!WAIT(!(__raw_readl(MXC_CCM_CDHIPR)
1039              & MXC_CCM_CDHIPR_AXI_PODF_BUSY), SPIN_DELAY))
1040                 panic("pll _clk_axi_a_set_rate failed\n");
1041
1042         return 0;
1043 }
1044
1045 static unsigned long _clk_axi_round_rate(struct clk *clk,
1046                                                 unsigned long rate)
1047 {
1048         u32 div;
1049         u32 parent_rate = clk_get_rate(clk->parent);
1050
1051         div = parent_rate / rate;
1052
1053         /* Make sure rate is not greater than the maximum
1054          * value for the clock.
1055          * Also prevent a div of 0.
1056          */
1057
1058         if (div > 8)
1059                 div = 8;
1060         else if (div == 0)
1061                 div++;
1062
1063         return parent_rate / div;
1064 }
1065
1066 static int _clk_axi_set_parent(struct clk *clk, struct clk *parent)
1067 {
1068         u32 reg;
1069         int mux;
1070
1071         mux = _get_mux6(parent, &periph_clk, &pll2_pfd_400M,
1072                                 &pll3_pfd_540M, NULL, NULL, NULL);
1073
1074         if (mux == 0) {
1075                 /* Set the AXI_SEL mux */
1076                 reg = __raw_readl(MXC_CCM_CBCDR) & ~MXC_CCM_CBCDR_AXI_SEL;
1077                 __raw_writel(reg, MXC_CCM_CBCDR);
1078         } else {
1079                 /* Set the AXI_ALT_SEL mux. */
1080                 reg = __raw_readl(MXC_CCM_CBCDR)
1081                         & ~MXC_CCM_CBCDR_AXI_ALT_SEL_MASK;
1082                 reg = ((mux - 1) << MXC_CCM_CBCDR_AXI_ALT_SEL_OFFSET);
1083                 __raw_writel(reg, MXC_CCM_CBCDR);
1084
1085                 /* Set the AXI_SEL mux */
1086                 reg = __raw_readl(MXC_CCM_CBCDR) & ~MXC_CCM_CBCDR_AXI_SEL;
1087                 reg |= MXC_CCM_CBCDR_AXI_SEL;
1088                 __raw_writel(reg, MXC_CCM_CBCDR);
1089         }
1090         return 0;
1091 }
1092
1093 static struct clk axi_clk = {
1094         __INIT_CLK_DEBUG(axi_clk)
1095         .parent = &periph_clk,
1096         .set_parent = _clk_axi_set_parent,
1097         .set_rate = _clk_axi_set_rate,
1098         .get_rate = _clk_axi_get_rate,
1099         .round_rate = _clk_axi_round_rate,
1100 };
1101
1102 static unsigned long _clk_ahb_get_rate(struct clk *clk)
1103 {
1104         u32 reg, div;
1105
1106         reg = __raw_readl(MXC_CCM_CBCDR);
1107         div = ((reg & MXC_CCM_CBCDR_AHB_PODF_MASK) >>
1108                MXC_CCM_CBCDR_AHB_PODF_OFFSET) + 1;
1109
1110         return clk_get_rate(clk->parent) / div;
1111 }
1112
1113 static int _clk_ahb_set_rate(struct clk *clk, unsigned long rate)
1114 {
1115         u32 reg, div;
1116         u32 parent_rate = clk_get_rate(clk->parent);
1117
1118         div = parent_rate / rate;
1119         if (div == 0)
1120                 div++;
1121         if (((parent_rate / div) != rate) || (div > 8))
1122                 return -EINVAL;
1123
1124         reg = __raw_readl(MXC_CCM_CBCDR);
1125         reg &= ~MXC_CCM_CBCDR_AHB_PODF_MASK;
1126         reg |= (div - 1) << MXC_CCM_CBCDR_AHB_PODF_OFFSET;
1127         __raw_writel(reg, MXC_CCM_CBCDR);
1128
1129         if (!WAIT(!(__raw_readl(MXC_CCM_CDHIPR) & MXC_CCM_CDHIPR_AHB_PODF_BUSY),
1130                                 SPIN_DELAY))
1131                         panic("_clk_ahb_set_rate failed\n");
1132
1133         return 0;
1134 }
1135
1136 static unsigned long _clk_ahb_round_rate(struct clk *clk,
1137                                                 unsigned long rate)
1138 {
1139         u32 div;
1140         u32 parent_rate = clk_get_rate(clk->parent);
1141
1142         div = parent_rate / rate;
1143
1144         /* Make sure rate is not greater than the maximum value for the clock.
1145          * Also prevent a div of 0.
1146          */
1147         if (div == 0)
1148                 div++;
1149
1150         if (div > 8)
1151                 div = 8;
1152
1153         return parent_rate / div;
1154 }
1155
1156 static struct clk ahb_clk = {
1157         __INIT_CLK_DEBUG(ahb_clk)
1158         .parent = &periph_clk,
1159         .get_rate = _clk_ahb_get_rate,
1160         .set_rate = _clk_ahb_set_rate,
1161         .round_rate = _clk_ahb_round_rate,
1162 };
1163
1164 static unsigned long _clk_ipg_get_rate(struct clk *clk)
1165 {
1166         u32 reg, div;
1167
1168         reg = __raw_readl(MXC_CCM_CBCDR);
1169         div = ((reg & MXC_CCM_CBCDR_IPG_PODF_MASK) >>
1170                 MXC_CCM_CBCDR_IPG_PODF_OFFSET) + 1;
1171
1172         return clk_get_rate(clk->parent) / div;
1173 }
1174
1175
1176 static struct clk ipg_clk = {
1177         __INIT_CLK_DEBUG(ipg_clk)
1178         .parent = &ahb_clk,
1179         .get_rate = _clk_ipg_get_rate,
1180 };
1181
1182 static struct clk tzasc1_clk = {
1183         __INIT_CLK_DEBUG(tzasc1_clk)
1184         .id = 0,
1185         .parent = &ipg_clk,
1186         .enable_reg = MXC_CCM_CCGR2,
1187         .enable_shift = MXC_CCM_CCGRx_CG11_OFFSET,
1188         .enable = _clk_enable,
1189         .disable = _clk_disable_inwait,
1190 };
1191
1192 static struct clk tzasc2_clk = {
1193         __INIT_CLK_DEBUG(tzasc2_clk)
1194         .id = 0,
1195         .parent = &ipg_clk,
1196         .enable_reg = MXC_CCM_CCGR2,
1197         .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET,
1198         .enable = _clk_enable,
1199         .disable = _clk_disable_inwait,
1200 };
1201
1202 static struct clk mx6fast1_clk = {
1203         __INIT_CLK_DEBUG(mx6fast1_clk)
1204         .id = 0,
1205         .parent = &ahb_clk,
1206         .enable_reg = MXC_CCM_CCGR4,
1207         .enable_shift = MXC_CCM_CCGRx_CG4_OFFSET,
1208         .enable = _clk_enable,
1209         .disable = _clk_disable_inwait,
1210 };
1211
1212 static struct clk mx6per1_clk = {
1213         __INIT_CLK_DEBUG(mx6per1_clk)
1214         .id = 0,
1215         .parent = &ahb_clk,
1216         .secondary = &mx6fast1_clk,
1217         .enable_reg = MXC_CCM_CCGR4,
1218         .enable_shift = MXC_CCM_CCGRx_CG6_OFFSET,
1219         .enable = _clk_enable,
1220         .disable = _clk_disable_inwait,
1221 };
1222
1223 static struct clk mx6per2_clk = {
1224         __INIT_CLK_DEBUG(mx6per2_clk)
1225         .id = 0,
1226         .parent = &ahb_clk,
1227         .enable_reg = MXC_CCM_CCGR4,
1228         .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
1229         .enable = _clk_enable,
1230         .disable = _clk_disable_inwait,
1231 };
1232
1233 static unsigned long _clk_mmdc_ch0_axi_get_rate(struct clk *clk)
1234 {
1235         u32 reg, div;
1236
1237         reg = __raw_readl(MXC_CCM_CBCDR);
1238         div = ((reg & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
1239                         MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET) + 1;
1240
1241         return clk_get_rate(clk->parent) / div;
1242 }
1243
1244 static int _clk_mmdc_ch0_axi_set_rate(struct clk *clk, unsigned long rate)
1245 {
1246         u32 reg, div;
1247         u32 parent_rate = clk_get_rate(clk->parent);
1248
1249         div = parent_rate / rate;
1250         if (div == 0)
1251                 div++;
1252         if (((parent_rate / div) != rate) || (div > 8))
1253                 return -EINVAL;
1254
1255         reg = __raw_readl(MXC_CCM_CBCDR);
1256         reg &= ~MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK;
1257         reg |= (div - 1) << MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
1258         __raw_writel(reg, MXC_CCM_CBCDR);
1259
1260         if (!WAIT(!(__raw_readl(MXC_CCM_CDHIPR)
1261                 & MXC_CCM_CDHIPR_MMDC_CH0_PODF_BUSY),
1262                                 SPIN_DELAY))
1263                         panic("_clk_mmdc_ch0_axi_set_rate failed\n");
1264
1265         return 0;
1266 }
1267
1268 static unsigned long _clk_mmdc_ch0_axi_round_rate(struct clk *clk,
1269                                                 unsigned long rate)
1270 {
1271         u32 div;
1272         u32 parent_rate = clk_get_rate(clk->parent);
1273
1274         div = parent_rate / rate;
1275
1276         /* Make sure rate is not greater than the maximum value for the clock.
1277          * Also prevent a div of 0.
1278          */
1279         if (div == 0)
1280                 div++;
1281
1282         if (div > 8)
1283                 div = 8;
1284
1285         return parent_rate / div;
1286 }
1287
1288 static struct clk mmdc_ch0_axi_clk[] = {
1289         {
1290         __INIT_CLK_DEBUG(mmdc_ch0_axi_clk)
1291         .id = 0,
1292         .parent = &periph_clk,
1293         .enable = _clk_enable,
1294         .disable = _clk_disable_inwait,
1295         .enable_reg = MXC_CCM_CCGR3,
1296         .enable_shift = MXC_CCM_CCGRx_CG10_OFFSET,
1297         .secondary = &mmdc_ch0_axi_clk[1],
1298         .get_rate = _clk_mmdc_ch0_axi_get_rate,
1299         .set_rate = _clk_mmdc_ch0_axi_set_rate,
1300         .round_rate = _clk_mmdc_ch0_axi_round_rate,
1301         },
1302         {
1303         __INIT_CLK_DEBUG(mmdc_ch0_ipg_clk)
1304         .id = 0,
1305         .parent = &ipg_clk,
1306         .enable = _clk_enable,
1307         .disable = _clk_disable_inwait,
1308         .enable_reg = MXC_CCM_CCGR3,
1309         .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET,
1310         .secondary = &tzasc1_clk,
1311         },
1312 };
1313
1314 static unsigned long _clk_mmdc_ch1_axi_get_rate(struct clk *clk)
1315 {
1316         u32 reg, div;
1317
1318         reg = __raw_readl(MXC_CCM_CBCDR);
1319         div = ((reg & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) >>
1320                         MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET) + 1;
1321
1322         return clk_get_rate(clk->parent) / div;
1323 }
1324
1325 static int _clk_mmdc_ch1_axi_set_rate(struct clk *clk, unsigned long rate)
1326 {
1327         u32 reg, div;
1328         u32 parent_rate = clk_get_rate(clk->parent);
1329
1330         div = parent_rate / rate;
1331         if (div == 0)
1332                 div++;
1333         if (((parent_rate / div) != rate) || (div > 8))
1334                 return -EINVAL;
1335
1336         reg = __raw_readl(MXC_CCM_CBCDR);
1337         reg &= ~MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK;
1338         reg |= (div - 1) << MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
1339         __raw_writel(reg, MXC_CCM_CBCDR);
1340
1341         if (!WAIT(!(__raw_readl(MXC_CCM_CDHIPR)
1342                 & MXC_CCM_CDHIPR_MMDC_CH1_PODF_BUSY), SPIN_DELAY))
1343                         panic("_clk_mmdc_ch1_axi_set_rate failed\n");
1344
1345         return 0;
1346 }
1347
1348 static unsigned long _clk_mmdc_ch1_axi_round_rate(struct clk *clk,
1349                                                 unsigned long rate)
1350 {
1351         u32 div;
1352         u32 parent_rate = clk_get_rate(clk->parent);
1353
1354         div = parent_rate / rate;
1355
1356         /* Make sure rate is not greater than the maximum value for the clock.
1357          * Also prevent a div of 0.
1358          */
1359         if (div == 0)
1360                 div++;
1361
1362         if (div > 8)
1363                 div = 8;
1364
1365         return parent_rate / div;
1366 }
1367
1368 static struct clk mmdc_ch1_axi_clk[] = {
1369         {
1370         __INIT_CLK_DEBUG(mmdc_ch1_axi_clk)
1371         .id = 0,
1372         .parent = &pll2_pfd_400M,
1373         .enable = _clk_enable,
1374         .disable = _clk_disable,
1375         .enable_reg = MXC_CCM_CCGR3,
1376         .enable_shift = MXC_CCM_CCGRx_CG11_OFFSET,
1377         .secondary = &mmdc_ch1_axi_clk[1],
1378         .get_rate = _clk_mmdc_ch1_axi_get_rate,
1379         .set_rate = _clk_mmdc_ch1_axi_set_rate,
1380         .round_rate = _clk_mmdc_ch1_axi_round_rate,
1381         },
1382         {
1383         .id = 1,
1384         __INIT_CLK_DEBUG(mmdc_ch1_ipg_clk)
1385         .parent = &ipg_clk,
1386         .enable = _clk_enable,
1387         .disable = _clk_disable,
1388         .enable_reg = MXC_CCM_CCGR3,
1389         .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
1390         .secondary = &tzasc2_clk,
1391         },
1392 };
1393
1394 static struct clk ocram_clk = {
1395         __INIT_CLK_DEBUG(ocram_clk)
1396         .id = 0,
1397         .parent = &ahb_clk,
1398         .enable_reg = MXC_CCM_CCGR3,
1399         .enable_shift = MXC_CCM_CCGRx_CG14_OFFSET,
1400         .enable = _clk_enable,
1401         .disable = _clk_disable_inwait,
1402 };
1403
1404 static unsigned long _clk_ipg_perclk_get_rate(struct clk *clk)
1405 {
1406         u32 reg, div;
1407
1408         reg = __raw_readl(MXC_CCM_CSCMR1);
1409         div = ((reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK) >>
1410                         MXC_CCM_CSCMR1_PERCLK_PODF_OFFSET) + 1;
1411
1412         return clk_get_rate(clk->parent) / div;
1413 }
1414
1415 static int _clk_ipg_perclk_set_rate(struct clk *clk, unsigned long rate)
1416 {
1417         u32 reg, div;
1418         u32 parent_rate = clk_get_rate(clk->parent);
1419
1420         div = parent_rate / rate;
1421         if (div == 0)
1422                 div++;
1423         if (((parent_rate / div) != rate) || (div > 64))
1424                 return -EINVAL;
1425
1426         reg = __raw_readl(MXC_CCM_CSCMR1);
1427         reg &= ~MXC_CCM_CSCMR1_PERCLK_PODF_MASK;
1428         reg |= (div - 1) << MXC_CCM_CSCMR1_PERCLK_PODF_OFFSET;
1429         __raw_writel(reg, MXC_CCM_CSCMR1);
1430
1431         return 0;
1432 }
1433
1434
1435 static unsigned long _clk_ipg_perclk_round_rate(struct clk *clk,
1436                                                 unsigned long rate)
1437 {
1438         u32 div;
1439         u32 parent_rate = clk_get_rate(clk->parent);
1440
1441         div = parent_rate / rate;
1442
1443         /* Make sure rate is not greater than the maximum value for the clock.
1444          * Also prevent a div of 0.
1445          */
1446         if (div == 0)
1447                 div++;
1448
1449         if (div > 64)
1450                 div = 64;
1451
1452         return parent_rate / div;
1453 }
1454
1455 static struct clk ipg_perclk = {
1456         __INIT_CLK_DEBUG(ipg_perclk)
1457         .parent = &ipg_clk,
1458         .get_rate = _clk_ipg_perclk_get_rate,
1459         .set_rate = _clk_ipg_perclk_set_rate,
1460         .round_rate = _clk_ipg_perclk_round_rate,
1461 };
1462
1463 static struct clk spba_clk = {
1464         __INIT_CLK_DEBUG(spba_clk)
1465         .parent = &ipg_clk,
1466         .enable_reg = MXC_CCM_CCGR5,
1467         .enable_shift = MXC_CCM_CCGRx_CG6_OFFSET,
1468         .enable = _clk_enable,
1469         .disable = _clk_disable,
1470 };
1471
1472 static struct clk sdma_clk[] = {
1473         {
1474          __INIT_CLK_DEBUG(sdma_clk)
1475          .parent = &ahb_clk,
1476          .enable_reg = MXC_CCM_CCGR5,
1477          .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET,
1478          .enable = _clk_enable,
1479          .disable = _clk_disable,
1480          .secondary = &sdma_clk[1],
1481         },
1482         {
1483          .parent = &mx6per1_clk,
1484 #ifdef CONFIG_SDMA_IRAM
1485          .secondary = &ocram_clk,
1486 #else
1487         .secondary = &mmdc_ch0_axi_clk[0],
1488 #endif
1489         },
1490 };
1491
1492 static int _clk_gpu2d_axi_set_parent(struct clk *clk, struct clk *parent)
1493 {
1494         u32 reg = __raw_readl(MXC_CCM_CBCMR) & ~MXC_CCM_CBCMR_GPU2D_AXI_CLK_SEL;
1495
1496         if (parent == &ahb_clk)
1497                 reg |= MXC_CCM_CBCMR_GPU2D_AXI_CLK_SEL;
1498
1499         __raw_writel(reg, MXC_CCM_CBCMR);
1500
1501         return 0;
1502 }
1503
1504 static struct clk gpu2d_axi_clk = {
1505         __INIT_CLK_DEBUG(gpu2d_axi_clk)
1506         .parent = &axi_clk,
1507         .secondary = &mmdc_ch0_axi_clk[0],
1508         .set_parent = _clk_gpu2d_axi_set_parent,
1509 };
1510
1511 static int _clk_gpu3d_axi_set_parent(struct clk *clk, struct clk *parent)
1512 {
1513         u32 reg = __raw_readl(MXC_CCM_CBCMR) & ~MXC_CCM_CBCMR_GPU3D_AXI_CLK_SEL;
1514
1515         if (parent == &ahb_clk)
1516                 reg |= MXC_CCM_CBCMR_GPU3D_AXI_CLK_SEL;
1517
1518         __raw_writel(reg, MXC_CCM_CBCMR);
1519
1520         return 0;
1521 }
1522
1523 static struct clk gpu3d_axi_clk = {
1524         __INIT_CLK_DEBUG(gpu3d_axi_clk)
1525         .parent = &axi_clk,
1526         .secondary = &mmdc_ch0_axi_clk[0],
1527         .set_parent = _clk_gpu3d_axi_set_parent,
1528 };
1529
1530 static int _clk_pcie_axi_set_parent(struct clk *clk, struct clk *parent)
1531 {
1532         u32 reg = __raw_readl(MXC_CCM_CBCMR) & ~MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL;
1533
1534         if (parent == &ahb_clk)
1535                 reg |= MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL;
1536
1537         __raw_writel(reg, MXC_CCM_CBCMR);
1538
1539         return 0;
1540 }
1541
1542 static struct clk pcie_axi_clk = {
1543         __INIT_CLK_DEBUG(pcie_axi_clk)
1544         .parent = &axi_clk,
1545         .set_parent = _clk_pcie_axi_set_parent,
1546 };
1547
1548 static int _clk_vdo_axi_set_parent(struct clk *clk, struct clk *parent)
1549 {
1550         u32 reg = __raw_readl(MXC_CCM_CBCMR) & ~MXC_CCM_CBCMR_VDOAXI_CLK_SEL;
1551
1552         if (parent == &ahb_clk)
1553                 reg |= MXC_CCM_CBCMR_VDOAXI_CLK_SEL;
1554
1555         __raw_writel(reg, MXC_CCM_CBCMR);
1556
1557         return 0;
1558 }
1559
1560 static struct clk vdo_axi_clk = {
1561         __INIT_CLK_DEBUG(vdo_axi_clk)
1562         .parent = &axi_clk,
1563         .enable_reg = MXC_CCM_CCGR6,
1564         .enable_shift = MXC_CCM_CCGRx_CG6_OFFSET,
1565         .enable = _clk_enable,
1566         .disable = _clk_disable,
1567         .set_parent = _clk_vdo_axi_set_parent,
1568 };
1569
1570 static struct clk vdoa_clk = {
1571         __INIT_CLK_DEBUG(vdoa_clk)
1572         .id = 0,
1573         .parent = &axi_clk,
1574         .secondary = &mx6fast1_clk,
1575         .enable_reg = MXC_CCM_CCGR2,
1576         .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
1577         .enable = _clk_enable,
1578         .disable = _clk_disable,
1579 };
1580
1581 static struct clk gpt_clk[] = {
1582         {
1583         __INIT_CLK_DEBUG(gpt_clk)
1584          .parent = &ipg_perclk,
1585          .id = 0,
1586          .enable_reg = MXC_CCM_CCGR1,
1587          .enable_shift = MXC_CCM_CCGRx_CG10_OFFSET,
1588          .enable = _clk_enable,
1589          .disable = _clk_disable,
1590          .secondary = &gpt_clk[1],
1591          },
1592         {
1593         __INIT_CLK_DEBUG(gpt_serial_clk)
1594          .id = 0,
1595          .enable_reg = MXC_CCM_CCGR1,
1596          .enable_shift = MXC_CCM_CCGRx_CG11_OFFSET,
1597          .enable = _clk_enable,
1598          .disable = _clk_disable,
1599          },
1600 };
1601
1602 static struct clk iim_clk = {
1603         __INIT_CLK_DEBUG(iim_clk)
1604         .parent = &ipg_clk,
1605         .enable = _clk_enable,
1606         .enable_reg = MXC_CCM_CCGR2,
1607         .enable_shift = MXC_CCM_CCGRx_CG6_OFFSET,
1608         .disable = _clk_disable,
1609 };
1610
1611 static struct clk i2c_clk[] = {
1612         {
1613         __INIT_CLK_DEBUG(i2c_clk_0)
1614          .id = 0,
1615          .parent = &ipg_perclk,
1616          .enable_reg = MXC_CCM_CCGR2,
1617          .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET,
1618          .enable = _clk_enable,
1619          .disable = _clk_disable,
1620          },
1621         {
1622         __INIT_CLK_DEBUG(i2c_clk_1)
1623          .id = 1,
1624          .parent = &ipg_perclk,
1625          .enable_reg = MXC_CCM_CCGR2,
1626          .enable_shift = MXC_CCM_CCGRx_CG4_OFFSET,
1627          .enable = _clk_enable,
1628          .disable = _clk_disable,
1629          },
1630         {
1631         __INIT_CLK_DEBUG(i2c_clk_2)
1632          .id = 2,
1633          .parent = &ipg_perclk,
1634          .enable_reg = MXC_CCM_CCGR2,
1635          .enable_shift = MXC_CCM_CCGRx_CG5_OFFSET,
1636          .enable = _clk_enable,
1637          .disable = _clk_disable,
1638          },
1639 };
1640
1641 static int _clk_vpu_axi_set_parent(struct clk *clk, struct clk *parent)
1642 {
1643         int mux;
1644         u32 reg = __raw_readl(MXC_CCM_CBCMR)
1645                 & ~MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK;
1646
1647         mux = _get_mux6(parent, &axi_clk, &pll2_pfd_400M,
1648                 &pll2_pfd_352M, NULL, NULL, NULL);
1649
1650         reg |= (mux << MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET);
1651
1652         __raw_writel(reg, MXC_CCM_CBCMR);
1653
1654         return 0;
1655 }
1656
1657 static unsigned long _clk_vpu_axi_get_rate(struct clk *clk)
1658 {
1659         u32 reg, div;
1660
1661         reg = __raw_readl(MXC_CCM_CSCDR1);
1662         div = ((reg & MXC_CCM_CSCDR1_VPU_AXI_PODF_MASK) >>
1663                         MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET) + 1;
1664
1665         return clk_get_rate(clk->parent) / div;
1666 }
1667
1668 static int _clk_vpu_axi_set_rate(struct clk *clk, unsigned long rate)
1669 {
1670         u32 reg, div;
1671         u32 parent_rate = clk_get_rate(clk->parent);
1672
1673         div = parent_rate / rate;
1674         if (div == 0)
1675                 div++;
1676         if (((parent_rate / div) != rate) || (div > 8))
1677                 return -EINVAL;
1678
1679         reg = __raw_readl(MXC_CCM_CSCDR1);
1680         reg &= ~MXC_CCM_CSCDR1_VPU_AXI_PODF_MASK;
1681         reg |= (div - 1) << MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET;
1682         __raw_writel(reg, MXC_CCM_CSCDR1);
1683
1684         return 0;
1685 }
1686
1687 static unsigned long _clk_vpu_axi_round_rate(struct clk *clk,
1688                                                 unsigned long rate)
1689 {
1690         u32 div;
1691         u32 parent_rate = clk_get_rate(clk->parent);
1692
1693         div = parent_rate / rate;
1694
1695         /* Make sure rate is not greater than the maximum value for the clock.
1696          * Also prevent a div of 0.
1697          */
1698         if (div == 0)
1699                 div++;
1700
1701         if (div > 8)
1702                 div = 8;
1703
1704         return parent_rate / div;
1705 }
1706
1707 static struct clk vpu_clk[] = {
1708         {
1709         __INIT_CLK_DEBUG(vpu_clk)
1710         .parent = &axi_clk,
1711         .enable_reg = MXC_CCM_CCGR6,
1712         .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
1713         .enable = _clk_enable,
1714         .disable = _clk_disable,
1715         .set_parent = _clk_vpu_axi_set_parent,
1716         .round_rate = _clk_vpu_axi_round_rate,
1717         .set_rate = _clk_vpu_axi_set_rate,
1718         .get_rate = _clk_vpu_axi_get_rate,
1719         .secondary = &vpu_clk[1],
1720         },
1721         {
1722         .parent =  &mmdc_ch0_axi_clk[0],
1723         .secondary = &vpu_clk[2],
1724         },
1725         {
1726         .parent =  &mx6fast1_clk,
1727         .secondary = &ocram_clk,
1728         },
1729
1730 };
1731
1732 static int _clk_ipu1_set_parent(struct clk *clk, struct clk *parent)
1733 {
1734         int mux;
1735         u32 reg = __raw_readl(MXC_CCM_CSCDR3)
1736                 & ~MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_MASK;
1737
1738         mux = _get_mux6(parent, &mmdc_ch0_axi_clk[0],
1739                 &pll2_pfd_400M, &pll3_120M, &pll3_pfd_540M, NULL, NULL);
1740
1741         reg |= (mux << MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_OFFSET);
1742
1743         __raw_writel(reg, MXC_CCM_CSCDR3);
1744
1745         return 0;
1746 }
1747
1748 static unsigned long _clk_ipu1_get_rate(struct clk *clk)
1749 {
1750         u32 reg, div;
1751
1752         reg = __raw_readl(MXC_CCM_CSCDR3);
1753         div = ((reg & MXC_CCM_CSCDR3_IPU1_HSP_PODF_MASK) >>
1754                         MXC_CCM_CSCDR3_IPU1_HSP_PODF_OFFSET) + 1;
1755
1756         return clk_get_rate(clk->parent) / div;
1757 }
1758
1759 static int _clk_ipu1_set_rate(struct clk *clk, unsigned long rate)
1760 {
1761         u32 reg, div;
1762         u32 parent_rate = clk_get_rate(clk->parent);
1763
1764         div = parent_rate / rate;
1765         if (div == 0)
1766                 div++;
1767         if (((parent_rate / div) != rate) || (div > 8))
1768                 return -EINVAL;
1769
1770         reg = __raw_readl(MXC_CCM_CSCDR3);
1771         reg &= ~MXC_CCM_CSCDR3_IPU1_HSP_PODF_MASK;
1772         reg |= (div - 1) << MXC_CCM_CSCDR3_IPU1_HSP_PODF_OFFSET;
1773         __raw_writel(reg, MXC_CCM_CSCDR3);
1774
1775         return 0;
1776 }
1777
1778 static unsigned long _clk_ipu_round_rate(struct clk *clk,
1779                                                 unsigned long rate)
1780 {
1781         u32 div;
1782         u32 parent_rate = clk_get_rate(clk->parent);
1783
1784         div = parent_rate / rate;
1785
1786         /* Make sure rate is not greater than the maximum value for the clock.
1787          * Also prevent a div of 0.
1788          */
1789         if (div == 0)
1790                 div++;
1791
1792         if (div > 8)
1793                 div = 8;
1794
1795         return parent_rate / div;
1796 }
1797
1798 static struct clk ipu1_clk = {
1799         __INIT_CLK_DEBUG(ipu1_clk)
1800         .parent = &mmdc_ch0_axi_clk[0],
1801         .secondary = &mmdc_ch0_axi_clk[0],
1802         .enable_reg = MXC_CCM_CCGR3,
1803         .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET,
1804         .enable = _clk_enable,
1805         .disable = _clk_disable,
1806         .set_parent = _clk_ipu1_set_parent,
1807         .round_rate = _clk_ipu_round_rate,
1808         .set_rate = _clk_ipu1_set_rate,
1809         .get_rate = _clk_ipu1_get_rate,
1810         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
1811 };
1812
1813 static int _clk_cko1_clk0_set_parent(struct clk *clk, struct clk *parent)
1814 {
1815         u32 sel, reg;
1816
1817         if (parent == &pll3_sw_clk)
1818                 sel = 0;
1819         else if (parent == &pll2_528_bus_main_clk)
1820                 sel = 1;
1821         else if (parent == &pll1_sys_main_clk)
1822                 sel = 2;
1823         else if (parent == &pll5_video_main_clk)
1824                 sel = 3;
1825         else if (parent == &axi_clk)
1826                 sel = 5;
1827         else if (parent == &enfc_clk)
1828                 sel = 6;
1829         else if (parent == &ipu1_di_clk_root)
1830                 sel = 7;
1831         else if (parent == &ipu1_di_clk_root)
1832                 sel = 8;
1833         else if (parent == &ipu2_di_clk_root)
1834                 sel = 9;
1835         else if (parent == &ipu2_di_clk_root)
1836                 sel = 10;
1837         else if (parent == &ahb_clk)
1838                 sel = 11;
1839         else if (parent == &ipg_clk)
1840                 sel = 12;
1841         else if (parent == &ipg_perclk)
1842                 sel = 13;
1843         else if (parent == &ckil_clk)
1844                 sel = 14;
1845         else if (parent == &pll4_audio_main_clk)
1846                 sel = 15;
1847         else
1848                 return -EINVAL;
1849
1850         reg = __raw_readl(MXC_CCM_CCOSR);
1851         reg &= ~MXC_CCM_CCOSR_CKOL_SEL_MASK;
1852         reg |= sel << MXC_CCM_CCOSR_CKOL_SEL_OFFSET;
1853         __raw_writel(reg, MXC_CCM_CCOSR);
1854         return 0;
1855 }
1856
1857 static unsigned long _clk_cko1_round_rate(struct clk *clk,
1858                                                 unsigned long rate)
1859 {
1860         u32 div;
1861         u32 parent_rate = clk_get_rate(clk->parent);
1862
1863         div = parent_rate / rate;
1864
1865         /* Make sure rate is not greater than the maximum value for the clock.
1866          * Also prevent a div of 0.
1867          */
1868         if (div == 0)
1869                 div++;
1870
1871         if (div > 8)
1872                 div = 8;
1873
1874         return parent_rate / div;
1875 }
1876
1877 static int _clk_cko1_set_rate(struct clk *clk, unsigned long rate)
1878 {
1879         u32 reg, div;
1880         u32 parent_rate = clk_get_rate(clk->parent);
1881
1882         div = parent_rate / rate;
1883         if (div == 0)
1884                 div++;
1885         if (((parent_rate / div) != rate) || (div > 8))
1886                 return -EINVAL;
1887
1888         reg = __raw_readl(MXC_CCM_CCOSR);
1889         reg &= ~MXC_CCM_CCOSR_CKOL_DIV_MASK;
1890         reg |= div << MXC_CCM_CCOSR_CKOL_DIV_OFFSET;
1891         __raw_writel(reg, MXC_CCM_CCOSR);
1892
1893         return 0;
1894 }
1895
1896 static unsigned long _clk_cko1_get_rate(struct clk *clk)
1897 {
1898         u32 reg, div;
1899
1900         reg = __raw_readl(MXC_CCM_CCOSR);
1901         div = ((reg & MXC_CCM_CCOSR_CKOL_DIV_MASK) >>
1902                         MXC_CCM_CCOSR_CKOL_DIV_OFFSET) + 1;
1903
1904         return clk_get_rate(clk->parent) / div;
1905 }
1906
1907 static int cko1_clk_enable(struct clk *clk)
1908 {
1909         u32 reg;
1910         reg = __raw_readl(clk->enable_reg);
1911         reg |= clk->enable_shift;
1912         __raw_writel(reg, clk->enable_reg);
1913
1914         return 0;
1915 }
1916
1917 static struct clk cko1_clk0 = {
1918         __INIT_CLK_DEBUG(cko1_clk0)
1919         .parent = &ipg_clk,
1920         .enable_reg = MXC_CCM_CCOSR,
1921         .enable_shift = MXC_CCM_CCOSR_CKOL_EN,
1922         .enable = cko1_clk_enable,
1923         .disable = _clk_disable,
1924         .set_parent = _clk_cko1_clk0_set_parent,
1925         .round_rate = _clk_cko1_round_rate,
1926         .set_rate = _clk_cko1_set_rate,
1927         .get_rate = _clk_cko1_get_rate,
1928 };
1929
1930 static int _clk_ipu2_set_parent(struct clk *clk, struct clk *parent)
1931 {
1932         int mux;
1933         u32 reg = __raw_readl(MXC_CCM_CSCDR3)
1934                 & ~MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_MASK;
1935
1936         mux = _get_mux6(parent, &mmdc_ch0_axi_clk[0],
1937                 &pll2_pfd_400M, &pll3_120M, &pll3_pfd_540M, NULL, NULL);
1938
1939         reg |= (mux << MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_OFFSET);
1940
1941         __raw_writel(reg, MXC_CCM_CSCDR3);
1942
1943         return 0;
1944 }
1945
1946 static unsigned long _clk_ipu2_get_rate(struct clk *clk)
1947 {
1948         u32 reg, div;
1949
1950         reg = __raw_readl(MXC_CCM_CSCDR3);
1951         div = ((reg & MXC_CCM_CSCDR3_IPU2_HSP_PODF_MASK) >>
1952                         MXC_CCM_CSCDR3_IPU2_HSP_PODF_OFFSET) + 1;
1953
1954         return clk_get_rate(clk->parent) / div;
1955 }
1956
1957 static int _clk_ipu2_set_rate(struct clk *clk, unsigned long rate)
1958 {
1959         u32 reg, div;
1960         u32 parent_rate = clk_get_rate(clk->parent);
1961
1962         div = parent_rate / rate;
1963         if (div == 0)
1964                 div++;
1965         if (((parent_rate / div) != rate) || (div > 8))
1966                 return -EINVAL;
1967
1968         reg = __raw_readl(MXC_CCM_CSCDR3);
1969         reg &= ~MXC_CCM_CSCDR3_IPU2_HSP_PODF_MASK;
1970         reg |= (div - 1) << MXC_CCM_CSCDR3_IPU2_HSP_PODF_OFFSET;
1971         __raw_writel(reg, MXC_CCM_CSCDR3);
1972
1973         return 0;
1974 }
1975
1976 static struct clk ipu2_clk = {
1977         __INIT_CLK_DEBUG(ipu2_clk)
1978         .parent = &mmdc_ch0_axi_clk[0],
1979         .secondary = &mmdc_ch0_axi_clk[0],
1980         .enable_reg = MXC_CCM_CCGR3,
1981         .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET,
1982         .enable = _clk_enable,
1983         .disable = _clk_disable,
1984         .set_parent = _clk_ipu2_set_parent,
1985         .round_rate = _clk_ipu_round_rate,
1986         .set_rate = _clk_ipu2_set_rate,
1987         .get_rate = _clk_ipu2_get_rate,
1988         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
1989 };
1990
1991 static struct clk usdhc_dep_clk = {
1992         .parent = &mmdc_ch0_axi_clk[0],
1993         .secondary = &mx6per1_clk,
1994         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
1995         };
1996
1997 static unsigned long _clk_usdhc_round_rate(struct clk *clk,
1998                                                 unsigned long rate)
1999 {
2000         u32 div;
2001         u32 parent_rate = clk_get_rate(clk->parent);
2002
2003         div = parent_rate / rate;
2004
2005         /* Make sure rate is not greater than the maximum value for the clock.
2006          * Also prevent a div of 0.
2007          */
2008         if (div == 0)
2009                 div++;
2010
2011         if (div > 8)
2012                 div = 8;
2013
2014         return parent_rate / div;
2015 }
2016
2017 static int _clk_usdhc1_set_parent(struct clk *clk, struct clk *parent)
2018 {
2019         u32 reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_USDHC1_CLK_SEL;
2020
2021         if (parent == &pll2_pfd_352M)
2022                 reg |= (MXC_CCM_CSCMR1_USDHC1_CLK_SEL);
2023
2024         __raw_writel(reg, MXC_CCM_CSCMR1);
2025
2026         return 0;
2027 }
2028
2029 static unsigned long _clk_usdhc1_get_rate(struct clk *clk)
2030 {
2031         u32 reg, div;
2032
2033         reg = __raw_readl(MXC_CCM_CSCDR1);
2034         div = ((reg & MXC_CCM_CSCDR1_USDHC1_PODF_MASK) >>
2035                         MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET) + 1;
2036
2037         return clk_get_rate(clk->parent) / div;
2038 }
2039
2040 static int _clk_usdhc1_set_rate(struct clk *clk, unsigned long rate)
2041 {
2042         u32 reg, div;
2043         u32 parent_rate = clk_get_rate(clk->parent);
2044
2045         div = parent_rate / rate;
2046         if (div == 0)
2047                 div++;
2048         if (((parent_rate / div) != rate) || (div > 8))
2049                 return -EINVAL;
2050
2051         reg = __raw_readl(MXC_CCM_CSCDR1);
2052         reg &= ~MXC_CCM_CSCDR1_USDHC1_PODF_MASK;
2053         reg |= (div - 1) << MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET;
2054         __raw_writel(reg, MXC_CCM_CSCDR1);
2055
2056         return 0;
2057 }
2058
2059 static struct clk usdhc1_clk = {
2060         __INIT_CLK_DEBUG(usdhc1_clk)
2061         .id = 0,
2062         .parent = &pll2_pfd_400M,
2063         .secondary = &usdhc_dep_clk,
2064         .enable_reg = MXC_CCM_CCGR6,
2065         .enable_shift = MXC_CCM_CCGRx_CG1_OFFSET,
2066         .enable = _clk_enable,
2067         .disable = _clk_disable,
2068         .set_parent = _clk_usdhc1_set_parent,
2069         .round_rate = _clk_usdhc_round_rate,
2070         .set_rate = _clk_usdhc1_set_rate,
2071         .get_rate = _clk_usdhc1_get_rate,
2072         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
2073 };
2074
2075 static int _clk_usdhc2_set_parent(struct clk *clk, struct clk *parent)
2076 {
2077         u32 reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_USDHC2_CLK_SEL;
2078
2079         if (parent == &pll2_pfd_352M)
2080                 reg |= (MXC_CCM_CSCMR1_USDHC2_CLK_SEL);
2081
2082         __raw_writel(reg, MXC_CCM_CSCMR1);
2083
2084         return 0;
2085 }
2086
2087 static unsigned long _clk_usdhc2_get_rate(struct clk *clk)
2088 {
2089         u32 reg, div;
2090
2091         reg = __raw_readl(MXC_CCM_CSCDR1);
2092         div = ((reg & MXC_CCM_CSCDR1_USDHC2_PODF_MASK) >>
2093                         MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET) + 1;
2094
2095         return clk_get_rate(clk->parent) / div;
2096 }
2097
2098 static int _clk_usdhc2_set_rate(struct clk *clk, unsigned long rate)
2099 {
2100         u32 reg, div;
2101         u32 parent_rate = clk_get_rate(clk->parent);
2102
2103         div = parent_rate / rate;
2104         if (div == 0)
2105                 div++;
2106         if (((parent_rate / div) != rate) || (div > 8))
2107                 return -EINVAL;
2108
2109         reg = __raw_readl(MXC_CCM_CSCDR1);
2110         reg &= ~MXC_CCM_CSCDR1_USDHC2_PODF_MASK;
2111         reg |= (div - 1) << MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET;
2112         __raw_writel(reg, MXC_CCM_CSCDR1);
2113
2114         return 0;
2115 }
2116
2117 static struct clk usdhc2_clk = {
2118         __INIT_CLK_DEBUG(usdhc2_clk)
2119         .id = 1,
2120         .parent = &pll2_pfd_400M,
2121         .secondary = &usdhc_dep_clk,
2122         .enable_reg = MXC_CCM_CCGR6,
2123         .enable_shift = MXC_CCM_CCGRx_CG2_OFFSET,
2124         .enable = _clk_enable,
2125         .disable = _clk_disable,
2126         .set_parent = _clk_usdhc2_set_parent,
2127         .round_rate = _clk_usdhc_round_rate,
2128         .set_rate = _clk_usdhc2_set_rate,
2129         .get_rate = _clk_usdhc2_get_rate,
2130         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
2131 };
2132
2133 static int _clk_usdhc3_set_parent(struct clk *clk, struct clk *parent)
2134 {
2135         u32 reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_USDHC3_CLK_SEL;
2136
2137         if (parent == &pll2_pfd_352M)
2138                 reg |= (MXC_CCM_CSCMR1_USDHC3_CLK_SEL);
2139
2140         __raw_writel(reg, MXC_CCM_CSCMR1);
2141
2142         return 0;
2143 }
2144
2145 static unsigned long _clk_usdhc3_get_rate(struct clk *clk)
2146 {
2147         u32 reg, div;
2148
2149         reg = __raw_readl(MXC_CCM_CSCDR1);
2150         div = ((reg & MXC_CCM_CSCDR1_USDHC3_PODF_MASK) >>
2151                         MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET) + 1;
2152
2153         return clk_get_rate(clk->parent) / div;
2154 }
2155
2156 static int _clk_usdhc3_set_rate(struct clk *clk, unsigned long rate)
2157 {
2158         u32 reg, div;
2159         u32 parent_rate = clk_get_rate(clk->parent);
2160
2161         div = parent_rate / rate;
2162         if (div == 0)
2163                 div++;
2164         if (((parent_rate / div) != rate) || (div > 8))
2165                 return -EINVAL;
2166
2167         reg = __raw_readl(MXC_CCM_CSCDR1);
2168         reg &= ~MXC_CCM_CSCDR1_USDHC3_PODF_MASK;
2169         reg |= (div - 1) << MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET;
2170         __raw_writel(reg, MXC_CCM_CSCDR1);
2171
2172         return 0;
2173 }
2174
2175
2176 static struct clk usdhc3_clk = {
2177         __INIT_CLK_DEBUG(usdhc3_clk)
2178         .id = 2,
2179         .parent = &pll2_pfd_400M,
2180         .secondary = &usdhc_dep_clk,
2181         .enable_reg = MXC_CCM_CCGR6,
2182         .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET,
2183         .enable = _clk_enable,
2184         .disable = _clk_disable,
2185         .set_parent = _clk_usdhc3_set_parent,
2186         .round_rate = _clk_usdhc_round_rate,
2187         .set_rate = _clk_usdhc3_set_rate,
2188         .get_rate = _clk_usdhc3_get_rate,
2189         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
2190 };
2191
2192 static int _clk_usdhc4_set_parent(struct clk *clk, struct clk *parent)
2193 {
2194         u32 reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_USDHC4_CLK_SEL;
2195
2196         if (parent == &pll2_pfd_352M)
2197                 reg |= (MXC_CCM_CSCMR1_USDHC4_CLK_SEL);
2198
2199         __raw_writel(reg, MXC_CCM_CSCMR1);
2200
2201         return 0;
2202 }
2203
2204 static unsigned long _clk_usdhc4_get_rate(struct clk *clk)
2205 {
2206         u32 reg, div;
2207
2208         reg = __raw_readl(MXC_CCM_CSCDR1);
2209         div = ((reg & MXC_CCM_CSCDR1_USDHC4_PODF_MASK) >>
2210                         MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET) + 1;
2211
2212         return clk_get_rate(clk->parent) / div;
2213 }
2214
2215 static int _clk_usdhc4_set_rate(struct clk *clk, unsigned long rate)
2216 {
2217         u32 reg, div;
2218         u32 parent_rate = clk_get_rate(clk->parent);
2219
2220         div = parent_rate / rate;
2221         if (div == 0)
2222                 div++;
2223         if (((parent_rate / div) != rate) || (div > 8))
2224                 return -EINVAL;
2225
2226         reg = __raw_readl(MXC_CCM_CSCDR1);
2227         reg &= ~MXC_CCM_CSCDR1_USDHC4_PODF_MASK;
2228         reg |= (div - 1) << MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET;
2229         __raw_writel(reg, MXC_CCM_CSCDR1);
2230
2231         return 0;
2232 }
2233
2234
2235 static struct clk usdhc4_clk = {
2236         __INIT_CLK_DEBUG(usdhc4_clk)
2237         .id = 3,
2238         .parent = &pll2_pfd_400M,
2239         .secondary = &usdhc_dep_clk,
2240         .enable_reg = MXC_CCM_CCGR6,
2241         .enable_shift = MXC_CCM_CCGRx_CG4_OFFSET,
2242         .enable = _clk_enable,
2243         .disable = _clk_disable,
2244         .set_parent = _clk_usdhc4_set_parent,
2245         .round_rate = _clk_usdhc_round_rate,
2246         .set_rate = _clk_usdhc4_set_rate,
2247         .get_rate = _clk_usdhc4_get_rate,
2248         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
2249 };
2250
2251 static unsigned long _clk_ssi_round_rate(struct clk *clk,
2252                                                 unsigned long rate)
2253 {
2254         u32 pre, post;
2255         u32 parent_rate = clk_get_rate(clk->parent);
2256         u32 div = parent_rate / rate;
2257
2258         if (parent_rate % rate)
2259                 div++;
2260
2261         __calc_pre_post_dividers(1 << 6, div, &pre, &post);
2262
2263         return parent_rate / (pre * post);
2264 }
2265
2266 static unsigned long _clk_ssi1_get_rate(struct clk *clk)
2267 {
2268         u32 reg, prediv, podf;
2269
2270         reg = __raw_readl(MXC_CCM_CS1CDR);
2271
2272         prediv = ((reg & MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK)
2273                 >> MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET) + 1;
2274         podf = ((reg & MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK)
2275                 >> MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET) + 1;
2276
2277         return clk_get_rate(clk->parent) / (prediv * podf);
2278 }
2279
2280 static int _clk_ssi1_set_rate(struct clk *clk, unsigned long rate)
2281 {
2282         u32 reg, div, pre, post;
2283         u32 parent_rate = clk_get_rate(clk->parent);
2284
2285         div = parent_rate / rate;
2286         if (div == 0)
2287                 div++;
2288         if (((parent_rate / div) != rate) || div > 512)
2289                 return -EINVAL;
2290
2291         __calc_pre_post_dividers(1 << 6, div, &pre, &post);
2292
2293         reg = __raw_readl(MXC_CCM_CS1CDR);
2294         reg &= ~(MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK |
2295                  MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK);
2296         reg |= (post - 1) << MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET;
2297         reg |= (pre - 1) << MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET;
2298
2299         __raw_writel(reg, MXC_CCM_CS1CDR);
2300
2301         return 0;
2302 }
2303
2304
2305 static int _clk_ssi1_set_parent(struct clk *clk, struct clk *parent)
2306 {
2307         u32 reg, mux;
2308
2309         reg = __raw_readl(MXC_CCM_CSCMR1)
2310                 & ~MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK;
2311
2312         mux = _get_mux6(parent, &pll3_pfd_508M, &pll3_pfd_454M,
2313                         &pll4_audio_main_clk, NULL, NULL, NULL);
2314         reg |= (mux << MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET);
2315
2316         __raw_writel(reg, MXC_CCM_CSCMR1);
2317
2318         return 0;
2319 }
2320
2321 static struct clk ssi1_clk = {
2322         __INIT_CLK_DEBUG(ssi1_clk)
2323         .parent = &pll3_pfd_508M,
2324         .enable_reg = MXC_CCM_CCGR5,
2325         .enable_shift = MXC_CCM_CCGRx_CG9_OFFSET,
2326         .enable = _clk_enable,
2327         .disable = _clk_disable,
2328         .set_parent = _clk_ssi1_set_parent,
2329         .set_rate = _clk_ssi1_set_rate,
2330         .round_rate = _clk_ssi_round_rate,
2331         .get_rate = _clk_ssi1_get_rate,
2332 #ifdef CONFIG_SND_MXC_SOC_IRAM
2333          .secondary = &ocram_clk,
2334 #else
2335          .secondary = &mmdc_ch0_axi_clk[0],
2336 #endif
2337 };
2338
2339 static unsigned long _clk_ssi2_get_rate(struct clk *clk)
2340 {
2341         u32 reg, prediv, podf;
2342
2343         reg = __raw_readl(MXC_CCM_CS2CDR);
2344
2345         prediv = ((reg & MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK)
2346                 >> MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET) + 1;
2347         podf = ((reg & MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK)
2348                 >> MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET) + 1;
2349
2350         return clk_get_rate(clk->parent) / (prediv * podf);
2351 }
2352
2353 static int _clk_ssi2_set_rate(struct clk *clk, unsigned long rate)
2354 {
2355         u32 reg, div, pre, post;
2356         u32 parent_rate = clk_get_rate(clk->parent);
2357
2358         div = parent_rate / rate;
2359         if (div == 0)
2360                 div++;
2361         if (((parent_rate / div) != rate) || div > 512)
2362                 return -EINVAL;
2363
2364         __calc_pre_post_dividers(1 << 6, div, &pre, &post);
2365
2366         reg = __raw_readl(MXC_CCM_CS2CDR);
2367         reg &= ~(MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK |
2368                  MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK);
2369         reg |= (post - 1) << MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET;
2370         reg |= (pre - 1) << MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET;
2371
2372         __raw_writel(reg, MXC_CCM_CS2CDR);
2373
2374         return 0;
2375 }
2376
2377
2378 static int _clk_ssi2_set_parent(struct clk *clk, struct clk *parent)
2379 {
2380         u32 reg, mux;
2381
2382         reg = __raw_readl(MXC_CCM_CSCMR1)
2383                 & ~MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK;
2384
2385         mux = _get_mux6(parent, &pll3_pfd_508M, &pll3_pfd_454M,
2386                         &pll4_audio_main_clk, NULL, NULL, NULL);
2387         reg |= (mux << MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET);
2388
2389         __raw_writel(reg, MXC_CCM_CSCMR1);
2390
2391         return 0;
2392 }
2393
2394 static struct clk ssi2_clk = {
2395         __INIT_CLK_DEBUG(ssi2_clk)
2396         .parent = &pll3_pfd_508M,
2397         .enable_reg = MXC_CCM_CCGR5,
2398         .enable_shift = MXC_CCM_CCGRx_CG10_OFFSET,
2399         .enable = _clk_enable,
2400         .disable = _clk_disable,
2401         .set_parent = _clk_ssi2_set_parent,
2402         .set_rate = _clk_ssi2_set_rate,
2403         .round_rate = _clk_ssi_round_rate,
2404         .get_rate = _clk_ssi2_get_rate,
2405 #ifdef CONFIG_SND_MXC_SOC_IRAM
2406          .secondary = &ocram_clk,
2407 #else
2408          .secondary = &mmdc_ch0_axi_clk[0],
2409 #endif
2410 };
2411
2412 static unsigned long _clk_ssi3_get_rate(struct clk *clk)
2413 {
2414         u32 reg, prediv, podf;
2415
2416         reg = __raw_readl(MXC_CCM_CS1CDR);
2417
2418         prediv = ((reg & MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK)
2419                 >> MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET) + 1;
2420         podf = ((reg & MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK)
2421                 >> MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET) + 1;
2422
2423         return clk_get_rate(clk->parent) / (prediv * podf);
2424 }
2425
2426 static int _clk_ssi3_set_rate(struct clk *clk, unsigned long rate)
2427 {
2428         u32 reg, div, pre, post;
2429         u32 parent_rate = clk_get_rate(clk->parent);
2430
2431         div = parent_rate / rate;
2432         if (div == 0)
2433                 div++;
2434         if (((parent_rate / div) != rate) || div > 512)
2435                 return -EINVAL;
2436
2437         __calc_pre_post_dividers(1 << 6, div, &pre, &post);
2438
2439         reg = __raw_readl(MXC_CCM_CS1CDR);
2440         reg &= ~(MXC_CCM_CS1CDR_SSI3_CLK_PODF_MASK|
2441                  MXC_CCM_CS1CDR_SSI3_CLK_PRED_MASK);
2442         reg |= (post - 1) << MXC_CCM_CS1CDR_SSI3_CLK_PODF_OFFSET;
2443         reg |= (pre - 1) << MXC_CCM_CS1CDR_SSI3_CLK_PRED_OFFSET;
2444
2445         __raw_writel(reg, MXC_CCM_CS1CDR);
2446
2447         return 0;
2448 }
2449
2450
2451 static int _clk_ssi3_set_parent(struct clk *clk, struct clk *parent)
2452 {
2453         u32 reg, mux;
2454
2455         reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_SSI3_CLK_SEL_MASK;
2456
2457         mux = _get_mux6(parent, &pll3_pfd_508M, &pll3_pfd_454M,
2458                                 &pll4_audio_main_clk, NULL, NULL, NULL);
2459         reg |= (mux << MXC_CCM_CSCMR1_SSI3_CLK_SEL_OFFSET);
2460
2461         __raw_writel(reg, MXC_CCM_CSCMR1);
2462
2463         return 0;
2464 }
2465
2466 static struct clk ssi3_clk = {
2467         __INIT_CLK_DEBUG(ssi3_clk)
2468         .parent = &pll3_pfd_508M,
2469         .enable_reg = MXC_CCM_CCGR5,
2470         .enable_shift = MXC_CCM_CCGRx_CG11_OFFSET,
2471         .enable = _clk_enable,
2472         .disable = _clk_disable,
2473         .set_parent = _clk_ssi3_set_parent,
2474         .set_rate = _clk_ssi3_set_rate,
2475         .round_rate = _clk_ssi_round_rate,
2476         .get_rate = _clk_ssi3_get_rate,
2477 #ifdef CONFIG_SND_MXC_SOC_IRAM
2478          .secondary = &ocram_clk,
2479 #else
2480          .secondary = &mmdc_ch0_axi_clk[0],
2481 #endif
2482 };
2483
2484 static unsigned long _clk_ldb_di_round_rate(struct clk *clk,
2485                                                 unsigned long rate)
2486 {
2487         u32 parent_rate = clk_get_rate(clk->parent);
2488
2489         if (rate * 7 <= parent_rate + parent_rate/20)
2490                 return parent_rate / 7;
2491         else
2492                 return 2 * parent_rate / 7;
2493 }
2494
2495 static unsigned long _clk_ldb_di0_get_rate(struct clk *clk)
2496 {
2497         u32 div;
2498
2499         div = __raw_readl(MXC_CCM_CSCMR2) &
2500                 MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
2501
2502         if (div)
2503                 return clk_get_rate(clk->parent) / 7;
2504
2505         return (2 * clk_get_rate(clk->parent)) / 7;
2506 }
2507
2508 static int _clk_ldb_di0_set_rate(struct clk *clk, unsigned long rate)
2509 {
2510         u32 reg, div = 0;
2511         u32 parent_rate = clk_get_rate(clk->parent);
2512
2513         if (rate * 7 <= parent_rate + parent_rate/20) {
2514                 div = 7;
2515                 rate = parent_rate / 7;
2516         } else
2517                 rate = 2 * parent_rate / 7;
2518
2519         reg = __raw_readl(MXC_CCM_CSCMR2);
2520         if (div == 7)
2521                 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
2522         else
2523                 reg &= ~MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
2524
2525         __raw_writel(reg, MXC_CCM_CSCMR2);
2526
2527         return 0;
2528 }
2529
2530 static int _clk_ldb_di0_set_parent(struct clk *clk, struct clk *parent)
2531 {
2532         u32 reg, mux;
2533
2534         reg = __raw_readl(MXC_CCM_CS2CDR)
2535                 & ~MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK;
2536
2537         mux = _get_mux6(parent, &pll5_video_main_clk,
2538                 &pll2_pfd_352M, &pll2_pfd_400M, &pll3_pfd_540M,
2539                 &pll3_usb_otg_main_clk, NULL);
2540         reg |= (mux << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET);
2541
2542         __raw_writel(reg, MXC_CCM_CS2CDR);
2543
2544         return 0;
2545 }
2546
2547 static struct clk ldb_di0_clk = {
2548          __INIT_CLK_DEBUG(ldb_di0_clk)
2549         .id = 0,
2550         .parent = &pll3_pfd_540M,
2551         .enable_reg = MXC_CCM_CCGR3,
2552         .enable_shift = MXC_CCM_CCGRx_CG6_OFFSET,
2553         .enable = _clk_enable,
2554         .disable = _clk_disable,
2555         .set_parent = _clk_ldb_di0_set_parent,
2556         .set_rate = _clk_ldb_di0_set_rate,
2557         .round_rate = _clk_ldb_di_round_rate,
2558         .get_rate = _clk_ldb_di0_get_rate,
2559         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
2560 };
2561
2562 static unsigned long _clk_ldb_di1_get_rate(struct clk *clk)
2563 {
2564         u32 div;
2565
2566         div = __raw_readl(MXC_CCM_CSCMR2) &
2567                 MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
2568
2569         if (div)
2570                 return clk_get_rate(clk->parent) / 7;
2571
2572         return (2 * clk_get_rate(clk->parent)) / 7;
2573 }
2574
2575 static int _clk_ldb_di1_set_rate(struct clk *clk, unsigned long rate)
2576 {
2577         u32 reg, div = 0;
2578         u32 parent_rate = clk_get_rate(clk->parent);
2579
2580         if (rate * 7 <= parent_rate + parent_rate/20) {
2581                 div = 7;
2582                 rate = parent_rate / 7;
2583         } else
2584                 rate = 2 * parent_rate / 7;
2585
2586         reg = __raw_readl(MXC_CCM_CSCMR2);
2587         if (div == 7)
2588                 reg |= MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
2589         else
2590                 reg &= ~MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
2591
2592         __raw_writel(reg, MXC_CCM_CSCMR2);
2593
2594         return 0;
2595 }
2596
2597 static int _clk_ldb_di1_set_parent(struct clk *clk, struct clk *parent)
2598 {
2599         u32 reg, mux;
2600
2601         reg = __raw_readl(MXC_CCM_CS2CDR)
2602                 & ~MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK;
2603
2604         mux = _get_mux6(parent, &pll5_video_main_clk,
2605                 &pll2_pfd_352M, &pll2_pfd_400M, &pll3_pfd_540M,
2606                 &pll3_usb_otg_main_clk, NULL);
2607         reg |= (mux << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
2608
2609         __raw_writel(reg, MXC_CCM_CS2CDR);
2610
2611         return 0;
2612 }
2613
2614 static struct clk ldb_di1_clk = {
2615          __INIT_CLK_DEBUG(ldb_di1_clk)
2616         .id = 0,
2617         .parent = &pll3_pfd_540M,
2618         .enable_reg = MXC_CCM_CCGR3,
2619         .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
2620         .enable = _clk_enable,
2621         .disable = _clk_disable,
2622         .set_parent = _clk_ldb_di1_set_parent,
2623         .set_rate = _clk_ldb_di1_set_rate,
2624         .round_rate = _clk_ldb_di_round_rate,
2625         .get_rate = _clk_ldb_di1_get_rate,
2626         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
2627 };
2628
2629
2630 static unsigned long _clk_ipu_di_round_rate(struct clk *clk,
2631                                                 unsigned long rate)
2632 {
2633         u32 div;
2634         u32 parent_rate = clk_get_rate(clk->parent);
2635
2636         if ((clk->parent == &ldb_di0_clk) ||
2637                 (clk->parent == &ldb_di1_clk))
2638                 return parent_rate;
2639
2640         div = parent_rate / rate;
2641
2642         /* Make sure rate is not greater than the maximum value for the clock.
2643          * Also prevent a div of 0.
2644          */
2645         if (div == 0)
2646                 div++;
2647
2648         if (div > 8)
2649                 div = 8;
2650
2651         return parent_rate / div;
2652 }
2653
2654 static unsigned long _clk_ipu1_di0_get_rate(struct clk *clk)
2655 {
2656         u32 reg, div;
2657
2658         if ((clk->parent == &ldb_di0_clk) ||
2659                 (clk->parent == &ldb_di1_clk))
2660                 return clk_get_rate(clk->parent);
2661
2662         reg = __raw_readl(MXC_CCM_CHSCCDR);
2663
2664         div = ((reg & MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK) >>
2665                          MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET) + 1;
2666
2667         return clk_get_rate(clk->parent) / div;
2668 }
2669
2670 static int _clk_ipu1_di0_set_rate(struct clk *clk, unsigned long rate)
2671 {
2672         u32 reg, div;
2673         u32 parent_rate = clk_get_rate(clk->parent);
2674
2675         if ((clk->parent == &ldb_di0_clk) ||
2676                 (clk->parent == &ldb_di1_clk)) {
2677                 if (parent_rate == rate)
2678                         return 0;
2679                 else
2680                         return -EINVAL;
2681         }
2682
2683         div = parent_rate / rate;
2684         if (div == 0)
2685                 div++;
2686         if (((parent_rate / div) != rate) || (div > 8))
2687                 return -EINVAL;
2688
2689         reg = __raw_readl(MXC_CCM_CHSCCDR);
2690         reg &= ~MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK;
2691         reg |= (div - 1) << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET;
2692         __raw_writel(reg, MXC_CCM_CHSCCDR);
2693
2694         return 0;
2695 }
2696
2697
2698 static int _clk_ipu1_di0_set_parent(struct clk *clk, struct clk *parent)
2699 {
2700         u32 reg, mux;
2701
2702         if (parent == &ldb_di0_clk)
2703                 mux = 0x3;
2704         else if (parent == &ldb_di1_clk)
2705                 mux = 0x4;
2706         else {
2707                 reg = __raw_readl(MXC_CCM_CHSCCDR)
2708                         & ~MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK;
2709
2710                 mux = _get_mux6(parent, &mmdc_ch0_axi_clk[0],
2711                                 &pll3_usb_otg_main_clk, &pll5_video_main_clk,
2712                                 &pll2_pfd_352M, &pll2_pfd_400M, &pll3_pfd_540M);
2713                 reg |= (mux << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
2714
2715                 __raw_writel(reg, MXC_CCM_CHSCCDR);
2716
2717                 /* Derive clock from divided pre-muxed ipu1_di0 clock.*/
2718                 mux = 0;
2719         }
2720
2721         reg = __raw_readl(MXC_CCM_CHSCCDR)
2722                 & ~MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK;
2723         __raw_writel(reg | (mux << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET),
2724                 MXC_CCM_CHSCCDR);
2725
2726         return 0;
2727 }
2728
2729 static unsigned long _clk_ipu1_di1_get_rate(struct clk *clk)
2730 {
2731         u32 reg, div;
2732
2733         if ((clk->parent == &ldb_di0_clk) ||
2734                 (clk->parent == &ldb_di1_clk))
2735                 return clk_get_rate(clk->parent);
2736
2737         reg = __raw_readl(MXC_CCM_CHSCCDR);
2738
2739         div = ((reg & MXC_CCM_CHSCCDR_IPU1_DI1_PODF_MASK)
2740                         >> MXC_CCM_CHSCCDR_IPU1_DI1_PODF_OFFSET) + 1;
2741
2742         return clk_get_rate(clk->parent) / div;
2743 }
2744
2745 static int _clk_ipu1_di1_set_rate(struct clk *clk, unsigned long rate)
2746 {
2747         u32 reg, div;
2748         u32 parent_rate = clk_get_rate(clk->parent);
2749
2750         if ((clk->parent == &ldb_di0_clk) ||
2751                 (clk->parent == &ldb_di1_clk)) {
2752                 if (parent_rate == rate)
2753                         return 0;
2754                 else
2755                         return -EINVAL;
2756         }
2757
2758         div = parent_rate / rate;
2759         if (div == 0)
2760                 div++;
2761         if (((parent_rate / div) != rate) || (div > 8))
2762                 return -EINVAL;
2763
2764         reg = __raw_readl(MXC_CCM_CHSCCDR);
2765         reg &= ~MXC_CCM_CHSCCDR_IPU1_DI1_PODF_MASK;
2766         reg |= (div - 1) << MXC_CCM_CHSCCDR_IPU1_DI1_PODF_OFFSET;
2767         __raw_writel(reg, MXC_CCM_CHSCCDR);
2768
2769         return 0;
2770 }
2771
2772
2773 static int _clk_ipu1_di1_set_parent(struct clk *clk, struct clk *parent)
2774 {
2775         u32 reg, mux;
2776
2777         if (parent == &ldb_di0_clk)
2778                 mux = 0x3;
2779         else if (parent == &ldb_di1_clk)
2780                 mux = 0x4;
2781         else {
2782                 reg = __raw_readl(MXC_CCM_CHSCCDR)
2783                         & ~MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_MASK;
2784
2785                 mux = _get_mux6(parent, &mmdc_ch0_axi_clk[0],
2786                                 &pll3_usb_otg_main_clk, &pll5_video_main_clk,
2787                                 &pll2_pfd_352M, &pll2_pfd_400M, &pll3_pfd_540M);
2788                 reg |= (mux << MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_OFFSET);
2789
2790                 __raw_writel(reg, MXC_CCM_CHSCCDR);
2791
2792                 /* Derive clock from divided pre-muxed ipu1_di0 clock.*/
2793                 mux = 0;
2794         }
2795         reg = __raw_readl(MXC_CCM_CHSCCDR)
2796                 & ~MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_MASK;
2797         __raw_writel(reg | (mux << MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET),
2798                 MXC_CCM_CHSCCDR);
2799
2800         return 0;
2801 }
2802
2803 static struct clk ipu1_di_clk[] = {
2804         {
2805          __INIT_CLK_DEBUG(ipu1_di_clk_0)
2806         .id = 0,
2807         .parent = &pll5_video_main_clk,
2808         .enable_reg = MXC_CCM_CCGR3,
2809         .enable_shift = MXC_CCM_CCGRx_CG1_OFFSET,
2810         .enable = _clk_enable,
2811         .disable = _clk_disable,
2812         .set_parent = _clk_ipu1_di0_set_parent,
2813         .set_rate = _clk_ipu1_di0_set_rate,
2814         .round_rate = _clk_ipu_di_round_rate,
2815         .get_rate = _clk_ipu1_di0_get_rate,
2816         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
2817         },
2818         {
2819          __INIT_CLK_DEBUG(ipu1_di_clk_1)
2820         .id = 1,
2821         .parent = &pll5_video_main_clk,
2822         .enable_reg = MXC_CCM_CCGR3,
2823         .enable_shift = MXC_CCM_CCGRx_CG2_OFFSET,
2824         .enable = _clk_enable,
2825         .disable = _clk_disable,
2826         .set_parent = _clk_ipu1_di1_set_parent,
2827         .set_rate = _clk_ipu1_di1_set_rate,
2828         .round_rate = _clk_ipu_di_round_rate,
2829         .get_rate = _clk_ipu1_di1_get_rate,
2830         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
2831         },
2832 };
2833
2834 static unsigned long _clk_ipu2_di0_get_rate(struct clk *clk)
2835 {
2836         u32 reg, div;
2837
2838         if ((clk->parent == &ldb_di0_clk) ||
2839                 (clk->parent == &ldb_di1_clk))
2840                 return clk_get_rate(clk->parent);
2841
2842         reg = __raw_readl(MXC_CCM_CSCDR2);
2843
2844         div = ((reg & MXC_CCM_CSCDR2_IPU2_DI0_PODF_MASK) >>
2845                         MXC_CCM_CSCDR2_IPU2_DI0_PODF_OFFSET) + 1;
2846
2847         return clk_get_rate(clk->parent) / div;
2848 }
2849
2850 static int _clk_ipu2_di0_set_rate(struct clk *clk, unsigned long rate)
2851 {
2852         u32 reg, div;
2853         u32 parent_rate = clk_get_rate(clk->parent);
2854
2855         if ((clk->parent == &ldb_di0_clk) ||
2856                 (clk->parent == &ldb_di1_clk)) {
2857                 if (parent_rate == rate)
2858                         return 0;
2859                 else
2860                         return -EINVAL;
2861         }
2862
2863         div = parent_rate / rate;
2864         if (div == 0)
2865                 div++;
2866         if (((parent_rate / div) != rate) || (div > 8))
2867                 return -EINVAL;
2868
2869         reg = __raw_readl(MXC_CCM_CSCDR2);
2870         reg &= ~MXC_CCM_CSCDR2_IPU2_DI0_PODF_MASK;
2871         reg |= (div - 1) << MXC_CCM_CSCDR2_IPU2_DI0_PODF_OFFSET;
2872         __raw_writel(reg, MXC_CCM_CSCDR2);
2873
2874         return 0;
2875 }
2876
2877 static int _clk_ipu2_di0_set_parent(struct clk *clk, struct clk *parent)
2878 {
2879         u32 reg, mux;
2880
2881         if (parent == &ldb_di0_clk)
2882                 mux = 0x3;
2883         else if (parent == &ldb_di1_clk)
2884                 mux = 0x4;
2885         else {
2886                 reg = __raw_readl(MXC_CCM_CSCDR2)
2887                         & ~MXC_CCM_CSCDR2_IPU2_DI0_PRE_CLK_SEL_MASK;
2888
2889                 mux = _get_mux6(parent, &mmdc_ch0_axi_clk[0],
2890                                 &pll3_usb_otg_main_clk, &pll5_video_main_clk,
2891                                 &pll2_pfd_352M, &pll2_pfd_400M, &pll3_pfd_540M);
2892                 reg |= (mux << MXC_CCM_CSCDR2_IPU2_DI0_PRE_CLK_SEL_OFFSET);
2893
2894                 __raw_writel(reg, MXC_CCM_CSCDR2);
2895
2896                 /* Derive clock from divided pre-muxed ipu2_di0 clock.*/
2897                 mux = 0;
2898         }
2899         reg = __raw_readl(MXC_CCM_CSCDR2)
2900                 & ~MXC_CCM_CSCDR2_IPU2_DI0_CLK_SEL_MASK;
2901         __raw_writel(reg | (mux << MXC_CCM_CSCDR2_IPU2_DI0_CLK_SEL_OFFSET),
2902                 MXC_CCM_CSCDR2);
2903
2904         return 0;
2905 }
2906
2907 static unsigned long _clk_ipu2_di1_get_rate(struct clk *clk)
2908 {
2909         u32 reg, div;
2910
2911         if ((clk->parent == &ldb_di0_clk) ||
2912                 (clk->parent == &ldb_di1_clk))
2913                 return clk_get_rate(clk->parent);
2914
2915         reg = __raw_readl(MXC_CCM_CSCDR2);
2916
2917         div = ((reg & MXC_CCM_CSCDR2_IPU2_DI1_PODF_MASK)
2918                 >> MXC_CCM_CSCDR2_IPU2_DI1_PODF_OFFSET) + 1;
2919
2920         return clk_get_rate(clk->parent) / div;
2921 }
2922
2923 static int _clk_ipu2_di1_set_rate(struct clk *clk, unsigned long rate)
2924 {
2925         u32 reg, div;
2926         u32 parent_rate = clk_get_rate(clk->parent);
2927
2928         if ((clk->parent == &ldb_di0_clk) ||
2929                 (clk->parent == &ldb_di1_clk)) {
2930                 if (parent_rate == rate)
2931                         return 0;
2932                 else
2933                         return -EINVAL;
2934         }
2935
2936         div = parent_rate / rate;
2937         if (div == 0)
2938                 div++;
2939         if (((parent_rate / div) != rate) || (div > 8))
2940                 return -EINVAL;
2941
2942         reg = __raw_readl(MXC_CCM_CSCDR2);
2943         reg &= ~MXC_CCM_CSCDR2_IPU2_DI1_PODF_MASK;
2944         reg |= (div - 1) << MXC_CCM_CSCDR2_IPU2_DI1_PODF_OFFSET;
2945         __raw_writel(reg, MXC_CCM_CSCDR2);
2946
2947         return 0;
2948 }
2949
2950 static int _clk_ipu2_di1_set_parent(struct clk *clk, struct clk *parent)
2951 {
2952         u32 reg, mux;
2953
2954         if (parent == &ldb_di0_clk)
2955                 mux = 0x3;
2956         else if (parent == &ldb_di1_clk)
2957                 mux = 0x4;
2958         else {
2959                 reg = __raw_readl(MXC_CCM_CSCDR2)
2960                         & ~MXC_CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_MASK;
2961
2962                 mux = _get_mux6(parent, &mmdc_ch0_axi_clk[0],
2963                                 &pll3_usb_otg_main_clk, &pll5_video_main_clk,
2964                                 &pll2_pfd_352M, &pll2_pfd_400M, &pll3_pfd_540M);
2965                 reg |= (mux << MXC_CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_OFFSET);
2966
2967                 __raw_writel(reg, MXC_CCM_CSCDR2);
2968
2969                 /* Derive clock from divided pre-muxed ipu1_di0 clock.*/
2970                 mux = 0;
2971         }
2972         reg = __raw_readl(MXC_CCM_CSCDR2)
2973                 & ~MXC_CCM_CSCDR2_IPU2_DI1_CLK_SEL_MASK;
2974         __raw_writel(reg | (mux << MXC_CCM_CSCDR2_IPU2_DI1_CLK_SEL_OFFSET),
2975                 MXC_CCM_CSCDR2);
2976
2977         return 0;
2978 }
2979
2980 static struct clk ipu2_di_clk[] = {
2981         {
2982          __INIT_CLK_DEBUG(ipu2_di_clk_0)
2983         .id = 0,
2984         .parent = &pll5_video_main_clk,
2985         .enable_reg = MXC_CCM_CCGR3,
2986         .enable_shift = MXC_CCM_CCGRx_CG4_OFFSET,
2987         .enable = _clk_enable,
2988         .disable = _clk_disable,
2989         .set_parent = _clk_ipu2_di0_set_parent,
2990         .set_rate = _clk_ipu2_di0_set_rate,
2991         .round_rate = _clk_ipu_di_round_rate,
2992         .get_rate = _clk_ipu2_di0_get_rate,
2993         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
2994         },
2995         {
2996          __INIT_CLK_DEBUG(ipu2_di_clk_1)
2997         .id = 1,
2998         .parent = &pll5_video_main_clk,
2999         .enable_reg = MXC_CCM_CCGR3,
3000         .enable_shift = MXC_CCM_CCGRx_CG5_OFFSET,
3001         .enable = _clk_enable,
3002         .disable = _clk_disable,
3003         .set_parent = _clk_ipu2_di1_set_parent,
3004         .set_rate = _clk_ipu2_di1_set_rate,
3005         .round_rate = _clk_ipu_di_round_rate,
3006         .get_rate = _clk_ipu2_di1_get_rate,
3007         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
3008         },
3009 };
3010
3011 static struct clk can2_clk[] = {
3012         {
3013          __INIT_CLK_DEBUG(can2_module_clk)
3014         .id = 0,
3015         .parent = &pll3_60M,
3016         .enable_reg = MXC_CCM_CCGR0,
3017         .enable_shift = MXC_CCM_CCGRx_CG9_OFFSET,
3018         .enable = _clk_enable,
3019         .disable = _clk_disable,
3020         .secondary = &can2_clk[1],
3021         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
3022         },
3023         {
3024          __INIT_CLK_DEBUG(can2_serial_clk)
3025         .id = 1,
3026         .parent = &pll3_60M,
3027         .enable_reg = MXC_CCM_CCGR0,
3028         .enable_shift = MXC_CCM_CCGRx_CG10_OFFSET,
3029         .enable = _clk_enable,
3030         .disable = _clk_disable,
3031         },
3032 };
3033
3034
3035 static struct clk can1_clk[] = {
3036         {
3037          __INIT_CLK_DEBUG(can1_module_clk)
3038         .id = 0,
3039         .parent = &pll3_60M,
3040         .enable_reg = MXC_CCM_CCGR0,
3041         .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
3042         .enable = _clk_enable,
3043         .disable = _clk_disable,
3044         .secondary = &can1_clk[1],
3045         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
3046         },
3047         {
3048          __INIT_CLK_DEBUG(can1_serial_clk)
3049         .id = 1,
3050         .parent = &pll3_60M,
3051         .enable_reg = MXC_CCM_CCGR0,
3052         .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET,
3053         .enable = _clk_enable,
3054         .disable = _clk_disable,
3055         },
3056 };
3057
3058 static unsigned long _clk_spdif_round_rate(struct clk *clk,
3059                                                 unsigned long rate)
3060 {
3061         u32 pre, post;
3062         u32 parent_rate = clk_get_rate(clk->parent);
3063         u32 div = parent_rate / rate;
3064
3065         if (parent_rate % rate)
3066                 div++;
3067
3068         __calc_pre_post_dividers(1 << 3, div, &pre, &post);
3069
3070         return parent_rate / (pre * post);
3071 }
3072
3073 static int _clk_spdif0_set_parent(struct clk *clk, struct clk *parent)
3074 {
3075         u32 reg, mux;
3076
3077         reg = __raw_readl(MXC_CCM_CDCDR)
3078                 & ~MXC_CCM_CDCDR_SPDIF0_CLK_SEL_MASK;
3079
3080         mux = _get_mux6(parent, &pll4_audio_main_clk,
3081                 &pll3_pfd_508M, &pll3_pfd_454M,
3082                 &pll3_sw_clk, NULL, NULL);
3083         reg |= mux << MXC_CCM_CDCDR_SPDIF0_CLK_SEL_OFFSET;
3084
3085         __raw_writel(reg, MXC_CCM_CDCDR);
3086
3087         return 0;
3088 }
3089
3090 static unsigned long _clk_spdif0_get_rate(struct clk *clk)
3091 {
3092         u32 reg, pred, podf;
3093
3094         reg = __raw_readl(MXC_CCM_CDCDR);
3095
3096         pred = ((reg & MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK)
3097                 >> MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET) + 1;
3098         podf = ((reg & MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK)
3099                 >> MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET) + 1;
3100
3101         return clk_get_rate(clk->parent) / (pred * podf);
3102 }
3103
3104 static int _clk_spdif0_set_rate(struct clk *clk, unsigned long rate)
3105 {
3106         u32 reg, div, pre, post;
3107         u32 parent_rate = clk_get_rate(clk->parent);
3108
3109         div = parent_rate / rate;
3110         if (div == 0)
3111                 div++;
3112         if (((parent_rate / div) != rate) || div > 64)
3113                 return -EINVAL;
3114
3115         __calc_pre_post_dividers(1 << 3, div, &pre, &post);
3116
3117         reg = __raw_readl(MXC_CCM_CDCDR);
3118         reg &= ~(MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK|
3119                  MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK);
3120         reg |= (post - 1) << MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET;
3121         reg |= (pre - 1) << MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET;
3122
3123         __raw_writel(reg, MXC_CCM_CDCDR);
3124
3125         return 0;
3126 }
3127
3128 static struct clk spdif0_clk[] = {
3129         {
3130         __INIT_CLK_DEBUG(spdif0_clk_0)
3131         .id = 0,
3132         .parent = &pll3_sw_clk,
3133          .enable = _clk_enable,
3134          .enable_reg = MXC_CCM_CCGR5,
3135          .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
3136          .disable = _clk_disable,
3137          .secondary = &spdif0_clk[1],
3138          .set_rate = _clk_spdif0_set_rate,
3139          .get_rate = _clk_spdif0_get_rate,
3140          .set_parent = _clk_spdif0_set_parent,
3141          .round_rate = _clk_spdif_round_rate,
3142         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
3143         },
3144         {
3145         __INIT_CLK_DEBUG(spdif0_clk_1)
3146          .id = 1,
3147          .parent = &ipg_clk,
3148          .secondary = &spba_clk,
3149          },
3150 };
3151
3152 static unsigned long _clk_esai_round_rate(struct clk *clk,
3153                                                 unsigned long rate)
3154 {
3155         u32 pre, post;
3156         u32 parent_rate = clk_get_rate(clk->parent);
3157         u32 div = parent_rate / rate;
3158
3159         if (parent_rate % rate)
3160                 div++;
3161
3162         __calc_pre_post_dividers(1 << 3, div, &pre, &post);
3163
3164         return parent_rate / (pre * post);
3165 }
3166
3167 static int _clk_esai_set_parent(struct clk *clk, struct clk *parent)
3168 {
3169         u32 reg, mux;
3170
3171         reg = __raw_readl(MXC_CCM_CSCMR2) & ~MXC_CCM_CSCMR2_ESAI_CLK_SEL_MASK;
3172
3173         mux = _get_mux6(parent, &pll4_audio_main_clk, &pll3_pfd_508M,
3174                         &pll3_pfd_454M, &pll3_sw_clk, NULL, NULL);
3175         reg |= mux << MXC_CCM_CSCMR2_ESAI_CLK_SEL_OFFSET;
3176
3177         __raw_writel(reg, MXC_CCM_CSCMR2);
3178
3179         return 0;
3180 }
3181
3182 static unsigned long _clk_esai_get_rate(struct clk *clk)
3183 {
3184         u32 reg, pred, podf;
3185
3186         reg = __raw_readl(MXC_CCM_CS1CDR);
3187
3188         pred = ((reg & MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK)
3189                 >> MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET) + 1;
3190         podf = ((reg & MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK)
3191                 >> MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET) + 1;
3192
3193         return clk_get_rate(clk->parent) / (pred * podf);
3194 }
3195
3196 static int _clk_esai_set_rate(struct clk *clk, unsigned long rate)
3197 {
3198         u32 reg, div, pre, post;
3199         u32 parent_rate = clk_get_rate(clk->parent);
3200
3201         div = parent_rate / rate;
3202         if (div == 0)
3203                 div++;
3204         if (((parent_rate / div) != rate) || div > 64)
3205                 return -EINVAL;
3206
3207         __calc_pre_post_dividers(1 << 3, div, &pre, &post);
3208
3209         reg = __raw_readl(MXC_CCM_CS1CDR);
3210         reg &= ~(MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK|
3211                  MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK);
3212         reg |= (post - 1) << MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET;
3213         reg |= (pre - 1) << MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET;
3214
3215         __raw_writel(reg, MXC_CCM_CS1CDR);
3216
3217         return 0;
3218 }
3219
3220 static struct clk esai_clk = {
3221         __INIT_CLK_DEBUG(esai_clk)
3222          .id = 0,
3223          .parent = &pll3_sw_clk,
3224          .secondary = &spba_clk,
3225          .enable_reg = MXC_CCM_CCGR1,
3226          .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET,
3227          .enable = _clk_enable,
3228          .disable = _clk_disable,
3229          .set_rate = _clk_esai_set_rate,
3230          .get_rate = _clk_esai_get_rate,
3231          .set_parent = _clk_esai_set_parent,
3232          .round_rate = _clk_esai_round_rate,
3233 };
3234
3235 static int _clk_enet_enable(struct clk *clk)
3236 {
3237         unsigned int reg;
3238
3239         /* Enable ENET ref clock */
3240         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
3241         reg &= ~ANADIG_PLL_BYPASS;
3242         reg &= ~ANADIG_PLL_ENABLE;
3243         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
3244
3245         _clk_enable(clk);
3246         return 0;
3247 }
3248
3249 static void _clk_enet_disable(struct clk *clk)
3250 {
3251         unsigned int reg;
3252
3253         _clk_disable(clk);
3254
3255         /* Enable ENET ref clock */
3256         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
3257         reg |= ANADIG_PLL_BYPASS;
3258         reg |= ANADIG_PLL_ENABLE;
3259         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
3260 }
3261
3262 static int _clk_enet_set_rate(struct clk *clk, unsigned long rate)
3263 {
3264         unsigned int reg, div = 1;
3265
3266         switch (rate) {
3267         case 25000000:
3268                 div = 0;
3269                 break;
3270         case 50000000:
3271                 div = 1;
3272                 break;
3273         case 100000000:
3274                 div = 2;
3275                 break;
3276         case 125000000:
3277                 div = 3;
3278                 break;
3279         default:
3280                 return -EINVAL;
3281         }
3282         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
3283         reg &= ~ANADIG_PLL_ENET_DIV_SELECT_MASK;
3284         reg |= (div << ANADIG_PLL_ENET_DIV_SELECT_OFFSET);
3285         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
3286
3287         return 0;
3288 }
3289
3290 static unsigned long _clk_enet_get_rate(struct clk *clk)
3291 {
3292         unsigned int div;
3293
3294         div = (__raw_readl(PLL8_ENET_BASE_ADDR))
3295                 & ANADIG_PLL_ENET_DIV_SELECT_MASK;
3296
3297         return 500000000 / (div + 1);
3298 }
3299
3300 static struct clk enet_clk[] = {
3301         {
3302         __INIT_CLK_DEBUG(enet_clk)
3303          .id = 0,
3304          .parent = &pll8_enet_main_clk,
3305          .enable_reg = MXC_CCM_CCGR1,
3306          .enable_shift = MXC_CCM_CCGRx_CG5_OFFSET,
3307          .enable = _clk_enet_enable,
3308          .disable = _clk_enet_disable,
3309          .set_rate = _clk_enet_set_rate,
3310          .get_rate = _clk_enet_get_rate,
3311         .secondary = &enet_clk[1],
3312         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
3313         },
3314         {
3315         .parent = &mmdc_ch0_axi_clk[0],
3316         .secondary = &mx6per1_clk,
3317         },
3318 };
3319
3320 static struct clk ecspi_clk[] = {
3321         {
3322         __INIT_CLK_DEBUG(ecspi0_clk)
3323         .id = 0,
3324         .parent = &pll3_60M,
3325         .secondary = &spba_clk,
3326         .enable_reg = MXC_CCM_CCGR1,
3327         .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET,
3328         .enable = _clk_enable,
3329         .disable = _clk_disable,
3330         },
3331         {
3332         __INIT_CLK_DEBUG(ecspi1_clk)
3333         .id = 1,
3334         .parent = &pll3_60M,
3335         .secondary = &spba_clk,
3336         .enable_reg = MXC_CCM_CCGR1,
3337         .enable_shift = MXC_CCM_CCGRx_CG1_OFFSET,
3338         .enable = _clk_enable,
3339         .disable = _clk_disable,
3340         },
3341         {
3342         __INIT_CLK_DEBUG(ecspi2_clk)
3343         .id = 2,
3344         .parent = &pll3_60M,
3345         .secondary = &spba_clk,
3346         .enable_reg = MXC_CCM_CCGR1,
3347         .enable_shift = MXC_CCM_CCGRx_CG2_OFFSET,
3348         .enable = _clk_enable,
3349         .disable = _clk_disable,
3350         },
3351         {
3352         __INIT_CLK_DEBUG(ecspi3_clk)
3353         .id = 3,
3354         .parent = &pll3_60M,
3355         .secondary = &spba_clk,
3356         .enable_reg = MXC_CCM_CCGR1,
3357         .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET,
3358         .enable = _clk_enable,
3359         .disable = _clk_disable,
3360         },
3361         {
3362         __INIT_CLK_DEBUG(ecspi4_clk)
3363         .id = 4,
3364         .parent = &pll3_60M,
3365         .secondary = &spba_clk,
3366         .enable_reg = MXC_CCM_CCGR1,
3367         .enable_shift = MXC_CCM_CCGRx_CG4_OFFSET,
3368         .enable = _clk_enable,
3369         .disable = _clk_disable,
3370         },
3371 };
3372
3373 static unsigned long _clk_emi_slow_round_rate(struct clk *clk,
3374                                                 unsigned long rate)
3375 {
3376         u32 div;
3377         u32 parent_rate = clk_get_rate(clk->parent);
3378
3379         div = parent_rate / rate;
3380
3381         /* Make sure rate is not greater than the maximum value for the clock.
3382          * Also prevent a div of 0.
3383          */
3384         if (div == 0)
3385                 div++;
3386
3387         if (div > 8)
3388                 div = 8;
3389
3390         return parent_rate / div;
3391 }
3392
3393 static int _clk_emi_slow_set_parent(struct clk *clk, struct clk *parent)
3394 {
3395         int mux;
3396         u32 reg = __raw_readl(MXC_CCM_CSCMR1)
3397                 & ~MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK;
3398
3399         mux = _get_mux6(parent, &axi_clk, &pll3_usb_otg_main_clk,
3400                                 &pll2_pfd_400M, &pll2_pfd_352M, NULL, NULL);
3401         reg |= (mux << MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET);
3402         __raw_writel(reg, MXC_CCM_CSCMR1);
3403
3404         return 0;
3405 }
3406
3407 static unsigned long _clk_emi_slow_get_rate(struct clk *clk)
3408 {
3409         u32 reg, div;
3410
3411         reg = __raw_readl(MXC_CCM_CSCMR1);
3412         div = ((reg & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK) >>
3413                         MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET) + 1;
3414
3415         return clk_get_rate(clk->parent) / div;
3416 }
3417
3418 static int _clk_emi_slow_set_rate(struct clk *clk, unsigned long rate)
3419 {
3420         u32 reg, div;
3421         u32 parent_rate = clk_get_rate(clk->parent);
3422
3423         div = parent_rate / rate;
3424         if (div == 0)
3425                 div++;
3426         if (((parent_rate / div) != rate) || (div > 8))
3427                 return -EINVAL;
3428
3429         reg = __raw_readl(MXC_CCM_CSCMR1);
3430         reg &= ~MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK;
3431         reg |= (div - 1) << MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET;
3432         __raw_writel(reg, MXC_CCM_CSCMR1);
3433
3434         return 0;
3435 }
3436
3437 static struct clk emi_slow_clk = {
3438         __INIT_CLK_DEBUG(emi_slow_clk)
3439          .id = 0,
3440          .parent = &axi_clk,
3441          .enable_reg = MXC_CCM_CCGR6,
3442          .enable_shift = MXC_CCM_CCGRx_CG5_OFFSET,
3443          .enable = _clk_enable,
3444          .disable = _clk_disable,
3445          .set_rate = _clk_emi_slow_set_rate,
3446          .get_rate = _clk_emi_slow_get_rate,
3447          .round_rate = _clk_emi_slow_round_rate,
3448          .set_parent = _clk_emi_slow_set_parent,
3449 };
3450
3451 static unsigned long _clk_emi_round_rate(struct clk *clk,
3452                                                 unsigned long rate)
3453 {
3454         u32 div;
3455         u32 parent_rate = clk_get_rate(clk->parent);
3456
3457         div = parent_rate / rate;
3458
3459         /* Make sure rate is not greater than the maximum value for the clock.
3460          * Also prevent a div of 0.
3461          */
3462         if (div == 0)
3463                 div++;
3464
3465         if (div > 8)
3466                 div = 8;
3467
3468         return parent_rate / div;
3469 }
3470
3471 static int _clk_emi_set_parent(struct clk *clk, struct clk *parent)
3472 {
3473         int mux;
3474         u32 reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_ACLK_EMI_MASK;
3475
3476         mux = _get_mux6(parent, &axi_clk, &pll3_usb_otg_main_clk,
3477                         &pll2_pfd_400M, &pll2_pfd_352M, NULL, NULL);
3478         reg |= (mux << MXC_CCM_CSCMR1_ACLK_EMI_OFFSET);
3479         __raw_writel(reg, MXC_CCM_CSCMR1);
3480
3481         return 0;
3482 }
3483
3484 static unsigned long _clk_emi_get_rate(struct clk *clk)
3485 {
3486         u32 reg, div;
3487
3488         reg = __raw_readl(MXC_CCM_CSCMR1);
3489         div = ((reg & MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK) >>
3490                         MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET) + 1;
3491
3492         return clk_get_rate(clk->parent) / div;
3493 }
3494
3495 static int _clk_emi_set_rate(struct clk *clk, unsigned long rate)
3496 {
3497         u32 reg, div;
3498         u32 parent_rate = clk_get_rate(clk->parent);
3499
3500         div = parent_rate / rate;
3501         if (div == 0)
3502                 div++;
3503         if (((parent_rate / div) != rate) || (div > 8))
3504                 return -EINVAL;
3505
3506         reg = __raw_readl(MXC_CCM_CSCMR1);
3507         reg &= ~MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK;
3508         reg |= (div - 1) << MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET;
3509         __raw_writel(reg, MXC_CCM_CSCMR1);
3510
3511         return 0;
3512 }
3513
3514 static struct clk emi_clk = {
3515         __INIT_CLK_DEBUG(emi_clk)
3516          .id = 0,
3517          .parent = &axi_clk,
3518          .set_rate = _clk_emi_set_rate,
3519          .get_rate = _clk_emi_get_rate,
3520          .round_rate = _clk_emi_round_rate,
3521          .set_parent = _clk_emi_set_parent,
3522 };
3523
3524 static unsigned long _clk_enfc_round_rate(struct clk *clk,
3525                                                 unsigned long rate)
3526 {
3527         u32 pre, post;
3528         u32 parent_rate = clk_get_rate(clk->parent);
3529         u32 div = parent_rate / rate;
3530
3531         if (parent_rate % rate)
3532                 div++;
3533
3534         __calc_pre_post_dividers(1 << 6, div, &pre, &post);
3535
3536         return parent_rate / (pre * post);
3537 }
3538
3539 static int _clk_enfc_set_parent(struct clk *clk, struct clk *parent)
3540 {
3541         u32 reg, mux;
3542
3543         reg = __raw_readl(MXC_CCM_CS2CDR)
3544                 & ~MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK;
3545
3546         mux = _get_mux6(parent, &pll2_pfd_352M,
3547                 &pll2_528_bus_main_clk, &pll3_usb_otg_main_clk,
3548                 &pll2_pfd_400M, NULL, NULL);
3549         reg |= mux << MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET;
3550
3551         __raw_writel(reg, MXC_CCM_CS2CDR);
3552
3553         return 0;
3554 }
3555
3556 static unsigned long _clk_enfc_get_rate(struct clk *clk)
3557 {
3558         u32 reg, pred, podf;
3559
3560         reg = __raw_readl(MXC_CCM_CS2CDR);
3561
3562         pred = ((reg & MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK)
3563                 >> MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET) + 1;
3564         podf = ((reg & MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK)
3565                 >> MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET) + 1;
3566
3567         return clk_get_rate(clk->parent) / (pred * podf);
3568 }
3569
3570 static int _clk_enfc_set_rate(struct clk *clk, unsigned long rate)
3571 {
3572         u32 reg, div, pre, post;
3573         u32 parent_rate = clk_get_rate(clk->parent);
3574
3575         div = parent_rate / rate;
3576         if (div == 0)
3577                 div++;
3578         if (((parent_rate / div) != rate) || div > 512)
3579                 return -EINVAL;
3580
3581         __calc_pre_post_dividers(1 << 6, div, &pre, &post);
3582
3583         reg = __raw_readl(MXC_CCM_CS2CDR);
3584         reg &= ~(MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK|
3585                  MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK);
3586         reg |= (post - 1) << MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET;
3587         reg |= (pre - 1) << MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET;
3588
3589         __raw_writel(reg, MXC_CCM_CS2CDR);
3590
3591         return 0;
3592 }
3593
3594 static struct clk enfc_clk = {
3595         __INIT_CLK_DEBUG(enfc_clk)
3596          .id = 0,
3597          .parent = &pll2_pfd_352M,
3598          .enable_reg = MXC_CCM_CCGR2,
3599          .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
3600          .enable = _clk_enable,
3601          .disable = _clk_disable,
3602          .set_rate = _clk_enfc_set_rate,
3603          .get_rate = _clk_enfc_get_rate,
3604          .round_rate = _clk_enfc_round_rate,
3605          .set_parent = _clk_enfc_set_parent,
3606 };
3607
3608 static unsigned long _clk_uart_round_rate(struct clk *clk,
3609                                                 unsigned long rate)
3610 {
3611         u32 div;
3612         u32 parent_rate = clk_get_rate(clk->parent);
3613
3614         div = parent_rate / rate;
3615
3616         /* Make sure rate is not greater than the maximum value for the clock.
3617          * Also prevent a div of 0.
3618          */
3619         if (div == 0)
3620                 div++;
3621
3622         if (div > 64)
3623                 div = 64;
3624
3625         return parent_rate / div;
3626 }
3627
3628 static int _clk_uart_set_rate(struct clk *clk, unsigned long rate)
3629 {
3630         u32 reg, div;
3631         u32 parent_rate = clk_get_rate(clk->parent);
3632
3633         div = parent_rate / rate;
3634         if (div == 0)
3635                 div++;
3636         if (((parent_rate / div) != rate) || (div > 64))
3637                 return -EINVAL;
3638
3639         reg = __raw_readl(MXC_CCM_CSCDR1) & MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
3640         reg |= ((div - 1) << MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET);
3641
3642         __raw_writel(reg, MXC_CCM_CSCDR1);
3643
3644         return 0;
3645 }
3646
3647 static unsigned long _clk_uart_get_rate(struct clk *clk)
3648 {
3649         u32 reg, div;
3650         unsigned long val;
3651
3652         reg = __raw_readl(MXC_CCM_CSCDR1) & MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
3653         div = (reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET) + 1;
3654         val = clk_get_rate(clk->parent) / div;
3655
3656         return val;
3657 }
3658
3659 static struct clk uart_clk[] = {
3660         {
3661         __INIT_CLK_DEBUG(uart_clk)
3662          .id = 0,
3663          .parent = &pll3_80M,
3664          .enable_reg = MXC_CCM_CCGR5,
3665          .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET,
3666          .enable = _clk_enable,
3667          .disable = _clk_disable,
3668          .secondary = &uart_clk[1],
3669          .set_rate = _clk_uart_set_rate,
3670          .get_rate = _clk_uart_get_rate,
3671          .round_rate = _clk_uart_round_rate,
3672         },
3673         {
3674         __INIT_CLK_DEBUG(uart_serial_clk)
3675          .id = 1,
3676          .enable_reg = MXC_CCM_CCGR5,
3677          .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
3678          .enable = _clk_enable,
3679          .disable = _clk_disable,
3680         },
3681 };
3682
3683 static unsigned long _clk_hsi_tx_round_rate(struct clk *clk,
3684                                                 unsigned long rate)
3685 {
3686         u32 div;
3687         u32 parent_rate = clk_get_rate(clk->parent);
3688
3689         div = parent_rate / rate;
3690
3691         /* Make sure rate is not greater than the maximum value for the clock.
3692          * Also prevent a div of 0.
3693          */
3694         if (div == 0)
3695                 div++;
3696
3697         if (div > 8)
3698                 div = 8;
3699
3700         return parent_rate / div;
3701 }
3702
3703 static int _clk_hsi_tx_set_parent(struct clk *clk, struct clk *parent)
3704 {
3705         u32 reg = __raw_readl(MXC_CCM_CDCDR) & ~MXC_CCM_CDCDR_HSI_TX_CLK_SEL;
3706
3707         if (parent == &pll2_pfd_400M)
3708                 reg |= (MXC_CCM_CDCDR_HSI_TX_CLK_SEL);
3709
3710         __raw_writel(reg, MXC_CCM_CDCDR);
3711
3712         return 0;
3713 }
3714
3715 static unsigned long _clk_hsi_tx_get_rate(struct clk *clk)
3716 {
3717         u32 reg, div;
3718
3719         reg = __raw_readl(MXC_CCM_CDCDR);
3720         div = ((reg & MXC_CCM_CDCDR_HSI_TX_PODF_MASK) >>
3721                         MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET) + 1;
3722
3723         return clk_get_rate(clk->parent) / div;
3724 }
3725
3726 static int _clk_hsi_tx_set_rate(struct clk *clk, unsigned long rate)
3727 {
3728         u32 reg, div;
3729         u32 parent_rate = clk_get_rate(clk->parent);
3730
3731         div = parent_rate / rate;
3732         if (div == 0)
3733                 div++;
3734         if (((parent_rate / div) != rate) || (div > 8))
3735                 return -EINVAL;
3736
3737         reg = __raw_readl(MXC_CCM_CDCDR);
3738         reg &= ~MXC_CCM_CDCDR_HSI_TX_PODF_MASK;
3739         reg |= (div - 1) << MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET;
3740         __raw_writel(reg, MXC_CCM_CDCDR);
3741
3742         return 0;
3743 }
3744
3745 static struct clk hsi_tx_clk[] = {
3746         {
3747          __INIT_CLK_DEBUG(hsi_tx_clk)
3748         .id = 0,
3749          .parent = &pll2_pfd_400M,
3750         .enable_reg = MXC_CCM_CCGR3,
3751         .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET,
3752         .enable = _clk_enable,
3753         .disable = _clk_disable,
3754         .set_parent = _clk_hsi_tx_set_parent,
3755         .round_rate = _clk_hsi_tx_round_rate,
3756         .set_rate = _clk_hsi_tx_set_rate,
3757         .get_rate = _clk_hsi_tx_get_rate,
3758          .secondary = &hsi_tx_clk[1],
3759         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
3760         },
3761         {
3762         .parent = &mx6per1_clk,
3763         .secondary = &mx6per2_clk,
3764          },
3765 };
3766
3767 static struct clk hdmi_clk[] = {
3768         {
3769          __INIT_CLK_DEBUG(hdmi_isfr_clk)
3770         .id = 0,
3771         .parent = &pll3_pfd_540M,
3772         .enable_reg = MXC_CCM_CCGR2,
3773         .enable_shift = MXC_CCM_CCGRx_CG2_OFFSET,
3774         .enable = _clk_enable,
3775         .disable = _clk_disable,
3776         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
3777         },
3778         {
3779          __INIT_CLK_DEBUG(hdmi_iahb_clk)
3780         .id = 1,
3781          .parent = &ahb_clk,
3782         .enable_reg = MXC_CCM_CCGR2,
3783         .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET,
3784         .enable = _clk_enable,
3785         .disable = _clk_disable,
3786         },
3787 };
3788
3789 static struct clk caam_clk[] = {
3790         {
3791          __INIT_CLK_DEBUG(caam_mem_clk)
3792         .id = 0,
3793         .enable_reg = MXC_CCM_CCGR0,
3794         .enable_shift = MXC_CCM_CCGRx_CG4_OFFSET,
3795         .enable = _clk_enable,
3796         .disable = _clk_disable,
3797         .secondary = &caam_clk[1],
3798         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
3799         },
3800         {
3801          __INIT_CLK_DEBUG(caam_aclk_clk)
3802         .id = 1,
3803         .enable_reg = MXC_CCM_CCGR0,
3804         .enable_shift = MXC_CCM_CCGRx_CG5_OFFSET,
3805         .enable = _clk_enable,
3806         .disable = _clk_disable,
3807         .secondary = &caam_clk[2],
3808         },
3809         {
3810          __INIT_CLK_DEBUG(caam_ipg_clk)
3811         .id = 2,
3812         .enable_reg = MXC_CCM_CCGR0,
3813         .enable_shift = MXC_CCM_CCGRx_CG4_OFFSET,
3814         .enable = _clk_enable,
3815         .disable = _clk_disable,
3816         .parent = &mmdc_ch0_axi_clk[0],
3817         .secondary = &mx6per1_clk,
3818         },
3819 };
3820
3821 static int _clk_asrc_serial_set_parent(struct clk *clk, struct clk *parent)
3822 {
3823         u32 reg, mux;
3824
3825         reg = __raw_readl(MXC_CCM_CDCDR) & ~MXC_CCM_CDCDR_SPDIF1_CLK_SEL_MASK;
3826
3827         mux = _get_mux6(parent, &pll4_audio_main_clk, &pll3_pfd_508M,
3828                         &pll3_pfd_454M, &pll3_sw_clk, NULL, NULL);
3829         reg |= mux << MXC_CCM_CDCDR_SPDIF1_CLK_SEL_OFFSET;
3830
3831         __raw_writel(reg, MXC_CCM_CDCDR);
3832
3833         return 0;
3834 }
3835
3836 static unsigned long _clk_asrc_serial_get_rate(struct clk *clk)
3837 {
3838         u32 reg, pred, podf;
3839
3840         reg = __raw_readl(MXC_CCM_CDCDR);
3841
3842         pred = ((reg & MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK)
3843                 >> MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET) + 1;
3844         podf = ((reg & MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK)
3845                 >> MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET) + 1;
3846
3847         return clk_get_rate(clk->parent) / (pred * podf);
3848 }
3849
3850 static int _clk_asrc_serial_set_rate(struct clk *clk, unsigned long rate)
3851 {
3852         u32 reg, div, pre, post;
3853         u32 parent_rate = clk_get_rate(clk->parent);
3854
3855         div = parent_rate / rate;
3856         if (div == 0)
3857                 div++;
3858         if (((parent_rate / div) != rate) || div > 64)
3859                 return -EINVAL;
3860
3861         __calc_pre_post_dividers(1 << 3, div, &pre, &post);
3862
3863         reg = __raw_readl(MXC_CCM_CDCDR);
3864         reg &= ~(MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK|
3865                  MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK);
3866         reg |= (post - 1) << MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET;
3867         reg |= (pre - 1) << MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET;
3868
3869         __raw_writel(reg, MXC_CCM_CDCDR);
3870
3871         return 0;
3872 }
3873
3874 static unsigned long _clk_asrc_serial_round_rate(struct clk *clk,
3875                                                 unsigned long rate)
3876 {
3877         u32 pre, post;
3878         u32 parent_rate = clk_get_rate(clk->parent);
3879         u32 div = parent_rate / rate;
3880
3881         if (parent_rate % rate)
3882                 div++;
3883
3884         __calc_pre_post_dividers(1 << 3, div, &pre, &post);
3885
3886         return parent_rate / (pre * post);
3887 }
3888
3889 static struct clk asrc_clk[] = {
3890         {
3891         __INIT_CLK_DEBUG(asrc_clk)
3892         .id = 0,
3893         .parent = &pll4_audio_main_clk,
3894         .enable_reg = MXC_CCM_CCGR0,
3895         .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET,
3896         .enable = _clk_enable,
3897         .disable = _clk_disable,
3898         .secondary = &spba_clk,
3899         },
3900         {
3901         /*In the MX6 spec, asrc_serial_clk is listed as SPDIF1 clk
3902          * This clock can never be gated and does  not have any
3903          * CCGR bits associated with it.
3904          */
3905         __INIT_CLK_DEBUG(asrc_serial_clk)
3906         .id = 1,
3907         .parent = &pll3_sw_clk,
3908          .set_rate = _clk_asrc_serial_set_rate,
3909          .get_rate = _clk_asrc_serial_get_rate,
3910          .set_parent = _clk_asrc_serial_set_parent,
3911          .round_rate = _clk_asrc_serial_round_rate,
3912         },
3913 };
3914
3915 static struct clk apbh_dma_clk = {
3916         __INIT_CLK_DEBUG(apbh_dma_clk)
3917         .parent = &usdhc3_clk,
3918         .secondary = &mx6per1_clk,
3919         .enable = _clk_enable,
3920         .disable = _clk_disable_inwait,
3921         .enable_reg = MXC_CCM_CCGR0,
3922         .enable_shift = MXC_CCM_CCGRx_CG2_OFFSET,
3923 };
3924
3925 static struct clk aips_tz2_clk = {
3926         __INIT_CLK_DEBUG(aips_tz2_clk)
3927         .parent = &ahb_clk,
3928         .enable_reg = MXC_CCM_CCGR0,
3929         .enable_shift = MXC_CCM_CCGRx_CG1_OFFSET,
3930         .enable = _clk_enable,
3931         .disable = _clk_disable_inwait,
3932 };
3933
3934 static struct clk aips_tz1_clk = {
3935         __INIT_CLK_DEBUG(aips_tz1_clk)
3936         .parent = &ahb_clk,
3937         .enable_reg = MXC_CCM_CCGR0,
3938         .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET,
3939         .enable = _clk_enable,
3940         .disable = _clk_disable_inwait,
3941 };
3942
3943
3944 static struct clk openvg_axi_clk = {
3945         __INIT_CLK_DEBUG(openvg_axi_clk)
3946         .parent = &gpu2d_axi_clk,
3947         .enable = _clk_enable,
3948         .enable_reg = MXC_CCM_CCGR3,
3949         .enable_shift = MXC_CCM_CCGRx_CG15_OFFSET,
3950         .disable = _clk_disable,
3951         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
3952 };
3953
3954 static unsigned long _clk_gpu3d_core_round_rate(struct clk *clk,
3955                                                 unsigned long rate)
3956 {
3957         u32 div;
3958         u32 parent_rate = clk_get_rate(clk->parent);
3959
3960         div = parent_rate / rate;
3961
3962         /* Make sure rate is not greater than the maximum value for the clock.
3963          * Also prevent a div of 0.
3964          */
3965         if (div == 0)
3966                 div++;
3967
3968         if (div > 8)
3969                 div = 8;
3970
3971         return parent_rate / div;
3972 }
3973
3974 static int _clk_gpu3d_core_set_parent(struct clk *clk, struct clk *parent)
3975 {
3976         int mux;
3977         u32 reg = __raw_readl(MXC_CCM_CBCMR)
3978                 & ~MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK;
3979
3980         mux = _get_mux6(parent, &mmdc_ch0_axi_clk[0],
3981                 &pll3_usb_otg_main_clk,
3982                 &pll2_pfd_594M, &pll2_pfd_400M, NULL, NULL);
3983         reg |= (mux << MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET);
3984         __raw_writel(reg, MXC_CCM_CBCMR);
3985
3986         return 0;
3987 }
3988
3989 static unsigned long _clk_gpu3d_core_get_rate(struct clk *clk)
3990 {
3991         u32 reg, div;
3992
3993         reg = __raw_readl(MXC_CCM_CBCMR);
3994         div = ((reg & MXC_CCM_CBCMR_GPU3D_CORE_PODF_MASK) >>
3995                         MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET) + 1;
3996
3997         return clk_get_rate(clk->parent) / div;
3998 }
3999
4000 static int _clk_gpu3d_core_set_rate(struct clk *clk, unsigned long rate)
4001 {
4002         u32 reg, div;
4003         u32 parent_rate = clk_get_rate(clk->parent);
4004
4005         div = parent_rate / rate;
4006         if (div == 0)
4007                 div++;
4008         if (div > 8)
4009                 div = 8;
4010
4011         reg = __raw_readl(MXC_CCM_CBCMR);
4012         reg &= ~MXC_CCM_CBCMR_GPU3D_CORE_PODF_MASK;
4013         reg |= (div - 1) << MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET;
4014         __raw_writel(reg, MXC_CCM_CBCMR);
4015
4016         return 0;
4017 }
4018
4019 static struct clk gpu3d_core_clk[] = {
4020         {
4021         __INIT_CLK_DEBUG(gpu3d_core_clk)
4022         .parent = &pll2_pfd_594M,
4023         .enable = _clk_enable,
4024         .enable_reg = MXC_CCM_CCGR1,
4025         .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
4026         .disable = _clk_disable,
4027         .set_parent = _clk_gpu3d_core_set_parent,
4028         .set_rate = _clk_gpu3d_core_set_rate,
4029         .get_rate = _clk_gpu3d_core_get_rate,
4030         .round_rate = _clk_gpu3d_core_round_rate,
4031         .secondary = &gpu3d_core_clk[1],
4032         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
4033         },
4034         {
4035         .parent = &gpu3d_axi_clk,
4036         .secondary = &mx6fast1_clk,
4037         },
4038 };
4039
4040 static unsigned long _clk_gpu2d_core_round_rate(struct clk *clk,
4041                                                 unsigned long rate)
4042 {
4043         u32 div;
4044         u32 parent_rate = clk_get_rate(clk->parent);
4045
4046         div = parent_rate / rate;
4047
4048         /* Make sure rate is not greater than the maximum value for the clock.
4049          * Also prevent a div of 0.
4050          */
4051         if (div == 0)
4052                 div++;
4053
4054         if (div > 8)
4055                 div = 8;
4056
4057         return parent_rate / div;
4058 }
4059
4060 static int _clk_gpu2d_core_set_parent(struct clk *clk, struct clk *parent)
4061 {
4062         int mux;
4063         u32 reg = __raw_readl(MXC_CCM_CBCMR) &
4064                                 ~MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK;
4065
4066         mux = _get_mux6(parent, &axi_clk, &pll3_usb_otg_main_clk,
4067                 &pll2_pfd_352M, &pll2_pfd_400M, NULL, NULL);
4068         reg |= (mux << MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET);
4069         __raw_writel(reg, MXC_CCM_CBCMR);
4070
4071         return 0;
4072 }
4073
4074 static unsigned long _clk_gpu2d_core_get_rate(struct clk *clk)
4075 {
4076         u32 reg, div;
4077
4078         reg = __raw_readl(MXC_CCM_CBCMR);
4079         div = ((reg & MXC_CCM_CBCMR_GPU2D_CORE_PODF_MASK) >>
4080                         MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET) + 1;
4081
4082         return clk_get_rate(clk->parent) / div;
4083 }
4084
4085 static int _clk_gpu2d_core_set_rate(struct clk *clk, unsigned long rate)
4086 {
4087         u32 reg, div;
4088         u32 parent_rate = clk_get_rate(clk->parent);
4089
4090         div = parent_rate / rate;
4091         if (div == 0)
4092                 div++;
4093         if (((parent_rate / div) != rate) || (div > 8))
4094                 return -EINVAL;
4095
4096         reg = __raw_readl(MXC_CCM_CBCMR);
4097         reg &= ~MXC_CCM_CBCMR_GPU3D_CORE_PODF_MASK;
4098         reg |= (div - 1) << MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET;
4099         __raw_writel(reg, MXC_CCM_CBCMR);
4100
4101         return 0;
4102 }
4103 static struct clk gpu2d_core_clk[] = {
4104         {
4105         __INIT_CLK_DEBUG(gpu2d_core_clk)
4106         .parent = &pll2_pfd_352M,
4107         .enable = _clk_enable,
4108         .enable_reg = MXC_CCM_CCGR1,
4109         .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET,
4110         .disable = _clk_disable,
4111         .set_parent = _clk_gpu2d_core_set_parent,
4112         .set_rate = _clk_gpu2d_core_set_rate,
4113         .get_rate = _clk_gpu2d_core_get_rate,
4114         .round_rate = _clk_gpu2d_core_round_rate,
4115         .secondary = &gpu2d_core_clk[0],
4116         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
4117         },
4118         {
4119         .parent = &gpu2d_axi_clk,
4120         .secondary = &mx6fast1_clk,
4121         },
4122 };
4123
4124 static unsigned long _clk_gpu3d_shader_round_rate(struct clk *clk,
4125                                                 unsigned long rate)
4126 {
4127         u32 div;
4128         u32 parent_rate = clk_get_rate(clk->parent);
4129
4130         div = parent_rate / rate;
4131
4132         /* Make sure rate is not greater than the maximum value for the clock.
4133          * Also prevent a div of 0.
4134          */
4135         if (div == 0)
4136                 div++;
4137
4138         if (div > 8)
4139                 div = 8;
4140
4141         return parent_rate / div;
4142 }
4143
4144 static int _clk_gpu3d_shader_set_parent(struct clk *clk, struct clk *parent)
4145 {
4146         int mux;
4147         u32 reg = __raw_readl(MXC_CCM_CBCMR)
4148                 & ~MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_MASK;
4149
4150         mux = _get_mux6(parent, &mmdc_ch0_axi_clk[0],
4151                 &pll3_usb_otg_main_clk,
4152                 &pll2_pfd_594M, &pll3_pfd_720M, NULL, NULL);
4153         reg |= (mux << MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET);
4154         __raw_writel(reg, MXC_CCM_CBCMR);
4155
4156         return 0;
4157 }
4158
4159 static unsigned long _clk_gpu3d_shader_get_rate(struct clk *clk)
4160 {
4161         u32 reg, div;
4162
4163         reg = __raw_readl(MXC_CCM_CBCMR);
4164         div = ((reg & MXC_CCM_CBCMR_GPU3D_SHADER_PODF_MASK) >>
4165                         MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET) + 1;
4166
4167         return clk_get_rate(clk->parent) / div;
4168 }
4169
4170 static int _clk_gpu3d_shader_set_rate(struct clk *clk, unsigned long rate)
4171 {
4172         u32 reg, div;
4173         u32 parent_rate = clk_get_rate(clk->parent);
4174
4175         div = parent_rate / rate;
4176         if (div == 0)
4177                 div++;
4178         if (div > 8)
4179                 div = 8;
4180
4181         reg = __raw_readl(MXC_CCM_CBCMR);
4182         reg &= ~MXC_CCM_CBCMR_GPU3D_SHADER_PODF_MASK;
4183         reg |= (div - 1) << MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET;
4184         __raw_writel(reg, MXC_CCM_CBCMR);
4185
4186         return 0;
4187 }
4188
4189
4190 static struct clk gpu3d_shader_clk = {
4191         __INIT_CLK_DEBUG(gpu3d_shader_clk)
4192         .parent = &pll3_pfd_720M,
4193         .secondary = &mmdc_ch0_axi_clk[0],
4194         .enable = _clk_enable,
4195         .enable_reg = MXC_CCM_CCGR1,
4196         .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
4197         .disable = _clk_disable,
4198         .set_parent = _clk_gpu3d_shader_set_parent,
4199         .set_rate = _clk_gpu3d_shader_set_rate,
4200         .get_rate = _clk_gpu3d_shader_get_rate,
4201         .round_rate = _clk_gpu3d_shader_round_rate,
4202         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
4203 };
4204
4205 /* set the parent by the ipcg table */
4206 static struct clk gpmi_nfc_clk[] = {
4207         {       /* gpmi_io_clk */
4208         __INIT_CLK_DEBUG(gpmi_io_clk)
4209         .parent = &enfc_clk,
4210         .secondary = &gpmi_nfc_clk[1],
4211         .enable = _clk_enable,
4212         .enable_reg = MXC_CCM_CCGR4,
4213         .enable_shift = MXC_CCM_CCGRx_CG14_OFFSET,
4214         .disable = _clk_disable,
4215         },
4216         {       /* gpmi_apb_clk */
4217         __INIT_CLK_DEBUG(gpmi_apb_clk)
4218         .parent = &usdhc3_clk,
4219         .secondary = &gpmi_nfc_clk[2],
4220         .enable = _clk_enable,
4221         .enable_reg = MXC_CCM_CCGR4,
4222         .enable_shift = MXC_CCM_CCGRx_CG15_OFFSET,
4223         .disable = _clk_disable,
4224         },
4225         {       /* bch_clk */
4226         __INIT_CLK_DEBUG(gpmi_bch_clk)
4227         .parent = &usdhc4_clk,
4228         .secondary = &gpmi_nfc_clk[3],
4229         .enable = _clk_enable,
4230         .enable_reg = MXC_CCM_CCGR4,
4231         .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
4232         .disable = _clk_disable,
4233         },
4234         {       /* bch_apb_clk */
4235         __INIT_CLK_DEBUG(gpmi_bch_apb_clk)
4236         .parent = &usdhc3_clk,
4237         .secondary = &gpmi_nfc_clk[4],
4238         .enable = _clk_enable,
4239         .enable_reg = MXC_CCM_CCGR4,
4240         .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET,
4241         .disable = _clk_disable,
4242         },
4243         {       /* bch relative clk */
4244         __INIT_CLK_DEBUG(pl301_mx6qperl_bch)
4245         .parent = &mx6per1_clk,
4246         .secondary = &mmdc_ch0_axi_clk[0],
4247         },
4248 };
4249
4250 static struct clk pwm_clk[] = {
4251         {
4252         __INIT_CLK_DEBUG(pwm_clk_0)
4253          .parent = &ipg_perclk,
4254          .id = 0,
4255          .enable_reg = MXC_CCM_CCGR4,
4256          .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET,
4257          .enable = _clk_enable,
4258          .disable = _clk_disable,
4259          },
4260         {
4261         __INIT_CLK_DEBUG(pwm_clk_1)
4262          .parent = &ipg_perclk,
4263          .id = 1,
4264          .enable_reg = MXC_CCM_CCGR4,
4265          .enable_shift = MXC_CCM_CCGRx_CG9_OFFSET,
4266          .enable = _clk_enable,
4267          .disable = _clk_disable,
4268          },
4269         {
4270         __INIT_CLK_DEBUG(pwm_clk_2)
4271          .parent = &ipg_perclk,
4272          .id = 2,
4273          .enable_reg = MXC_CCM_CCGR4,
4274          .enable_shift = MXC_CCM_CCGRx_CG10_OFFSET,
4275          .enable = _clk_enable,
4276          .disable = _clk_disable,
4277          },
4278         {
4279         __INIT_CLK_DEBUG(pwm_clk_3)
4280          .parent = &ipg_perclk,
4281          .id = 3,
4282          .enable_reg = MXC_CCM_CCGR4,
4283          .enable_shift = MXC_CCM_CCGRx_CG11_OFFSET,
4284          .enable = _clk_enable,
4285          .disable = _clk_disable,
4286          },
4287 };
4288
4289 static int _clk_pcie_enable(struct clk *clk)
4290 {
4291         unsigned int reg;
4292
4293         /* Enable SATA ref clock */
4294         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
4295         reg |= ANADIG_PLL_ENET_EN_PCIE;
4296         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
4297
4298         _clk_enable(clk);
4299
4300         return 0;
4301 }
4302
4303 static void _clk_pcie_disable(struct clk *clk)
4304 {
4305         unsigned int reg;
4306
4307         _clk_disable(clk);
4308
4309         /* Disable SATA ref clock */
4310         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
4311         reg &= ~ANADIG_PLL_ENET_EN_PCIE;
4312         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
4313 }
4314
4315 static struct clk pcie_clk[] = {
4316         {
4317         __INIT_CLK_DEBUG(pcie_clk)
4318         .parent = &pcie_axi_clk,
4319         .enable = _clk_pcie_enable,
4320         .disable = _clk_pcie_disable,
4321         .enable_reg = MXC_CCM_CCGR4,
4322         .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET,
4323         .secondary = &pcie_clk[1],
4324         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
4325         },
4326         {
4327         .parent = &mmdc_ch0_axi_clk[0],
4328         .secondary = &mx6fast1_clk,
4329         },
4330 };
4331
4332 static int _clk_sata_enable(struct clk *clk)
4333 {
4334         unsigned int reg;
4335
4336         /* Clear Power Down and Enable PLLs */
4337         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
4338         reg &= ~ANADIG_PLL_ENET_POWER_DOWN;
4339         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
4340
4341         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
4342         reg |= ANADIG_PLL_ENET_EN;
4343         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
4344
4345         /* Waiting for the PLL is locked */
4346         if (!WAIT(ANADIG_PLL_ENET_LOCK & __raw_readl(PLL8_ENET_BASE_ADDR),
4347                                 SPIN_DELAY))
4348                 panic("pll8 lock failed\n");
4349
4350         /* Disable the bypass */
4351         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
4352         reg &= ~ANADIG_PLL_ENET_BYPASS;
4353         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
4354
4355         /* Enable SATA ref clock */
4356         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
4357         reg |= ANADIG_PLL_ENET_EN_SATA;
4358         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
4359
4360         _clk_enable(clk);
4361
4362         return 0;
4363 }
4364
4365 static void _clk_sata_disable(struct clk *clk)
4366 {
4367         unsigned int reg;
4368
4369         _clk_disable(clk);
4370
4371         /* Disable SATA ref clock */
4372         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
4373         reg &= ~ANADIG_PLL_ENET_EN_SATA;
4374         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
4375 }
4376
4377 static struct clk sata_clk[] = {
4378         {
4379         __INIT_CLK_DEBUG(sata_clk)
4380         .parent = &ipg_clk,
4381         .enable = _clk_sata_enable,
4382         .enable_reg = MXC_CCM_CCGR5,
4383         .enable_shift = MXC_CCM_CCGRx_CG2_OFFSET,
4384         .disable = _clk_sata_disable,
4385         .secondary = &sata_clk[1],
4386         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
4387         },
4388         {
4389         .parent = &mmdc_ch0_axi_clk[0],
4390         .secondary = &mx6per1_clk,
4391         }
4392 };
4393
4394 static struct clk usboh3_clk[] = {
4395         {
4396         __INIT_CLK_DEBUG(usboh3_clk)
4397         .parent = &ahb_clk,
4398         .enable = _clk_enable,
4399         .enable_reg = MXC_CCM_CCGR6,
4400         .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET,
4401         .disable = _clk_disable,
4402         .secondary = &usboh3_clk[1],
4403         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
4404         },
4405         {
4406         .parent = &mmdc_ch0_axi_clk[0],
4407         .secondary = &mx6per1_clk,
4408         },
4409 };
4410
4411 static int _clk_enable1(struct clk *clk)
4412 {
4413         u32 reg;
4414         reg = __raw_readl(clk->enable_reg);
4415         reg |= 1 << clk->enable_shift;
4416         __raw_writel(reg, clk->enable_reg);
4417
4418         return 0;
4419 }
4420
4421 static void _clk_disable1(struct clk *clk)
4422 {
4423         u32 reg;
4424         reg = __raw_readl(clk->enable_reg);
4425         reg &= ~(1 << clk->enable_shift);
4426         __raw_writel(reg, clk->enable_reg);
4427 }
4428
4429 static int _clk_clko_set_parent(struct clk *clk, struct clk *parent)
4430 {
4431         u32 sel, reg;
4432
4433         if (parent == &pll3_usb_otg_main_clk)
4434                 sel = 0;
4435         else if (parent == &pll2_528_bus_main_clk)
4436                 sel = 1;
4437         else if (parent == &pll1_sys_main_clk)
4438                 sel = 2;
4439         else if (parent == &pll5_video_main_clk)
4440                 sel = 3;
4441         else if (parent == &axi_clk)
4442                 sel = 5;
4443         else if (parent == &enfc_clk)
4444                 sel = 6;
4445         else if (parent == &ipu1_di_clk[0])
4446                 sel = 7;
4447         else if (parent == &ipu1_di_clk[1])
4448                 sel = 8;
4449         else if (parent == &ipu2_di_clk[0])
4450                 sel = 9;
4451         else if (parent == &ipu2_di_clk[1])
4452                 sel = 10;
4453         else if (parent == &ahb_clk)
4454                 sel = 11;
4455         else if (parent == &ipg_clk)
4456                 sel = 12;
4457         else if (parent == &ipg_perclk)
4458                 sel = 13;
4459         else if (parent == &ckil_clk)
4460                 sel = 14;
4461         else if (parent == &pll4_audio_main_clk)
4462                 sel = 15;
4463         else
4464                 return -EINVAL;
4465
4466         reg = __raw_readl(MXC_CCM_CCOSR);
4467         reg &= ~MXC_CCM_CCOSR_CKOL_SEL_MASK;
4468         reg |= sel << MXC_CCM_CCOSR_CKOL_SEL_OFFSET;
4469         __raw_writel(reg, MXC_CCM_CCOSR);
4470         return 0;
4471 }
4472
4473 static unsigned long _clk_clko_get_rate(struct clk *clk)
4474 {
4475         u32 reg = __raw_readl(MXC_CCM_CCOSR);
4476         u32 div = ((reg & MXC_CCM_CCOSR_CKOL_DIV_MASK) >>
4477                         MXC_CCM_CCOSR_CKOL_DIV_OFFSET) + 1;
4478         return clk_get_rate(clk->parent) / div;
4479 }
4480
4481 static int _clk_clko_set_rate(struct clk *clk, unsigned long rate)
4482 {
4483         u32 reg;
4484         u32 parent_rate = clk_get_rate(clk->parent);
4485         u32 div = parent_rate / rate;
4486
4487         if (div == 0)
4488                 div++;
4489         if (((parent_rate / div) != rate) || (div > 8))
4490                 return -EINVAL;
4491
4492         reg = __raw_readl(MXC_CCM_CCOSR);
4493         reg &= ~MXC_CCM_CCOSR_CKOL_DIV_MASK;
4494         reg |= (div - 1) << MXC_CCM_CCOSR_CKOL_DIV_OFFSET;
4495         __raw_writel(reg, MXC_CCM_CCOSR);
4496         return 0;
4497 }
4498
4499 static unsigned long _clk_clko_round_rate(struct clk *clk,
4500                                                 unsigned long rate)
4501 {
4502         u32 parent_rate = clk_get_rate(clk->parent);
4503         u32 div = parent_rate / rate;
4504
4505         /* Make sure rate is not greater than the maximum value for the clock.
4506          * Also prevent a div of 0.
4507          */
4508         if (div == 0)
4509                 div++;
4510         if (div > 8)
4511                 div = 8;
4512         return parent_rate / div;
4513 }
4514
4515 static struct clk clko_clk = {
4516         __INIT_CLK_DEBUG(clko_clk)
4517         .parent = &pll2_528_bus_main_clk,
4518         .enable = _clk_enable1,
4519         .enable_reg = MXC_CCM_CCOSR,
4520         .enable_shift = MXC_CCM_CCOSR_CKOL_EN_OFFSET,
4521         .disable = _clk_disable1,
4522         .set_parent = _clk_clko_set_parent,
4523         .set_rate = _clk_clko_set_rate,
4524         .get_rate = _clk_clko_get_rate,
4525         .round_rate = _clk_clko_round_rate,
4526 };
4527
4528 static struct clk dummy_clk = {
4529         .id = 0,
4530 };
4531
4532 #define _REGISTER_CLOCK(d, n, c) \
4533         { \
4534                 .dev_id = d, \
4535                 .con_id = n, \
4536                 .clk = &c, \
4537         }
4538
4539
4540 static struct clk_lookup lookups[] = {
4541         _REGISTER_CLOCK(NULL, "osc", osc_clk),
4542         _REGISTER_CLOCK(NULL, "ckih", ckih_clk),
4543         _REGISTER_CLOCK(NULL, "ckih2", ckih2_clk),
4544         _REGISTER_CLOCK(NULL, "ckil", ckil_clk),
4545         _REGISTER_CLOCK(NULL, "pll1_main_clk", pll1_sys_main_clk),
4546         _REGISTER_CLOCK(NULL, "pll1_sw_clk", pll1_sw_clk),
4547         _REGISTER_CLOCK(NULL, "pll2", pll2_528_bus_main_clk),
4548         _REGISTER_CLOCK(NULL, "pll2_pfd_400M", pll2_pfd_400M),
4549         _REGISTER_CLOCK(NULL, "pll2_pfd_352M", pll2_pfd_352M),
4550         _REGISTER_CLOCK(NULL, "pll2_pfd_594M", pll2_pfd_594M),
4551         _REGISTER_CLOCK(NULL, "pll2_200M", pll2_200M),
4552         _REGISTER_CLOCK(NULL, "pll3_main_clk", pll3_usb_otg_main_clk),
4553         _REGISTER_CLOCK(NULL, "pll3_pfd_508M", pll3_pfd_508M),
4554         _REGISTER_CLOCK(NULL, "pll3_pfd_454M", pll3_pfd_454M),
4555         _REGISTER_CLOCK(NULL, "pll3_pfd_720M", pll3_pfd_720M),
4556         _REGISTER_CLOCK(NULL, "pll3_pfd_540M", pll3_pfd_540M),
4557         _REGISTER_CLOCK(NULL, "pll3_sw_clk", pll3_sw_clk),
4558         _REGISTER_CLOCK(NULL, "pll3_120M", pll3_120M),
4559         _REGISTER_CLOCK(NULL, "pll3_120M", pll3_80M),
4560         _REGISTER_CLOCK(NULL, "pll3_120M", pll3_60M),
4561         _REGISTER_CLOCK(NULL, "pll4", pll4_audio_main_clk),
4562         _REGISTER_CLOCK(NULL, "pll5", pll5_video_main_clk),
4563         _REGISTER_CLOCK(NULL, "pll4", pll6_MLB_main_clk),
4564         _REGISTER_CLOCK(NULL, "pll3", pll7_usb_host_main_clk),
4565         _REGISTER_CLOCK(NULL, "pll4", pll8_enet_main_clk),
4566         _REGISTER_CLOCK(NULL, "cpu_clk", cpu_clk),
4567         _REGISTER_CLOCK(NULL, "periph_clk", periph_clk),
4568         _REGISTER_CLOCK(NULL, "axi_clk", axi_clk),
4569         _REGISTER_CLOCK(NULL, "mmdc_ch0_axi", mmdc_ch0_axi_clk[0]),
4570         _REGISTER_CLOCK(NULL, "mmdc_ch1_axi", mmdc_ch1_axi_clk[0]),
4571         _REGISTER_CLOCK(NULL, "ahb", ahb_clk),
4572         _REGISTER_CLOCK(NULL, "ipg_clk", ipg_clk),
4573         _REGISTER_CLOCK(NULL, "ipg_perclk", ipg_perclk),
4574         _REGISTER_CLOCK(NULL, "spba", spba_clk),
4575         _REGISTER_CLOCK("imx-sdma", NULL, sdma_clk[0]),
4576         _REGISTER_CLOCK(NULL, "gpu2d_axi_clk", gpu2d_axi_clk),
4577         _REGISTER_CLOCK(NULL, "gpu3d_axi_clk", gpu3d_axi_clk),
4578         _REGISTER_CLOCK(NULL, "pcie_axi_clk", pcie_axi_clk),
4579         _REGISTER_CLOCK(NULL, "vdo_axi_clk", vdo_axi_clk),
4580         _REGISTER_CLOCK(NULL, "iim_clk", iim_clk),
4581         _REGISTER_CLOCK(NULL, "i2c_clk", i2c_clk[0]),
4582         _REGISTER_CLOCK("imx-i2c.1", NULL, i2c_clk[1]),
4583         _REGISTER_CLOCK("imx-i2c.2", NULL, i2c_clk[2]),
4584         _REGISTER_CLOCK(NULL, "vpu_clk", vpu_clk[0]),
4585         _REGISTER_CLOCK(NULL, "ipu1_clk", ipu1_clk),
4586         _REGISTER_CLOCK(NULL, "ipu2_clk", ipu2_clk),
4587         _REGISTER_CLOCK(NULL, "cko1_clk0", cko1_clk0),
4588         _REGISTER_CLOCK("sdhci-esdhc-imx.0", NULL, usdhc1_clk),
4589         _REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL, usdhc2_clk),
4590         _REGISTER_CLOCK("sdhci-esdhc-imx.2", NULL, usdhc3_clk),
4591         _REGISTER_CLOCK("sdhci-esdhc-imx.3", NULL, usdhc4_clk),
4592         _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk),
4593         _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk),
4594         _REGISTER_CLOCK("imx-ssi.2", NULL, ssi3_clk),
4595         _REGISTER_CLOCK(NULL, "ipu1_di0_clk", ipu1_di_clk[0]),
4596         _REGISTER_CLOCK(NULL, "ipu1_di1_clk", ipu1_di_clk[1]),
4597         _REGISTER_CLOCK(NULL, "ipu2_di0_clk", ipu2_di_clk[0]),
4598         _REGISTER_CLOCK(NULL, "ipu2_di1_clk", ipu2_di_clk[1]),
4599         _REGISTER_CLOCK("FlexCAN.0", "can_clk", can1_clk[0]),
4600         _REGISTER_CLOCK("FlexCAN.1", "can_clk", can2_clk[0]),
4601         _REGISTER_CLOCK(NULL, "ldb_di0_clk", ldb_di0_clk),
4602         _REGISTER_CLOCK(NULL, "ldb_di1_clk", ldb_di1_clk),
4603         _REGISTER_CLOCK("mxc_spdif.0", NULL, spdif0_clk[0]),
4604         _REGISTER_CLOCK(NULL, "esai_clk", esai_clk),
4605         _REGISTER_CLOCK("mxc_spi.0", NULL, ecspi_clk[0]),
4606         _REGISTER_CLOCK("mxc_spi.1", NULL, ecspi_clk[1]),
4607         _REGISTER_CLOCK("mxc_spi.2", NULL, ecspi_clk[2]),
4608         _REGISTER_CLOCK("mxc_spi.3", NULL, ecspi_clk[3]),
4609         _REGISTER_CLOCK("mxc_spi.4", NULL, ecspi_clk[4]),
4610         _REGISTER_CLOCK(NULL, "emi_slow_clk", emi_slow_clk),
4611         _REGISTER_CLOCK(NULL, "emi_clk", emi_clk),
4612         _REGISTER_CLOCK(NULL, "enfc_clk", enfc_clk),
4613         _REGISTER_CLOCK("imx-uart.0", NULL, uart_clk[0]),
4614         _REGISTER_CLOCK(NULL, "hsi_tx", hsi_tx_clk[0]),
4615         _REGISTER_CLOCK(NULL, "caam_clk", caam_clk[0]),
4616         _REGISTER_CLOCK(NULL, "asrc_clk", asrc_clk[0]),
4617         _REGISTER_CLOCK(NULL, "asrc_serial_clk", asrc_clk[1]),
4618         _REGISTER_CLOCK("mxs-dma-apbh", NULL, apbh_dma_clk),
4619         _REGISTER_CLOCK(NULL, "openvg_axi_clk", openvg_axi_clk),
4620         _REGISTER_CLOCK(NULL, "gpu3d_clk", gpu3d_core_clk[0]),
4621         _REGISTER_CLOCK(NULL, "gpu2d_clk", gpu2d_core_clk[0]),
4622         _REGISTER_CLOCK(NULL, "gpu3d_shader_clk", gpu3d_shader_clk),
4623         _REGISTER_CLOCK(NULL, "gpt", gpt_clk[0]),
4624         _REGISTER_CLOCK("imx6q-gpmi-nfc.0", NULL, gpmi_nfc_clk[0]),
4625         _REGISTER_CLOCK(NULL, "gpmi-apb", gpmi_nfc_clk[1]),
4626         _REGISTER_CLOCK(NULL, "bch", gpmi_nfc_clk[2]),
4627         _REGISTER_CLOCK(NULL, "bch-apb", gpmi_nfc_clk[3]),
4628         _REGISTER_CLOCK(NULL, "pl301_mx6qperl-bch", gpmi_nfc_clk[4]),
4629         _REGISTER_CLOCK("mxc_pwm.0", NULL, pwm_clk[0]),
4630         _REGISTER_CLOCK("mxc_pwm.1", NULL, pwm_clk[1]),
4631         _REGISTER_CLOCK("mxc_pwm.2", NULL, pwm_clk[2]),
4632         _REGISTER_CLOCK("mxc_pwm.3", NULL, pwm_clk[3]),
4633         _REGISTER_CLOCK(NULL, "pcie_clk", pcie_clk[0]),
4634         _REGISTER_CLOCK("fec.0", NULL, enet_clk[0]),
4635         _REGISTER_CLOCK(NULL, "imx_sata_clk", sata_clk[0]),
4636         _REGISTER_CLOCK(NULL, "usboh3_clk", usboh3_clk[0]),
4637         _REGISTER_CLOCK(NULL, "usb_phy1_clk", usb_phy1_clk),
4638         _REGISTER_CLOCK("imx2-wdt.0", NULL, dummy_clk),
4639         _REGISTER_CLOCK("imx2-wdt.1", NULL, dummy_clk),
4640         _REGISTER_CLOCK(NULL, "hdmi_isfr_clk", hdmi_clk[0]),
4641         _REGISTER_CLOCK(NULL, "hdmi_iahb_clk", hdmi_clk[1]),
4642         _REGISTER_CLOCK(NULL, NULL, vdoa_clk),
4643         _REGISTER_CLOCK(NULL, NULL, aips_tz2_clk),
4644         _REGISTER_CLOCK(NULL, NULL, aips_tz1_clk),
4645         _REGISTER_CLOCK(NULL, "clko_clk", clko_clk),
4646 };
4647
4648
4649 static void clk_tree_init(void)
4650
4651 {
4652         unsigned int reg;
4653
4654         reg = __raw_readl(MMDC_MDMISC_OFFSET);
4655         if ((reg & MMDC_MDMISC_DDR_TYPE_MASK) ==
4656                 (0x1 << MMDC_MDMISC_DDR_TYPE_OFFSET)) {
4657                 clk_set_parent(&periph_clk, &pll2_pfd_400M);
4658                 printk(KERN_INFO "Set periph_clk's parent to pll2_pfd_400M!\n");
4659         }
4660 }
4661
4662
4663 int __init mx6_clocks_init(unsigned long ckil, unsigned long osc,
4664         unsigned long ckih1, unsigned long ckih2)
4665 {
4666         __iomem void *base;
4667         int i;
4668
4669         external_low_reference = ckil;
4670         external_high_reference = ckih1;
4671         ckih2_reference = ckih2;
4672         oscillator_reference = osc;
4673
4674         apll_base = ioremap(ANATOP_BASE_ADDR, SZ_4K);
4675
4676         for (i = 0; i < ARRAY_SIZE(lookups); i++) {
4677                 clkdev_add(&lookups[i]);
4678                 clk_debug_register(lookups[i].clk);
4679         }
4680
4681         /* Disable un-necessary PFDs & PLLs */
4682
4683         /* keep correct count. */
4684         clk_enable(&cpu_clk);
4685         clk_enable(&periph_clk);
4686
4687         clk_tree_init();
4688
4689         if (pll2_pfd_400M.usecount == 0)
4690                 pll2_pfd_400M.disable(&pll2_pfd_400M);
4691         pll2_pfd_352M.disable(&pll2_pfd_352M);
4692         pll2_pfd_594M.disable(&pll2_pfd_594M);
4693
4694         pll3_pfd_454M.disable(&pll3_pfd_454M);
4695         pll3_pfd_508M.disable(&pll3_pfd_508M);
4696         pll3_pfd_540M.disable(&pll3_pfd_540M);
4697         pll3_pfd_720M.disable(&pll3_pfd_720M);
4698
4699         pll3_usb_otg_main_clk.disable(&pll3_usb_otg_main_clk);
4700         pll4_audio_main_clk.disable(&pll4_audio_main_clk);
4701         pll5_video_main_clk.disable(&pll5_video_main_clk);
4702         pll6_MLB_main_clk.disable(&pll6_MLB_main_clk);
4703         pll7_usb_host_main_clk.disable(&pll7_usb_host_main_clk);
4704         pll8_enet_main_clk.disable(&pll8_enet_main_clk);
4705
4706         sata_clk[0].disable(&sata_clk[0]);
4707         pcie_clk[0].disable(&pcie_clk[0]);
4708
4709         /* Initialize Audio and Video PLLs to valid frequency (650MHz). */
4710         clk_set_rate(&pll4_audio_main_clk, 650000000);
4711         clk_set_rate(&pll5_video_main_clk, 650000000);
4712
4713         clk_set_parent(&ipu1_di_clk[0], &pll5_video_main_clk);
4714         clk_set_parent(&ipu1_di_clk[1], &pll5_video_main_clk);
4715         clk_set_parent(&ipu2_di_clk[0], &pll5_video_main_clk);
4716         clk_set_parent(&ipu2_di_clk[1], &pll5_video_main_clk);
4717
4718         clk_set_parent(&cko1_clk0, &ipg_clk);
4719         clk_set_rate(&cko1_clk0, 22000000);
4720         clk_enable(&cko1_clk0);
4721
4722         clk_set_parent(&gpu3d_shader_clk, &pll2_pfd_594M);
4723         clk_set_rate(&gpu3d_shader_clk, 594000000);
4724         clk_set_parent(&gpu3d_core_clk[0], &mmdc_ch0_axi_clk[0]);
4725         clk_set_rate(&gpu3d_core_clk[0], 528000000);
4726
4727         /*
4728          * FIXME: asrc needs to use asrc_serial(spdif1) clock to do sample rate convertion,
4729          * however we found it only works when set to 1.5M clock and the
4730          * parent is pll3_sw_clk.
4731          */
4732         clk_set_parent(&asrc_clk[1], &pll3_sw_clk);
4733         clk_set_rate(&asrc_clk[1], 1500000);
4734
4735         /* set the NAND to 11MHz. Too fast will cause dma timeout. */
4736         clk_set_rate(&enfc_clk, enfc_clk.round_rate(&enfc_clk, 11000000));
4737
4738         mx6_cpu_op_init();
4739         cpu_op_tbl = get_cpu_op(&cpu_op_nr);
4740
4741         /* Gate off all possible clocks */
4742         if (mxc_jtag_enabled) {
4743                 __raw_writel(3 << MXC_CCM_CCGRx_CG11_OFFSET |
4744                              3 << MXC_CCM_CCGRx_CG2_OFFSET |
4745                              3 << MXC_CCM_CCGRx_CG1_OFFSET |
4746                              3 << MXC_CCM_CCGRx_CG0_OFFSET, MXC_CCM_CCGR0);
4747         } else {
4748                 __raw_writel(1 << MXC_CCM_CCGRx_CG11_OFFSET |
4749                              3 << MXC_CCM_CCGRx_CG2_OFFSET |
4750                              3 << MXC_CCM_CCGRx_CG1_OFFSET |
4751                              3 << MXC_CCM_CCGRx_CG0_OFFSET, MXC_CCM_CCGR0);
4752         }
4753         __raw_writel(3 << MXC_CCM_CCGRx_CG10_OFFSET, MXC_CCM_CCGR1);
4754         __raw_writel(1 << MXC_CCM_CCGRx_CG12_OFFSET |
4755                      1 << MXC_CCM_CCGRx_CG11_OFFSET |
4756                      3 << MXC_CCM_CCGRx_CG10_OFFSET |
4757                      3 << MXC_CCM_CCGRx_CG9_OFFSET |
4758                      3 << MXC_CCM_CCGRx_CG8_OFFSET, MXC_CCM_CCGR2);
4759         __raw_writel(1 << MXC_CCM_CCGRx_CG14_OFFSET |
4760                      3 << MXC_CCM_CCGRx_CG13_OFFSET |
4761                      3 << MXC_CCM_CCGRx_CG12_OFFSET |
4762                      3 << MXC_CCM_CCGRx_CG11_OFFSET |
4763                      3 << MXC_CCM_CCGRx_CG10_OFFSET, MXC_CCM_CCGR3);
4764         __raw_writel(3 << MXC_CCM_CCGRx_CG7_OFFSET |
4765                         1 << MXC_CCM_CCGRx_CG6_OFFSET |
4766                         1 << MXC_CCM_CCGRx_CG4_OFFSET, MXC_CCM_CCGR4);
4767         __raw_writel(1 << MXC_CCM_CCGRx_CG0_OFFSET, MXC_CCM_CCGR5);
4768
4769         __raw_writel(0, MXC_CCM_CCGR6);
4770
4771         /* Lower the ipg_perclk frequency to 8.25MHz. */
4772         clk_set_rate(&ipg_perclk, 8250000);
4773
4774         /* S/PDIF */
4775         clk_set_parent(&spdif0_clk[0], &pll3_pfd_454M);
4776
4777         base = ioremap(GPT_BASE_ADDR, SZ_4K);
4778         mxc_timer_init(&gpt_clk[0], base, MXC_INT_GPT);
4779
4780         lp_high_freq = 0;
4781         lp_med_freq = 0;
4782
4783         return 0;
4784
4785 }