arch/arm/mach-mx6/clock.c

   1
   2 /*
   3  * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
   4  */
   5
   6 /*
   7  * The code contained herein is licensed under the GNU General Public
   8  * License. You may obtain a copy of the GNU General Public License
   9  * Version 2 or later at the following locations:
  10  *
  11  * http://www.opensource.org/licenses/gpl-license.html
  12  * http://www.gnu.org/copyleft/gpl.html
  13  */
  14
  15 #include <linux/kernel.h>
  16 #include <linux/init.h>
  17 #include <linux/types.h>
  18 #include <linux/time.h>
  19 #include <linux/hrtimer.h>
  20 #include <linux/mm.h>
  21 #include <linux/errno.h>
  22 #include <linux/delay.h>
  23 #include <linux/clk.h>
  24 #include <linux/io.h>
  25 #include <linux/clkdev.h>
  26 #include <asm/div64.h>
  27 #include <mach/hardware.h>
  28 #include <mach/common.h>
  29 #include <mach/clock.h>
  30 #include <mach/mxc_dvfs.h>
  31 #include "crm_regs.h"
  32 #include "cpu_op-mx6.h"
  33
  34 #ifdef CONFIG_CLK_DEBUG
  35 #define __INIT_CLK_DEBUG(n)     .name = #n,
  36 #else
  37 #define __INIT_CLK_DEBUG(n)
  38 #endif
  39
  40 extern int mxc_jtag_enabled;
  41 extern struct cpu_op *(*get_cpu_op)(int *op);
  42
  43 void __iomem *apll_base;
  44 static struct clk pll1_sys_main_clk;
  45 static struct clk pll2_528_bus_main_clk;
  46 static struct clk pll3_usb_otg_main_clk;
  47 static struct clk pll4_audio_main_clk;
  48 static struct clk pll5_video_main_clk;
  49 static struct clk pll6_MLB_main_clk;
  50 static struct clk pll7_usb_host_main_clk;
  51 static struct clk pll8_enet_main_clk;
  52 static struct clk apbh_dma_clk;
  53 static struct clk openvg_axi_clk;
  54 static struct cpu_op *cpu_op_tbl;
  55 static int cpu_op_nr;
  56
  57 #define SPIN_DELAY      1000000 /* in nanoseconds */
  58
  59 #define AUDIO_VIDEO_MIN_CLK_FREQ        650000000
  60 #define AUDIO_VIDEO_MAX_CLK_FREQ        1300000000
  61
  62 #define WAIT(exp, timeout) \
  63 ({ \
  64         struct timespec nstimeofday; \
  65         struct timespec curtime; \
  66         int result = 1; \
  67         getnstimeofday(&nstimeofday); \
  68         while (!(exp)) { \
  69                 getnstimeofday(&curtime); \
  70                 if ((curtime.tv_nsec - nstimeofday.tv_nsec) > (timeout)) { \
  71                         result = 0; \
  72                         break; \
  73                 } \
  74         } \
  75         result; \
  76 })
  77
  78 /* External clock values passed-in by the board code */
  79 static unsigned long external_high_reference, external_low_reference;
  80 static unsigned long oscillator_reference, ckih2_reference;
  81
  82 static void __calc_pre_post_dividers(u32 max_podf, u32 div, u32 *pre, u32 *post)
  83 {
  84         u32 min_pre, temp_pre, old_err, err;
  85
  86         /* Some of the podfs are 3 bits while others are 6 bits.
  87           * Handle both cases here.
  88           */
  89         if (div >= 512 && (max_podf == 64)) {
  90                 /* For pre = 3bits and podf = 6 bits, max divider is 512. */
  91                 *pre = 8;
  92                 *post = 64;
  93         } else if (div >= 64 && (max_podf == 8)) {
  94                 /* For pre = 3bits and podf = 3 bits, max divider is 64. */
  95                 *pre = 8;
  96                 *post = 8;
  97         } else if (div >= 8) {
  98                 /* Find the minimum pre-divider for a max podf */
  99                 if (max_podf == 64)
 100                         min_pre = (div - 1) / (1 << 6) + 1;
 101                 else
 102                         min_pre = (div - 1) / (1 << 3) + 1;
 103                 old_err = 8;
 104                 /* Now loop through to find the max pre-divider. */
 105                 for (temp_pre = 8; temp_pre >= min_pre; temp_pre--) {
 106                         err = div % temp_pre;
 107                         if (err == 0) {
 108                                 *pre = temp_pre;
 109                                 break;
 110                         }
 111                         err = temp_pre - err;
 112                         if (err < old_err) {
 113                                 old_err = err;
 114                                 *pre = temp_pre;
 115                         }
 116                 }
 117                 *post = (div + *pre - 1) / *pre;
 118         } else if (div < 8) {
 119                 *pre = div;
 120                 *post = 1;
 121         }
 122 }
 123
 124 static int _clk_enable(struct clk *clk)
 125 {
 126         u32 reg;
 127         reg = __raw_readl(clk->enable_reg);
 128         reg |= MXC_CCM_CCGRx_CG_MASK << clk->enable_shift;
 129         __raw_writel(reg, clk->enable_reg);
 130
 131         return 0;
 132 }
 133
 134 static void _clk_disable(struct clk *clk)
 135 {
 136         u32 reg;
 137         reg = __raw_readl(clk->enable_reg);
 138         reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift);
 139         __raw_writel(reg, clk->enable_reg);
 140 }
 141
 142 static void _clk_disable_inwait(struct clk *clk)
 143 {
 144         u32 reg;
 145         reg = __raw_readl(clk->enable_reg);
 146         reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift);
 147         reg |= 1 << clk->enable_shift;
 148         __raw_writel(reg, clk->enable_reg);
 149 }
 150
 151 /*
 152  * For the 4-to-1 muxed input clock
 153  */
 154 static inline u32 _get_mux(struct clk *parent, struct clk *m0,
 155                            struct clk *m1, struct clk *m2, struct clk *m3)
 156 {
 157         if (parent == m0)
 158                 return 0;
 159         else if (parent == m1)
 160                 return 1;
 161         else if (parent == m2)
 162                 return 2;
 163         else if (parent == m3)
 164                 return 3;
 165         else
 166                 BUG();
 167
 168         return 0;
 169 }
 170
 171 static inline void __iomem *_get_pll_base(struct clk *pll)
 172 {
 173         if (pll == &pll1_sys_main_clk)
 174                 return PLL1_SYS_BASE_ADDR;
 175         else if (pll == &pll2_528_bus_main_clk)
 176                 return PLL2_528_BASE_ADDR;
 177         else if (pll == &pll3_usb_otg_main_clk)
 178                 return PLL3_480_USB1_BASE_ADDR;
 179         else if (pll == &pll4_audio_main_clk)
 180                 return PLL4_AUDIO_BASE_ADDR;
 181         else if (pll == &pll5_video_main_clk)
 182                 return PLL5_VIDEO_BASE_ADDR;
 183         else if (pll == &pll6_MLB_main_clk)
 184                 return PLL6_MLB_BASE_ADDR;
 185         else if (pll == &pll7_usb_host_main_clk)
 186                 return PLL7_480_USB2_BASE_ADDR;
 187         else if (pll == &pll8_enet_main_clk)
 188                 return PLL8_ENET_BASE_ADDR;
 189         else
 190                 BUG();
 191         return NULL;
 192 }
 193
 194
 195 /*
 196  * For the 6-to-1 muxed input clock
 197  */
 198 static inline u32 _get_mux6(struct clk *parent, struct clk *m0, struct clk *m1,
 199                             struct clk *m2, struct clk *m3, struct clk *m4,
 200                             struct clk *m5)
 201 {
 202         if (parent == m0)
 203                 return 0;
 204         else if (parent == m1)
 205                 return 1;
 206         else if (parent == m2)
 207                 return 2;
 208         else if (parent == m3)
 209                 return 3;
 210         else if (parent == m4)
 211                 return 4;
 212         else if (parent == m5)
 213                 return 5;
 214         else
 215                 BUG();
 216
 217         return 0;
 218 }
 219 static unsigned long get_high_reference_clock_rate(struct clk *clk)
 220 {
 221         return external_high_reference;
 222 }
 223
 224 static unsigned long get_low_reference_clock_rate(struct clk *clk)
 225 {
 226         return external_low_reference;
 227 }
 228
 229 static unsigned long get_oscillator_reference_clock_rate(struct clk *clk)
 230 {
 231         return oscillator_reference;
 232 }
 233
 234 static unsigned long get_ckih2_reference_clock_rate(struct clk *clk)
 235 {
 236         return ckih2_reference;
 237 }
 238
 239 /* External high frequency clock */
 240 static struct clk ckih_clk = {
 241         __INIT_CLK_DEBUG(ckih_clk)
 242         .get_rate = get_high_reference_clock_rate,
 243 };
 244
 245 static struct clk ckih2_clk = {
 246         __INIT_CLK_DEBUG(ckih2_clk)
 247         .get_rate = get_ckih2_reference_clock_rate,
 248 };
 249
 250 static struct clk osc_clk = {
 251         __INIT_CLK_DEBUG(osc_clk)
 252         .get_rate = get_oscillator_reference_clock_rate,
 253 };
 254
 255 /* External low frequency (32kHz) clock */
 256 static struct clk ckil_clk = {
 257         __INIT_CLK_DEBUG(ckil_clk)
 258         .get_rate = get_low_reference_clock_rate,
 259 };
 260
 261 static unsigned long pfd_round_rate(struct clk *clk, unsigned long rate)
 262 {
 263         u32 frac;
 264         u64 tmp;
 265
 266         tmp = (u64)clk_get_rate(clk->parent) * 18;
 267         tmp += rate/2;
 268         do_div(tmp, rate);
 269         frac = tmp;
 270         frac = frac < 12 ? 12 : frac;
 271         frac = frac > 35 ? 35 : frac;
 272         tmp = (u64)clk_get_rate(clk->parent) * 18;
 273         do_div(tmp, frac);
 274         return tmp;
 275 }
 276
 277 static unsigned long pfd_get_rate(struct clk *clk)
 278 {
 279         u32 frac;
 280         u64 tmp;
 281         tmp = (u64)clk_get_rate(clk->parent) * 18;
 282
 283         if (apbh_dma_clk.usecount == 0)
 284                 apbh_dma_clk.enable(&apbh_dma_clk);
 285
 286         frac = (__raw_readl(clk->enable_reg) >> clk->enable_shift) &
 287                         ANADIG_PFD_FRAC_MASK;
 288
 289         do_div(tmp, frac);
 290
 291         return tmp;
 292 }
 293
 294 static int pfd_set_rate(struct clk *clk, unsigned long rate)
 295 {
 296         u32 frac;
 297         u64 tmp;
 298         tmp = (u64)clk_get_rate(clk->parent) * 18;
 299
 300         if (apbh_dma_clk.usecount == 0)
 301                 apbh_dma_clk.enable(&apbh_dma_clk);
 302
 303         /* Round up the divider so that we don't set a rate
 304           * higher than what is requested. */
 305         tmp += rate/2;
 306         do_div(tmp, rate);
 307         frac = tmp;
 308         frac = frac < 12 ? 12 : frac;
 309         frac = frac > 35 ? 35 : frac;
 310         /* clear clk frac bits */
 311         __raw_writel(ANADIG_PFD_FRAC_MASK << clk->enable_shift,
 312                         (int)clk->enable_reg + 8);
 313         /* set clk frac bits */
 314         __raw_writel(frac << clk->enable_shift,
 315                         (int)clk->enable_reg + 4);
 316
 317         tmp = (u64)clk_get_rate(clk->parent) * 18;
 318         do_div(tmp, frac);
 319
 320         if (apbh_dma_clk.usecount == 0)
 321                 apbh_dma_clk.disable(&apbh_dma_clk);
 322         return 0;
 323 }
 324
 325 static int _clk_pfd_enable(struct clk *clk)
 326 {
 327         if (apbh_dma_clk.usecount == 0)
 328                 apbh_dma_clk.enable(&apbh_dma_clk);
 329
 330         /* clear clk gate bit */
 331         __raw_writel((1 << (clk->enable_shift + 7)),
 332                         (int)clk->enable_reg + 8);
 333
 334         if (apbh_dma_clk.usecount == 0)
 335                 apbh_dma_clk.disable(&apbh_dma_clk);
 336
 337         return 0;
 338 }
 339
 340 static void _clk_pfd_disable(struct clk *clk)
 341 {
 342         if (apbh_dma_clk.usecount == 0)
 343                 apbh_dma_clk.enable(&apbh_dma_clk);
 344
 345         /* set clk gate bit */
 346         __raw_writel((1 << (clk->enable_shift + 7)),
 347                         (int)clk->enable_reg + 4);
 348
 349         if (apbh_dma_clk.usecount == 0)
 350                 apbh_dma_clk.disable(&apbh_dma_clk);
 351 }
 352
 353 static int _clk_pll_enable(struct clk *clk)
 354 {
 355         unsigned int reg;
 356         void __iomem *pllbase;
 357
 358         pllbase = _get_pll_base(clk);
 359
 360         reg = __raw_readl(pllbase);
 361         reg &= ~ANADIG_PLL_BYPASS;
 362         reg &= ~ANADIG_PLL_POWER_DOWN;
 363
 364         /* The 480MHz PLLs have the opposite definition for power bit. */
 365         if (clk == &pll3_usb_otg_main_clk || clk == &pll7_usb_host_main_clk)
 366                 reg |= ANADIG_PLL_POWER_DOWN;
 367
 368         __raw_writel(reg, pllbase);
 369
 370         /* Wait for PLL to lock */
 371         if (!WAIT(__raw_readl(pllbase) & ANADIG_PLL_LOCK,
 372                                 SPIN_DELAY))
 373                 panic("pll enable failed\n");
 374
 375         /* Enable the PLL output now*/
 376         reg = __raw_readl(pllbase);
 377         reg |= ANADIG_PLL_ENABLE;
 378         __raw_writel(reg, pllbase);
 379
 380         return 0;
 381 }
 382
 383 static void _clk_pll_disable(struct clk *clk)
 384 {
 385         unsigned int reg;
 386         void __iomem *pllbase;
 387
 388         pllbase = _get_pll_base(clk);
 389
 390         reg = __raw_readl(pllbase);
 391         reg &= ~ANADIG_PLL_ENABLE;
 392         reg |= ANADIG_PLL_BYPASS;
 393         reg |= ANADIG_PLL_POWER_DOWN;
 394
 395         /* The 480MHz PLLs, pll3 & pll7, have the opposite
 396          * definition for power bit.
 397          */
 398         if (clk == &pll3_usb_otg_main_clk || clk == &pll7_usb_host_main_clk)
 399                 reg &= ~ANADIG_PLL_POWER_DOWN;
 400         __raw_writel(reg, pllbase);
 401 }
 402
 403 static unsigned long  _clk_pll1_main_get_rate(struct clk *clk)
 404 {
 405         unsigned int div;
 406         unsigned long val;
 407
 408         div = __raw_readl(PLL1_SYS_BASE_ADDR) & ANADIG_PLL_SYS_DIV_SELECT_MASK;
 409         val = (clk_get_rate(clk->parent) * div) / 2;
 410         return val;
 411 }
 412
 413 static int _clk_pll1_main_set_rate(struct clk *clk, unsigned long rate)
 414 {
 415         unsigned int reg,  div;
 416
 417         if (rate < AUDIO_VIDEO_MIN_CLK_FREQ || rate > AUDIO_VIDEO_MAX_CLK_FREQ)
 418                 return -EINVAL;
 419
 420         div = (rate * 2) / clk_get_rate(clk->parent) ;
 421
 422         reg = __raw_readl(PLL1_SYS_BASE_ADDR) & ~ANADIG_PLL_SYS_DIV_SELECT_MASK;
 423         reg |= div;
 424         __raw_writel(reg, PLL1_SYS_BASE_ADDR);
 425
 426         return 0;
 427 }
 428
 429 static struct clk pll1_sys_main_clk = {
 430         __INIT_CLK_DEBUG(pll1_sys_main_clk)
 431         .parent = &osc_clk,
 432         .get_rate = _clk_pll1_main_get_rate,
 433         .set_rate = _clk_pll1_main_set_rate,
 434         .enable = _clk_pll_enable,
 435         .disable = _clk_pll_disable,
 436 };
 437
 438 static int _clk_pll1_sw_set_parent(struct clk *clk, struct clk *parent)
 439 {
 440         u32 reg;
 441
 442         reg = __raw_readl(MXC_CCM_CCSR);
 443
 444         if (parent == &pll1_sys_main_clk) {
 445                 reg &= ~MXC_CCM_CCSR_PLL1_SW_CLK_SEL;
 446                 __raw_writel(reg, MXC_CCM_CCSR);
 447                 /* Set the step_clk parent to be lp_apm, to save power. */
 448                 reg = __raw_readl(MXC_CCM_CCSR);
 449                 reg = (reg & ~MXC_CCM_CCSR_STEP_SEL);
 450         } else {
 451                 /* Set STEP_CLK to be the parent*/
 452                 if (parent == &osc_clk) {
 453                         /* Set STEP_CLK to be sourced from LPAPM. */
 454                         reg = __raw_readl(MXC_CCM_CCSR);
 455                         reg = (reg & ~MXC_CCM_CCSR_STEP_SEL);
 456                         __raw_writel(reg, MXC_CCM_CCSR);
 457                 } else {
 458                         /* Set STEP_CLK to be sourced from PLL2-PDF (400MHz). */
 459                         reg = __raw_readl(MXC_CCM_CCSR);
 460                         reg |= MXC_CCM_CCSR_STEP_SEL;
 461                         __raw_writel(reg, MXC_CCM_CCSR);
 462
 463                 }
 464                 reg = __raw_readl(MXC_CCM_CCSR);
 465                 reg |= MXC_CCM_CCSR_PLL1_SW_CLK_SEL;
 466                 reg = __raw_readl(MXC_CCM_CCSR);
 467         }
 468         __raw_writel(reg, MXC_CCM_CCSR);
 469
 470         return 0;
 471 }
 472
 473 static unsigned long _clk_pll1_sw_get_rate(struct clk *clk)
 474 {
 475         return clk_get_rate(clk->parent);
 476 }
 477
 478 static struct clk pll1_sw_clk = {
 479         __INIT_CLK_DEBUG(pll1_sw_clk)
 480         .parent = &pll1_sys_main_clk,
 481         .set_parent = _clk_pll1_sw_set_parent,
 482         .get_rate = _clk_pll1_sw_get_rate,
 483 };
 484
 485 static unsigned long _clk_pll2_main_get_rate(struct clk *clk)
 486 {
 487         unsigned int div;
 488         unsigned long val;
 489
 490         div = __raw_readl(PLL2_528_BASE_ADDR) & ANADIG_PLL_528_DIV_SELECT;
 491
 492         if (div == 1)
 493                 val = clk_get_rate(clk->parent) * 22;
 494
 495         else
 496                 val = clk_get_rate(clk->parent) * 20;
 497
 498         return val;
 499 }
 500
 501 static int _clk_pll2_main_set_rate(struct clk *clk, unsigned long rate)
 502 {
 503         unsigned int reg,  div;
 504
 505         if (rate == 528000000)
 506                 div = 1;
 507         else if (rate == 480000000)
 508                 div = 0;
 509         else
 510                 return -EINVAL;
 511
 512         reg = __raw_readl(PLL2_528_BASE_ADDR);
 513         reg &= ~ANADIG_PLL_528_DIV_SELECT;
 514         reg |= div;
 515         __raw_writel(reg, PLL2_528_BASE_ADDR);
 516
 517         return 0;
 518 }
 519
 520 static struct clk pll2_528_bus_main_clk = {
 521         __INIT_CLK_DEBUG(pll2_528_bus_main_clk)
 522         .parent = &osc_clk,
 523         .get_rate = _clk_pll2_main_get_rate,
 524         .set_rate = _clk_pll2_main_set_rate,
 525         .enable = _clk_pll_enable,
 526         .disable = _clk_pll_disable,
 527 };
 528
 529 static struct clk pll2_pfd_400M = {
 530         __INIT_CLK_DEBUG(pll2_pfd_400M)
 531         .parent = &pll2_528_bus_main_clk,
 532         .enable_reg = (void *)PFD_528_BASE_ADDR,
 533         .enable_shift = ANADIG_PFD2_FRAC_OFFSET,
 534         .enable = _clk_pfd_enable,
 535         .disable = _clk_pfd_disable,
 536         .get_rate = pfd_get_rate,
 537         .set_rate = pfd_set_rate,
 538         .get_rate = pfd_get_rate,
 539         .round_rate = pfd_round_rate,
 540 };
 541
 542 static struct clk pll2_pfd_352M = {
 543         __INIT_CLK_DEBUG(pll2_pfd_352M)
 544         .parent = &pll2_528_bus_main_clk,
 545         .enable_reg = (void *)PFD_528_BASE_ADDR,
 546         .enable_shift = ANADIG_PFD0_FRAC_OFFSET,
 547         .enable = _clk_pfd_enable,
 548         .disable = _clk_pfd_disable,
 549         .set_rate = pfd_set_rate,
 550         .get_rate = pfd_get_rate,
 551         .round_rate = pfd_round_rate,
 552 };
 553
 554 static struct clk pll2_pfd_594M = {
 555         __INIT_CLK_DEBUG(pll2_pfd_594M)
 556         .parent = &pll2_528_bus_main_clk,
 557         .enable_reg = (void *)PFD_528_BASE_ADDR,
 558         .enable_shift = ANADIG_PFD1_FRAC_OFFSET,
 559         .enable = _clk_pfd_enable,
 560         .disable = _clk_pfd_disable,
 561         .set_rate = pfd_set_rate,
 562         .get_rate = pfd_get_rate,
 563         .round_rate = pfd_round_rate,
 564 };
 565
 566 static unsigned long _clk_pll2_200M_get_rate(struct clk *clk)
 567 {
 568         return clk_get_rate(clk->parent) / 2;
 569 }
 570
 571 static struct clk pll2_200M = {
 572         __INIT_CLK_DEBUG(pll2_200M)
 573         .parent = &pll2_pfd_400M,
 574         .get_rate = _clk_pll2_200M_get_rate,
 575 };
 576
 577 static unsigned long _clk_pll3_usb_otg_get_rate(struct clk *clk)
 578 {
 579         unsigned int div;
 580         unsigned long val;
 581
 582         div = __raw_readl(PLL3_480_USB1_BASE_ADDR)
 583                 & ANADIG_PLL_480_DIV_SELECT_MASK;
 584
 585         if (div == 1)
 586                 val = clk_get_rate(clk->parent) * 22;
 587         else
 588                 val = clk_get_rate(clk->parent) * 20;
 589         return val;
 590 }
 591
 592 static int _clk_pll3_usb_otg_set_rate(struct clk *clk, unsigned long rate)
 593 {
 594         unsigned int reg,  div;
 595
 596         if (rate == 528000000)
 597                 div = 1;
 598         else if (rate == 480000000)
 599                 div = 0;
 600         else
 601                 return -EINVAL;
 602
 603         reg = __raw_readl(PLL3_480_USB1_BASE_ADDR);
 604         reg &= ~ANADIG_PLL_480_DIV_SELECT_MASK;
 605         reg |= div;
 606         __raw_writel(reg, PLL3_480_USB1_BASE_ADDR);
 607
 608         return 0;
 609 }
 610
 611
 612 /* same as pll3_main_clk. These two clocks should always be the same */
 613 static struct clk pll3_usb_otg_main_clk = {
 614         __INIT_CLK_DEBUG(pll3_usb_otg_main_clk)
 615         .parent = &osc_clk,
 616         .enable = _clk_pll_enable,
 617         .disable = _clk_pll_disable,
 618         .set_rate = _clk_pll3_usb_otg_set_rate,
 619         .get_rate = _clk_pll3_usb_otg_get_rate,
 620 };
 621
 622 static struct clk usb_phy1_clk = {
 623         __INIT_CLK_DEBUG(usb_phy1_clk)
 624         .parent = &pll3_usb_otg_main_clk,
 625         .set_rate = _clk_pll3_usb_otg_set_rate,
 626         .get_rate = _clk_pll3_usb_otg_get_rate,
 627 };
 628
 629 static struct clk pll3_pfd_508M = {
 630         __INIT_CLK_DEBUG(pll3_pfd_508M)
 631         .parent = &pll3_usb_otg_main_clk,
 632         .enable_reg = (void *)PFD_480_BASE_ADDR,
 633         .enable_shift = ANADIG_PFD2_FRAC_OFFSET,
 634         .enable = _clk_pfd_enable,
 635         .disable = _clk_pfd_disable,
 636         .set_rate = pfd_set_rate,
 637         .get_rate = pfd_get_rate,
 638         .round_rate = pfd_round_rate,
 639 };
 640
 641 static struct clk pll3_pfd_454M = {
 642         __INIT_CLK_DEBUG(pll3_pfd_454M)
 643         .parent = &pll3_usb_otg_main_clk,
 644         .enable_reg = (void *)PFD_480_BASE_ADDR,
 645         .enable_shift = ANADIG_PFD3_FRAC_OFFSET,
 646         .enable = _clk_pfd_enable,
 647         .disable = _clk_pfd_disable,
 648         .set_rate = pfd_set_rate,
 649         .get_rate = pfd_get_rate,
 650         .round_rate = pfd_round_rate,
 651 };
 652
 653 static struct clk pll3_pfd_720M = {
 654         __INIT_CLK_DEBUG(pll3_pfd_720M)
 655         .parent = &pll3_usb_otg_main_clk,
 656         .enable_reg = (void *)PFD_480_BASE_ADDR,
 657         .enable_shift = ANADIG_PFD0_FRAC_OFFSET,
 658         .enable = _clk_pfd_enable,
 659         .disable = _clk_pfd_disable,
 660         .set_rate = pfd_set_rate,
 661         .get_rate = pfd_get_rate,
 662         .round_rate = pfd_round_rate,
 663 };
 664
 665 static struct clk pll3_pfd_540M = {
 666         __INIT_CLK_DEBUG(pll3_pfd_540M)
 667         .parent = &pll3_usb_otg_main_clk,
 668         .enable_reg = (void *)PFD_480_BASE_ADDR,
 669         .enable_shift = ANADIG_PFD1_FRAC_OFFSET,
 670         .enable = _clk_pfd_enable,
 671         .disable = _clk_pfd_disable,
 672         .set_rate = pfd_set_rate,
 673         .get_rate = pfd_get_rate,
 674         .round_rate = pfd_round_rate,
 675         .get_rate = pfd_get_rate,
 676 };
 677
 678 static unsigned long _clk_pll3_sw_get_rate(struct clk *clk)
 679 {
 680         return clk_get_rate(clk->parent);
 681 }
 682
 683 /* same as pll3_main_clk. These two clocks should always be the same */
 684 static struct clk pll3_sw_clk = {
 685         __INIT_CLK_DEBUG(pll3_sw_clk)
 686         .parent = &pll3_usb_otg_main_clk,
 687         .get_rate = _clk_pll3_sw_get_rate,
 688 };
 689
 690 static unsigned long _clk_pll3_120M_get_rate(struct clk *clk)
 691 {
 692         return clk_get_rate(clk->parent) / 4;
 693 }
 694
 695 static struct clk pll3_120M = {
 696         __INIT_CLK_DEBUG(pll3_120M)
 697         .parent = &pll3_sw_clk,
 698         .get_rate = _clk_pll3_120M_get_rate,
 699 };
 700
 701 static unsigned long _clk_pll3_80M_get_rate(struct clk *clk)
 702 {
 703         return clk_get_rate(clk->parent) / 6;
 704 }
 705
 706 static struct clk pll3_80M = {
 707         __INIT_CLK_DEBUG(pll3_80M)
 708         .parent = &pll3_sw_clk,
 709         .get_rate = _clk_pll3_80M_get_rate,
 710 };
 711
 712 static unsigned long _clk_pll3_60M_get_rate(struct clk *clk)
 713 {
 714         return clk_get_rate(clk->parent) / 8;
 715 }
 716
 717 static struct clk pll3_60M = {
 718         __INIT_CLK_DEBUG(pll3_60M)
 719         .parent = &pll3_sw_clk,
 720         .get_rate = _clk_pll3_60M_get_rate,
 721 };
 722
 723 static unsigned long  _clk_audio_video_get_rate(struct clk *clk)
 724 {
 725         unsigned int div, mfn, mfd;
 726         unsigned long rate;
 727         unsigned int parent_rate = clk_get_rate(clk->parent);
 728         void __iomem *pllbase;
 729
 730         if (clk == &pll4_audio_main_clk)
 731                 pllbase = PLL4_AUDIO_BASE_ADDR;
 732         else
 733                 pllbase = PLL5_VIDEO_BASE_ADDR;
 734
 735         div = __raw_readl(pllbase) & ANADIG_PLL_SYS_DIV_SELECT_MASK;
 736         mfn = __raw_readl(pllbase + PLL_NUM_DIV_OFFSET);
 737         mfd = __raw_readl(pllbase + PLL_DENOM_DIV_OFFSET);
 738
 739         rate = (parent_rate * div) + ((parent_rate / mfd) * mfn);
 740
 741         return rate;
 742 }
 743
 744 static int _clk_audio_video_set_rate(struct clk *clk, unsigned long rate)
 745 {
 746         unsigned int reg,  div;
 747         unsigned int mfn, mfd = 1000000;
 748         s64 temp64;
 749         unsigned int parent_rate = clk_get_rate(clk->parent);
 750         void __iomem *pllbase;
 751
 752         if ((rate < AUDIO_VIDEO_MIN_CLK_FREQ) ||
 753                 (rate > AUDIO_VIDEO_MAX_CLK_FREQ))
 754                 return -EINVAL;
 755
 756         if (clk == &pll4_audio_main_clk)
 757                 pllbase = PLL4_AUDIO_BASE_ADDR;
 758         else
 759                 pllbase = PLL5_VIDEO_BASE_ADDR;
 760
 761         div = rate / parent_rate ;
 762         temp64 = (u64) (rate - (div * parent_rate));
 763         temp64 *= mfd;
 764         do_div(temp64, parent_rate);
 765         mfn = temp64;
 766
 767         reg = __raw_readl(pllbase) & ~ANADIG_PLL_SYS_DIV_SELECT_MASK;
 768         reg |= div;
 769         __raw_writel(reg, pllbase);
 770         __raw_writel(mfn, pllbase + PLL_NUM_DIV_OFFSET);
 771         __raw_writel(mfd, pllbase + PLL_DENOM_DIV_OFFSET);
 772
 773         return 0;
 774 }
 775
 776 static unsigned long _clk_audio_video_round_rate(struct clk *clk,
 777                                                 unsigned long rate)
 778 {
 779         if (rate < AUDIO_VIDEO_MIN_CLK_FREQ)
 780                 return AUDIO_VIDEO_MIN_CLK_FREQ;
 781
 782         if (rate > AUDIO_VIDEO_MAX_CLK_FREQ)
 783                 return AUDIO_VIDEO_MAX_CLK_FREQ;
 784
 785         return rate;
 786 }
 787
 788
 789 static struct clk pll4_audio_main_clk = {
 790         __INIT_CLK_DEBUG(pll4_audio_main_clk)
 791         .parent = &osc_clk,
 792         .enable = _clk_pll_enable,
 793         .disable = _clk_pll_disable,
 794         .set_rate = _clk_audio_video_set_rate,
 795         .get_rate = _clk_audio_video_get_rate,
 796         .round_rate = _clk_audio_video_round_rate,
 797 };
 798
 799
 800 static struct clk pll5_video_main_clk = {
 801         __INIT_CLK_DEBUG(pll5_video_main_clk)
 802         .parent = &osc_clk,
 803         .enable = _clk_pll_enable,
 804         .disable = _clk_pll_disable,
 805         .set_rate = _clk_audio_video_set_rate,
 806         .get_rate = _clk_audio_video_get_rate,
 807         .round_rate = _clk_audio_video_round_rate,
 808 };
 809
 810 static struct clk pll6_MLB_main_clk = {
 811         __INIT_CLK_DEBUG(pll6_MLB_main_clk)
 812         .parent = &osc_clk,
 813         .enable = _clk_pll_enable,
 814         .disable = _clk_pll_disable,
 815 };
 816
 817 static unsigned long _clk_pll7_usb_otg_get_rate(struct clk *clk)
 818 {
 819         unsigned int div;
 820         unsigned long val;
 821
 822         div = __raw_readl(PLL7_480_USB2_BASE_ADDR)
 823                 & ANADIG_PLL_480_DIV_SELECT_MASK;
 824
 825         if (div == 1)
 826                 val = clk_get_rate(clk->parent) * 22;
 827         else
 828                 val = clk_get_rate(clk->parent) * 20;
 829         return val;
 830 }
 831
 832 static int _clk_pll7_usb_otg_set_rate(struct clk *clk, unsigned long rate)
 833 {
 834         unsigned int reg,  div;
 835
 836         if (rate == 528000000)
 837                 div = 1;
 838         else if (rate == 480000000)
 839                 div = 0;
 840         else
 841                 return -EINVAL;
 842
 843         reg = __raw_readl(PLL7_480_USB2_BASE_ADDR);
 844         reg &= ~ANADIG_PLL_480_DIV_SELECT_MASK;
 845         reg |= div;
 846         __raw_writel(reg, PLL7_480_USB2_BASE_ADDR);
 847
 848         return 0;
 849 }
 850
 851 static struct clk pll7_usb_host_main_clk = {
 852         __INIT_CLK_DEBUG(pll7_usb_host_main_clk)
 853         .parent = &osc_clk,
 854         .enable = _clk_pll_enable,
 855         .disable = _clk_pll_disable,
 856         .set_rate = _clk_pll7_usb_otg_set_rate,
 857         .get_rate = _clk_pll7_usb_otg_get_rate,
 858
 859 };
 860
 861 static struct clk pll8_enet_main_clk = {
 862         __INIT_CLK_DEBUG(pll8_enet_main_clk)
 863         .parent = &osc_clk,
 864         .enable = _clk_pll_enable,
 865         .disable = _clk_pll_disable,
 866 };
 867
 868 static unsigned long _clk_arm_get_rate(struct clk *clk)
 869 {
 870         u32 cacrr, div;
 871
 872         cacrr = __raw_readl(MXC_CCM_CACRR);
 873         div = (cacrr & MXC_CCM_CACRR_ARM_PODF_MASK) + 1;
 874         return clk_get_rate(clk->parent) / div;
 875 }
 876
 877 static int _clk_arm_set_rate(struct clk *clk, unsigned long rate)
 878 {
 879         int i;
 880         u32 div;
 881         u32 parent_rate;
 882
 883
 884         for (i = 0; i < cpu_op_nr; i++) {
 885                 if (rate == cpu_op_tbl[i].cpu_rate)
 886                         break;
 887         }
 888         if (i >= cpu_op_nr)
 889                 return -EINVAL;
 890
 891         if (cpu_op_tbl[i].pll_rate != clk_get_rate(&pll1_sys_main_clk)) {
 892                 /* Change the PLL1 rate. */
 893                 if (pll2_pfd_400M.usecount != 0)
 894                         pll1_sw_clk.set_parent(&pll1_sw_clk, &pll2_pfd_400M);
 895                 else
 896                         pll1_sw_clk.set_parent(&pll1_sw_clk, &osc_clk);
 897                 pll1_sys_main_clk.set_rate(&pll1_sys_main_clk, cpu_op_tbl[i].pll_rate);
 898                 pll1_sw_clk.set_parent(&pll1_sw_clk, &pll1_sys_main_clk);
 899         }
 900
 901         parent_rate = clk_get_rate(clk->parent);
 902         div = parent_rate / rate;
 903
 904         if (div == 0)
 905                 div = 1;
 906
 907         if ((parent_rate / div) > rate)
 908                 div++;
 909
 910         if (div > 8)
 911                 return -1;
 912
 913         __raw_writel(div - 1, MXC_CCM_CACRR);
 914
 915         return 0;
 916 }
 917
 918 static struct clk cpu_clk = {
 919         __INIT_CLK_DEBUG(cpu_clk)
 920         .parent = &pll1_sw_clk,
 921         .set_rate = _clk_arm_set_rate,
 922         .get_rate = _clk_arm_get_rate,
 923 };
 924
 925 static int _clk_periph_set_parent(struct clk *clk, struct clk *parent)
 926 {
 927         u32 reg;
 928         int mux;
 929
 930         mux = _get_mux6(parent, &pll2_528_bus_main_clk, &pll2_pfd_400M,
 931                 &pll2_pfd_352M, &pll2_200M, &pll3_sw_clk, &osc_clk);
 932
 933         if (mux <= 3) {
 934                 /* Set the pre_periph_clk multiplexer */
 935                 reg = __raw_readl(MXC_CCM_CBCMR);
 936                 reg &= ~MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK;
 937                 reg |= mux << MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET;
 938                 __raw_writel(reg, MXC_CCM_CBCMR);
 939
 940                 /* Set the periph_clk_sel multiplexer. */
 941                 reg = __raw_readl(MXC_CCM_CBCDR);
 942                 reg &= ~MXC_CCM_CBCDR_PERIPH_CLK_SEL;
 943                 __raw_writel(reg, MXC_CCM_CBCDR);
 944         } else {
 945                 reg = __raw_readl(MXC_CCM_CBCDR);
 946                 /* Set the periph_clk2_podf divider to divide by 1. */
 947                 reg &= ~MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK;
 948                 __raw_writel(reg, MXC_CCM_CBCDR);
 949
 950                 /* Set the periph_clk2_sel mux. */
 951                 reg = __raw_readl(MXC_CCM_CBCMR);
 952                 reg &= ~MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK;
 953                 reg |= ((mux - 4) << MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET);
 954                 __raw_writel(reg, MXC_CCM_CBCMR);
 955
 956                 reg = __raw_readl(MXC_CCM_CBCDR);
 957                 /* Set periph_clk_sel to select periph_clk2. */
 958                 reg |= MXC_CCM_CBCDR_PERIPH_CLK_SEL;
 959                 __raw_writel(reg, MXC_CCM_CBCDR);
 960         }
 961
 962         if (!WAIT(!(__raw_readl(MXC_CCM_CDHIPR)
 963              & MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY), SPIN_DELAY))
 964                 panic("_clk_periph_set_parent failed\n");
 965
 966         return 0;
 967 }
 968
 969 static unsigned long _clk_periph_get_rate(struct clk *clk)
 970 {
 971         u32 div = 1;
 972         u32 reg;
 973         unsigned long val;
 974
 975         if ((clk->parent == &pll3_sw_clk) || (clk->parent == &osc_clk)) {
 976                 reg = __raw_readl(MXC_CCM_CBCDR)
 977                         & MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK;
 978                 div = (reg >> MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET) + 1;
 979         }
 980         val = clk_get_rate(clk->parent) / div;
 981         return val;
 982 }
 983
 984 static struct clk periph_clk = {
 985         __INIT_CLK_DEBUG(periph_clk)
 986         .parent = &pll2_528_bus_main_clk,
 987         .set_parent = _clk_periph_set_parent,
 988         .get_rate = _clk_periph_get_rate,
 989 };
 990
 991 static unsigned long _clk_axi_get_rate(struct clk *clk)
 992 {
 993         u32 div, reg;
 994         unsigned long val;
 995
 996         reg = __raw_readl(MXC_CCM_CBCDR) & MXC_CCM_CBCDR_AXI_PODF_MASK;
 997         div = (reg >> MXC_CCM_CBCDR_AXI_PODF_OFFSET);
 998
 999         val = clk_get_rate(clk->parent) / (div + 1);
1000         return val;
1001 }
1002
1003 static int _clk_axi_set_rate(struct clk *clk, unsigned long rate)
1004 {
1005         u32 reg, div;
1006         u32 parent_rate = clk_get_rate(clk->parent);
1007
1008         div = parent_rate / rate;
1009
1010         if (div == 0)
1011                 div++;
1012         if (((parent_rate / div) != rate) || (div > 8))
1013                 return -EINVAL;
1014
1015         reg = __raw_readl(MXC_CCM_CBCDR);
1016         reg &= ~MXC_CCM_CBCDR_AXI_PODF_MASK;
1017         reg |= (div - 1) << MXC_CCM_CBCDR_AXI_PODF_OFFSET;
1018         __raw_writel(reg, MXC_CCM_CBCDR);
1019
1020         if (!WAIT(!(__raw_readl(MXC_CCM_CDHIPR)
1021              & MXC_CCM_CDHIPR_AXI_PODF_BUSY), SPIN_DELAY))
1022                 panic("pll _clk_axi_a_set_rate failed\n");
1023
1024         return 0;
1025 }
1026
1027 static unsigned long _clk_axi_round_rate(struct clk *clk,
1028                                                 unsigned long rate)
1029 {
1030         u32 div;
1031         u32 parent_rate = clk_get_rate(clk->parent);
1032
1033         div = parent_rate / rate;
1034
1035         /* Make sure rate is not greater than the maximum
1036          * value for the clock.
1037          * Also prevent a div of 0.
1038          */
1039
1040         if (div > 8)
1041                 div = 8;
1042         else if (div == 0)
1043                 div++;
1044
1045         return parent_rate / div;
1046 }
1047
1048 static int _clk_axi_set_parent(struct clk *clk, struct clk *parent)
1049 {
1050         u32 reg;
1051         int mux;
1052
1053         mux = _get_mux6(parent, &periph_clk, &pll2_pfd_400M,
1054                                 &pll3_pfd_540M, NULL, NULL, NULL);
1055
1056         if (mux == 0) {
1057                 /* Set the AXI_SEL mux */
1058                 reg = __raw_readl(MXC_CCM_CBCDR) & ~MXC_CCM_CBCDR_AXI_SEL;
1059                 __raw_writel(reg, MXC_CCM_CBCDR);
1060         } else {
1061                 /* Set the AXI_ALT_SEL mux. */
1062                 reg = __raw_readl(MXC_CCM_CBCDR)
1063                         & ~MXC_CCM_CBCDR_AXI_ALT_SEL_MASK;
1064                 reg = ((mux - 1) << MXC_CCM_CBCDR_AXI_ALT_SEL_OFFSET);
1065                 __raw_writel(reg, MXC_CCM_CBCDR);
1066
1067                 /* Set the AXI_SEL mux */
1068                 reg = __raw_readl(MXC_CCM_CBCDR) & ~MXC_CCM_CBCDR_AXI_SEL;
1069                 reg |= MXC_CCM_CBCDR_AXI_SEL;
1070                 __raw_writel(reg, MXC_CCM_CBCDR);
1071         }
1072         return 0;
1073 }
1074
1075 static struct clk axi_clk = {
1076         __INIT_CLK_DEBUG(axi_clk)
1077         .parent = &periph_clk,
1078         .set_parent = _clk_axi_set_parent,
1079         .set_rate = _clk_axi_set_rate,
1080         .get_rate = _clk_axi_get_rate,
1081         .round_rate = _clk_axi_round_rate,
1082 };
1083
1084 static unsigned long _clk_ahb_get_rate(struct clk *clk)
1085 {
1086         u32 reg, div;
1087
1088         reg = __raw_readl(MXC_CCM_CBCDR);
1089         div = ((reg & MXC_CCM_CBCDR_AHB_PODF_MASK) >>
1090                MXC_CCM_CBCDR_AHB_PODF_OFFSET) + 1;
1091
1092         return clk_get_rate(clk->parent) / div;
1093 }
1094
1095 static int _clk_ahb_set_rate(struct clk *clk, unsigned long rate)
1096 {
1097         u32 reg, div;
1098         u32 parent_rate = clk_get_rate(clk->parent);
1099
1100         div = parent_rate / rate;
1101         if (div == 0)
1102                 div++;
1103         if (((parent_rate / div) != rate) || (div > 8))
1104                 return -EINVAL;
1105
1106         reg = __raw_readl(MXC_CCM_CBCDR);
1107         reg &= ~MXC_CCM_CBCDR_AHB_PODF_MASK;
1108         reg |= (div - 1) << MXC_CCM_CBCDR_AHB_PODF_OFFSET;
1109         __raw_writel(reg, MXC_CCM_CBCDR);
1110
1111         if (!WAIT(!(__raw_readl(MXC_CCM_CDHIPR) & MXC_CCM_CDHIPR_AHB_PODF_BUSY),
1112                                 SPIN_DELAY))
1113                         panic("_clk_ahb_set_rate failed\n");
1114
1115         return 0;
1116 }
1117
1118 static unsigned long _clk_ahb_round_rate(struct clk *clk,
1119                                                 unsigned long rate)
1120 {
1121         u32 div;
1122         u32 parent_rate = clk_get_rate(clk->parent);
1123
1124         div = parent_rate / rate;
1125
1126         /* Make sure rate is not greater than the maximum value for the clock.
1127          * Also prevent a div of 0.
1128          */
1129         if (div == 0)
1130                 div++;
1131
1132         if (div > 8)
1133                 div = 8;
1134
1135         return parent_rate / div;
1136 }
1137
1138 static struct clk ahb_clk = {
1139         __INIT_CLK_DEBUG(ahb_clk)
1140         .parent = &periph_clk,
1141         .get_rate = _clk_ahb_get_rate,
1142         .set_rate = _clk_ahb_set_rate,
1143         .round_rate = _clk_ahb_round_rate,
1144 };
1145
1146 static unsigned long _clk_ipg_get_rate(struct clk *clk)
1147 {
1148         u32 reg, div;
1149
1150         reg = __raw_readl(MXC_CCM_CBCDR);
1151         div = ((reg & MXC_CCM_CBCDR_IPG_PODF_MASK) >>
1152                 MXC_CCM_CBCDR_IPG_PODF_OFFSET) + 1;
1153
1154         return clk_get_rate(clk->parent) / div;
1155 }
1156
1157
1158 static struct clk ipg_clk = {
1159         __INIT_CLK_DEBUG(ipg_clk)
1160         .parent = &ahb_clk,
1161         .get_rate = _clk_ipg_get_rate,
1162 };
1163
1164 static unsigned long _clk_mmdc_ch0_axi_get_rate(struct clk *clk)
1165 {
1166         u32 reg, div;
1167
1168         reg = __raw_readl(MXC_CCM_CBCDR);
1169         div = ((reg & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
1170                         MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET) + 1;
1171
1172         return clk_get_rate(clk->parent) / div;
1173 }
1174
1175 static int _clk_mmdc_ch0_axi_set_rate(struct clk *clk, unsigned long rate)
1176 {
1177         u32 reg, div;
1178         u32 parent_rate = clk_get_rate(clk->parent);
1179
1180         div = parent_rate / rate;
1181         if (div == 0)
1182                 div++;
1183         if (((parent_rate / div) != rate) || (div > 8))
1184                 return -EINVAL;
1185
1186         reg = __raw_readl(MXC_CCM_CBCDR);
1187         reg &= ~MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK;
1188         reg |= (div - 1) << MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
1189         __raw_writel(reg, MXC_CCM_CBCDR);
1190
1191         if (!WAIT(!(__raw_readl(MXC_CCM_CDHIPR)
1192                 & MXC_CCM_CDHIPR_MMDC_CH0_PODF_BUSY),
1193                                 SPIN_DELAY))
1194                         panic("_clk_mmdc_ch0_axi_set_rate failed\n");
1195
1196         return 0;
1197 }
1198
1199 static unsigned long _clk_mmdc_ch0_axi_round_rate(struct clk *clk,
1200                                                 unsigned long rate)
1201 {
1202         u32 div;
1203         u32 parent_rate = clk_get_rate(clk->parent);
1204
1205         div = parent_rate / rate;
1206
1207         /* Make sure rate is not greater than the maximum value for the clock.
1208          * Also prevent a div of 0.
1209          */
1210         if (div == 0)
1211                 div++;
1212
1213         if (div > 8)
1214                 div = 8;
1215
1216         return parent_rate / div;
1217 }
1218
1219 static struct clk mmdc_ch0_axi_clk[] = {
1220         {
1221         __INIT_CLK_DEBUG(mmdc_ch0_axi_clk)
1222         .id = 0,
1223         .parent = &periph_clk,
1224         .enable = _clk_enable,
1225         .disable = _clk_disable,
1226         .enable_reg = MXC_CCM_CCGR3,
1227         .enable_shift = MXC_CCM_CCGRx_CG10_OFFSET,
1228         .secondary = &mmdc_ch0_axi_clk[1],
1229         .get_rate = _clk_mmdc_ch0_axi_get_rate,
1230         .set_rate = _clk_mmdc_ch0_axi_set_rate,
1231         .round_rate = _clk_mmdc_ch0_axi_round_rate,
1232         },
1233         {
1234         __INIT_CLK_DEBUG(mmdc_ch0_ipg_clk)
1235         .id = 0,
1236         .parent = &ipg_clk,
1237         .enable = _clk_enable,
1238         .disable = _clk_disable,
1239         .enable_reg = MXC_CCM_CCGR3,
1240         .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET,
1241         },
1242 };
1243
1244 static unsigned long _clk_mmdc_ch1_axi_get_rate(struct clk *clk)
1245 {
1246         u32 reg, div;
1247
1248         reg = __raw_readl(MXC_CCM_CBCDR);
1249         div = ((reg & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) >>
1250                         MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET) + 1;
1251
1252         return clk_get_rate(clk->parent) / div;
1253 }
1254
1255 static int _clk_mmdc_ch1_axi_set_rate(struct clk *clk, unsigned long rate)
1256 {
1257         u32 reg, div;
1258         u32 parent_rate = clk_get_rate(clk->parent);
1259
1260         div = parent_rate / rate;
1261         if (div == 0)
1262                 div++;
1263         if (((parent_rate / div) != rate) || (div > 8))
1264                 return -EINVAL;
1265
1266         reg = __raw_readl(MXC_CCM_CBCDR);
1267         reg &= ~MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK;
1268         reg |= (div - 1) << MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
1269         __raw_writel(reg, MXC_CCM_CBCDR);
1270
1271         if (!WAIT(!(__raw_readl(MXC_CCM_CDHIPR)
1272                 & MXC_CCM_CDHIPR_MMDC_CH1_PODF_BUSY), SPIN_DELAY))
1273                         panic("_clk_mmdc_ch1_axi_set_rate failed\n");
1274
1275         return 0;
1276 }
1277
1278 static unsigned long _clk_mmdc_ch1_axi_round_rate(struct clk *clk,
1279                                                 unsigned long rate)
1280 {
1281         u32 div;
1282         u32 parent_rate = clk_get_rate(clk->parent);
1283
1284         div = parent_rate / rate;
1285
1286         /* Make sure rate is not greater than the maximum value for the clock.
1287          * Also prevent a div of 0.
1288          */
1289         if (div == 0)
1290                 div++;
1291
1292         if (div > 8)
1293                 div = 8;
1294
1295         return parent_rate / div;
1296 }
1297
1298 static struct clk mmdc_ch1_axi_clk[] = {
1299         {
1300         __INIT_CLK_DEBUG(mmdc_ch1_axi_clk)
1301         .id = 0,
1302         .parent = &pll2_pfd_400M,
1303         .enable = _clk_enable,
1304         .disable = _clk_disable,
1305         .enable_reg = MXC_CCM_CCGR3,
1306         .enable_shift = MXC_CCM_CCGRx_CG11_OFFSET,
1307         .secondary = &mmdc_ch1_axi_clk[1],
1308         .get_rate = _clk_mmdc_ch1_axi_get_rate,
1309         .set_rate = _clk_mmdc_ch1_axi_set_rate,
1310         .round_rate = _clk_mmdc_ch1_axi_round_rate,
1311         },
1312         {
1313         .id = 1,
1314         __INIT_CLK_DEBUG(mmdc_ch1_ipg_clk)
1315         .parent = &ipg_clk,
1316         .enable = _clk_enable,
1317         .disable = _clk_disable,
1318         .enable_reg = MXC_CCM_CCGR3,
1319         .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
1320         },
1321 };
1322
1323 static unsigned long _clk_ipg_perclk_get_rate(struct clk *clk)
1324 {
1325         u32 reg, div;
1326
1327         reg = __raw_readl(MXC_CCM_CSCMR1);
1328         div = ((reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK) >>
1329                         MXC_CCM_CSCMR1_PERCLK_PODF_OFFSET) + 1;
1330
1331         return clk_get_rate(clk->parent) / div;
1332 }
1333
1334 static int _clk_ipg_perclk_set_rate(struct clk *clk, unsigned long rate)
1335 {
1336         u32 reg, div;
1337         u32 parent_rate = clk_get_rate(clk->parent);
1338
1339         div = parent_rate / rate;
1340         if (div == 0)
1341                 div++;
1342         if (((parent_rate / div) != rate) || (div > 64))
1343                 return -EINVAL;
1344
1345         reg = __raw_readl(MXC_CCM_CSCMR1);
1346         reg &= ~MXC_CCM_CSCMR1_PERCLK_PODF_MASK;
1347         reg |= (div - 1) << MXC_CCM_CSCMR1_PERCLK_PODF_OFFSET;
1348         __raw_writel(reg, MXC_CCM_CSCMR1);
1349
1350         return 0;
1351 }
1352
1353
1354 static unsigned long _clk_ipg_perclk_round_rate(struct clk *clk,
1355                                                 unsigned long rate)
1356 {
1357         u32 div;
1358         u32 parent_rate = clk_get_rate(clk->parent);
1359
1360         div = parent_rate / rate;
1361
1362         /* Make sure rate is not greater than the maximum value for the clock.
1363          * Also prevent a div of 0.
1364          */
1365         if (div == 0)
1366                 div++;
1367
1368         if (div > 64)
1369                 div = 64;
1370
1371         return parent_rate / div;
1372 }
1373
1374 static struct clk ipg_perclk = {
1375         __INIT_CLK_DEBUG(ipg_perclk)
1376         .parent = &ipg_clk,
1377         .get_rate = _clk_ipg_perclk_get_rate,
1378         .set_rate = _clk_ipg_perclk_set_rate,
1379         .round_rate = _clk_ipg_perclk_round_rate,
1380 };
1381
1382 static struct clk spba_clk = {
1383         __INIT_CLK_DEBUG(spba_clk)
1384         .parent = &ipg_clk,
1385         .enable_reg = MXC_CCM_CCGR5,
1386         .enable_shift = MXC_CCM_CCGRx_CG6_OFFSET,
1387         .enable = _clk_enable,
1388         .disable = _clk_disable,
1389 };
1390
1391 static struct clk sdma_clk = {
1392          __INIT_CLK_DEBUG(sdma_clk)
1393          .parent = &ahb_clk,
1394          .enable_reg = MXC_CCM_CCGR5,
1395          .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET,
1396          .enable = _clk_enable,
1397          .disable = _clk_disable,
1398 };
1399
1400 static int _clk_gpu2d_axi_set_parent(struct clk *clk, struct clk *parent)
1401 {
1402         u32 reg = __raw_readl(MXC_CCM_CBCMR) & ~MXC_CCM_CBCMR_GPU2D_AXI_CLK_SEL;
1403
1404         if (parent == &ahb_clk)
1405                 reg |= MXC_CCM_CBCMR_GPU2D_AXI_CLK_SEL;
1406
1407         __raw_writel(reg, MXC_CCM_CBCMR);
1408
1409         return 0;
1410 }
1411
1412 static struct clk gpu2d_axi_clk = {
1413         __INIT_CLK_DEBUG(gpu2d_axi_clk)
1414         .parent = &axi_clk,
1415         .secondary = &openvg_axi_clk,
1416         .set_parent = _clk_gpu2d_axi_set_parent,
1417 };
1418
1419 static int _clk_gpu3d_axi_set_parent(struct clk *clk, struct clk *parent)
1420 {
1421         u32 reg = __raw_readl(MXC_CCM_CBCMR) & ~MXC_CCM_CBCMR_GPU3D_AXI_CLK_SEL;
1422
1423         if (parent == &ahb_clk)
1424                 reg |= MXC_CCM_CBCMR_GPU3D_AXI_CLK_SEL;
1425
1426         __raw_writel(reg, MXC_CCM_CBCMR);
1427
1428         return 0;
1429 }
1430
1431 static struct clk gpu3d_axi_clk = {
1432         __INIT_CLK_DEBUG(gpu3d_axi_clk)
1433         .parent = &axi_clk,
1434         .set_parent = _clk_gpu3d_axi_set_parent,
1435 };
1436
1437 static int _clk_pcie_axi_set_parent(struct clk *clk, struct clk *parent)
1438 {
1439         u32 reg = __raw_readl(MXC_CCM_CBCMR) & ~MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL;
1440
1441         if (parent == &ahb_clk)
1442                 reg |= MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL;
1443
1444         __raw_writel(reg, MXC_CCM_CBCMR);
1445
1446         return 0;
1447 }
1448
1449 static struct clk pcie_axi_clk = {
1450         __INIT_CLK_DEBUG(pcie_axi_clk)
1451         .parent = &axi_clk,
1452         .set_parent = _clk_pcie_axi_set_parent,
1453 };
1454
1455 static int _clk_vdo_axi_set_parent(struct clk *clk, struct clk *parent)
1456 {
1457         u32 reg = __raw_readl(MXC_CCM_CBCMR) & ~MXC_CCM_CBCMR_VDOAXI_CLK_SEL;
1458
1459         if (parent == &ahb_clk)
1460                 reg |= MXC_CCM_CBCMR_VDOAXI_CLK_SEL;
1461
1462         __raw_writel(reg, MXC_CCM_CBCMR);
1463
1464         return 0;
1465 }
1466
1467 static struct clk vdo_axi_clk = {
1468         __INIT_CLK_DEBUG(vdo_axi_clk)
1469         .parent = &axi_clk,
1470         .enable_reg = MXC_CCM_CCGR6,
1471         .enable_shift = MXC_CCM_CCGRx_CG6_OFFSET,
1472         .enable = _clk_enable,
1473         .disable = _clk_disable,
1474         .set_parent = _clk_vdo_axi_set_parent,
1475 };
1476
1477 static struct clk vdoa_clk = {
1478         __INIT_CLK_DEBUG(vdoa_clk)
1479         .id = 0,
1480         .parent = &axi_clk,
1481         .enable_reg = MXC_CCM_CCGR2,
1482         .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
1483         .enable = _clk_enable,
1484         .disable = _clk_disable,
1485 };
1486
1487 static struct clk gpt_clk[] = {
1488         {
1489         __INIT_CLK_DEBUG(gpt_clk)
1490          .parent = &ipg_perclk,
1491          .id = 0,
1492          .enable_reg = MXC_CCM_CCGR1,
1493          .enable_shift = MXC_CCM_CCGRx_CG10_OFFSET,
1494          .enable = _clk_enable,
1495          .disable = _clk_disable,
1496          .secondary = &gpt_clk[1],
1497          },
1498         {
1499         __INIT_CLK_DEBUG(gpt_serial_clk)
1500          .id = 0,
1501          .enable_reg = MXC_CCM_CCGR1,
1502          .enable_shift = MXC_CCM_CCGRx_CG11_OFFSET,
1503          .enable = _clk_enable,
1504          .disable = _clk_disable,
1505          },
1506 };
1507
1508 static struct clk iim_clk = {
1509         __INIT_CLK_DEBUG(iim_clk)
1510         .parent = &ipg_clk,
1511         .enable = _clk_enable,
1512         .enable_reg = MXC_CCM_CCGR2,
1513         .enable_shift = MXC_CCM_CCGRx_CG6_OFFSET,
1514         .disable = _clk_disable,
1515 };
1516
1517 static struct clk i2c_clk[] = {
1518         {
1519         __INIT_CLK_DEBUG(i2c_clk_0)
1520          .id = 0,
1521          .parent = &ipg_perclk,
1522          .enable_reg = MXC_CCM_CCGR2,
1523          .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET,
1524          .enable = _clk_enable,
1525          .disable = _clk_disable,
1526          },
1527         {
1528         __INIT_CLK_DEBUG(i2c_clk_1)
1529          .id = 1,
1530          .parent = &ipg_perclk,
1531          .enable_reg = MXC_CCM_CCGR2,
1532          .enable_shift = MXC_CCM_CCGRx_CG4_OFFSET,
1533          .enable = _clk_enable,
1534          .disable = _clk_disable,
1535          },
1536         {
1537         __INIT_CLK_DEBUG(i2c_clk_2)
1538          .id = 2,
1539          .parent = &ipg_perclk,
1540          .enable_reg = MXC_CCM_CCGR2,
1541          .enable_shift = MXC_CCM_CCGRx_CG5_OFFSET,
1542          .enable = _clk_enable,
1543          .disable = _clk_disable,
1544          },
1545 };
1546
1547 static int _clk_vpu_axi_set_parent(struct clk *clk, struct clk *parent)
1548 {
1549         int mux;
1550         u32 reg = __raw_readl(MXC_CCM_CBCMR)
1551                 & ~MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK;
1552
1553         mux = _get_mux6(parent, &axi_clk, &pll2_pfd_400M,
1554                 &pll2_pfd_352M, NULL, NULL, NULL);
1555
1556         reg |= (mux << MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET);
1557
1558         __raw_writel(reg, MXC_CCM_CBCMR);
1559
1560         return 0;
1561 }
1562
1563 static unsigned long _clk_vpu_axi_get_rate(struct clk *clk)
1564 {
1565         u32 reg, div;
1566
1567         reg = __raw_readl(MXC_CCM_CSCDR1);
1568         div = ((reg & MXC_CCM_CSCDR1_VPU_AXI_PODF_MASK) >>
1569                         MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET) + 1;
1570
1571         return clk_get_rate(clk->parent) / div;
1572 }
1573
1574 static int _clk_vpu_axi_set_rate(struct clk *clk, unsigned long rate)
1575 {
1576         u32 reg, div;
1577         u32 parent_rate = clk_get_rate(clk->parent);
1578
1579         div = parent_rate / rate;
1580         if (div == 0)
1581                 div++;
1582         if (((parent_rate / div) != rate) || (div > 8))
1583                 return -EINVAL;
1584
1585         reg = __raw_readl(MXC_CCM_CSCDR1);
1586         reg &= ~MXC_CCM_CSCDR1_VPU_AXI_PODF_MASK;
1587         reg |= (div - 1) << MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET;
1588         __raw_writel(reg, MXC_CCM_CSCDR1);
1589
1590         return 0;
1591 }
1592
1593 static unsigned long _clk_vpu_axi_round_rate(struct clk *clk,
1594                                                 unsigned long rate)
1595 {
1596         u32 div;
1597         u32 parent_rate = clk_get_rate(clk->parent);
1598
1599         div = parent_rate / rate;
1600
1601         /* Make sure rate is not greater than the maximum value for the clock.
1602          * Also prevent a div of 0.
1603          */
1604         if (div == 0)
1605                 div++;
1606
1607         if (div > 8)
1608                 div = 8;
1609
1610         return parent_rate / div;
1611 }
1612
1613 static struct clk vpu_clk = {
1614         __INIT_CLK_DEBUG(vpu_clk)
1615         .parent = &axi_clk,
1616         .enable_reg = MXC_CCM_CCGR6,
1617         .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
1618         .enable = _clk_enable,
1619         .disable = _clk_disable,
1620         .set_parent = _clk_vpu_axi_set_parent,
1621         .round_rate = _clk_vpu_axi_round_rate,
1622         .set_rate = _clk_vpu_axi_set_rate,
1623         .get_rate = _clk_vpu_axi_get_rate,
1624 };
1625
1626 static int _clk_ipu1_set_parent(struct clk *clk, struct clk *parent)
1627 {
1628         int mux;
1629         u32 reg = __raw_readl(MXC_CCM_CSCDR3)
1630                 & ~MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_MASK;
1631
1632         mux = _get_mux6(parent, &mmdc_ch0_axi_clk[0],
1633                 &pll2_pfd_400M, &pll3_120M, &pll3_pfd_540M, NULL, NULL);
1634
1635         reg |= (mux << MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_OFFSET);
1636
1637         __raw_writel(reg, MXC_CCM_CSCDR3);
1638
1639         return 0;
1640 }
1641
1642 static unsigned long _clk_ipu1_get_rate(struct clk *clk)
1643 {
1644         u32 reg, div;
1645
1646         reg = __raw_readl(MXC_CCM_CSCDR3);
1647         div = ((reg & MXC_CCM_CSCDR3_IPU1_HSP_PODF_MASK) >>
1648                         MXC_CCM_CSCDR3_IPU1_HSP_PODF_OFFSET) + 1;
1649
1650         return clk_get_rate(clk->parent) / div;
1651 }
1652
1653 static int _clk_ipu1_set_rate(struct clk *clk, unsigned long rate)
1654 {
1655         u32 reg, div;
1656         u32 parent_rate = clk_get_rate(clk->parent);
1657
1658         div = parent_rate / rate;
1659         if (div == 0)
1660                 div++;
1661         if (((parent_rate / div) != rate) || (div > 8))
1662                 return -EINVAL;
1663
1664         reg = __raw_readl(MXC_CCM_CSCDR3);
1665         reg &= ~MXC_CCM_CSCDR3_IPU1_HSP_PODF_MASK;
1666         reg |= (div - 1) << MXC_CCM_CSCDR3_IPU1_HSP_PODF_OFFSET;
1667         __raw_writel(reg, MXC_CCM_CSCDR3);
1668
1669         return 0;
1670 }
1671
1672 static unsigned long _clk_ipu_round_rate(struct clk *clk,
1673                                                 unsigned long rate)
1674 {
1675         u32 div;
1676         u32 parent_rate = clk_get_rate(clk->parent);
1677
1678         div = parent_rate / rate;
1679
1680         /* Make sure rate is not greater than the maximum value for the clock.
1681          * Also prevent a div of 0.
1682          */
1683         if (div == 0)
1684                 div++;
1685
1686         if (div > 8)
1687                 div = 8;
1688
1689         return parent_rate / div;
1690 }
1691
1692 static struct clk ipu1_clk = {
1693         __INIT_CLK_DEBUG(ipu1_clk)
1694         .parent = &mmdc_ch0_axi_clk[0],
1695         .enable_reg = MXC_CCM_CCGR3,
1696         .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET,
1697         .enable = _clk_enable,
1698         .disable = _clk_disable,
1699         .set_parent = _clk_ipu1_set_parent,
1700         .round_rate = _clk_ipu_round_rate,
1701         .set_rate = _clk_ipu1_set_rate,
1702         .get_rate = _clk_ipu1_get_rate,
1703 };
1704
1705 static int _clk_ipu2_set_parent(struct clk *clk, struct clk *parent)
1706 {
1707         int mux;
1708         u32 reg = __raw_readl(MXC_CCM_CSCDR3)
1709                 & ~MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_MASK;
1710
1711         mux = _get_mux6(parent, &mmdc_ch0_axi_clk[0],
1712                 &pll2_pfd_400M, &pll3_120M, &pll3_pfd_540M, NULL, NULL);
1713
1714         reg |= (mux << MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_OFFSET);
1715
1716         __raw_writel(reg, MXC_CCM_CSCDR3);
1717
1718         return 0;
1719 }
1720
1721 static unsigned long _clk_ipu2_get_rate(struct clk *clk)
1722 {
1723         u32 reg, div;
1724
1725         reg = __raw_readl(MXC_CCM_CSCDR3);
1726         div = ((reg & MXC_CCM_CSCDR3_IPU2_HSP_PODF_MASK) >>
1727                         MXC_CCM_CSCDR3_IPU2_HSP_PODF_OFFSET) + 1;
1728
1729         return clk_get_rate(clk->parent) / div;
1730 }
1731
1732 static int _clk_ipu2_set_rate(struct clk *clk, unsigned long rate)
1733 {
1734         u32 reg, div;
1735         u32 parent_rate = clk_get_rate(clk->parent);
1736
1737         div = parent_rate / rate;
1738         if (div == 0)
1739                 div++;
1740         if (((parent_rate / div) != rate) || (div > 8))
1741                 return -EINVAL;
1742
1743         reg = __raw_readl(MXC_CCM_CSCDR3);
1744         reg &= ~MXC_CCM_CSCDR3_IPU2_HSP_PODF_MASK;
1745         reg |= (div - 1) << MXC_CCM_CSCDR3_IPU2_HSP_PODF_OFFSET;
1746         __raw_writel(reg, MXC_CCM_CSCDR3);
1747
1748         return 0;
1749 }
1750
1751 static struct clk ipu2_clk = {
1752         __INIT_CLK_DEBUG(ipu2_clk)
1753         .parent = &mmdc_ch0_axi_clk[0],
1754         .enable_reg = MXC_CCM_CCGR3,
1755         .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET,
1756         .enable = _clk_enable,
1757         .disable = _clk_disable,
1758         .set_parent = _clk_ipu2_set_parent,
1759         .round_rate = _clk_ipu_round_rate,
1760         .set_rate = _clk_ipu2_set_rate,
1761         .get_rate = _clk_ipu2_get_rate,
1762 };
1763
1764 static unsigned long _clk_usdhc_round_rate(struct clk *clk,
1765                                                 unsigned long rate)
1766 {
1767         u32 div;
1768         u32 parent_rate = clk_get_rate(clk->parent);
1769
1770         div = parent_rate / rate;
1771
1772         /* Make sure rate is not greater than the maximum value for the clock.
1773          * Also prevent a div of 0.
1774          */
1775         if (div == 0)
1776                 div++;
1777
1778         if (div > 8)
1779                 div = 8;
1780
1781         return parent_rate / div;
1782 }
1783
1784 static int _clk_usdhc1_set_parent(struct clk *clk, struct clk *parent)
1785 {
1786         u32 reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_USDHC1_CLK_SEL;
1787
1788         if (parent == &pll2_pfd_352M)
1789                 reg |= (MXC_CCM_CSCMR1_USDHC1_CLK_SEL);
1790
1791         __raw_writel(reg, MXC_CCM_CSCMR1);
1792
1793         return 0;
1794 }
1795
1796 static unsigned long _clk_usdhc1_get_rate(struct clk *clk)
1797 {
1798         u32 reg, div;
1799
1800         reg = __raw_readl(MXC_CCM_CSCDR1);
1801         div = ((reg & MXC_CCM_CSCDR1_USDHC1_PODF_MASK) >>
1802                         MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET) + 1;
1803
1804         return clk_get_rate(clk->parent) / div;
1805 }
1806
1807 static int _clk_usdhc1_set_rate(struct clk *clk, unsigned long rate)
1808 {
1809         u32 reg, div;
1810         u32 parent_rate = clk_get_rate(clk->parent);
1811
1812         div = parent_rate / rate;
1813         if (div == 0)
1814                 div++;
1815         if (((parent_rate / div) != rate) || (div > 8))
1816                 return -EINVAL;
1817
1818         reg = __raw_readl(MXC_CCM_CSCDR1);
1819         reg &= ~MXC_CCM_CSCDR1_USDHC1_PODF_MASK;
1820         reg |= (div - 1) << MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET;
1821         __raw_writel(reg, MXC_CCM_CSCDR1);
1822
1823         return 0;
1824 }
1825
1826 static struct clk usdhc1_clk = {
1827         __INIT_CLK_DEBUG(usdhc1_clk)
1828         .id = 0,
1829         .parent = &pll2_pfd_400M,
1830         .enable_reg = MXC_CCM_CCGR6,
1831         .enable_shift = MXC_CCM_CCGRx_CG1_OFFSET,
1832         .enable = _clk_enable,
1833         .disable = _clk_disable,
1834         .set_parent = _clk_usdhc1_set_parent,
1835         .round_rate = _clk_usdhc_round_rate,
1836         .set_rate = _clk_usdhc1_set_rate,
1837         .get_rate = _clk_usdhc1_get_rate,
1838 };
1839
1840 static int _clk_usdhc2_set_parent(struct clk *clk, struct clk *parent)
1841 {
1842         u32 reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_USDHC2_CLK_SEL;
1843
1844         if (parent == &pll2_pfd_352M)
1845                 reg |= (MXC_CCM_CSCMR1_USDHC2_CLK_SEL);
1846
1847         __raw_writel(reg, MXC_CCM_CSCMR1);
1848
1849         return 0;
1850 }
1851
1852 static unsigned long _clk_usdhc2_get_rate(struct clk *clk)
1853 {
1854         u32 reg, div;
1855
1856         reg = __raw_readl(MXC_CCM_CSCDR1);
1857         div = ((reg & MXC_CCM_CSCDR1_USDHC2_PODF_MASK) >>
1858                         MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET) + 1;
1859
1860         return clk_get_rate(clk->parent) / div;
1861 }
1862
1863 static int _clk_usdhc2_set_rate(struct clk *clk, unsigned long rate)
1864 {
1865         u32 reg, div;
1866         u32 parent_rate = clk_get_rate(clk->parent);
1867
1868         div = parent_rate / rate;
1869         if (div == 0)
1870                 div++;
1871         if (((parent_rate / div) != rate) || (div > 8))
1872                 return -EINVAL;
1873
1874         reg = __raw_readl(MXC_CCM_CSCDR1);
1875         reg &= ~MXC_CCM_CSCDR1_USDHC2_PODF_MASK;
1876         reg |= (div - 1) << MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET;
1877         __raw_writel(reg, MXC_CCM_CSCDR1);
1878
1879         return 0;
1880 }
1881
1882 static struct clk usdhc2_clk = {
1883         __INIT_CLK_DEBUG(usdhc2_clk)
1884         .id = 1,
1885         .parent = &pll2_pfd_400M,
1886         .enable_reg = MXC_CCM_CCGR6,
1887         .enable_shift = MXC_CCM_CCGRx_CG2_OFFSET,
1888         .enable = _clk_enable,
1889         .disable = _clk_disable,
1890         .set_parent = _clk_usdhc2_set_parent,
1891         .round_rate = _clk_usdhc_round_rate,
1892         .set_rate = _clk_usdhc2_set_rate,
1893         .get_rate = _clk_usdhc2_get_rate,
1894 };
1895
1896 static int _clk_usdhc3_set_parent(struct clk *clk, struct clk *parent)
1897 {
1898         u32 reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_USDHC3_CLK_SEL;
1899
1900         if (parent == &pll2_pfd_352M)
1901                 reg |= (MXC_CCM_CSCMR1_USDHC3_CLK_SEL);
1902
1903         __raw_writel(reg, MXC_CCM_CSCMR1);
1904
1905         return 0;
1906 }
1907
1908 static unsigned long _clk_usdhc3_get_rate(struct clk *clk)
1909 {
1910         u32 reg, div;
1911
1912         reg = __raw_readl(MXC_CCM_CSCDR1);
1913         div = ((reg & MXC_CCM_CSCDR1_USDHC3_PODF_MASK) >>
1914                         MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET) + 1;
1915
1916         return clk_get_rate(clk->parent) / div;
1917 }
1918
1919 static int _clk_usdhc3_set_rate(struct clk *clk, unsigned long rate)
1920 {
1921         u32 reg, div;
1922         u32 parent_rate = clk_get_rate(clk->parent);
1923
1924         div = parent_rate / rate;
1925         if (div == 0)
1926                 div++;
1927         if (((parent_rate / div) != rate) || (div > 8))
1928                 return -EINVAL;
1929
1930         reg = __raw_readl(MXC_CCM_CSCDR1);
1931         reg &= ~MXC_CCM_CSCDR1_USDHC3_PODF_MASK;
1932         reg |= (div - 1) << MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET;
1933         __raw_writel(reg, MXC_CCM_CSCDR1);
1934
1935         return 0;
1936 }
1937
1938
1939 static struct clk usdhc3_clk = {
1940         __INIT_CLK_DEBUG(usdhc3_clk)
1941         .id = 2,
1942         .parent = &pll2_pfd_400M,
1943         .enable_reg = MXC_CCM_CCGR6,
1944         .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET,
1945         .enable = _clk_enable,
1946         .disable = _clk_disable,
1947         .set_parent = _clk_usdhc3_set_parent,
1948         .round_rate = _clk_usdhc_round_rate,
1949         .set_rate = _clk_usdhc3_set_rate,
1950         .get_rate = _clk_usdhc3_get_rate,
1951 };
1952
1953 static int _clk_usdhc4_set_parent(struct clk *clk, struct clk *parent)
1954 {
1955         u32 reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_USDHC4_CLK_SEL;
1956
1957         if (parent == &pll2_pfd_352M)
1958                 reg |= (MXC_CCM_CSCMR1_USDHC4_CLK_SEL);
1959
1960         __raw_writel(reg, MXC_CCM_CSCMR1);
1961
1962         return 0;
1963 }
1964
1965 static unsigned long _clk_usdhc4_get_rate(struct clk *clk)
1966 {
1967         u32 reg, div;
1968
1969         reg = __raw_readl(MXC_CCM_CSCDR1);
1970         div = ((reg & MXC_CCM_CSCDR1_USDHC4_PODF_MASK) >>
1971                         MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET) + 1;
1972
1973         return clk_get_rate(clk->parent) / div;
1974 }
1975
1976 static int _clk_usdhc4_set_rate(struct clk *clk, unsigned long rate)
1977 {
1978         u32 reg, div;
1979         u32 parent_rate = clk_get_rate(clk->parent);
1980
1981         div = parent_rate / rate;
1982         if (div == 0)
1983                 div++;
1984         if (((parent_rate / div) != rate) || (div > 8))
1985                 return -EINVAL;
1986
1987         reg = __raw_readl(MXC_CCM_CSCDR1);
1988         reg &= ~MXC_CCM_CSCDR1_USDHC4_PODF_MASK;
1989         reg |= (div - 1) << MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET;
1990         __raw_writel(reg, MXC_CCM_CSCDR1);
1991
1992         return 0;
1993 }
1994
1995
1996 static struct clk usdhc4_clk = {
1997         __INIT_CLK_DEBUG(usdhc4_clk)
1998         .id = 3,
1999         .parent = &pll2_pfd_400M,
2000         .enable_reg = MXC_CCM_CCGR6,
2001         .enable_shift = MXC_CCM_CCGRx_CG4_OFFSET,
2002         .enable = _clk_enable,
2003         .disable = _clk_disable,
2004         .set_parent = _clk_usdhc4_set_parent,
2005         .round_rate = _clk_usdhc_round_rate,
2006         .set_rate = _clk_usdhc4_set_rate,
2007         .get_rate = _clk_usdhc4_get_rate,
2008 };
2009
2010 static unsigned long _clk_ssi_round_rate(struct clk *clk,
2011                                                 unsigned long rate)
2012 {
2013         u32 pre, post;
2014         u32 parent_rate = clk_get_rate(clk->parent);
2015         u32 div = parent_rate / rate;
2016
2017         if (parent_rate % rate)
2018                 div++;
2019
2020         __calc_pre_post_dividers(1 << 6, div, &pre, &post);
2021
2022         return parent_rate / (pre * post);
2023 }
2024
2025 static unsigned long _clk_ssi1_get_rate(struct clk *clk)
2026 {
2027         u32 reg, prediv, podf;
2028
2029         reg = __raw_readl(MXC_CCM_CS1CDR);
2030
2031         prediv = ((reg & MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK)
2032                 >> MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET) + 1;
2033         podf = ((reg & MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK)
2034                 >> MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET) + 1;
2035
2036         return clk_get_rate(clk->parent) / (prediv * podf);
2037 }
2038
2039 static int _clk_ssi1_set_rate(struct clk *clk, unsigned long rate)
2040 {
2041         u32 reg, div, pre, post;
2042         u32 parent_rate = clk_get_rate(clk->parent);
2043
2044         div = parent_rate / rate;
2045         if (div == 0)
2046                 div++;
2047         if (((parent_rate / div) != rate) || div > 512)
2048                 return -EINVAL;
2049
2050         __calc_pre_post_dividers(1 << 6, div, &pre, &post);
2051
2052         reg = __raw_readl(MXC_CCM_CS1CDR);
2053         reg &= ~(MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK |
2054                  MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK);
2055         reg |= (post - 1) << MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET;
2056         reg |= (pre - 1) << MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET;
2057
2058         __raw_writel(reg, MXC_CCM_CS1CDR);
2059
2060         return 0;
2061 }
2062
2063
2064 static int _clk_ssi1_set_parent(struct clk *clk, struct clk *parent)
2065 {
2066         u32 reg, mux;
2067
2068         reg = __raw_readl(MXC_CCM_CSCMR1)
2069                 & ~MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK;
2070
2071         mux = _get_mux6(parent, &pll3_pfd_508M, &pll3_pfd_454M,
2072                         &pll4_audio_main_clk, NULL, NULL, NULL);
2073         reg |= (mux << MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET);
2074
2075         __raw_writel(reg, MXC_CCM_CSCMR1);
2076
2077         return 0;
2078 }
2079
2080 static struct clk ssi1_clk = {
2081         __INIT_CLK_DEBUG(ssi1_clk)
2082         .parent = &pll3_pfd_508M,
2083         .enable_reg = MXC_CCM_CCGR5,
2084         .enable_shift = MXC_CCM_CCGRx_CG9_OFFSET,
2085         .enable = _clk_enable,
2086         .disable = _clk_disable,
2087         .set_parent = _clk_ssi1_set_parent,
2088         .set_rate = _clk_ssi1_set_rate,
2089         .round_rate = _clk_ssi_round_rate,
2090         .get_rate = _clk_ssi1_get_rate,
2091 };
2092
2093 static unsigned long _clk_ssi2_get_rate(struct clk *clk)
2094 {
2095         u32 reg, prediv, podf;
2096
2097         reg = __raw_readl(MXC_CCM_CS2CDR);
2098
2099         prediv = ((reg & MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK)
2100                 >> MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET) + 1;
2101         podf = ((reg & MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK)
2102                 >> MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET) + 1;
2103
2104         return clk_get_rate(clk->parent) / (prediv * podf);
2105 }
2106
2107 static int _clk_ssi2_set_rate(struct clk *clk, unsigned long rate)
2108 {
2109         u32 reg, div, pre, post;
2110         u32 parent_rate = clk_get_rate(clk->parent);
2111
2112         div = parent_rate / rate;
2113         if (div == 0)
2114                 div++;
2115         if (((parent_rate / div) != rate) || div > 512)
2116                 return -EINVAL;
2117
2118         __calc_pre_post_dividers(1 << 6, div, &pre, &post);
2119
2120         reg = __raw_readl(MXC_CCM_CS2CDR);
2121         reg &= ~(MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK |
2122                  MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK);
2123         reg |= (post - 1) << MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET;
2124         reg |= (pre - 1) << MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET;
2125
2126         __raw_writel(reg, MXC_CCM_CS2CDR);
2127
2128         return 0;
2129 }
2130
2131
2132 static int _clk_ssi2_set_parent(struct clk *clk, struct clk *parent)
2133 {
2134         u32 reg, mux;
2135
2136         reg = __raw_readl(MXC_CCM_CSCMR1)
2137                 & ~MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK;
2138
2139         mux = _get_mux6(parent, &pll3_pfd_508M, &pll3_pfd_454M,
2140                         &pll4_audio_main_clk, NULL, NULL, NULL);
2141         reg |= (mux << MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET);
2142
2143         __raw_writel(reg, MXC_CCM_CSCMR1);
2144
2145         return 0;
2146 }
2147
2148 static struct clk ssi2_clk = {
2149         __INIT_CLK_DEBUG(ssi2_clk)
2150         .parent = &pll3_pfd_508M,
2151         .enable_reg = MXC_CCM_CCGR5,
2152         .enable_shift = MXC_CCM_CCGRx_CG10_OFFSET,
2153         .enable = _clk_enable,
2154         .disable = _clk_disable,
2155         .set_parent = _clk_ssi2_set_parent,
2156         .set_rate = _clk_ssi2_set_rate,
2157         .round_rate = _clk_ssi_round_rate,
2158         .get_rate = _clk_ssi2_get_rate,
2159 };
2160
2161 static unsigned long _clk_ssi3_get_rate(struct clk *clk)
2162 {
2163         u32 reg, prediv, podf;
2164
2165         reg = __raw_readl(MXC_CCM_CS1CDR);
2166
2167         prediv = ((reg & MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK)
2168                 >> MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET) + 1;
2169         podf = ((reg & MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK)
2170                 >> MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET) + 1;
2171
2172         return clk_get_rate(clk->parent) / (prediv * podf);
2173 }
2174
2175 static int _clk_ssi3_set_rate(struct clk *clk, unsigned long rate)
2176 {
2177         u32 reg, div, pre, post;
2178         u32 parent_rate = clk_get_rate(clk->parent);
2179
2180         div = parent_rate / rate;
2181         if (div == 0)
2182                 div++;
2183         if (((parent_rate / div) != rate) || div > 512)
2184                 return -EINVAL;
2185
2186         __calc_pre_post_dividers(1 << 6, div, &pre, &post);
2187
2188         reg = __raw_readl(MXC_CCM_CS1CDR);
2189         reg &= ~(MXC_CCM_CS1CDR_SSI3_CLK_PODF_MASK|
2190                  MXC_CCM_CS1CDR_SSI3_CLK_PRED_MASK);
2191         reg |= (post - 1) << MXC_CCM_CS1CDR_SSI3_CLK_PODF_OFFSET;
2192         reg |= (pre - 1) << MXC_CCM_CS1CDR_SSI3_CLK_PRED_OFFSET;
2193
2194         __raw_writel(reg, MXC_CCM_CS1CDR);
2195
2196         return 0;
2197 }
2198
2199
2200 static int _clk_ssi3_set_parent(struct clk *clk, struct clk *parent)
2201 {
2202         u32 reg, mux;
2203
2204         reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_SSI3_CLK_SEL_MASK;
2205
2206         mux = _get_mux6(parent, &pll3_pfd_508M, &pll3_pfd_454M,
2207                                 &pll4_audio_main_clk, NULL, NULL, NULL);
2208         reg |= (mux << MXC_CCM_CSCMR1_SSI3_CLK_SEL_OFFSET);
2209
2210         __raw_writel(reg, MXC_CCM_CSCMR1);
2211
2212         return 0;
2213 }
2214
2215 static struct clk ssi3_clk = {
2216         __INIT_CLK_DEBUG(ssi3_clk)
2217         .parent = &pll3_pfd_508M,
2218         .enable_reg = MXC_CCM_CCGR5,
2219         .enable_shift = MXC_CCM_CCGRx_CG11_OFFSET,
2220         .enable = _clk_enable,
2221         .disable = _clk_disable,
2222         .set_parent = _clk_ssi3_set_parent,
2223         .set_rate = _clk_ssi3_set_rate,
2224         .round_rate = _clk_ssi_round_rate,
2225         .get_rate = _clk_ssi3_get_rate,
2226 };
2227
2228 static unsigned long _clk_ldb_di_round_rate(struct clk *clk,
2229                                                 unsigned long rate)
2230 {
2231         u32 parent_rate = clk_get_rate(clk->parent);
2232
2233         if (rate * 7 <= parent_rate + parent_rate/20)
2234                 return parent_rate / 7;
2235         else
2236                 return 2 * parent_rate / 7;
2237 }
2238
2239 static unsigned long _clk_ldb_di0_get_rate(struct clk *clk)
2240 {
2241         u32 div;
2242
2243         div = __raw_readl(MXC_CCM_CSCMR2) &
2244                 MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
2245
2246         if (div)
2247                 return clk_get_rate(clk->parent) / 7;
2248
2249         return (2 * clk_get_rate(clk->parent)) / 7;
2250 }
2251
2252 static int _clk_ldb_di0_set_rate(struct clk *clk, unsigned long rate)
2253 {
2254         u32 reg, div = 0;
2255         u32 parent_rate = clk_get_rate(clk->parent);
2256
2257         if (rate * 7 <= parent_rate + parent_rate/20) {
2258                 div = 7;
2259                 rate = parent_rate / 7;
2260         } else
2261                 rate = 2 * parent_rate / 7;
2262
2263         reg = __raw_readl(MXC_CCM_CSCMR2);
2264         if (div == 7)
2265                 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
2266         else
2267                 reg &= ~MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
2268
2269         __raw_writel(reg, MXC_CCM_CSCMR2);
2270
2271         return 0;
2272 }
2273
2274 static int _clk_ldb_di0_set_parent(struct clk *clk, struct clk *parent)
2275 {
2276         u32 reg, mux;
2277
2278         reg = __raw_readl(MXC_CCM_CS2CDR)
2279                 & ~MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK;
2280
2281         mux = _get_mux6(parent, &pll5_video_main_clk,
2282                 &pll2_pfd_352M, &pll2_pfd_400M, &pll3_pfd_540M,
2283                 &pll3_usb_otg_main_clk, NULL);
2284         reg |= (mux << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET);
2285
2286         __raw_writel(reg, MXC_CCM_CS2CDR);
2287
2288         return 0;
2289 }
2290
2291 static struct clk ldb_di0_clk = {
2292          __INIT_CLK_DEBUG(ldb_di0_clk)
2293         .id = 0,
2294         .parent = &pll3_pfd_540M,
2295         .enable_reg = MXC_CCM_CCGR3,
2296         .enable_shift = MXC_CCM_CCGRx_CG6_OFFSET,
2297         .enable = _clk_enable,
2298         .disable = _clk_disable,
2299         .set_parent = _clk_ldb_di0_set_parent,
2300         .set_rate = _clk_ldb_di0_set_rate,
2301         .round_rate = _clk_ldb_di_round_rate,
2302         .get_rate = _clk_ldb_di0_get_rate,
2303 };
2304
2305 static unsigned long _clk_ldb_di1_get_rate(struct clk *clk)
2306 {
2307         u32 div;
2308
2309         div = __raw_readl(MXC_CCM_CSCMR2) &
2310                 MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
2311
2312         if (div)
2313                 return clk_get_rate(clk->parent) / 7;
2314
2315         return (2 * clk_get_rate(clk->parent)) / 7;
2316 }
2317
2318 static int _clk_ldb_di1_set_rate(struct clk *clk, unsigned long rate)
2319 {
2320         u32 reg, div = 0;
2321         u32 parent_rate = clk_get_rate(clk->parent);
2322
2323         if (rate * 7 <= parent_rate + parent_rate/20) {
2324                 div = 7;
2325                 rate = parent_rate / 7;
2326         } else
2327                 rate = 2 * parent_rate / 7;
2328
2329         reg = __raw_readl(MXC_CCM_CSCMR2);
2330         if (div == 7)
2331                 reg |= MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
2332         else
2333                 reg &= ~MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
2334
2335         __raw_writel(reg, MXC_CCM_CSCMR2);
2336
2337         return 0;
2338 }
2339
2340 static int _clk_ldb_di1_set_parent(struct clk *clk, struct clk *parent)
2341 {
2342         u32 reg, mux;
2343
2344         reg = __raw_readl(MXC_CCM_CS2CDR)
2345                 & ~MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK;
2346
2347         mux = _get_mux6(parent, &pll5_video_main_clk,
2348                 &pll2_pfd_352M, &pll2_pfd_400M, &pll3_pfd_540M,
2349                 &pll3_usb_otg_main_clk, NULL);
2350         reg |= (mux << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
2351
2352         __raw_writel(reg, MXC_CCM_CS2CDR);
2353
2354         return 0;
2355 }
2356
2357 static struct clk ldb_di1_clk = {
2358          __INIT_CLK_DEBUG(ldb_di1_clk)
2359         .id = 0,
2360         .parent = &pll3_pfd_540M,
2361         .enable_reg = MXC_CCM_CCGR3,
2362         .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
2363         .enable = _clk_enable,
2364         .disable = _clk_disable,
2365         .set_parent = _clk_ldb_di1_set_parent,
2366         .set_rate = _clk_ldb_di1_set_rate,
2367         .round_rate = _clk_ldb_di_round_rate,
2368         .get_rate = _clk_ldb_di1_get_rate,
2369 };
2370
2371
2372 static unsigned long _clk_ipu_di_round_rate(struct clk *clk,
2373                                                 unsigned long rate)
2374 {
2375         u32 div;
2376         u32 parent_rate = clk_get_rate(clk->parent);
2377
2378         if ((clk->parent == &ldb_di0_clk) ||
2379                 (clk->parent == &ldb_di1_clk))
2380                 return parent_rate;
2381
2382         div = parent_rate / rate;
2383
2384         /* Make sure rate is not greater than the maximum value for the clock.
2385          * Also prevent a div of 0.
2386          */
2387         if (div == 0)
2388                 div++;
2389
2390         if (div > 8)
2391                 div = 8;
2392
2393         return parent_rate / div;
2394 }
2395
2396 static unsigned long _clk_ipu1_di0_get_rate(struct clk *clk)
2397 {
2398         u32 reg, div;
2399
2400         if ((clk->parent == &ldb_di0_clk) ||
2401                 (clk->parent == &ldb_di1_clk))
2402                 return clk_get_rate(clk->parent);
2403
2404         reg = __raw_readl(MXC_CCM_CHSCCDR);
2405
2406         div = ((reg & MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK) >>
2407                          MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET) + 1;
2408
2409         return clk_get_rate(clk->parent) / div;
2410 }
2411
2412 static int _clk_ipu1_di0_set_rate(struct clk *clk, unsigned long rate)
2413 {
2414         u32 reg, div;
2415         u32 parent_rate = clk_get_rate(clk->parent);
2416
2417         if ((clk->parent == &ldb_di0_clk) ||
2418                 (clk->parent == &ldb_di1_clk)) {
2419                 if (parent_rate == rate)
2420                         return 0;
2421                 else
2422                         return -EINVAL;
2423         }
2424
2425         div = parent_rate / rate;
2426         if (div == 0)
2427                 div++;
2428         if (((parent_rate / div) != rate) || (div > 8))
2429                 return -EINVAL;
2430
2431         reg = __raw_readl(MXC_CCM_CHSCCDR);
2432         reg &= ~MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK;
2433         reg |= (div - 1) << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET;
2434         __raw_writel(reg, MXC_CCM_CHSCCDR);
2435
2436         return 0;
2437 }
2438
2439
2440 static int _clk_ipu1_di0_set_parent(struct clk *clk, struct clk *parent)
2441 {
2442         u32 reg, mux;
2443
2444         if (parent == &ldb_di0_clk)
2445                 mux = 0x3;
2446         else if (parent == &ldb_di1_clk)
2447                 mux = 0x4;
2448         else {
2449                 reg = __raw_readl(MXC_CCM_CHSCCDR)
2450                         & ~MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK;
2451
2452                 mux = _get_mux6(parent, &mmdc_ch0_axi_clk[0],
2453                                 &pll3_usb_otg_main_clk, &pll5_video_main_clk,
2454                                 &pll2_pfd_352M, &pll2_pfd_400M, &pll3_pfd_540M);
2455                 reg |= (mux << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
2456
2457                 __raw_writel(reg, MXC_CCM_CHSCCDR);
2458
2459                 /* Derive clock from divided pre-muxed ipu1_di0 clock.*/
2460                 mux = 0;
2461         }
2462
2463         reg = __raw_readl(MXC_CCM_CHSCCDR)
2464                 & ~MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK;
2465         __raw_writel(reg | (mux << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET),
2466                 MXC_CCM_CHSCCDR);
2467
2468         return 0;
2469 }
2470
2471 static unsigned long _clk_ipu1_di1_get_rate(struct clk *clk)
2472 {
2473         u32 reg, div;
2474
2475         if ((clk->parent == &ldb_di0_clk) ||
2476                 (clk->parent == &ldb_di1_clk))
2477                 return clk_get_rate(clk->parent);
2478
2479         reg = __raw_readl(MXC_CCM_CHSCCDR);
2480
2481         div = ((reg & MXC_CCM_CHSCCDR_IPU1_DI1_PODF_MASK)
2482                         >> MXC_CCM_CHSCCDR_IPU1_DI1_PODF_OFFSET) + 1;
2483
2484         return clk_get_rate(clk->parent) / div;
2485 }
2486
2487 static int _clk_ipu1_di1_set_rate(struct clk *clk, unsigned long rate)
2488 {
2489         u32 reg, div;
2490         u32 parent_rate = clk_get_rate(clk->parent);
2491
2492         if ((clk->parent == &ldb_di0_clk) ||
2493                 (clk->parent == &ldb_di1_clk)) {
2494                 if (parent_rate == rate)
2495                         return 0;
2496                 else
2497                         return -EINVAL;
2498         }
2499
2500         div = parent_rate / rate;
2501         if (div == 0)
2502                 div++;
2503         if (((parent_rate / div) != rate) || (div > 8))
2504                 return -EINVAL;
2505
2506         reg = __raw_readl(MXC_CCM_CHSCCDR);
2507         reg &= ~MXC_CCM_CHSCCDR_IPU1_DI1_PODF_MASK;
2508         reg |= (div - 1) << MXC_CCM_CHSCCDR_IPU1_DI1_PODF_OFFSET;
2509         __raw_writel(reg, MXC_CCM_CHSCCDR);
2510
2511         return 0;
2512 }
2513
2514
2515 static int _clk_ipu1_di1_set_parent(struct clk *clk, struct clk *parent)
2516 {
2517         u32 reg, mux;
2518
2519         if (parent == &ldb_di0_clk)
2520                 mux = 0x3;
2521         else if (parent == &ldb_di1_clk)
2522                 mux = 0x4;
2523         else {
2524                 reg = __raw_readl(MXC_CCM_CHSCCDR)
2525                         & ~MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_MASK;
2526
2527                 mux = _get_mux6(parent, &mmdc_ch0_axi_clk[0],
2528                                 &pll3_usb_otg_main_clk, &pll5_video_main_clk,
2529                                 &pll2_pfd_352M, &pll2_pfd_400M, &pll3_pfd_540M);
2530                 reg |= (mux << MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_OFFSET);
2531
2532                 __raw_writel(reg, MXC_CCM_CHSCCDR);
2533
2534                 /* Derive clock from divided pre-muxed ipu1_di0 clock.*/
2535                 mux = 0;
2536         }
2537         reg = __raw_readl(MXC_CCM_CHSCCDR)
2538                 & ~MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_MASK;
2539         __raw_writel(reg | (mux << MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET),
2540                 MXC_CCM_CHSCCDR);
2541
2542         return 0;
2543 }
2544
2545 static struct clk ipu1_di_clk[] = {
2546         {
2547          __INIT_CLK_DEBUG(ipu1_di_clk_0)
2548         .id = 0,
2549         .parent = &pll5_video_main_clk,
2550         .enable_reg = MXC_CCM_CCGR3,
2551         .enable_shift = MXC_CCM_CCGRx_CG1_OFFSET,
2552         .enable = _clk_enable,
2553         .disable = _clk_disable,
2554         .set_parent = _clk_ipu1_di0_set_parent,
2555         .set_rate = _clk_ipu1_di0_set_rate,
2556         .round_rate = _clk_ipu_di_round_rate,
2557         .get_rate = _clk_ipu1_di0_get_rate,
2558         },
2559         {
2560          __INIT_CLK_DEBUG(ipu1_di_clk_1)
2561         .id = 1,
2562         .parent = &pll5_video_main_clk,
2563         .enable_reg = MXC_CCM_CCGR3,
2564         .enable_shift = MXC_CCM_CCGRx_CG2_OFFSET,
2565         .enable = _clk_enable,
2566         .disable = _clk_disable,
2567         .set_parent = _clk_ipu1_di1_set_parent,
2568         .set_rate = _clk_ipu1_di1_set_rate,
2569         .round_rate = _clk_ipu_di_round_rate,
2570         .get_rate = _clk_ipu1_di1_get_rate,
2571         },
2572 };
2573
2574 static unsigned long _clk_ipu2_di0_get_rate(struct clk *clk)
2575 {
2576         u32 reg, div;
2577
2578         if ((clk->parent == &ldb_di0_clk) ||
2579                 (clk->parent == &ldb_di1_clk))
2580                 return clk_get_rate(clk->parent);
2581
2582         reg = __raw_readl(MXC_CCM_CSCDR2);
2583
2584         div = ((reg & MXC_CCM_CSCDR2_IPU2_DI0_PODF_MASK) >>
2585                         MXC_CCM_CSCDR2_IPU2_DI0_PODF_OFFSET) + 1;
2586
2587         return clk_get_rate(clk->parent) / div;
2588 }
2589
2590 static int _clk_ipu2_di0_set_rate(struct clk *clk, unsigned long rate)
2591 {
2592         u32 reg, div;
2593         u32 parent_rate = clk_get_rate(clk->parent);
2594
2595         if ((clk->parent == &ldb_di0_clk) ||
2596                 (clk->parent == &ldb_di1_clk)) {
2597                 if (parent_rate == rate)
2598                         return 0;
2599                 else
2600                         return -EINVAL;
2601         }
2602
2603         div = parent_rate / rate;
2604         if (div == 0)
2605                 div++;
2606         if (((parent_rate / div) != rate) || (div > 8))
2607                 return -EINVAL;
2608
2609         reg = __raw_readl(MXC_CCM_CSCDR2);
2610         reg &= ~MXC_CCM_CSCDR2_IPU2_DI0_PODF_MASK;
2611         reg |= (div - 1) << MXC_CCM_CSCDR2_IPU2_DI0_PODF_OFFSET;
2612         __raw_writel(reg, MXC_CCM_CSCDR2);
2613
2614         return 0;
2615 }
2616
2617 static int _clk_ipu2_di0_set_parent(struct clk *clk, struct clk *parent)
2618 {
2619         u32 reg, mux;
2620
2621         if (parent == &ldb_di0_clk)
2622                 mux = 0x3;
2623         else if (parent == &ldb_di1_clk)
2624                 mux = 0x4;
2625         else {
2626                 reg = __raw_readl(MXC_CCM_CSCDR2)
2627                         & ~MXC_CCM_CSCDR2_IPU2_DI0_PRE_CLK_SEL_MASK;
2628
2629                 mux = _get_mux6(parent, &mmdc_ch0_axi_clk[0],
2630                                 &pll3_usb_otg_main_clk, &pll5_video_main_clk,
2631                                 &pll2_pfd_352M, &pll2_pfd_400M, &pll3_pfd_540M);
2632                 reg |= (mux << MXC_CCM_CSCDR2_IPU2_DI0_PRE_CLK_SEL_OFFSET);
2633
2634                 __raw_writel(reg, MXC_CCM_CSCDR2);
2635
2636                 /* Derive clock from divided pre-muxed ipu2_di0 clock.*/
2637                 mux = 0;
2638         }
2639         reg = __raw_readl(MXC_CCM_CSCDR2)
2640                 & ~MXC_CCM_CSCDR2_IPU2_DI0_CLK_SEL_MASK;
2641         __raw_writel(reg | (mux << MXC_CCM_CSCDR2_IPU2_DI0_CLK_SEL_OFFSET),
2642                 MXC_CCM_CSCDR2);
2643
2644         return 0;
2645 }
2646
2647 static unsigned long _clk_ipu2_di1_get_rate(struct clk *clk)
2648 {
2649         u32 reg, div;
2650
2651         if ((clk->parent == &ldb_di0_clk) ||
2652                 (clk->parent == &ldb_di1_clk))
2653                 return clk_get_rate(clk->parent);
2654
2655         reg = __raw_readl(MXC_CCM_CSCDR2);
2656
2657         div = ((reg & MXC_CCM_CSCDR2_IPU2_DI1_PODF_MASK)
2658                 >> MXC_CCM_CSCDR2_IPU2_DI1_PODF_OFFSET) + 1;
2659
2660         return clk_get_rate(clk->parent) / div;
2661 }
2662
2663 static int _clk_ipu2_di1_set_rate(struct clk *clk, unsigned long rate)
2664 {
2665         u32 reg, div;
2666         u32 parent_rate = clk_get_rate(clk->parent);
2667
2668         if ((clk->parent == &ldb_di0_clk) ||
2669                 (clk->parent == &ldb_di1_clk)) {
2670                 if (parent_rate == rate)
2671                         return 0;
2672                 else
2673                         return -EINVAL;
2674         }
2675
2676         div = parent_rate / rate;
2677         if (div == 0)
2678                 div++;
2679         if (((parent_rate / div) != rate) || (div > 8))
2680                 return -EINVAL;
2681
2682         reg = __raw_readl(MXC_CCM_CSCDR2);
2683         reg &= ~MXC_CCM_CSCDR2_IPU2_DI1_PODF_MASK;
2684         reg |= (div - 1) << MXC_CCM_CSCDR2_IPU2_DI1_PODF_OFFSET;
2685         __raw_writel(reg, MXC_CCM_CSCDR2);
2686
2687         return 0;
2688 }
2689
2690 static int _clk_ipu2_di1_set_parent(struct clk *clk, struct clk *parent)
2691 {
2692         u32 reg, mux;
2693
2694         if (parent == &ldb_di0_clk)
2695                 mux = 0x3;
2696         else if (parent == &ldb_di1_clk)
2697                 mux = 0x4;
2698         else {
2699                 reg = __raw_readl(MXC_CCM_CSCDR2)
2700                         & ~MXC_CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_MASK;
2701
2702                 mux = _get_mux6(parent, &mmdc_ch0_axi_clk[0],
2703                                 &pll3_usb_otg_main_clk, &pll5_video_main_clk,
2704                                 &pll2_pfd_352M, &pll2_pfd_400M, &pll3_pfd_540M);
2705                 reg |= (mux << MXC_CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_OFFSET);
2706
2707                 __raw_writel(reg, MXC_CCM_CSCDR2);
2708
2709                 /* Derive clock from divided pre-muxed ipu1_di0 clock.*/
2710                 mux = 0;
2711         }
2712         reg = __raw_readl(MXC_CCM_CSCDR2)
2713                 & ~MXC_CCM_CSCDR2_IPU2_DI1_CLK_SEL_MASK;
2714         __raw_writel(reg | (mux << MXC_CCM_CSCDR2_IPU2_DI1_CLK_SEL_OFFSET),
2715                 MXC_CCM_CSCDR2);
2716
2717         return 0;
2718 }
2719
2720 static struct clk ipu2_di_clk[] = {
2721         {
2722          __INIT_CLK_DEBUG(ipu2_di_clk_0)
2723         .id = 0,
2724         .parent = &pll5_video_main_clk,
2725         .enable_reg = MXC_CCM_CCGR3,
2726         .enable_shift = MXC_CCM_CCGRx_CG4_OFFSET,
2727         .enable = _clk_enable,
2728         .disable = _clk_disable,
2729         .set_parent = _clk_ipu2_di0_set_parent,
2730         .set_rate = _clk_ipu2_di0_set_rate,
2731         .round_rate = _clk_ipu_di_round_rate,
2732         .get_rate = _clk_ipu2_di0_get_rate,
2733         },
2734         {
2735          __INIT_CLK_DEBUG(ipu2_di_clk_1)
2736         .id = 1,
2737         .parent = &pll5_video_main_clk,
2738         .enable_reg = MXC_CCM_CCGR3,
2739         .enable_shift = MXC_CCM_CCGRx_CG5_OFFSET,
2740         .enable = _clk_enable,
2741         .disable = _clk_disable,
2742         .set_parent = _clk_ipu2_di1_set_parent,
2743         .set_rate = _clk_ipu2_di1_set_rate,
2744         .round_rate = _clk_ipu_di_round_rate,
2745         .get_rate = _clk_ipu2_di1_get_rate,
2746         },
2747 };
2748
2749 static struct clk can2_clk[] = {
2750         {
2751          __INIT_CLK_DEBUG(can2_module_clk)
2752         .id = 0,
2753         .parent = &pll3_60M,
2754         .enable_reg = MXC_CCM_CCGR0,
2755         .enable_shift = MXC_CCM_CCGRx_CG9_OFFSET,
2756         .enable = _clk_enable,
2757         .disable = _clk_disable,
2758         .secondary = &can2_clk[1],
2759         },
2760         {
2761          __INIT_CLK_DEBUG(can2_serial_clk)
2762         .id = 1,
2763         .parent = &pll3_60M,
2764         .enable_reg = MXC_CCM_CCGR0,
2765         .enable_shift = MXC_CCM_CCGRx_CG10_OFFSET,
2766         .enable = _clk_enable,
2767         .disable = _clk_disable,
2768         },
2769 };
2770
2771
2772 static struct clk can1_clk[] = {
2773         {
2774          __INIT_CLK_DEBUG(can1_module_clk)
2775         .id = 0,
2776         .parent = &pll3_60M,
2777         .enable_reg = MXC_CCM_CCGR0,
2778         .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
2779         .enable = _clk_enable,
2780         .disable = _clk_disable,
2781         .secondary = &can1_clk[1],
2782         },
2783         {
2784          __INIT_CLK_DEBUG(can1_serial_clk)
2785         .id = 1,
2786         .parent = &pll3_60M,
2787         .enable_reg = MXC_CCM_CCGR0,
2788         .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET,
2789         .enable = _clk_enable,
2790         .disable = _clk_disable,
2791         },
2792 };
2793
2794 static unsigned long _clk_spdif_round_rate(struct clk *clk,
2795                                                 unsigned long rate)
2796 {
2797         u32 pre, post;
2798         u32 parent_rate = clk_get_rate(clk->parent);
2799         u32 div = parent_rate / rate;
2800
2801         if (parent_rate % rate)
2802                 div++;
2803
2804         __calc_pre_post_dividers(1 << 3, div, &pre, &post);
2805
2806         return parent_rate / (pre * post);
2807 }
2808
2809 static int _clk_spdif0_set_parent(struct clk *clk, struct clk *parent)
2810 {
2811         u32 reg, mux;
2812
2813         reg = __raw_readl(MXC_CCM_CDCDR)
2814                 & ~MXC_CCM_CDCDR_SPDIF0_CLK_SEL_MASK;
2815
2816         mux = _get_mux6(parent, &pll4_audio_main_clk,
2817                 &pll3_pfd_508M, &pll3_pfd_454M,
2818                 &pll3_sw_clk, NULL, NULL);
2819         reg |= mux << MXC_CCM_CDCDR_SPDIF0_CLK_SEL_OFFSET;
2820
2821         __raw_writel(reg, MXC_CCM_CDCDR);
2822
2823         return 0;
2824 }
2825
2826 static unsigned long _clk_spdif0_get_rate(struct clk *clk)
2827 {
2828         u32 reg, pred, podf;
2829
2830         reg = __raw_readl(MXC_CCM_CDCDR);
2831
2832         pred = ((reg & MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK)
2833                 >> MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET) + 1;
2834         podf = ((reg & MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK)
2835                 >> MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET) + 1;
2836
2837         return clk_get_rate(clk->parent) / (pred * podf);
2838 }
2839
2840 static int _clk_spdif0_set_rate(struct clk *clk, unsigned long rate)
2841 {
2842         u32 reg, div, pre, post;
2843         u32 parent_rate = clk_get_rate(clk->parent);
2844
2845         div = parent_rate / rate;
2846         if (div == 0)
2847                 div++;
2848         if (((parent_rate / div) != rate) || div > 64)
2849                 return -EINVAL;
2850
2851         __calc_pre_post_dividers(1 << 3, div, &pre, &post);
2852
2853         reg = __raw_readl(MXC_CCM_CDCDR);
2854         reg &= ~(MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK|
2855                  MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK);
2856         reg |= (post - 1) << MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET;
2857         reg |= (pre - 1) << MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET;
2858
2859         __raw_writel(reg, MXC_CCM_CDCDR);
2860
2861         return 0;
2862 }
2863
2864 static struct clk spdif0_clk[] = {
2865         {
2866         __INIT_CLK_DEBUG(spdif0_clk_0)
2867         .id = 0,
2868         .parent = &pll3_sw_clk,
2869          .enable = _clk_enable,
2870          .enable_reg = MXC_CCM_CCGR5,
2871          .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
2872          .disable = _clk_disable,
2873          .secondary = &spdif0_clk[1],
2874          .set_rate = _clk_spdif0_set_rate,
2875          .get_rate = _clk_spdif0_get_rate,
2876          .set_parent = _clk_spdif0_set_parent,
2877          .round_rate = _clk_spdif_round_rate,
2878         },
2879         {
2880         __INIT_CLK_DEBUG(spdif0_clk_1)
2881          .id = 1,
2882          .parent = &ipg_clk,
2883          .secondary = &spba_clk,
2884          },
2885 };
2886
2887 static unsigned long _clk_esai_round_rate(struct clk *clk,
2888                                                 unsigned long rate)
2889 {
2890         u32 pre, post;
2891         u32 parent_rate = clk_get_rate(clk->parent);
2892         u32 div = parent_rate / rate;
2893
2894         if (parent_rate % rate)
2895                 div++;
2896
2897         __calc_pre_post_dividers(1 << 3, div, &pre, &post);
2898
2899         return parent_rate / (pre * post);
2900 }
2901
2902 static int _clk_esai_set_parent(struct clk *clk, struct clk *parent)
2903 {
2904         u32 reg, mux;
2905
2906         reg = __raw_readl(MXC_CCM_CSCMR2) & ~MXC_CCM_CSCMR2_ESAI_CLK_SEL_MASK;
2907
2908         mux = _get_mux6(parent, &pll4_audio_main_clk, &pll3_pfd_508M,
2909                         &pll3_pfd_454M, &pll3_sw_clk, NULL, NULL);
2910         reg |= mux << MXC_CCM_CSCMR2_ESAI_CLK_SEL_OFFSET;
2911
2912         __raw_writel(reg, MXC_CCM_CSCMR2);
2913
2914         return 0;
2915 }
2916
2917 static unsigned long _clk_esai_get_rate(struct clk *clk)
2918 {
2919         u32 reg, pred, podf;
2920
2921         reg = __raw_readl(MXC_CCM_CS1CDR);
2922
2923         pred = ((reg & MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK)
2924                 >> MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET) + 1;
2925         podf = ((reg & MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK)
2926                 >> MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET) + 1;
2927
2928         return clk_get_rate(clk->parent) / (pred * podf);
2929 }
2930
2931 static int _clk_esai_set_rate(struct clk *clk, unsigned long rate)
2932 {
2933         u32 reg, div, pre, post;
2934         u32 parent_rate = clk_get_rate(clk->parent);
2935
2936         div = parent_rate / rate;
2937         if (div == 0)
2938                 div++;
2939         if (((parent_rate / div) != rate) || div > 64)
2940                 return -EINVAL;
2941
2942         __calc_pre_post_dividers(1 << 3, div, &pre, &post);
2943
2944         reg = __raw_readl(MXC_CCM_CS1CDR);
2945         reg &= ~(MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK|
2946                  MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK);
2947         reg |= (post - 1) << MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET;
2948         reg |= (pre - 1) << MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET;
2949
2950         __raw_writel(reg, MXC_CCM_CS1CDR);
2951
2952         return 0;
2953 }
2954
2955 static struct clk esai_clk = {
2956         __INIT_CLK_DEBUG(esai_clk)
2957          .id = 0,
2958          .parent = &pll3_sw_clk,
2959          .enable_reg = MXC_CCM_CCGR1,
2960          .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET,
2961          .enable = _clk_enable,
2962          .disable = _clk_disable,
2963          .set_rate = _clk_esai_set_rate,
2964          .get_rate = _clk_esai_get_rate,
2965          .set_parent = _clk_esai_set_parent,
2966          .round_rate = _clk_esai_round_rate,
2967 };
2968
2969 static int _clk_enet_enable(struct clk *clk)
2970 {
2971         unsigned int reg;
2972
2973         /* Enable ENET ref clock */
2974         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
2975         reg &= ~ANADIG_PLL_BYPASS;
2976         reg &= ~ANADIG_PLL_ENABLE;
2977         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
2978
2979         _clk_enable(clk);
2980         return 0;
2981 }
2982
2983 static void _clk_enet_disable(struct clk *clk)
2984 {
2985         unsigned int reg;
2986
2987         _clk_disable(clk);
2988
2989         /* Enable ENET ref clock */
2990         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
2991         reg |= ANADIG_PLL_BYPASS;
2992         reg |= ANADIG_PLL_ENABLE;
2993         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
2994 }
2995
2996 static int _clk_enet_set_rate(struct clk *clk, unsigned long rate)
2997 {
2998         unsigned int reg, div = 1;
2999
3000         switch (rate) {
3001         case 25000000:
3002                 div = 0;
3003                 break;
3004         case 50000000:
3005                 div = 1;
3006                 break;
3007         case 100000000:
3008                 div = 2;
3009                 break;
3010         case 125000000:
3011                 div = 3;
3012                 break;
3013         default:
3014                 return -EINVAL;
3015         }
3016         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
3017         reg &= ~ANADIG_PLL_ENET_DIV_SELECT_MASK;
3018         reg |= (div << ANADIG_PLL_ENET_DIV_SELECT_OFFSET);
3019         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
3020
3021         return 0;
3022 }
3023
3024 static unsigned long _clk_enet_get_rate(struct clk *clk)
3025 {
3026         unsigned int div;
3027
3028         div = (__raw_readl(PLL8_ENET_BASE_ADDR))
3029                 & ANADIG_PLL_ENET_DIV_SELECT_MASK;
3030
3031         return 500000000 / (div + 1);
3032 }
3033
3034 static struct clk enet_clk = {
3035         __INIT_CLK_DEBUG(enet_clk)
3036          .id = 0,
3037          .parent = &pll8_enet_main_clk,
3038          .enable_reg = MXC_CCM_CCGR1,
3039          .enable_shift = MXC_CCM_CCGRx_CG5_OFFSET,
3040          .enable = _clk_enet_enable,
3041          .disable = _clk_enet_disable,
3042          .set_rate = _clk_enet_set_rate,
3043          .get_rate = _clk_enet_get_rate,
3044 };
3045
3046 static struct clk ecspi_clk[] = {
3047         {
3048         __INIT_CLK_DEBUG(ecspi0_clk)
3049         .id = 0,
3050         .parent = &pll3_60M,
3051         .enable_reg = MXC_CCM_CCGR1,
3052         .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET,
3053         .enable = _clk_enable,
3054         .disable = _clk_disable,
3055         },
3056         {
3057         __INIT_CLK_DEBUG(ecspi1_clk)
3058         .id = 1,
3059         .parent = &pll3_60M,
3060         .enable_reg = MXC_CCM_CCGR1,
3061         .enable_shift = MXC_CCM_CCGRx_CG1_OFFSET,
3062         .enable = _clk_enable,
3063         .disable = _clk_disable,
3064         },
3065         {
3066         __INIT_CLK_DEBUG(ecspi2_clk)
3067         .id = 2,
3068         .parent = &pll3_60M,
3069         .enable_reg = MXC_CCM_CCGR1,
3070         .enable_shift = MXC_CCM_CCGRx_CG2_OFFSET,
3071         .enable = _clk_enable,
3072         .disable = _clk_disable,
3073         },
3074         {
3075         __INIT_CLK_DEBUG(ecspi3_clk)
3076         .id = 3,
3077         .parent = &pll3_60M,
3078         .enable_reg = MXC_CCM_CCGR1,
3079         .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET,
3080         .enable = _clk_enable,
3081         .disable = _clk_disable,
3082         },
3083         {
3084         __INIT_CLK_DEBUG(ecspi4_clk)
3085         .id = 4,
3086         .parent = &pll3_60M,
3087         .enable_reg = MXC_CCM_CCGR1,
3088         .enable_shift = MXC_CCM_CCGRx_CG4_OFFSET,
3089         .enable = _clk_enable,
3090         .disable = _clk_disable,
3091         },
3092 };
3093
3094 static unsigned long _clk_emi_slow_round_rate(struct clk *clk,
3095                                                 unsigned long rate)
3096 {
3097         u32 div;
3098         u32 parent_rate = clk_get_rate(clk->parent);
3099
3100         div = parent_rate / rate;
3101
3102         /* Make sure rate is not greater than the maximum value for the clock.
3103          * Also prevent a div of 0.
3104          */
3105         if (div == 0)
3106                 div++;
3107
3108         if (div > 8)
3109                 div = 8;
3110
3111         return parent_rate / div;
3112 }
3113
3114 static int _clk_emi_slow_set_parent(struct clk *clk, struct clk *parent)
3115 {
3116         int mux;
3117         u32 reg = __raw_readl(MXC_CCM_CSCMR1)
3118                 & ~MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK;
3119
3120         mux = _get_mux6(parent, &axi_clk, &pll3_usb_otg_main_clk,
3121                                 &pll2_pfd_400M, &pll2_pfd_352M, NULL, NULL);
3122         reg |= (mux << MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET);
3123         __raw_writel(reg, MXC_CCM_CSCMR1);
3124
3125         return 0;
3126 }
3127
3128 static unsigned long _clk_emi_slow_get_rate(struct clk *clk)
3129 {
3130         u32 reg, div;
3131
3132         reg = __raw_readl(MXC_CCM_CSCMR1);
3133         div = ((reg & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK) >>
3134                         MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET) + 1;
3135
3136         return clk_get_rate(clk->parent) / div;
3137 }
3138
3139 static int _clk_emi_slow_set_rate(struct clk *clk, unsigned long rate)
3140 {
3141         u32 reg, div;
3142         u32 parent_rate = clk_get_rate(clk->parent);
3143
3144         div = parent_rate / rate;
3145         if (div == 0)
3146                 div++;
3147         if (((parent_rate / div) != rate) || (div > 8))
3148                 return -EINVAL;
3149
3150         reg = __raw_readl(MXC_CCM_CSCMR1);
3151         reg &= ~MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK;
3152         reg |= (div - 1) << MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET;
3153         __raw_writel(reg, MXC_CCM_CSCMR1);
3154
3155         return 0;
3156 }
3157
3158 static struct clk emi_slow_clk = {
3159         __INIT_CLK_DEBUG(emi_slow_clk)
3160          .id = 0,
3161          .parent = &axi_clk,
3162          .enable_reg = MXC_CCM_CCGR6,
3163          .enable_shift = MXC_CCM_CCGRx_CG5_OFFSET,
3164          .enable = _clk_enable,
3165          .disable = _clk_disable,
3166          .set_rate = _clk_emi_slow_set_rate,
3167          .get_rate = _clk_emi_slow_get_rate,
3168          .round_rate = _clk_emi_slow_round_rate,
3169          .set_parent = _clk_emi_slow_set_parent,
3170 };
3171
3172 static unsigned long _clk_emi_round_rate(struct clk *clk,
3173                                                 unsigned long rate)
3174 {
3175         u32 div;
3176         u32 parent_rate = clk_get_rate(clk->parent);
3177
3178         div = parent_rate / rate;
3179
3180         /* Make sure rate is not greater than the maximum value for the clock.
3181          * Also prevent a div of 0.
3182          */
3183         if (div == 0)
3184                 div++;
3185
3186         if (div > 8)
3187                 div = 8;
3188
3189         return parent_rate / div;
3190 }
3191
3192 static int _clk_emi_set_parent(struct clk *clk, struct clk *parent)
3193 {
3194         int mux;
3195         u32 reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_ACLK_EMI_MASK;
3196
3197         mux = _get_mux6(parent, &axi_clk, &pll3_usb_otg_main_clk,
3198                         &pll2_pfd_400M, &pll2_pfd_352M, NULL, NULL);
3199         reg |= (mux << MXC_CCM_CSCMR1_ACLK_EMI_OFFSET);
3200         __raw_writel(reg, MXC_CCM_CSCMR1);
3201
3202         return 0;
3203 }
3204
3205 static unsigned long _clk_emi_get_rate(struct clk *clk)
3206 {
3207         u32 reg, div;
3208
3209         reg = __raw_readl(MXC_CCM_CSCMR1);
3210         div = ((reg & MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK) >>
3211                         MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET) + 1;
3212
3213         return clk_get_rate(clk->parent) / div;
3214 }
3215
3216 static int _clk_emi_set_rate(struct clk *clk, unsigned long rate)
3217 {
3218         u32 reg, div;
3219         u32 parent_rate = clk_get_rate(clk->parent);
3220
3221         div = parent_rate / rate;
3222         if (div == 0)
3223                 div++;
3224         if (((parent_rate / div) != rate) || (div > 8))
3225                 return -EINVAL;
3226
3227         reg = __raw_readl(MXC_CCM_CSCMR1);
3228         reg &= ~MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK;
3229         reg |= (div - 1) << MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET;
3230         __raw_writel(reg, MXC_CCM_CSCMR1);
3231
3232         return 0;
3233 }
3234
3235 static struct clk emi_clk = {
3236         __INIT_CLK_DEBUG(emi_clk)
3237          .id = 0,
3238          .parent = &axi_clk,
3239          .set_rate = _clk_emi_set_rate,
3240          .get_rate = _clk_emi_get_rate,
3241          .round_rate = _clk_emi_round_rate,
3242          .set_parent = _clk_emi_set_parent,
3243 };
3244
3245 static unsigned long _clk_enfc_round_rate(struct clk *clk,
3246                                                 unsigned long rate)
3247 {
3248         u32 pre, post;
3249         u32 parent_rate = clk_get_rate(clk->parent);
3250         u32 div = parent_rate / rate;
3251
3252         if (parent_rate % rate)
3253                 div++;
3254
3255         __calc_pre_post_dividers(1 << 6, div, &pre, &post);
3256
3257         return parent_rate / (pre * post);
3258 }
3259
3260 static int _clk_enfc_set_parent(struct clk *clk, struct clk *parent)
3261 {
3262         u32 reg, mux;
3263
3264         reg = __raw_readl(MXC_CCM_CS2CDR)
3265                 & ~MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK;
3266
3267         mux = _get_mux6(parent, &pll2_pfd_352M,
3268                 &pll2_528_bus_main_clk, &pll3_usb_otg_main_clk,
3269                 &pll2_pfd_400M, NULL, NULL);
3270         reg |= mux << MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET;
3271
3272         __raw_writel(reg, MXC_CCM_CS2CDR);
3273
3274         return 0;
3275 }
3276
3277 static unsigned long _clk_enfc_get_rate(struct clk *clk)
3278 {
3279         u32 reg, pred, podf;
3280
3281         reg = __raw_readl(MXC_CCM_CS2CDR);
3282
3283         pred = ((reg & MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK)
3284                 >> MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET) + 1;
3285         podf = ((reg & MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK)
3286                 >> MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET) + 1;
3287
3288         return clk_get_rate(clk->parent) / (pred * podf);
3289 }
3290
3291 static int _clk_enfc_set_rate(struct clk *clk, unsigned long rate)
3292 {
3293         u32 reg, div, pre, post;
3294         u32 parent_rate = clk_get_rate(clk->parent);
3295
3296         div = parent_rate / rate;
3297         if (div == 0)
3298                 div++;
3299         if (((parent_rate / div) != rate) || div > 512)
3300                 return -EINVAL;
3301
3302         __calc_pre_post_dividers(1 << 6, div, &pre, &post);
3303
3304         reg = __raw_readl(MXC_CCM_CS2CDR);
3305         reg &= ~(MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK|
3306                  MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK);
3307         reg |= (post - 1) << MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET;
3308         reg |= (pre - 1) << MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET;
3309
3310         __raw_writel(reg, MXC_CCM_CS2CDR);
3311
3312         return 0;
3313 }
3314
3315 static struct clk enfc_clk = {
3316         __INIT_CLK_DEBUG(enfc_clk)
3317          .id = 0,
3318          .parent = &pll2_pfd_352M,
3319          .enable_reg = MXC_CCM_CCGR2,
3320          .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
3321          .enable = _clk_enable,
3322          .disable = _clk_disable,
3323          .set_rate = _clk_enfc_set_rate,
3324          .get_rate = _clk_enfc_get_rate,
3325          .round_rate = _clk_enfc_round_rate,
3326          .set_parent = _clk_enfc_set_parent,
3327 };
3328
3329 static unsigned long _clk_uart_round_rate(struct clk *clk,
3330                                                 unsigned long rate)
3331 {
3332         u32 div;
3333         u32 parent_rate = clk_get_rate(clk->parent);
3334
3335         div = parent_rate / rate;
3336
3337         /* Make sure rate is not greater than the maximum value for the clock.
3338          * Also prevent a div of 0.
3339          */
3340         if (div == 0)
3341                 div++;
3342
3343         if (div > 64)
3344                 div = 64;
3345
3346         return parent_rate / div;
3347 }
3348
3349 static int _clk_uart_set_rate(struct clk *clk, unsigned long rate)
3350 {
3351         u32 reg, div;
3352         u32 parent_rate = clk_get_rate(clk->parent);
3353
3354         div = parent_rate / rate;
3355         if (div == 0)
3356                 div++;
3357         if (((parent_rate / div) != rate) || (div > 64))
3358                 return -EINVAL;
3359
3360         reg = __raw_readl(MXC_CCM_CSCDR1) & MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
3361         reg |= ((div - 1) << MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET);
3362
3363         __raw_writel(reg, MXC_CCM_CSCDR1);
3364
3365         return 0;
3366 }
3367
3368 static unsigned long _clk_uart_get_rate(struct clk *clk)
3369 {
3370         u32 reg, div;
3371         unsigned long val;
3372
3373         reg = __raw_readl(MXC_CCM_CSCDR1) & MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
3374         div = (reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET) + 1;
3375         val = clk_get_rate(clk->parent) / div;
3376
3377         return val;
3378 }
3379
3380 static struct clk uart_clk[] = {
3381         {
3382         __INIT_CLK_DEBUG(uart_clk)
3383          .id = 0,
3384          .parent = &pll3_80M,
3385          .enable_reg = MXC_CCM_CCGR5,
3386          .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET,
3387          .enable = _clk_enable,
3388          .disable = _clk_disable,
3389          .secondary = &uart_clk[1],
3390          .set_rate = _clk_uart_set_rate,
3391          .get_rate = _clk_uart_get_rate,
3392          .round_rate = _clk_uart_round_rate,
3393         },
3394         {
3395         __INIT_CLK_DEBUG(uart_serial_clk)
3396          .id = 1,
3397          .enable_reg = MXC_CCM_CCGR5,
3398          .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
3399          .enable = _clk_enable,
3400          .disable = _clk_disable,
3401         },
3402 };
3403
3404 static unsigned long _clk_hsi_tx_round_rate(struct clk *clk,
3405                                                 unsigned long rate)
3406 {
3407         u32 div;
3408         u32 parent_rate = clk_get_rate(clk->parent);
3409
3410         div = parent_rate / rate;
3411
3412         /* Make sure rate is not greater than the maximum value for the clock.
3413          * Also prevent a div of 0.
3414          */
3415         if (div == 0)
3416                 div++;
3417
3418         if (div > 8)
3419                 div = 8;
3420
3421         return parent_rate / div;
3422 }
3423
3424 static int _clk_hsi_tx_set_parent(struct clk *clk, struct clk *parent)
3425 {
3426         u32 reg = __raw_readl(MXC_CCM_CDCDR) & ~MXC_CCM_CDCDR_HSI_TX_CLK_SEL;
3427
3428         if (parent == &pll2_pfd_400M)
3429                 reg |= (MXC_CCM_CDCDR_HSI_TX_CLK_SEL);
3430
3431         __raw_writel(reg, MXC_CCM_CDCDR);
3432
3433         return 0;
3434 }
3435
3436 static unsigned long _clk_hsi_tx_get_rate(struct clk *clk)
3437 {
3438         u32 reg, div;
3439
3440         reg = __raw_readl(MXC_CCM_CDCDR);
3441         div = ((reg & MXC_CCM_CDCDR_HSI_TX_PODF_MASK) >>
3442                         MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET) + 1;
3443
3444         return clk_get_rate(clk->parent) / div;
3445 }
3446
3447 static int _clk_hsi_tx_set_rate(struct clk *clk, unsigned long rate)
3448 {
3449         u32 reg, div;
3450         u32 parent_rate = clk_get_rate(clk->parent);
3451
3452         div = parent_rate / rate;
3453         if (div == 0)
3454                 div++;
3455         if (((parent_rate / div) != rate) || (div > 8))
3456                 return -EINVAL;
3457
3458         reg = __raw_readl(MXC_CCM_CDCDR);
3459         reg &= ~MXC_CCM_CDCDR_HSI_TX_PODF_MASK;
3460         reg |= (div - 1) << MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET;
3461         __raw_writel(reg, MXC_CCM_CDCDR);
3462
3463         return 0;
3464 }
3465
3466 static struct clk hsi_tx_clk = {
3467          __INIT_CLK_DEBUG(hsi_tx_clk)
3468         .id = 0,
3469          .parent = &pll2_pfd_400M,
3470         .enable_reg = MXC_CCM_CCGR3,
3471         .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET,
3472         .enable = _clk_enable,
3473         .disable = _clk_disable,
3474         .set_parent = _clk_hsi_tx_set_parent,
3475         .round_rate = _clk_hsi_tx_round_rate,
3476         .set_rate = _clk_hsi_tx_set_rate,
3477         .get_rate = _clk_hsi_tx_get_rate,
3478 };
3479
3480 static struct clk hdmi_clk[] = {
3481         {
3482          __INIT_CLK_DEBUG(hdmi_isfr_clk)
3483         .id = 0,
3484         .parent = &pll3_pfd_540M,
3485         .enable_reg = MXC_CCM_CCGR2,
3486         .enable_shift = MXC_CCM_CCGRx_CG2_OFFSET,
3487         .enable = _clk_enable,
3488         .disable = _clk_disable,
3489         },
3490         {
3491          __INIT_CLK_DEBUG(hdmi_iahb_clk)
3492         .id = 1,
3493          .parent = &ahb_clk,
3494         .enable_reg = MXC_CCM_CCGR2,
3495         .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET,
3496         .enable = _clk_enable,
3497         .disable = _clk_disable,
3498         },
3499 };
3500
3501 static struct clk caam_clk[] = {
3502         {
3503          __INIT_CLK_DEBUG(caam_mem_clk)
3504         .id = 0,
3505         .enable_reg = MXC_CCM_CCGR0,
3506         .enable_shift = MXC_CCM_CCGRx_CG4_OFFSET,
3507         .enable = _clk_enable,
3508         .disable = _clk_disable,
3509         .secondary = &caam_clk[1],
3510         },
3511         {
3512          __INIT_CLK_DEBUG(caam_aclk_clk)
3513         .id = 1,
3514         .enable_reg = MXC_CCM_CCGR0,
3515         .enable_shift = MXC_CCM_CCGRx_CG5_OFFSET,
3516         .enable = _clk_enable,
3517         .disable = _clk_disable,
3518         },
3519         {
3520          __INIT_CLK_DEBUG(caam_ipg_clk)
3521         .id = 2,
3522         .enable_reg = MXC_CCM_CCGR0,
3523         .enable_shift = MXC_CCM_CCGRx_CG4_OFFSET,
3524         .enable = _clk_enable,
3525         .disable = _clk_disable,
3526         },
3527 };
3528
3529 static int _clk_asrc_serial_set_parent(struct clk *clk, struct clk *parent)
3530 {
3531         u32 reg, mux;
3532
3533         reg = __raw_readl(MXC_CCM_CDCDR) & ~MXC_CCM_CDCDR_SPDIF1_CLK_SEL_MASK;
3534
3535         mux = _get_mux6(parent, &pll4_audio_main_clk, &pll3_pfd_508M,
3536                         &pll3_pfd_454M, &pll3_sw_clk, NULL, NULL);
3537         reg |= mux << MXC_CCM_CDCDR_SPDIF1_CLK_SEL_OFFSET;
3538
3539         __raw_writel(reg, MXC_CCM_CDCDR);
3540
3541         return 0;
3542 }
3543
3544 static unsigned long _clk_asrc_serial_get_rate(struct clk *clk)
3545 {
3546         u32 reg, pred, podf;
3547
3548         reg = __raw_readl(MXC_CCM_CDCDR);
3549
3550         pred = ((reg & MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK)
3551                 >> MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET) + 1;
3552         podf = ((reg & MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK)
3553                 >> MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET) + 1;
3554
3555         return clk_get_rate(clk->parent) / (pred * podf);
3556 }
3557
3558 static int _clk_asrc_serial_set_rate(struct clk *clk, unsigned long rate)
3559 {
3560         u32 reg, div, pre, post;
3561         u32 parent_rate = clk_get_rate(clk->parent);
3562
3563         div = parent_rate / rate;
3564         if (div == 0)
3565                 div++;
3566         if (((parent_rate / div) != rate) || div > 64)
3567                 return -EINVAL;
3568
3569         __calc_pre_post_dividers(1 << 3, div, &pre, &post);
3570
3571         reg = __raw_readl(MXC_CCM_CDCDR);
3572         reg &= ~(MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK|
3573                  MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK);
3574         reg |= (post - 1) << MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET;
3575         reg |= (pre - 1) << MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET;
3576
3577         __raw_writel(reg, MXC_CCM_CDCDR);
3578
3579         return 0;
3580 }
3581
3582 static unsigned long _clk_asrc_serial_round_rate(struct clk *clk,
3583                                                 unsigned long rate)
3584 {
3585         u32 pre, post;
3586         u32 parent_rate = clk_get_rate(clk->parent);
3587         u32 div = parent_rate / rate;
3588
3589         if (parent_rate % rate)
3590                 div++;
3591
3592         __calc_pre_post_dividers(1 << 3, div, &pre, &post);
3593
3594         return parent_rate / (pre * post);
3595 }
3596
3597 static struct clk asrc_clk[] = {
3598         {
3599         __INIT_CLK_DEBUG(asrc_clk)
3600         .id = 0,
3601         .parent = &pll4_audio_main_clk,
3602         .enable_reg = MXC_CCM_CCGR0,
3603         .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET,
3604         .enable = _clk_enable,
3605         .disable = _clk_disable,
3606         },
3607         {
3608         /*In the MX6 spec, asrc_serial_clk is listed as SPDIF1 clk
3609          * This clock can never be gated and does  not have any
3610          * CCGR bits associated with it.
3611          */
3612         __INIT_CLK_DEBUG(asrc_serial_clk)
3613         .id = 1,
3614         .parent = &pll3_sw_clk,
3615          .set_rate = _clk_asrc_serial_set_rate,
3616          .get_rate = _clk_asrc_serial_get_rate,
3617          .set_parent = _clk_asrc_serial_set_parent,
3618          .round_rate = _clk_asrc_serial_round_rate,
3619         },
3620 };
3621
3622 static struct clk apbh_dma_clk = {
3623         __INIT_CLK_DEBUG(apbh_dma_clk)
3624         .parent = &usdhc3_clk,
3625         .enable = _clk_enable,
3626         .disable = _clk_disable_inwait,
3627         .enable_reg = MXC_CCM_CCGR0,
3628         .enable_shift = MXC_CCM_CCGRx_CG2_OFFSET,
3629 };
3630
3631 static struct clk aips_tz2_clk = {
3632         __INIT_CLK_DEBUG(aips_tz2_clk)
3633         .parent = &ahb_clk,
3634         .enable_reg = MXC_CCM_CCGR0,
3635         .enable_shift = MXC_CCM_CCGRx_CG1_OFFSET,
3636         .enable = _clk_enable,
3637         .disable = _clk_disable_inwait,
3638 };
3639
3640 static struct clk aips_tz1_clk = {
3641         __INIT_CLK_DEBUG(aips_tz1_clk)
3642         .parent = &ahb_clk,
3643         .enable_reg = MXC_CCM_CCGR0,
3644         .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET,
3645         .enable = _clk_enable,
3646         .disable = _clk_disable_inwait,
3647 };
3648
3649
3650 static struct clk openvg_axi_clk = {
3651         __INIT_CLK_DEBUG(openvg_axi_clk)
3652         .enable = _clk_enable,
3653         .enable_reg = MXC_CCM_CCGR3,
3654         .enable_shift = MXC_CCM_CCGRx_CG15_OFFSET,
3655         .disable = _clk_disable,
3656 };
3657
3658 static unsigned long _clk_gpu3d_core_round_rate(struct clk *clk,
3659                                                 unsigned long rate)
3660 {
3661         u32 div;
3662         u32 parent_rate = clk_get_rate(clk->parent);
3663
3664         div = parent_rate / rate;
3665
3666         /* Make sure rate is not greater than the maximum value for the clock.
3667          * Also prevent a div of 0.
3668          */
3669         if (div == 0)
3670                 div++;
3671
3672         if (div > 8)
3673                 div = 8;
3674
3675         return parent_rate / div;
3676 }
3677
3678 static int _clk_gpu3d_core_set_parent(struct clk *clk, struct clk *parent)
3679 {
3680         int mux;
3681         u32 reg = __raw_readl(MXC_CCM_CBCMR)
3682                 & ~MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK;
3683
3684         mux = _get_mux6(parent, &mmdc_ch0_axi_clk[0],
3685                 &pll3_usb_otg_main_clk,
3686                 &pll2_pfd_594M, &pll2_pfd_400M, NULL, NULL);
3687         reg |= (mux << MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET);
3688         __raw_writel(reg, MXC_CCM_CBCMR);
3689
3690         return 0;
3691 }
3692
3693 static unsigned long _clk_gpu3d_core_get_rate(struct clk *clk)
3694 {
3695         u32 reg, div;
3696
3697         reg = __raw_readl(MXC_CCM_CBCMR);
3698         div = ((reg & MXC_CCM_CBCMR_GPU3D_CORE_PODF_MASK) >>
3699                         MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET) + 1;
3700
3701         return clk_get_rate(clk->parent) / div;
3702 }
3703
3704 static int _clk_gpu3d_core_set_rate(struct clk *clk, unsigned long rate)
3705 {
3706         u32 reg, div;
3707         u32 parent_rate = clk_get_rate(clk->parent);
3708
3709         div = parent_rate / rate;
3710         if (div == 0)
3711                 div++;
3712         if (div > 8)
3713                 div = 8;
3714
3715         reg = __raw_readl(MXC_CCM_CBCMR);
3716         reg &= ~MXC_CCM_CBCMR_GPU3D_CORE_PODF_MASK;
3717         reg |= (div - 1) << MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET;
3718         __raw_writel(reg, MXC_CCM_CBCMR);
3719
3720         return 0;
3721 }
3722
3723 static struct clk gpu3d_core_clk = {
3724         __INIT_CLK_DEBUG(gpu3d_core_clk)
3725         .parent = &pll2_pfd_594M,
3726         .secondary = &gpu3d_axi_clk,
3727         .enable = _clk_enable,
3728         .enable_reg = MXC_CCM_CCGR1,
3729         .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
3730         .disable = _clk_disable,
3731         .set_parent = _clk_gpu3d_core_set_parent,
3732         .set_rate = _clk_gpu3d_core_set_rate,
3733         .get_rate = _clk_gpu3d_core_get_rate,
3734         .round_rate = _clk_gpu3d_core_round_rate,
3735 };
3736
3737 static unsigned long _clk_gpu2d_core_round_rate(struct clk *clk,
3738                                                 unsigned long rate)
3739 {
3740         u32 div;
3741         u32 parent_rate = clk_get_rate(clk->parent);
3742
3743         div = parent_rate / rate;
3744
3745         /* Make sure rate is not greater than the maximum value for the clock.
3746          * Also prevent a div of 0.
3747          */
3748         if (div == 0)
3749                 div++;
3750
3751         if (div > 8)
3752                 div = 8;
3753
3754         return parent_rate / div;
3755 }
3756
3757 static int _clk_gpu2d_core_set_parent(struct clk *clk, struct clk *parent)
3758 {
3759         int mux;
3760         u32 reg = __raw_readl(MXC_CCM_CBCMR) &
3761                                 ~MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK;
3762
3763         mux = _get_mux6(parent, &axi_clk, &pll3_usb_otg_main_clk,
3764                 &pll2_pfd_352M, &pll2_pfd_400M, NULL, NULL);
3765         reg |= (mux << MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET);
3766         __raw_writel(reg, MXC_CCM_CBCMR);
3767
3768         return 0;
3769 }
3770
3771 static unsigned long _clk_gpu2d_core_get_rate(struct clk *clk)
3772 {
3773         u32 reg, div;
3774
3775         reg = __raw_readl(MXC_CCM_CBCMR);
3776         div = ((reg & MXC_CCM_CBCMR_GPU2D_CORE_PODF_MASK) >>
3777                         MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET) + 1;
3778
3779         return clk_get_rate(clk->parent) / div;
3780 }
3781
3782 static int _clk_gpu2d_core_set_rate(struct clk *clk, unsigned long rate)
3783 {
3784         u32 reg, div;
3785         u32 parent_rate = clk_get_rate(clk->parent);
3786
3787         div = parent_rate / rate;
3788         if (div == 0)
3789                 div++;
3790         if (((parent_rate / div) != rate) || (div > 8))
3791                 return -EINVAL;
3792
3793         reg = __raw_readl(MXC_CCM_CBCMR);
3794         reg &= ~MXC_CCM_CBCMR_GPU3D_CORE_PODF_MASK;
3795         reg |= (div - 1) << MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET;
3796         __raw_writel(reg, MXC_CCM_CBCMR);
3797
3798         return 0;
3799 }
3800 static struct clk gpu2d_core_clk = {
3801         __INIT_CLK_DEBUG(gpu2d_core_clk)
3802         .parent = &pll2_pfd_352M,
3803         .secondary = &gpu2d_axi_clk,
3804         .enable = _clk_enable,
3805         .enable_reg = MXC_CCM_CCGR1,
3806         .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET,
3807         .disable = _clk_disable,
3808         .set_parent = _clk_gpu2d_core_set_parent,
3809         .set_rate = _clk_gpu2d_core_set_rate,
3810         .get_rate = _clk_gpu2d_core_get_rate,
3811         .round_rate = _clk_gpu2d_core_round_rate,
3812 };
3813
3814 static unsigned long _clk_gpu3d_shader_round_rate(struct clk *clk,
3815                                                 unsigned long rate)
3816 {
3817         u32 div;
3818         u32 parent_rate = clk_get_rate(clk->parent);
3819
3820         div = parent_rate / rate;
3821
3822         /* Make sure rate is not greater than the maximum value for the clock.
3823          * Also prevent a div of 0.
3824          */
3825         if (div == 0)
3826                 div++;
3827
3828         if (div > 8)
3829                 div = 8;
3830
3831         return parent_rate / div;
3832 }
3833
3834 static int _clk_gpu3d_shader_set_parent(struct clk *clk, struct clk *parent)
3835 {
3836         int mux;
3837         u32 reg = __raw_readl(MXC_CCM_CBCMR)
3838                 & ~MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_MASK;
3839
3840         mux = _get_mux6(parent, &mmdc_ch0_axi_clk[0],
3841                 &pll3_usb_otg_main_clk,
3842                 &pll2_pfd_594M, &pll3_pfd_720M, NULL, NULL);
3843         reg |= (mux << MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET);
3844         __raw_writel(reg, MXC_CCM_CBCMR);
3845
3846         return 0;
3847 }
3848
3849 static unsigned long _clk_gpu3d_shader_get_rate(struct clk *clk)
3850 {
3851         u32 reg, div;
3852
3853         reg = __raw_readl(MXC_CCM_CBCMR);
3854         div = ((reg & MXC_CCM_CBCMR_GPU3D_SHADER_PODF_MASK) >>
3855                         MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET) + 1;
3856
3857         return clk_get_rate(clk->parent) / div;
3858 }
3859
3860 static int _clk_gpu3d_shader_set_rate(struct clk *clk, unsigned long rate)
3861 {
3862         u32 reg, div;
3863         u32 parent_rate = clk_get_rate(clk->parent);
3864
3865         div = parent_rate / rate;
3866         if (div == 0)
3867                 div++;
3868         if (div > 8)
3869                 div = 8;
3870
3871         reg = __raw_readl(MXC_CCM_CBCMR);
3872         reg &= ~MXC_CCM_CBCMR_GPU3D_SHADER_PODF_MASK;
3873         reg |= (div - 1) << MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET;
3874         __raw_writel(reg, MXC_CCM_CBCMR);
3875
3876         return 0;
3877 }
3878
3879
3880 static struct clk gpu3d_shader_clk = {
3881         __INIT_CLK_DEBUG(gpu3d_shader_clk)
3882         .parent = &pll3_pfd_720M,
3883         .enable = _clk_enable,
3884         .enable_reg = MXC_CCM_CCGR1,
3885         .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
3886         .disable = _clk_disable,
3887         .set_parent = _clk_gpu3d_shader_set_parent,
3888         .set_rate = _clk_gpu3d_shader_set_rate,
3889         .get_rate = _clk_gpu3d_shader_get_rate,
3890         .round_rate = _clk_gpu3d_shader_round_rate,
3891 };
3892
3893 /* set the parent by the ipcg table */
3894 static struct clk gpmi_nfc_clk[] = {
3895         {       /* gpmi_io_clk */
3896         __INIT_CLK_DEBUG(gpmi_io_clk)
3897         .parent = &enfc_clk,
3898         .secondary = &gpmi_nfc_clk[1],
3899         .enable = _clk_enable,
3900         .enable_reg = MXC_CCM_CCGR4,
3901         .enable_shift = MXC_CCM_CCGRx_CG14_OFFSET,
3902         .disable = _clk_disable,
3903         },
3904         {       /* gpmi_apb_clk */
3905         __INIT_CLK_DEBUG(gpmi_apb_clk)
3906         .parent = &usdhc3_clk,
3907         .secondary = &gpmi_nfc_clk[2],
3908         .enable = _clk_enable,
3909         .enable_reg = MXC_CCM_CCGR4,
3910         .enable_shift = MXC_CCM_CCGRx_CG15_OFFSET,
3911         .disable = _clk_disable,
3912         },
3913         {       /* bch_clk */
3914         __INIT_CLK_DEBUG(gpmi_bch_clk)
3915         .parent = &usdhc4_clk,
3916         .secondary = &gpmi_nfc_clk[3],
3917         .enable = _clk_enable,
3918         .enable_reg = MXC_CCM_CCGR4,
3919         .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
3920         .disable = _clk_disable,
3921         },
3922         {       /* bch_apb_clk */
3923         __INIT_CLK_DEBUG(gpmi_bch_apb_clk)
3924         .parent = &usdhc3_clk,
3925         .secondary = &gpmi_nfc_clk[4],
3926         .enable = _clk_enable,
3927         .enable_reg = MXC_CCM_CCGR4,
3928         .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET,
3929         .disable = _clk_disable,
3930         },
3931         {       /* bch relative clk */
3932         __INIT_CLK_DEBUG(pl301_mx6qperl_bch)
3933         .parent = &usdhc3_clk,
3934         .enable = _clk_enable,
3935         .enable_reg = MXC_CCM_CCGR4,
3936         .enable_shift = MXC_CCM_CCGRx_CG6_OFFSET,
3937         .disable = _clk_disable,
3938         },
3939 };
3940
3941 static struct clk pwm_clk[] = {
3942         {
3943         __INIT_CLK_DEBUG(pwm_clk_0)
3944          .parent = &ipg_perclk,
3945          .id = 0,
3946          .enable_reg = MXC_CCM_CCGR4,
3947          .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET,
3948          .enable = _clk_enable,
3949          .disable = _clk_disable,
3950          },
3951         {
3952         __INIT_CLK_DEBUG(pwm_clk_1)
3953          .parent = &ipg_perclk,
3954          .id = 1,
3955          .enable_reg = MXC_CCM_CCGR4,
3956          .enable_shift = MXC_CCM_CCGRx_CG9_OFFSET,
3957          .enable = _clk_enable,
3958          .disable = _clk_disable,
3959          },
3960         {
3961         __INIT_CLK_DEBUG(pwm_clk_2)
3962          .parent = &ipg_perclk,
3963          .id = 2,
3964          .enable_reg = MXC_CCM_CCGR4,
3965          .enable_shift = MXC_CCM_CCGRx_CG10_OFFSET,
3966          .enable = _clk_enable,
3967          .disable = _clk_disable,
3968          },
3969         {
3970         __INIT_CLK_DEBUG(pwm_clk_3)
3971          .parent = &ipg_perclk,
3972          .id = 3,
3973          .enable_reg = MXC_CCM_CCGR4,
3974          .enable_shift = MXC_CCM_CCGRx_CG11_OFFSET,
3975          .enable = _clk_enable,
3976          .disable = _clk_disable,
3977          },
3978 };
3979
3980 static int _clk_pcie_enable(struct clk *clk)
3981 {
3982         unsigned int reg;
3983
3984         /* Enable SATA ref clock */
3985         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
3986         reg |= ANADIG_PLL_ENET_EN_PCIE;
3987         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
3988
3989         _clk_enable(clk);
3990
3991         return 0;
3992 }
3993
3994 static void _clk_pcie_disable(struct clk *clk)
3995 {
3996         unsigned int reg;
3997
3998         _clk_disable(clk);
3999
4000         /* Disable SATA ref clock */
4001         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
4002         reg &= ~ANADIG_PLL_ENET_EN_PCIE;
4003         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
4004 }
4005
4006 static struct clk pcie_clk = {
4007         __INIT_CLK_DEBUG(pcie_clk)
4008         .parent = &pcie_axi_clk,
4009         .enable = _clk_pcie_enable,
4010         .disable = _clk_pcie_disable,
4011         .enable_reg = MXC_CCM_CCGR4,
4012         .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET,
4013 };
4014
4015 static int _clk_sata_enable(struct clk *clk)
4016 {
4017         unsigned int reg;
4018
4019         /* Clear Power Down and Enable PLLs */
4020         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
4021         reg &= ~ANADIG_PLL_ENET_POWER_DOWN;
4022         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
4023
4024         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
4025         reg |= ANADIG_PLL_ENET_EN;
4026         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
4027
4028         /* Waiting for the PLL is locked */
4029         if (!WAIT(ANADIG_PLL_ENET_LOCK & __raw_readl(PLL8_ENET_BASE_ADDR),
4030                                 SPIN_DELAY))
4031                 panic("pll8 lock failed\n");
4032
4033         /* Disable the bypass */
4034         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
4035         reg &= ~ANADIG_PLL_ENET_BYPASS;
4036         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
4037
4038         /* Enable SATA ref clock */
4039         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
4040         reg |= ANADIG_PLL_ENET_EN_SATA;
4041         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
4042
4043         _clk_enable(clk);
4044
4045         return 0;
4046 }
4047
4048 static void _clk_sata_disable(struct clk *clk)
4049 {
4050         unsigned int reg;
4051
4052         _clk_disable(clk);
4053
4054         /* Disable SATA ref clock */
4055         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
4056         reg &= ~ANADIG_PLL_ENET_EN_SATA;
4057         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
4058 }
4059
4060 static struct clk sata_clk = {
4061         __INIT_CLK_DEBUG(sata_clk)
4062         .parent = &ipg_clk,
4063         .enable = _clk_sata_enable,
4064         .enable_reg = MXC_CCM_CCGR5,
4065         .enable_shift = MXC_CCM_CCGRx_CG2_OFFSET,
4066         .disable = _clk_sata_disable,
4067 };
4068
4069 static struct clk usboh3_clk = {
4070         __INIT_CLK_DEBUG(usboh3_clk)
4071         .parent = &ipg_clk,
4072         .enable = _clk_enable,
4073         .enable_reg = MXC_CCM_CCGR6,
4074         .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET,
4075         .disable = _clk_disable,
4076 };
4077
4078 static struct clk dummy_clk = {
4079         .id = 0,
4080 };
4081
4082 #define _REGISTER_CLOCK(d, n, c) \
4083         { \
4084                 .dev_id = d, \
4085                 .con_id = n, \
4086                 .clk = &c, \
4087         }
4088
4089
4090 static struct clk_lookup lookups[] = {
4091         _REGISTER_CLOCK(NULL, "osc", osc_clk),
4092         _REGISTER_CLOCK(NULL, "ckih", ckih_clk),
4093         _REGISTER_CLOCK(NULL, "ckih2", ckih2_clk),
4094         _REGISTER_CLOCK(NULL, "ckil", ckil_clk),
4095         _REGISTER_CLOCK(NULL, "pll1_main_clk", pll1_sys_main_clk),
4096         _REGISTER_CLOCK(NULL, "pll1_sw_clk", pll1_sw_clk),
4097         _REGISTER_CLOCK(NULL, "pll2", pll2_528_bus_main_clk),
4098         _REGISTER_CLOCK(NULL, "pll2_pfd_400M", pll2_pfd_400M),
4099         _REGISTER_CLOCK(NULL, "pll2_pfd_352M", pll2_pfd_352M),
4100         _REGISTER_CLOCK(NULL, "pll2_pfd_594M", pll2_pfd_594M),
4101         _REGISTER_CLOCK(NULL, "pll2_200M", pll2_200M),
4102         _REGISTER_CLOCK(NULL, "pll3_main_clk", pll3_usb_otg_main_clk),
4103         _REGISTER_CLOCK(NULL, "pll3_pfd_508M", pll3_pfd_508M),
4104         _REGISTER_CLOCK(NULL, "pll3_pfd_454M", pll3_pfd_454M),
4105         _REGISTER_CLOCK(NULL, "pll3_pfd_720M", pll3_pfd_720M),
4106         _REGISTER_CLOCK(NULL, "pll3_pfd_540M", pll3_pfd_540M),
4107         _REGISTER_CLOCK(NULL, "pll3_sw_clk", pll3_sw_clk),
4108         _REGISTER_CLOCK(NULL, "pll3_120M", pll3_120M),
4109         _REGISTER_CLOCK(NULL, "pll3_120M", pll3_80M),
4110         _REGISTER_CLOCK(NULL, "pll3_120M", pll3_60M),
4111         _REGISTER_CLOCK(NULL, "pll4", pll4_audio_main_clk),
4112         _REGISTER_CLOCK(NULL, "pll5", pll5_video_main_clk),
4113         _REGISTER_CLOCK(NULL, "pll4", pll6_MLB_main_clk),
4114         _REGISTER_CLOCK(NULL, "pll3", pll7_usb_host_main_clk),
4115         _REGISTER_CLOCK(NULL, "pll4", pll8_enet_main_clk),
4116         _REGISTER_CLOCK(NULL, "cpu_clk", cpu_clk),
4117         _REGISTER_CLOCK(NULL, "periph_clk", periph_clk),
4118         _REGISTER_CLOCK(NULL, "axi_clk", axi_clk),
4119         _REGISTER_CLOCK(NULL, "mmdc_ch0_axi", mmdc_ch0_axi_clk[0]),
4120         _REGISTER_CLOCK(NULL, "mmdc_ch1_axi", mmdc_ch1_axi_clk[0]),
4121         _REGISTER_CLOCK(NULL, "ahb", ahb_clk),
4122         _REGISTER_CLOCK(NULL, "ipg_clk", ipg_clk),
4123         _REGISTER_CLOCK(NULL, "ipg_perclk", ipg_perclk),
4124         _REGISTER_CLOCK(NULL, "spba", spba_clk),
4125         _REGISTER_CLOCK("imx-sdma", NULL, sdma_clk),
4126         _REGISTER_CLOCK(NULL, "gpu2d_axi_clk", gpu2d_axi_clk),
4127         _REGISTER_CLOCK(NULL, "gpu3d_axi_clk", gpu3d_axi_clk),
4128         _REGISTER_CLOCK(NULL, "pcie_axi_clk", pcie_axi_clk),
4129         _REGISTER_CLOCK(NULL, "vdo_axi_clk", vdo_axi_clk),
4130         _REGISTER_CLOCK(NULL, "iim_clk", iim_clk),
4131         _REGISTER_CLOCK(NULL, "i2c_clk", i2c_clk[0]),
4132         _REGISTER_CLOCK("imx-i2c.1", NULL, i2c_clk[1]),
4133         _REGISTER_CLOCK("imx-i2c.2", NULL, i2c_clk[2]),
4134         _REGISTER_CLOCK(NULL, "vpu_clk", vpu_clk),
4135         _REGISTER_CLOCK(NULL, "ipu1_clk", ipu1_clk),
4136         _REGISTER_CLOCK(NULL, "ipu2_clk", ipu2_clk),
4137         _REGISTER_CLOCK("sdhci-esdhc-imx.0", NULL, usdhc1_clk),
4138         _REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL, usdhc2_clk),
4139         _REGISTER_CLOCK("sdhci-esdhc-imx.2", NULL, usdhc3_clk),
4140         _REGISTER_CLOCK("sdhci-esdhc-imx.3", NULL, usdhc4_clk),
4141         _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk),
4142         _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk),
4143         _REGISTER_CLOCK("imx-ssi.2", NULL, ssi3_clk),
4144         _REGISTER_CLOCK(NULL, "ipu1_di0_clk", ipu1_di_clk[0]),
4145         _REGISTER_CLOCK(NULL, "ipu1_di1_clk", ipu1_di_clk[1]),
4146         _REGISTER_CLOCK(NULL, "ipu2_di0_clk", ipu2_di_clk[0]),
4147         _REGISTER_CLOCK(NULL, "ipu2_di1_clk", ipu2_di_clk[1]),
4148         _REGISTER_CLOCK("FlexCAN.0", "can_clk", can1_clk[0]),
4149         _REGISTER_CLOCK("FlexCAN.1", "can_clk", can2_clk[0]),
4150         _REGISTER_CLOCK(NULL, "ldb_di0_clk", ldb_di0_clk),
4151         _REGISTER_CLOCK(NULL, "ldb_di1_clk", ldb_di1_clk),
4152         _REGISTER_CLOCK(NULL, "mxc_alsa_spdif.0", spdif0_clk[0]),
4153         _REGISTER_CLOCK(NULL, "esai_clk", esai_clk),
4154         _REGISTER_CLOCK("mxc_spi.0", NULL, ecspi_clk[0]),
4155         _REGISTER_CLOCK("mxc_spi.1", NULL, ecspi_clk[1]),
4156         _REGISTER_CLOCK("mxc_spi.2", NULL, ecspi_clk[2]),
4157         _REGISTER_CLOCK("mxc_spi.3", NULL, ecspi_clk[3]),
4158         _REGISTER_CLOCK("mxc_spi.4", NULL, ecspi_clk[4]),
4159         _REGISTER_CLOCK(NULL, "emi_slow_clk", emi_slow_clk),
4160         _REGISTER_CLOCK(NULL, "emi_clk", emi_clk),
4161         _REGISTER_CLOCK(NULL, "enfc_clk", enfc_clk),
4162         _REGISTER_CLOCK("imx-uart.0", NULL, uart_clk[0]),
4163         _REGISTER_CLOCK(NULL, "hsi_tx", hsi_tx_clk),
4164         _REGISTER_CLOCK(NULL, "caam_clk", caam_clk[0]),
4165         _REGISTER_CLOCK(NULL, "asrc_clk", asrc_clk[0]),
4166         _REGISTER_CLOCK(NULL, "asrc_serial_clk", asrc_clk[1]),
4167         _REGISTER_CLOCK("mxs-dma-apbh", NULL, apbh_dma_clk),
4168         _REGISTER_CLOCK(NULL, "openvg_axi_clk", openvg_axi_clk),
4169         _REGISTER_CLOCK(NULL, "gpu3d_clk", gpu3d_core_clk),
4170         _REGISTER_CLOCK(NULL, "gpu2d_clk", gpu2d_core_clk),
4171         _REGISTER_CLOCK(NULL, "gpu3d_shader_clk", gpu3d_shader_clk),
4172         _REGISTER_CLOCK(NULL, "gpt", gpt_clk[0]),
4173         _REGISTER_CLOCK("imx6q-gpmi-nfc.0", NULL, gpmi_nfc_clk[0]),
4174         _REGISTER_CLOCK(NULL, "gpmi-apb", gpmi_nfc_clk[1]),
4175         _REGISTER_CLOCK(NULL, "bch", gpmi_nfc_clk[2]),
4176         _REGISTER_CLOCK(NULL, "bch-apb", gpmi_nfc_clk[3]),
4177         _REGISTER_CLOCK(NULL, "pl301_mx6qperl-bch", gpmi_nfc_clk[4]),
4178         _REGISTER_CLOCK("mxc_pwm.0", NULL, pwm_clk[0]),
4179         _REGISTER_CLOCK("mxc_pwm.1", NULL, pwm_clk[1]),
4180         _REGISTER_CLOCK("mxc_pwm.2", NULL, pwm_clk[2]),
4181         _REGISTER_CLOCK("mxc_pwm.3", NULL, pwm_clk[3]),
4182         _REGISTER_CLOCK(NULL, "pcie_clk", pcie_clk),
4183         _REGISTER_CLOCK("fec.0", NULL, enet_clk),
4184         _REGISTER_CLOCK(NULL, "imx_sata_clk", sata_clk),
4185         _REGISTER_CLOCK(NULL, "usboh3_clk", usboh3_clk),
4186         _REGISTER_CLOCK(NULL, "usb_phy1_clk", usb_phy1_clk),
4187         _REGISTER_CLOCK("imx2-wdt.0", NULL, dummy_clk),
4188         _REGISTER_CLOCK("imx2-wdt.1", NULL, dummy_clk),
4189         _REGISTER_CLOCK(NULL, "hdmi_isfr_clk", hdmi_clk[0]),
4190         _REGISTER_CLOCK(NULL, "hdmi_iahb_clk", hdmi_clk[1]),
4191         _REGISTER_CLOCK(NULL, NULL, vdoa_clk),
4192         _REGISTER_CLOCK(NULL, NULL, aips_tz2_clk),
4193         _REGISTER_CLOCK(NULL, NULL, aips_tz1_clk),
4194 };
4195
4196
4197 static void clk_tree_init(void)
4198
4199 {
4200         unsigned int reg;
4201
4202         reg = __raw_readl(MMDC_MDMISC_OFFSET);
4203         if ((reg & MMDC_MDMISC_DDR_TYPE_MASK) ==
4204                 (0x1 << MMDC_MDMISC_DDR_TYPE_OFFSET)) {
4205                 clk_set_parent(&periph_clk, &pll2_pfd_400M);
4206                 printk(KERN_INFO "Set periph_clk's parent to pll2_pfd_400M!\n");
4207         }
4208 }
4209
4210
4211 int __init mx6_clocks_init(unsigned long ckil, unsigned long osc,
4212         unsigned long ckih1, unsigned long ckih2)
4213 {
4214         __iomem void *base;
4215         int i;
4216
4217         external_low_reference = ckil;
4218         external_high_reference = ckih1;
4219         ckih2_reference = ckih2;
4220         oscillator_reference = osc;
4221
4222         apll_base = ioremap(ANATOP_BASE_ADDR, SZ_4K);
4223
4224         for (i = 0; i < ARRAY_SIZE(lookups); i++) {
4225                 clkdev_add(&lookups[i]);
4226                 clk_debug_register(lookups[i].clk);
4227         }
4228
4229         clk_tree_init();
4230
4231         /* enable mmdc_ch0_axi_clk to make sure the usecount is > 0
4232          * or ipu's parent is mmdc_ch0_axi_clk, if ipu disable clk,
4233          * mmdc_ch0_axi_clk will also be disabled, system will hang */
4234         clk_enable(&mmdc_ch0_axi_clk[0]);
4235         /* Initialize Audio and Video PLLs to valid frequency (650MHz). */
4236         clk_set_rate(&pll4_audio_main_clk, 650000000);
4237         clk_set_rate(&pll5_video_main_clk, 650000000);
4238
4239         clk_set_parent(&ipu1_di_clk[0], &pll5_video_main_clk);
4240         clk_set_parent(&ipu1_di_clk[1], &pll5_video_main_clk);
4241         clk_set_parent(&ipu2_di_clk[0], &pll5_video_main_clk);
4242         clk_set_parent(&ipu2_di_clk[1], &pll5_video_main_clk);
4243
4244         clk_set_parent(&gpu3d_shader_clk, &pll2_pfd_594M);
4245         clk_set_rate(&gpu3d_shader_clk, 594000000);
4246         clk_set_parent(&gpu3d_core_clk, &mmdc_ch0_axi_clk[0]);
4247         clk_set_rate(&gpu3d_core_clk, 528000000);
4248
4249         /*
4250          * FIXME: asrc needs to use asrc_serial(spdif1) clock to do sample rate convertion,
4251          * however we found it only works when set to 1.5M clock and the
4252          * parent is pll3_sw_clk.
4253          */
4254         clk_set_parent(&asrc_clk[1], &pll3_sw_clk);
4255         clk_set_rate(&asrc_clk[1], 1500000);
4256
4257         /* set the NAND to 11MHz. Too fast will cause dma timeout. */
4258         clk_set_rate(&enfc_clk, enfc_clk.round_rate(&enfc_clk, 11000000));
4259
4260         mx6_cpu_op_init();
4261         cpu_op_tbl = get_cpu_op(&cpu_op_nr);
4262
4263         /* Gate off all possible clocks */
4264         if (mxc_jtag_enabled) {
4265                 __raw_writel(3 << MXC_CCM_CCGRx_CG11_OFFSET |
4266                              3 << MXC_CCM_CCGRx_CG2_OFFSET |
4267                              3 << MXC_CCM_CCGRx_CG1_OFFSET |
4268                              3 << MXC_CCM_CCGRx_CG0_OFFSET, MXC_CCM_CCGR0);
4269         } else {
4270                 __raw_writel(1 << MXC_CCM_CCGRx_CG11_OFFSET |
4271                              3 << MXC_CCM_CCGRx_CG2_OFFSET |
4272                              3 << MXC_CCM_CCGRx_CG1_OFFSET |
4273                              3 << MXC_CCM_CCGRx_CG0_OFFSET, MXC_CCM_CCGR0);
4274         }
4275         __raw_writel(3 << MXC_CCM_CCGRx_CG10_OFFSET, MXC_CCM_CCGR1);
4276         __raw_writel(3 << MXC_CCM_CCGRx_CG12_OFFSET |
4277                      3 << MXC_CCM_CCGRx_CG11_OFFSET |
4278                      3 << MXC_CCM_CCGRx_CG10_OFFSET |
4279                      3 << MXC_CCM_CCGRx_CG9_OFFSET |
4280                      3 << MXC_CCM_CCGRx_CG8_OFFSET, MXC_CCM_CCGR2);
4281         __raw_writel(3 << MXC_CCM_CCGRx_CG14_OFFSET |
4282                      3 << MXC_CCM_CCGRx_CG13_OFFSET |
4283                      3 << MXC_CCM_CCGRx_CG12_OFFSET |
4284                      3 << MXC_CCM_CCGRx_CG11_OFFSET |
4285                      3 << MXC_CCM_CCGRx_CG10_OFFSET, MXC_CCM_CCGR3);
4286         __raw_writel(3 << MXC_CCM_CCGRx_CG7_OFFSET |
4287                      3 << MXC_CCM_CCGRx_CG4_OFFSET, MXC_CCM_CCGR4);
4288         __raw_writel(3 << MXC_CCM_CCGRx_CG3_OFFSET |
4289                      3 << MXC_CCM_CCGRx_CG0_OFFSET, MXC_CCM_CCGR5);
4290         __raw_writel(0, MXC_CCM_CCGR6);
4291
4292         /* Lower the ipg_perclk frequency to 11MHz. */
4293         clk_set_rate(&ipg_perclk, 11000000);
4294
4295         base = ioremap(GPT_BASE_ADDR, SZ_4K);
4296         mxc_timer_init(&gpt_clk[0], base, MXC_INT_GPT);
4297
4298         return 0;
4299
4300 }