arch/arm/mach-mx6/clock.c

   1
   2 /*
   3  * Copyright (C) 2012 Freescale Semiconductor, Inc. All Rights Reserved.
   4  */
   5
   6 /*
   7  * The code contained herein is licensed under the GNU General Public
   8  * License. You may obtain a copy of the GNU General Public License
   9  * Version 2 or later at the following locations:
  10  *
  11  * http://www.opensource.org/licenses/gpl-license.html
  12  * http://www.gnu.org/copyleft/gpl.html
  13  */
  14
  15 #include <linux/kernel.h>
  16 #include <linux/init.h>
  17 #include <linux/types.h>
  18 #include <linux/time.h>
  19 #include <linux/hrtimer.h>
  20 #include <linux/mm.h>
  21 #include <linux/errno.h>
  22 #include <linux/delay.h>
  23 #include <linux/clk.h>
  24 #include <linux/io.h>
  25 #include <linux/clkdev.h>
  26 #include <linux/regulator/consumer.h>
  27 #include <asm/div64.h>
  28 #include <mach/hardware.h>
  29 #include <mach/common.h>
  30 #include <mach/clock.h>
  31 #include <mach/mxc_dvfs.h>
  32 #include "crm_regs.h"
  33 #include "cpu_op-mx6.h"
  34 #include "regs-anadig.h"
  35
  36 #ifdef CONFIG_CLK_DEBUG
  37 #define __INIT_CLK_DEBUG(n)     .name = #n,
  38 #else
  39 #define __INIT_CLK_DEBUG(n)
  40 #endif
  41
  42 extern u32 arm_max_freq;
  43 extern int mxc_jtag_enabled;
  44 extern struct regulator *cpu_regulator;
  45 extern struct cpu_op *(*get_cpu_op)(int *op);
  46 extern int lp_high_freq;
  47 extern int lp_med_freq;
  48 extern int mx6q_revision(void);
  49
  50 void __iomem *apll_base;
  51 static struct clk pll1_sys_main_clk;
  52 static struct clk pll2_528_bus_main_clk;
  53 static struct clk pll2_pfd_400M;
  54 static struct clk pll3_usb_otg_main_clk;
  55 static struct clk pll4_audio_main_clk;
  56 static struct clk pll5_video_main_clk;
  57 static struct clk pll6_mlb150_main_clk;
  58 static struct clk pll7_usb_host_main_clk;
  59 static struct clk pll8_enet_main_clk;
  60 static struct clk apbh_dma_clk;
  61 static struct clk openvg_axi_clk;
  62 static struct clk enfc_clk;
  63 static struct clk ipu1_di_clk_root;
  64 static struct clk ipu2_di_clk_root;
  65 static struct clk usdhc3_clk;
  66
  67 static struct cpu_op *cpu_op_tbl;
  68 static int cpu_op_nr;
  69
  70 #define SPIN_DELAY      1200000 /* in nanoseconds */
  71
  72 #define AUDIO_VIDEO_MIN_CLK_FREQ        650000000
  73 #define AUDIO_VIDEO_MAX_CLK_FREQ        1300000000
  74
  75 /* We need to check the exp status again after timer expiration,
  76  * as there might be interrupt coming between the first time exp
  77  * and the time reading, then the time reading may be several ms
  78  * after the exp checking due to the irq handle, so we need to
  79  * check it to make sure the exp return the right value after
  80  * timer expiration. */
  81 #define WAIT(exp, timeout) \
  82 ({ \
  83         struct timespec nstimeofday; \
  84         struct timespec curtime; \
  85         int result = 1; \
  86         getnstimeofday(&nstimeofday); \
  87         while (!(exp)) { \
  88                 getnstimeofday(&curtime); \
  89                 if ((curtime.tv_nsec - nstimeofday.tv_nsec) > (timeout)) { \
  90                         if (!(exp)) \
  91                                 result = 0; \
  92                         break; \
  93                 } \
  94         } \
  95         result; \
  96 })
  97
  98 /* External clock values passed-in by the board code */
  99 static unsigned long external_high_reference, external_low_reference;
 100 static unsigned long oscillator_reference, ckih2_reference;
 101
 102 static void __calc_pre_post_dividers(u32 max_podf, u32 div, u32 *pre, u32 *post)
 103 {
 104         u32 min_pre, temp_pre, old_err, err;
 105
 106         /* Some of the podfs are 3 bits while others are 6 bits.
 107           * Handle both cases here.
 108           */
 109         if (div >= 512 && (max_podf == 64)) {
 110                 /* For pre = 3bits and podf = 6 bits, max divider is 512. */
 111                 *pre = 8;
 112                 *post = 64;
 113         } else if (div >= 64 && (max_podf == 8)) {
 114                 /* For pre = 3bits and podf = 3 bits, max divider is 64. */
 115                 *pre = 8;
 116                 *post = 8;
 117         } else if (div >= 8) {
 118                 /* Find the minimum pre-divider for a max podf */
 119                 if (max_podf == 64)
 120                         min_pre = (div - 1) / (1 << 6) + 1;
 121                 else
 122                         min_pre = (div - 1) / (1 << 3) + 1;
 123                 old_err = 8;
 124                 /* Now loop through to find the max pre-divider. */
 125                 for (temp_pre = 8; temp_pre >= min_pre; temp_pre--) {
 126                         err = div % temp_pre;
 127                         if (err == 0) {
 128                                 *pre = temp_pre;
 129                                 break;
 130                         }
 131                         err = temp_pre - err;
 132                         if (err < old_err) {
 133                                 old_err = err;
 134                                 *pre = temp_pre;
 135                         }
 136                 }
 137                 *post = (div + *pre - 1) / *pre;
 138         } else if (div < 8) {
 139                 *pre = div;
 140                 *post = 1;
 141         }
 142 }
 143
 144 static int _clk_enable(struct clk *clk)
 145 {
 146         u32 reg;
 147         reg = __raw_readl(clk->enable_reg);
 148         reg |= MXC_CCM_CCGRx_CG_MASK << clk->enable_shift;
 149         __raw_writel(reg, clk->enable_reg);
 150
 151         if (clk->flags & AHB_HIGH_SET_POINT)
 152                 lp_high_freq++;
 153         else if (clk->flags & AHB_MED_SET_POINT)
 154                 lp_med_freq++;
 155
 156         return 0;
 157 }
 158
 159 static void _clk_disable(struct clk *clk)
 160 {
 161         u32 reg;
 162         reg = __raw_readl(clk->enable_reg);
 163         reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift);
 164         __raw_writel(reg, clk->enable_reg);
 165
 166         if (clk->flags & AHB_HIGH_SET_POINT)
 167                 lp_high_freq--;
 168         else if (clk->flags & AHB_MED_SET_POINT)
 169                 lp_med_freq--;
 170 }
 171
 172 static void _clk_disable_inwait(struct clk *clk)
 173 {
 174         u32 reg;
 175         reg = __raw_readl(clk->enable_reg);
 176         reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift);
 177         reg |= 1 << clk->enable_shift;
 178         __raw_writel(reg, clk->enable_reg);
 179 }
 180
 181 /*
 182  * For the 4-to-1 muxed input clock
 183  */
 184 static inline u32 _get_mux(struct clk *parent, struct clk *m0,
 185                            struct clk *m1, struct clk *m2, struct clk *m3)
 186 {
 187         if (parent == m0)
 188                 return 0;
 189         else if (parent == m1)
 190                 return 1;
 191         else if (parent == m2)
 192                 return 2;
 193         else if (parent == m3)
 194                 return 3;
 195         else
 196                 BUG();
 197
 198         return 0;
 199 }
 200
 201 static inline void __iomem *_get_pll_base(struct clk *pll)
 202 {
 203         if (pll == &pll1_sys_main_clk)
 204                 return PLL1_SYS_BASE_ADDR;
 205         else if (pll == &pll2_528_bus_main_clk)
 206                 return PLL2_528_BASE_ADDR;
 207         else if (pll == &pll3_usb_otg_main_clk)
 208                 return PLL3_480_USB1_BASE_ADDR;
 209         else if (pll == &pll4_audio_main_clk)
 210                 return PLL4_AUDIO_BASE_ADDR;
 211         else if (pll == &pll5_video_main_clk)
 212                 return PLL5_VIDEO_BASE_ADDR;
 213         else if (pll == &pll6_mlb150_main_clk)
 214                 return PLL6_MLB_BASE_ADDR;
 215         else if (pll == &pll7_usb_host_main_clk)
 216                 return PLL7_480_USB2_BASE_ADDR;
 217         else if (pll == &pll8_enet_main_clk)
 218                 return PLL8_ENET_BASE_ADDR;
 219         else
 220                 BUG();
 221         return NULL;
 222 }
 223
 224
 225 /*
 226  * For the 6-to-1 muxed input clock
 227  */
 228 static inline u32 _get_mux6(struct clk *parent, struct clk *m0, struct clk *m1,
 229                             struct clk *m2, struct clk *m3, struct clk *m4,
 230                             struct clk *m5)
 231 {
 232         if (parent == m0)
 233                 return 0;
 234         else if (parent == m1)
 235                 return 1;
 236         else if (parent == m2)
 237                 return 2;
 238         else if (parent == m3)
 239                 return 3;
 240         else if (parent == m4)
 241                 return 4;
 242         else if (parent == m5)
 243                 return 5;
 244         else
 245                 BUG();
 246
 247         return 0;
 248 }
 249 static unsigned long get_high_reference_clock_rate(struct clk *clk)
 250 {
 251         return external_high_reference;
 252 }
 253
 254 static unsigned long get_low_reference_clock_rate(struct clk *clk)
 255 {
 256         return external_low_reference;
 257 }
 258
 259 static unsigned long get_oscillator_reference_clock_rate(struct clk *clk)
 260 {
 261         return oscillator_reference;
 262 }
 263
 264 static unsigned long get_ckih2_reference_clock_rate(struct clk *clk)
 265 {
 266         return ckih2_reference;
 267 }
 268
 269 /* External high frequency clock */
 270 static struct clk ckih_clk = {
 271         __INIT_CLK_DEBUG(ckih_clk)
 272         .get_rate = get_high_reference_clock_rate,
 273 };
 274
 275 static struct clk ckih2_clk = {
 276         __INIT_CLK_DEBUG(ckih2_clk)
 277         .get_rate = get_ckih2_reference_clock_rate,
 278 };
 279
 280 static struct clk osc_clk = {
 281         __INIT_CLK_DEBUG(osc_clk)
 282         .get_rate = get_oscillator_reference_clock_rate,
 283 };
 284
 285 /* External low frequency (32kHz) clock */
 286 static struct clk ckil_clk = {
 287         __INIT_CLK_DEBUG(ckil_clk)
 288         .get_rate = get_low_reference_clock_rate,
 289 };
 290
 291 static unsigned long pfd_round_rate(struct clk *clk, unsigned long rate)
 292 {
 293         u32 frac;
 294         u64 tmp;
 295
 296         tmp = (u64)clk_get_rate(clk->parent) * 18;
 297         tmp += rate/2;
 298         do_div(tmp, rate);
 299         frac = tmp;
 300         frac = frac < 12 ? 12 : frac;
 301         frac = frac > 35 ? 35 : frac;
 302         tmp = (u64)clk_get_rate(clk->parent) * 18;
 303         do_div(tmp, frac);
 304         return tmp;
 305 }
 306
 307 static unsigned long pfd_get_rate(struct clk *clk)
 308 {
 309         u32 frac;
 310         u64 tmp;
 311         tmp = (u64)clk_get_rate(clk->parent) * 18;
 312
 313         if (apbh_dma_clk.usecount == 0)
 314                 apbh_dma_clk.enable(&apbh_dma_clk);
 315
 316         frac = (__raw_readl(clk->enable_reg) >> clk->enable_shift) &
 317                         ANADIG_PFD_FRAC_MASK;
 318
 319         do_div(tmp, frac);
 320
 321         return tmp;
 322 }
 323
 324 static int pfd_set_rate(struct clk *clk, unsigned long rate)
 325 {
 326         u32 frac;
 327         u64 tmp;
 328         tmp = (u64)clk_get_rate(clk->parent) * 18;
 329
 330         if (apbh_dma_clk.usecount == 0)
 331                 apbh_dma_clk.enable(&apbh_dma_clk);
 332
 333         /* Round up the divider so that we don't set a rate
 334           * higher than what is requested. */
 335         tmp += rate/2;
 336         do_div(tmp, rate);
 337         frac = tmp;
 338         frac = frac < 12 ? 12 : frac;
 339         frac = frac > 35 ? 35 : frac;
 340         /* clear clk frac bits */
 341         __raw_writel(ANADIG_PFD_FRAC_MASK << clk->enable_shift,
 342                         (int)clk->enable_reg + 8);
 343         /* set clk frac bits */
 344         __raw_writel(frac << clk->enable_shift,
 345                         (int)clk->enable_reg + 4);
 346
 347         tmp = (u64)clk_get_rate(clk->parent) * 18;
 348         do_div(tmp, frac);
 349
 350         if (apbh_dma_clk.usecount == 0)
 351                 apbh_dma_clk.disable(&apbh_dma_clk);
 352         return 0;
 353 }
 354
 355 static int _clk_pfd_enable(struct clk *clk)
 356 {
 357         if (apbh_dma_clk.usecount == 0)
 358                 apbh_dma_clk.enable(&apbh_dma_clk);
 359
 360         /* clear clk gate bit */
 361         __raw_writel((1 << (clk->enable_shift + 7)),
 362                         (int)clk->enable_reg + 8);
 363
 364         if (apbh_dma_clk.usecount == 0)
 365                 apbh_dma_clk.disable(&apbh_dma_clk);
 366
 367         return 0;
 368 }
 369
 370 static void _clk_pfd_disable(struct clk *clk)
 371 {
 372         if (apbh_dma_clk.usecount == 0)
 373                 apbh_dma_clk.enable(&apbh_dma_clk);
 374
 375         /* set clk gate bit */
 376         __raw_writel((1 << (clk->enable_shift + 7)),
 377                         (int)clk->enable_reg + 4);
 378
 379         if (apbh_dma_clk.usecount == 0)
 380                 apbh_dma_clk.disable(&apbh_dma_clk);
 381 }
 382
 383 static int _clk_pll_enable(struct clk *clk)
 384 {
 385         unsigned int reg;
 386         void __iomem *pllbase;
 387
 388         pllbase = _get_pll_base(clk);
 389
 390         reg = __raw_readl(pllbase);
 391         reg &= ~ANADIG_PLL_BYPASS;
 392         reg &= ~ANADIG_PLL_POWER_DOWN;
 393
 394         /* The 480MHz PLLs have the opposite definition for power bit. */
 395         if (clk == &pll3_usb_otg_main_clk || clk == &pll7_usb_host_main_clk)
 396                 reg |= ANADIG_PLL_POWER_DOWN;
 397
 398         __raw_writel(reg, pllbase);
 399
 400         /* It will power on pll3 */
 401         if (clk == &pll3_usb_otg_main_clk)
 402                 __raw_writel(BM_ANADIG_ANA_MISC2_CONTROL0, apll_base + HW_ANADIG_ANA_MISC2_CLR);
 403
 404         /* Wait for PLL to lock */
 405         if (!WAIT(__raw_readl(pllbase) & ANADIG_PLL_LOCK,
 406                                 SPIN_DELAY))
 407                 panic("pll enable failed\n");
 408
 409         /* Enable the PLL output now*/
 410         reg = __raw_readl(pllbase);
 411         reg |= ANADIG_PLL_ENABLE;
 412         __raw_writel(reg, pllbase);
 413
 414         return 0;
 415 }
 416
 417 static void _clk_pll_disable(struct clk *clk)
 418 {
 419         unsigned int reg;
 420         void __iomem *pllbase;
 421
 422         pllbase = _get_pll_base(clk);
 423
 424         reg = __raw_readl(pllbase);
 425         reg |= ANADIG_PLL_BYPASS;
 426         reg &= ~ANADIG_PLL_ENABLE;
 427
 428         __raw_writel(reg, pllbase);
 429
 430         /*
 431          * It will power off PLL3's power, it is the TO1.1 fix
 432          * Please see TKT064178 for detail.
 433          */
 434         if (clk == &pll3_usb_otg_main_clk)
 435                 __raw_writel(BM_ANADIG_ANA_MISC2_CONTROL0, apll_base + HW_ANADIG_ANA_MISC2_SET);
 436 }
 437
 438 static unsigned long  _clk_pll1_main_get_rate(struct clk *clk)
 439 {
 440         unsigned int div;
 441         unsigned long val;
 442
 443         div = __raw_readl(PLL1_SYS_BASE_ADDR) & ANADIG_PLL_SYS_DIV_SELECT_MASK;
 444         val = (clk_get_rate(clk->parent) * div) / 2;
 445         return val;
 446 }
 447
 448 static int _clk_pll1_main_set_rate(struct clk *clk, unsigned long rate)
 449 {
 450         unsigned int reg,  div;
 451
 452         if (rate < AUDIO_VIDEO_MIN_CLK_FREQ || rate > AUDIO_VIDEO_MAX_CLK_FREQ)
 453                 return -EINVAL;
 454
 455         div = (rate * 2) / clk_get_rate(clk->parent) ;
 456
 457         reg = __raw_readl(PLL1_SYS_BASE_ADDR) & ~ANADIG_PLL_SYS_DIV_SELECT_MASK;
 458         reg |= div;
 459         __raw_writel(reg, PLL1_SYS_BASE_ADDR);
 460
 461         return 0;
 462 }
 463
 464 static struct clk pll1_sys_main_clk = {
 465         __INIT_CLK_DEBUG(pll1_sys_main_clk)
 466         .parent = &osc_clk,
 467         .get_rate = _clk_pll1_main_get_rate,
 468         .set_rate = _clk_pll1_main_set_rate,
 469         .enable = _clk_pll_enable,
 470         .disable = _clk_pll_disable,
 471 };
 472
 473 static int _clk_pll1_sw_set_parent(struct clk *clk, struct clk *parent)
 474 {
 475         u32 reg;
 476
 477         reg = __raw_readl(MXC_CCM_CCSR);
 478
 479         if (parent == &pll1_sys_main_clk) {
 480                 reg &= ~MXC_CCM_CCSR_PLL1_SW_CLK_SEL;
 481                 __raw_writel(reg, MXC_CCM_CCSR);
 482                 /* Set the step_clk parent to be lp_apm, to save power. */
 483                 reg = __raw_readl(MXC_CCM_CCSR);
 484                 reg = (reg & ~MXC_CCM_CCSR_STEP_SEL);
 485         } else {
 486                 /* Set STEP_CLK to be the parent*/
 487                 if (parent == &osc_clk) {
 488                         /* Set STEP_CLK to be sourced from LPAPM. */
 489                         reg = __raw_readl(MXC_CCM_CCSR);
 490                         reg = (reg & ~MXC_CCM_CCSR_STEP_SEL);
 491                         __raw_writel(reg, MXC_CCM_CCSR);
 492                 } else {
 493                         /* Set STEP_CLK to be sourced from PLL2-PDF (400MHz). */
 494                         reg = __raw_readl(MXC_CCM_CCSR);
 495                         reg |= MXC_CCM_CCSR_STEP_SEL;
 496                         __raw_writel(reg, MXC_CCM_CCSR);
 497
 498                 }
 499                 reg = __raw_readl(MXC_CCM_CCSR);
 500                 reg |= MXC_CCM_CCSR_PLL1_SW_CLK_SEL;
 501         }
 502         __raw_writel(reg, MXC_CCM_CCSR);
 503         return 0;
 504 }
 505
 506 static unsigned long _clk_pll1_sw_get_rate(struct clk *clk)
 507 {
 508         return clk_get_rate(clk->parent);
 509 }
 510
 511 static struct clk pll1_sw_clk = {
 512         __INIT_CLK_DEBUG(pll1_sw_clk)
 513         .parent = &pll1_sys_main_clk,
 514         .set_parent = _clk_pll1_sw_set_parent,
 515         .get_rate = _clk_pll1_sw_get_rate,
 516 };
 517
 518 static unsigned long _clk_pll2_main_get_rate(struct clk *clk)
 519 {
 520         unsigned int div;
 521         unsigned long val;
 522
 523         div = __raw_readl(PLL2_528_BASE_ADDR) & ANADIG_PLL_528_DIV_SELECT;
 524
 525         if (div == 1)
 526                 val = clk_get_rate(clk->parent) * 22;
 527
 528         else
 529                 val = clk_get_rate(clk->parent) * 20;
 530
 531         return val;
 532 }
 533
 534 static int _clk_pll2_main_set_rate(struct clk *clk, unsigned long rate)
 535 {
 536         unsigned int reg,  div;
 537
 538         if (rate == 528000000)
 539                 div = 1;
 540         else if (rate == 480000000)
 541                 div = 0;
 542         else
 543                 return -EINVAL;
 544
 545         reg = __raw_readl(PLL2_528_BASE_ADDR);
 546         reg &= ~ANADIG_PLL_528_DIV_SELECT;
 547         reg |= div;
 548         __raw_writel(reg, PLL2_528_BASE_ADDR);
 549
 550         return 0;
 551 }
 552
 553 static struct clk pll2_528_bus_main_clk = {
 554         __INIT_CLK_DEBUG(pll2_528_bus_main_clk)
 555         .parent = &osc_clk,
 556         .get_rate = _clk_pll2_main_get_rate,
 557         .set_rate = _clk_pll2_main_set_rate,
 558         .enable = _clk_pll_enable,
 559         .disable = _clk_pll_disable,
 560 };
 561
 562 static struct clk pll2_pfd_400M = {
 563         __INIT_CLK_DEBUG(pll2_pfd_400M)
 564         .parent = &pll2_528_bus_main_clk,
 565         .enable_reg = (void *)PFD_528_BASE_ADDR,
 566         .enable_shift = ANADIG_PFD2_FRAC_OFFSET,
 567         .enable = _clk_pfd_enable,
 568         .disable = _clk_pfd_disable,
 569         .get_rate = pfd_get_rate,
 570         .set_rate = pfd_set_rate,
 571         .get_rate = pfd_get_rate,
 572         .round_rate = pfd_round_rate,
 573 };
 574
 575 static struct clk pll2_pfd_352M = {
 576         __INIT_CLK_DEBUG(pll2_pfd_352M)
 577         .parent = &pll2_528_bus_main_clk,
 578         .enable_reg = (void *)PFD_528_BASE_ADDR,
 579         .enable_shift = ANADIG_PFD0_FRAC_OFFSET,
 580         .enable = _clk_pfd_enable,
 581         .disable = _clk_pfd_disable,
 582         .set_rate = pfd_set_rate,
 583         .get_rate = pfd_get_rate,
 584         .round_rate = pfd_round_rate,
 585 };
 586
 587 static struct clk pll2_pfd_594M = {
 588         __INIT_CLK_DEBUG(pll2_pfd_594M)
 589         .parent = &pll2_528_bus_main_clk,
 590         .enable_reg = (void *)PFD_528_BASE_ADDR,
 591         .enable_shift = ANADIG_PFD1_FRAC_OFFSET,
 592         .enable = _clk_pfd_enable,
 593         .disable = _clk_pfd_disable,
 594         .set_rate = pfd_set_rate,
 595         .get_rate = pfd_get_rate,
 596         .round_rate = pfd_round_rate,
 597 };
 598
 599 static unsigned long _clk_pll2_200M_get_rate(struct clk *clk)
 600 {
 601         return clk_get_rate(clk->parent) / 2;
 602 }
 603
 604 static struct clk pll2_200M = {
 605         __INIT_CLK_DEBUG(pll2_200M)
 606         .parent = &pll2_pfd_400M,
 607         .get_rate = _clk_pll2_200M_get_rate,
 608 };
 609
 610 static unsigned long _clk_pll3_usb_otg_get_rate(struct clk *clk)
 611 {
 612         unsigned int div;
 613         unsigned long val;
 614
 615         div = __raw_readl(PLL3_480_USB1_BASE_ADDR)
 616                 & ANADIG_PLL_480_DIV_SELECT_MASK;
 617
 618         if (div == 1)
 619                 val = clk_get_rate(clk->parent) * 22;
 620         else
 621                 val = clk_get_rate(clk->parent) * 20;
 622         return val;
 623 }
 624
 625 static int _clk_pll3_usb_otg_set_rate(struct clk *clk, unsigned long rate)
 626 {
 627         unsigned int reg,  div;
 628
 629         if (rate == 528000000)
 630                 div = 1;
 631         else if (rate == 480000000)
 632                 div = 0;
 633         else
 634                 return -EINVAL;
 635
 636         reg = __raw_readl(PLL3_480_USB1_BASE_ADDR);
 637         reg &= ~ANADIG_PLL_480_DIV_SELECT_MASK;
 638         reg |= div;
 639         __raw_writel(reg, PLL3_480_USB1_BASE_ADDR);
 640
 641         return 0;
 642 }
 643
 644
 645 /* same as pll3_main_clk. These two clocks should always be the same */
 646 static struct clk pll3_usb_otg_main_clk = {
 647         __INIT_CLK_DEBUG(pll3_usb_otg_main_clk)
 648         .parent = &osc_clk,
 649         .enable = _clk_pll_enable,
 650         .disable = _clk_pll_disable,
 651         .set_rate = _clk_pll3_usb_otg_set_rate,
 652         .get_rate = _clk_pll3_usb_otg_get_rate,
 653 };
 654
 655 /* for USB OTG */
 656 static struct clk usb_phy1_clk = {
 657         __INIT_CLK_DEBUG(usb_phy1_clk)
 658         .parent = &pll3_usb_otg_main_clk,
 659         .set_rate = _clk_pll3_usb_otg_set_rate,
 660         .get_rate = _clk_pll3_usb_otg_get_rate,
 661 };
 662
 663 /* For HSIC port 1 */
 664 static struct clk usb_phy3_clk = {
 665         __INIT_CLK_DEBUG(usb_phy3_clk)
 666         .parent = &pll3_usb_otg_main_clk,
 667         .set_rate = _clk_pll3_usb_otg_set_rate,
 668         .get_rate = _clk_pll3_usb_otg_get_rate,
 669 };
 670
 671 /* For HSIC port 2 */
 672 static struct clk usb_phy4_clk = {
 673         __INIT_CLK_DEBUG(usb_phy4_clk)
 674         .parent = &pll3_usb_otg_main_clk,
 675         .set_rate = _clk_pll3_usb_otg_set_rate,
 676         .get_rate = _clk_pll3_usb_otg_get_rate,
 677 };
 678
 679 static struct clk pll3_pfd_508M = {
 680         __INIT_CLK_DEBUG(pll3_pfd_508M)
 681         .parent = &pll3_usb_otg_main_clk,
 682         .enable_reg = (void *)PFD_480_BASE_ADDR,
 683         .enable_shift = ANADIG_PFD2_FRAC_OFFSET,
 684         .enable = _clk_pfd_enable,
 685         .disable = _clk_pfd_disable,
 686         .set_rate = pfd_set_rate,
 687         .get_rate = pfd_get_rate,
 688         .round_rate = pfd_round_rate,
 689 };
 690
 691 static struct clk pll3_pfd_454M = {
 692         __INIT_CLK_DEBUG(pll3_pfd_454M)
 693         .parent = &pll3_usb_otg_main_clk,
 694         .enable_reg = (void *)PFD_480_BASE_ADDR,
 695         .enable_shift = ANADIG_PFD3_FRAC_OFFSET,
 696         .enable = _clk_pfd_enable,
 697         .disable = _clk_pfd_disable,
 698         .set_rate = pfd_set_rate,
 699         .get_rate = pfd_get_rate,
 700         .round_rate = pfd_round_rate,
 701 };
 702
 703 static struct clk pll3_pfd_720M = {
 704         __INIT_CLK_DEBUG(pll3_pfd_720M)
 705         .parent = &pll3_usb_otg_main_clk,
 706         .enable_reg = (void *)PFD_480_BASE_ADDR,
 707         .enable_shift = ANADIG_PFD0_FRAC_OFFSET,
 708         .enable = _clk_pfd_enable,
 709         .disable = _clk_pfd_disable,
 710         .set_rate = pfd_set_rate,
 711         .get_rate = pfd_get_rate,
 712         .round_rate = pfd_round_rate,
 713 };
 714
 715 static struct clk pll3_pfd_540M = {
 716         __INIT_CLK_DEBUG(pll3_pfd_540M)
 717         .parent = &pll3_usb_otg_main_clk,
 718         .enable_reg = (void *)PFD_480_BASE_ADDR,
 719         .enable_shift = ANADIG_PFD1_FRAC_OFFSET,
 720         .enable = _clk_pfd_enable,
 721         .disable = _clk_pfd_disable,
 722         .set_rate = pfd_set_rate,
 723         .get_rate = pfd_get_rate,
 724         .round_rate = pfd_round_rate,
 725         .get_rate = pfd_get_rate,
 726 };
 727
 728 static unsigned long _clk_pll3_sw_get_rate(struct clk *clk)
 729 {
 730         return clk_get_rate(clk->parent);
 731 }
 732
 733 /* same as pll3_main_clk. These two clocks should always be the same */
 734 static struct clk pll3_sw_clk = {
 735         __INIT_CLK_DEBUG(pll3_sw_clk)
 736         .parent = &pll3_usb_otg_main_clk,
 737         .get_rate = _clk_pll3_sw_get_rate,
 738 };
 739
 740 static unsigned long _clk_pll3_120M_get_rate(struct clk *clk)
 741 {
 742         return clk_get_rate(clk->parent) / 4;
 743 }
 744
 745 static struct clk pll3_120M = {
 746         __INIT_CLK_DEBUG(pll3_120M)
 747         .parent = &pll3_sw_clk,
 748         .get_rate = _clk_pll3_120M_get_rate,
 749 };
 750
 751 static unsigned long _clk_pll3_80M_get_rate(struct clk *clk)
 752 {
 753         return clk_get_rate(clk->parent) / 6;
 754 }
 755
 756 static struct clk pll3_80M = {
 757         __INIT_CLK_DEBUG(pll3_80M)
 758         .parent = &pll3_sw_clk,
 759         .get_rate = _clk_pll3_80M_get_rate,
 760 };
 761
 762 static unsigned long _clk_pll3_60M_get_rate(struct clk *clk)
 763 {
 764         return clk_get_rate(clk->parent) / 8;
 765 }
 766
 767 static struct clk pll3_60M = {
 768         __INIT_CLK_DEBUG(pll3_60M)
 769         .parent = &pll3_sw_clk,
 770         .get_rate = _clk_pll3_60M_get_rate,
 771 };
 772
 773 static unsigned long  _clk_audio_video_get_rate(struct clk *clk)
 774 {
 775         unsigned int div, mfn, mfd;
 776         unsigned long rate;
 777         unsigned int parent_rate = clk_get_rate(clk->parent);
 778         void __iomem *pllbase;
 779         int rev = mx6q_revision();
 780         unsigned int test_div_sel, control3, post_div = 1;
 781
 782         if (clk == &pll4_audio_main_clk)
 783                 pllbase = PLL4_AUDIO_BASE_ADDR;
 784         else
 785                 pllbase = PLL5_VIDEO_BASE_ADDR;
 786
 787         if (rev >= IMX_CHIP_REVISION_1_1) {
 788                 test_div_sel = (__raw_readl(pllbase)
 789                         & ANADIG_PLL_AV_TEST_DIV_SEL_MASK)
 790                         >> ANADIG_PLL_AV_TEST_DIV_SEL_OFFSET;
 791                 if (test_div_sel == 0)
 792                         post_div = 4;
 793                 else if (test_div_sel == 1)
 794                         post_div = 2;
 795
 796                 if (clk == &pll5_video_main_clk) {
 797                         control3 = (__raw_readl(ANA_MISC2_BASE_ADDR)
 798                                 & ANADIG_ANA_MISC2_CONTROL3_MASK)
 799                                 >> ANADIG_ANA_MISC2_CONTROL3_OFFSET;
 800                         if (control3 == 1)
 801                                 post_div *= 2;
 802                         else if (control3 == 3)
 803                                 post_div *= 4;
 804                 }
 805         }
 806
 807         div = __raw_readl(pllbase) & ANADIG_PLL_SYS_DIV_SELECT_MASK;
 808         mfn = __raw_readl(pllbase + PLL_NUM_DIV_OFFSET);
 809         mfd = __raw_readl(pllbase + PLL_DENOM_DIV_OFFSET);
 810
 811         rate = (parent_rate * div) + ((parent_rate / mfd) * mfn);
 812         rate = rate / post_div;
 813
 814         return rate;
 815 }
 816
 817 static int _clk_audio_video_set_rate(struct clk *clk, unsigned long rate)
 818 {
 819         unsigned int reg,  div;
 820         unsigned int mfn, mfd = 1000000;
 821         s64 temp64;
 822         unsigned int parent_rate = clk_get_rate(clk->parent);
 823         void __iomem *pllbase;
 824         unsigned long min_clk_rate, pre_div_rate;
 825         int rev = mx6q_revision();
 826         u32 test_div_sel = 2;
 827         u32 control3 = 0;
 828
 829         if (rev < IMX_CHIP_REVISION_1_1)
 830                 min_clk_rate = AUDIO_VIDEO_MIN_CLK_FREQ;
 831         else if (clk == &pll4_audio_main_clk)
 832                 min_clk_rate = AUDIO_VIDEO_MIN_CLK_FREQ / 4;
 833         else
 834                 min_clk_rate = AUDIO_VIDEO_MIN_CLK_FREQ / 16;
 835
 836         if ((rate < min_clk_rate) || (rate > AUDIO_VIDEO_MAX_CLK_FREQ))
 837                 return -EINVAL;
 838
 839         if (clk == &pll4_audio_main_clk)
 840                 pllbase = PLL4_AUDIO_BASE_ADDR;
 841         else
 842                 pllbase = PLL5_VIDEO_BASE_ADDR;
 843
 844         pre_div_rate = rate;
 845         if (rev >= IMX_CHIP_REVISION_1_1) {
 846                 while (pre_div_rate < AUDIO_VIDEO_MIN_CLK_FREQ) {
 847                         pre_div_rate *= 2;
 848                         /*
 849                          * test_div_sel field values:
 850                          * 2 -> Divide by 1
 851                          * 1 -> Divide by 2
 852                          * 0 -> Divide by 4
 853                          *
 854                          * control3 field values:
 855                          * 0 -> Divide by 1
 856                          * 1 -> Divide by 2
 857                          * 3 -> Divide by 4
 858                          */
 859                         if (test_div_sel != 0)
 860                                 test_div_sel--;
 861                         else {
 862                                 control3++;
 863                                 if (control3 == 2)
 864                                         control3++;
 865                         }
 866                 }
 867         }
 868
 869         div = pre_div_rate / parent_rate;
 870         temp64 = (u64) (pre_div_rate - (div * parent_rate));
 871         temp64 *= mfd;
 872         do_div(temp64, parent_rate);
 873         mfn = temp64;
 874
 875         reg = __raw_readl(pllbase)
 876                         & ~ANADIG_PLL_SYS_DIV_SELECT_MASK
 877                         & ~ANADIG_PLL_AV_TEST_DIV_SEL_MASK;
 878         reg |= div |
 879                 (test_div_sel << ANADIG_PLL_AV_TEST_DIV_SEL_OFFSET);
 880         __raw_writel(reg, pllbase);
 881         __raw_writel(mfn, pllbase + PLL_NUM_DIV_OFFSET);
 882         __raw_writel(mfd, pllbase + PLL_DENOM_DIV_OFFSET);
 883
 884         if (rev >= IMX_CHIP_REVISION_1_1) {
 885                 reg = __raw_readl(ANA_MISC2_BASE_ADDR)
 886                         & ~ANADIG_ANA_MISC2_CONTROL3_MASK;
 887                 reg |= control3 << ANADIG_ANA_MISC2_CONTROL3_OFFSET;
 888                 __raw_writel(reg, ANA_MISC2_BASE_ADDR);
 889         }
 890
 891         return 0;
 892 }
 893
 894 static unsigned long _clk_audio_video_round_rate(struct clk *clk,
 895                                                 unsigned long rate)
 896 {
 897         unsigned long min_clk_rate;
 898         unsigned int div, post_div = 1;
 899         unsigned int mfn, mfd = 1000000;
 900         s64 temp64;
 901         unsigned int parent_rate = clk_get_rate(clk->parent);
 902         unsigned long pre_div_rate;
 903         u32 test_div_sel = 2;
 904         u32 control3 = 0;
 905         unsigned long final_rate;
 906         int rev = mx6q_revision();
 907
 908         if (rev < IMX_CHIP_REVISION_1_1)
 909                 min_clk_rate = AUDIO_VIDEO_MIN_CLK_FREQ;
 910         else if (clk == &pll4_audio_main_clk)
 911                 min_clk_rate = AUDIO_VIDEO_MIN_CLK_FREQ / 4;
 912         else
 913                 min_clk_rate = AUDIO_VIDEO_MIN_CLK_FREQ / 16;
 914
 915         if (rate < min_clk_rate)
 916                 return min_clk_rate;
 917
 918         if (rate > AUDIO_VIDEO_MAX_CLK_FREQ)
 919                 return AUDIO_VIDEO_MAX_CLK_FREQ;
 920
 921         pre_div_rate = rate;
 922         if (rev >= IMX_CHIP_REVISION_1_1) {
 923                 while (pre_div_rate < AUDIO_VIDEO_MIN_CLK_FREQ) {
 924                         pre_div_rate *= 2;
 925                         post_div *= 2;
 926                         if (test_div_sel != 0)
 927                                 test_div_sel--;
 928                         else {
 929                                 control3++;
 930                                 if (control3 == 2)
 931                                         control3++;
 932                         }
 933                 }
 934         }
 935
 936         div = pre_div_rate / parent_rate;
 937         temp64 = (u64) (pre_div_rate - (div * parent_rate));
 938         temp64 *= mfd;
 939         do_div(temp64, parent_rate);
 940         mfn = temp64;
 941
 942         final_rate = (parent_rate * div) + ((parent_rate / mfd) * mfn);
 943         final_rate = final_rate / post_div;
 944
 945         return final_rate;
 946 }
 947
 948
 949 static struct clk pll4_audio_main_clk = {
 950         __INIT_CLK_DEBUG(pll4_audio_main_clk)
 951         .parent = &osc_clk,
 952         .enable = _clk_pll_enable,
 953         .disable = _clk_pll_disable,
 954         .set_rate = _clk_audio_video_set_rate,
 955         .get_rate = _clk_audio_video_get_rate,
 956         .round_rate = _clk_audio_video_round_rate,
 957 };
 958
 959
 960 static struct clk pll5_video_main_clk = {
 961         __INIT_CLK_DEBUG(pll5_video_main_clk)
 962         .parent = &osc_clk,
 963         .enable = _clk_pll_enable,
 964         .disable = _clk_pll_disable,
 965         .set_rate = _clk_audio_video_set_rate,
 966         .get_rate = _clk_audio_video_get_rate,
 967         .round_rate = _clk_audio_video_round_rate,
 968 };
 969
 970 static int _clk_pll_mlb_main_enable(struct clk *clk)
 971 {
 972         unsigned int reg;
 973         void __iomem *pllbase;
 974
 975         pllbase = _get_pll_base(clk);
 976
 977         reg = __raw_readl(pllbase);
 978         reg &= ~ANADIG_PLL_BYPASS;
 979
 980         reg = 0x0da20000;
 981         __raw_writel(reg, pllbase);
 982
 983         /* Wait for PLL to lock */
 984         if (!WAIT(__raw_readl(pllbase) & ANADIG_PLL_LOCK,
 985                 SPIN_DELAY))
 986                 panic("pll enable failed\n");
 987
 988         return 0;
 989 }
 990
 991 static struct clk pll6_mlb150_main_clk = {
 992         __INIT_CLK_DEBUG(pll6_mlb150_main_clk)
 993         .parent = &osc_clk,
 994         .enable = _clk_pll_mlb_main_enable,
 995         .disable = _clk_pll_disable,
 996 };
 997
 998 static unsigned long _clk_pll7_usb_otg_get_rate(struct clk *clk)
 999 {
1000         unsigned int div;
1001         unsigned long val;
1002
1003         div = __raw_readl(PLL7_480_USB2_BASE_ADDR)
1004                 & ANADIG_PLL_480_DIV_SELECT_MASK;
1005
1006         if (div == 1)
1007                 val = clk_get_rate(clk->parent) * 22;
1008         else
1009                 val = clk_get_rate(clk->parent) * 20;
1010         return val;
1011 }
1012
1013 static int _clk_pll7_usb_otg_set_rate(struct clk *clk, unsigned long rate)
1014 {
1015         unsigned int reg,  div;
1016
1017         if (rate == 528000000)
1018                 div = 1;
1019         else if (rate == 480000000)
1020                 div = 0;
1021         else
1022                 return -EINVAL;
1023
1024         reg = __raw_readl(PLL7_480_USB2_BASE_ADDR);
1025         reg &= ~ANADIG_PLL_480_DIV_SELECT_MASK;
1026         reg |= div;
1027         __raw_writel(reg, PLL7_480_USB2_BASE_ADDR);
1028
1029         return 0;
1030 }
1031
1032 static struct clk pll7_usb_host_main_clk = {
1033         __INIT_CLK_DEBUG(pll7_usb_host_main_clk)
1034         .parent = &osc_clk,
1035         .enable = _clk_pll_enable,
1036         .disable = _clk_pll_disable,
1037         .set_rate = _clk_pll7_usb_otg_set_rate,
1038         .get_rate = _clk_pll7_usb_otg_get_rate,
1039
1040 };
1041
1042 static struct clk pll8_enet_main_clk = {
1043         __INIT_CLK_DEBUG(pll8_enet_main_clk)
1044         .parent = &osc_clk,
1045         .enable = _clk_pll_enable,
1046         .disable = _clk_pll_disable,
1047 };
1048
1049 static unsigned long _clk_arm_get_rate(struct clk *clk)
1050 {
1051         u32 cacrr, div;
1052
1053         cacrr = __raw_readl(MXC_CCM_CACRR);
1054         div = (cacrr & MXC_CCM_CACRR_ARM_PODF_MASK) + 1;
1055         return clk_get_rate(clk->parent) / div;
1056 }
1057
1058 static int _clk_arm_set_rate(struct clk *clk, unsigned long rate)
1059 {
1060         int i;
1061         u32 div;
1062         u32 parent_rate;
1063
1064
1065         for (i = 0; i < cpu_op_nr; i++) {
1066                 if (rate == cpu_op_tbl[i].cpu_rate)
1067                         break;
1068         }
1069         if (i >= cpu_op_nr)
1070                 return -EINVAL;
1071
1072         if (cpu_op_tbl[i].pll_rate != clk_get_rate(&pll1_sys_main_clk)) {
1073                 /* Change the PLL1 rate. */
1074                 if (pll2_pfd_400M.usecount != 0)
1075                         pll1_sw_clk.set_parent(&pll1_sw_clk, &pll2_pfd_400M);
1076                 else
1077                         pll1_sw_clk.set_parent(&pll1_sw_clk, &osc_clk);
1078                 pll1_sys_main_clk.set_rate(&pll1_sys_main_clk, cpu_op_tbl[i].pll_rate);
1079                 pll1_sw_clk.set_parent(&pll1_sw_clk, &pll1_sys_main_clk);
1080         }
1081
1082         parent_rate = clk_get_rate(clk->parent);
1083         div = parent_rate / rate;
1084
1085         if (div == 0)
1086                 div = 1;
1087
1088         if ((parent_rate / div) > rate)
1089                 div++;
1090
1091         if (div > 8)
1092                 return -1;
1093
1094         __raw_writel(div - 1, MXC_CCM_CACRR);
1095
1096         return 0;
1097 }
1098
1099 static struct clk cpu_clk = {
1100         __INIT_CLK_DEBUG(cpu_clk)
1101         .parent = &pll1_sw_clk,
1102         .set_rate = _clk_arm_set_rate,
1103         .get_rate = _clk_arm_get_rate,
1104 };
1105
1106 static int _clk_periph_set_parent(struct clk *clk, struct clk *parent)
1107 {
1108         u32 reg;
1109         int mux;
1110
1111         mux = _get_mux6(parent, &pll2_528_bus_main_clk, &pll2_pfd_400M,
1112                 &pll2_pfd_352M, &pll2_200M, &pll3_sw_clk, &osc_clk);
1113
1114         if (mux <= 3) {
1115                 /* Set the pre_periph_clk multiplexer */
1116                 reg = __raw_readl(MXC_CCM_CBCMR);
1117                 reg &= ~MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK;
1118                 reg |= mux << MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET;
1119                 __raw_writel(reg, MXC_CCM_CBCMR);
1120
1121                 /* Set the periph_clk_sel multiplexer. */
1122                 reg = __raw_readl(MXC_CCM_CBCDR);
1123                 reg &= ~MXC_CCM_CBCDR_PERIPH_CLK_SEL;
1124                 __raw_writel(reg, MXC_CCM_CBCDR);
1125         } else {
1126                 reg = __raw_readl(MXC_CCM_CBCDR);
1127                 /* Set the periph_clk2_podf divider to divide by 1. */
1128                 reg &= ~MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK;
1129                 __raw_writel(reg, MXC_CCM_CBCDR);
1130
1131                 /* Set the periph_clk2_sel mux. */
1132                 reg = __raw_readl(MXC_CCM_CBCMR);
1133                 reg &= ~MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK;
1134                 reg |= ((mux - 4) << MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET);
1135                 __raw_writel(reg, MXC_CCM_CBCMR);
1136
1137                 while (__raw_readl(MXC_CCM_CDHIPR))
1138                         ;
1139
1140                 reg = __raw_readl(MXC_CCM_CBCDR);
1141                 /* Set periph_clk_sel to select periph_clk2. */
1142                 reg |= MXC_CCM_CBCDR_PERIPH_CLK_SEL;
1143                 __raw_writel(reg, MXC_CCM_CBCDR);
1144         }
1145
1146         if (!WAIT(!(__raw_readl(MXC_CCM_CDHIPR)
1147              & MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY), SPIN_DELAY))
1148                 panic("_clk_periph_set_parent failed\n");
1149
1150         return 0;
1151 }
1152
1153 static unsigned long _clk_periph_get_rate(struct clk *clk)
1154 {
1155         u32 div = 1;
1156         u32 reg;
1157         unsigned long val;
1158
1159         if ((clk->parent == &pll3_sw_clk) || (clk->parent == &osc_clk)) {
1160                 reg = __raw_readl(MXC_CCM_CBCDR)
1161                         & MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK;
1162                 div = (reg >> MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET) + 1;
1163         }
1164         val = clk_get_rate(clk->parent) / div;
1165         return val;
1166 }
1167
1168 static struct clk periph_clk = {
1169         __INIT_CLK_DEBUG(periph_clk)
1170         .parent = &pll2_528_bus_main_clk,
1171         .set_parent = _clk_periph_set_parent,
1172         .get_rate = _clk_periph_get_rate,
1173 };
1174
1175 static unsigned long _clk_axi_get_rate(struct clk *clk)
1176 {
1177         u32 div, reg;
1178         unsigned long val;
1179
1180         reg = __raw_readl(MXC_CCM_CBCDR) & MXC_CCM_CBCDR_AXI_PODF_MASK;
1181         div = (reg >> MXC_CCM_CBCDR_AXI_PODF_OFFSET);
1182
1183         val = clk_get_rate(clk->parent) / (div + 1);
1184         return val;
1185 }
1186
1187 static int _clk_axi_set_rate(struct clk *clk, unsigned long rate)
1188 {
1189         u32 reg, div;
1190         u32 parent_rate = clk_get_rate(clk->parent);
1191
1192         div = parent_rate / rate;
1193
1194         if (div == 0)
1195                 div++;
1196         if (((parent_rate / div) != rate) || (div > 8))
1197                 return -EINVAL;
1198
1199         reg = __raw_readl(MXC_CCM_CBCDR);
1200         reg &= ~MXC_CCM_CBCDR_AXI_PODF_MASK;
1201         reg |= (div - 1) << MXC_CCM_CBCDR_AXI_PODF_OFFSET;
1202         __raw_writel(reg, MXC_CCM_CBCDR);
1203
1204         if (!WAIT(!(__raw_readl(MXC_CCM_CDHIPR)
1205              & MXC_CCM_CDHIPR_AXI_PODF_BUSY), SPIN_DELAY))
1206                 panic("pll _clk_axi_a_set_rate failed\n");
1207
1208         return 0;
1209 }
1210
1211 static unsigned long _clk_axi_round_rate(struct clk *clk,
1212                                                 unsigned long rate)
1213 {
1214         u32 div;
1215         u32 parent_rate = clk_get_rate(clk->parent);
1216
1217         div = parent_rate / rate;
1218
1219         /* Make sure rate is not greater than the maximum
1220          * value for the clock.
1221          * Also prevent a div of 0.
1222          */
1223
1224         if (div > 8)
1225                 div = 8;
1226         else if (div == 0)
1227                 div++;
1228
1229         return parent_rate / div;
1230 }
1231
1232 static int _clk_axi_set_parent(struct clk *clk, struct clk *parent)
1233 {
1234         u32 reg;
1235         int mux;
1236
1237         mux = _get_mux6(parent, &periph_clk, &pll2_pfd_400M,
1238                                 &pll3_pfd_540M, NULL, NULL, NULL);
1239
1240         if (mux == 0) {
1241                 /* Set the AXI_SEL mux */
1242                 reg = __raw_readl(MXC_CCM_CBCDR) & ~MXC_CCM_CBCDR_AXI_SEL;
1243                 __raw_writel(reg, MXC_CCM_CBCDR);
1244         } else {
1245                 /* Set the AXI_ALT_SEL mux. */
1246                 reg = __raw_readl(MXC_CCM_CBCDR)
1247                         & ~MXC_CCM_CBCDR_AXI_ALT_SEL_MASK;
1248                 reg = ((mux - 1) << MXC_CCM_CBCDR_AXI_ALT_SEL_OFFSET);
1249                 __raw_writel(reg, MXC_CCM_CBCDR);
1250
1251                 /* Set the AXI_SEL mux */
1252                 reg = __raw_readl(MXC_CCM_CBCDR) & ~MXC_CCM_CBCDR_AXI_SEL;
1253                 reg |= MXC_CCM_CBCDR_AXI_SEL;
1254                 __raw_writel(reg, MXC_CCM_CBCDR);
1255         }
1256         return 0;
1257 }
1258
1259 static struct clk axi_clk = {
1260         __INIT_CLK_DEBUG(axi_clk)
1261         .parent = &periph_clk,
1262         .set_parent = _clk_axi_set_parent,
1263         .set_rate = _clk_axi_set_rate,
1264         .get_rate = _clk_axi_get_rate,
1265         .round_rate = _clk_axi_round_rate,
1266 };
1267
1268 static unsigned long _clk_ahb_get_rate(struct clk *clk)
1269 {
1270         u32 reg, div;
1271
1272         reg = __raw_readl(MXC_CCM_CBCDR);
1273         div = ((reg & MXC_CCM_CBCDR_AHB_PODF_MASK) >>
1274                MXC_CCM_CBCDR_AHB_PODF_OFFSET) + 1;
1275
1276         return clk_get_rate(clk->parent) / div;
1277 }
1278
1279 static int _clk_ahb_set_rate(struct clk *clk, unsigned long rate)
1280 {
1281         u32 reg, div;
1282         u32 parent_rate = clk_get_rate(clk->parent);
1283
1284         div = parent_rate / rate;
1285         if (div == 0)
1286                 div++;
1287         if (((parent_rate / div) != rate) || (div > 8))
1288                 return -EINVAL;
1289
1290         reg = __raw_readl(MXC_CCM_CBCDR);
1291         reg &= ~MXC_CCM_CBCDR_AHB_PODF_MASK;
1292         reg |= (div - 1) << MXC_CCM_CBCDR_AHB_PODF_OFFSET;
1293         __raw_writel(reg, MXC_CCM_CBCDR);
1294
1295         if (!WAIT(!(__raw_readl(MXC_CCM_CDHIPR) & MXC_CCM_CDHIPR_AHB_PODF_BUSY),
1296                                 SPIN_DELAY))
1297                         panic("_clk_ahb_set_rate failed\n");
1298
1299         return 0;
1300 }
1301
1302 static unsigned long _clk_ahb_round_rate(struct clk *clk,
1303                                                 unsigned long rate)
1304 {
1305         u32 div;
1306         u32 parent_rate = clk_get_rate(clk->parent);
1307
1308         div = parent_rate / rate;
1309
1310         /* Make sure rate is not greater than the maximum value for the clock.
1311          * Also prevent a div of 0.
1312          */
1313         if (div == 0)
1314                 div++;
1315
1316         if (div > 8)
1317                 div = 8;
1318
1319         return parent_rate / div;
1320 }
1321
1322 static struct clk ahb_clk = {
1323         __INIT_CLK_DEBUG(ahb_clk)
1324         .parent = &periph_clk,
1325         .get_rate = _clk_ahb_get_rate,
1326         .set_rate = _clk_ahb_set_rate,
1327         .round_rate = _clk_ahb_round_rate,
1328 };
1329
1330 static unsigned long _clk_ipg_get_rate(struct clk *clk)
1331 {
1332         u32 reg, div;
1333
1334         reg = __raw_readl(MXC_CCM_CBCDR);
1335         div = ((reg & MXC_CCM_CBCDR_IPG_PODF_MASK) >>
1336                 MXC_CCM_CBCDR_IPG_PODF_OFFSET) + 1;
1337
1338         return clk_get_rate(clk->parent) / div;
1339 }
1340
1341
1342 static struct clk ipg_clk = {
1343         __INIT_CLK_DEBUG(ipg_clk)
1344         .parent = &ahb_clk,
1345         .get_rate = _clk_ipg_get_rate,
1346 };
1347
1348 static struct clk tzasc1_clk = {
1349         __INIT_CLK_DEBUG(tzasc1_clk)
1350         .id = 0,
1351         .parent = &ipg_clk,
1352         .enable_reg = MXC_CCM_CCGR2,
1353         .enable_shift = MXC_CCM_CCGRx_CG11_OFFSET,
1354         .enable = _clk_enable,
1355         .disable = _clk_disable_inwait,
1356 };
1357
1358 static struct clk tzasc2_clk = {
1359         __INIT_CLK_DEBUG(tzasc2_clk)
1360         .id = 0,
1361         .parent = &ipg_clk,
1362         .enable_reg = MXC_CCM_CCGR2,
1363         .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET,
1364         .enable = _clk_enable,
1365         .disable = _clk_disable_inwait,
1366 };
1367
1368 static struct clk mx6fast1_clk = {
1369         __INIT_CLK_DEBUG(mx6fast1_clk)
1370         .id = 0,
1371         .parent = &ahb_clk,
1372         .enable_reg = MXC_CCM_CCGR4,
1373         .enable_shift = MXC_CCM_CCGRx_CG4_OFFSET,
1374         .enable = _clk_enable,
1375         .disable = _clk_disable_inwait,
1376 };
1377
1378 static struct clk mx6per1_clk = {
1379         __INIT_CLK_DEBUG(mx6per1_clk)
1380         .id = 0,
1381         .parent = &ahb_clk,
1382         .secondary = &mx6fast1_clk,
1383         .enable_reg = MXC_CCM_CCGR4,
1384         .enable_shift = MXC_CCM_CCGRx_CG6_OFFSET,
1385         .enable = _clk_enable,
1386         .disable = _clk_disable_inwait,
1387 };
1388
1389 static struct clk mx6per2_clk = {
1390         __INIT_CLK_DEBUG(mx6per2_clk)
1391         .id = 0,
1392         .parent = &ahb_clk,
1393         .enable_reg = MXC_CCM_CCGR4,
1394         .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
1395         .enable = _clk_enable,
1396         .disable = _clk_disable_inwait,
1397 };
1398
1399 static unsigned long _clk_mmdc_ch0_axi_get_rate(struct clk *clk)
1400 {
1401         u32 reg, div;
1402
1403         reg = __raw_readl(MXC_CCM_CBCDR);
1404         div = ((reg & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
1405                         MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET) + 1;
1406
1407         return clk_get_rate(clk->parent) / div;
1408 }
1409
1410 static int _clk_mmdc_ch0_axi_set_rate(struct clk *clk, unsigned long rate)
1411 {
1412         u32 reg, div;
1413         u32 parent_rate = clk_get_rate(clk->parent);
1414
1415         div = parent_rate / rate;
1416         if (div == 0)
1417                 div++;
1418         if (((parent_rate / div) != rate) || (div > 8))
1419                 return -EINVAL;
1420
1421         reg = __raw_readl(MXC_CCM_CBCDR);
1422         reg &= ~MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK;
1423         reg |= (div - 1) << MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
1424         __raw_writel(reg, MXC_CCM_CBCDR);
1425
1426         if (!WAIT(!(__raw_readl(MXC_CCM_CDHIPR)
1427                 & MXC_CCM_CDHIPR_MMDC_CH0_PODF_BUSY),
1428                                 SPIN_DELAY))
1429                         panic("_clk_mmdc_ch0_axi_set_rate failed\n");
1430
1431         return 0;
1432 }
1433
1434 static unsigned long _clk_mmdc_ch0_axi_round_rate(struct clk *clk,
1435                                                 unsigned long rate)
1436 {
1437         u32 div;
1438         u32 parent_rate = clk_get_rate(clk->parent);
1439
1440         div = parent_rate / rate;
1441
1442         /* Make sure rate is not greater than the maximum value for the clock.
1443          * Also prevent a div of 0.
1444          */
1445         if (div == 0)
1446                 div++;
1447
1448         if (div > 8)
1449                 div = 8;
1450
1451         return parent_rate / div;
1452 }
1453
1454 static struct clk mmdc_ch0_axi_clk[] = {
1455         {
1456         __INIT_CLK_DEBUG(mmdc_ch0_axi_clk)
1457         .id = 0,
1458         .parent = &periph_clk,
1459         .enable = _clk_enable,
1460         .disable = _clk_disable_inwait,
1461         .enable_reg = MXC_CCM_CCGR3,
1462         .enable_shift = MXC_CCM_CCGRx_CG10_OFFSET,
1463         .secondary = &mmdc_ch0_axi_clk[1],
1464         .get_rate = _clk_mmdc_ch0_axi_get_rate,
1465         .set_rate = _clk_mmdc_ch0_axi_set_rate,
1466         .round_rate = _clk_mmdc_ch0_axi_round_rate,
1467         },
1468         {
1469         __INIT_CLK_DEBUG(mmdc_ch0_ipg_clk)
1470         .id = 0,
1471         .parent = &ipg_clk,
1472         .enable = _clk_enable,
1473         .disable = _clk_disable_inwait,
1474         .enable_reg = MXC_CCM_CCGR3,
1475         .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET,
1476         .secondary = &tzasc1_clk,
1477         },
1478 };
1479
1480 static unsigned long _clk_mmdc_ch1_axi_get_rate(struct clk *clk)
1481 {
1482         u32 reg, div;
1483
1484         reg = __raw_readl(MXC_CCM_CBCDR);
1485         div = ((reg & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) >>
1486                         MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET) + 1;
1487
1488         return clk_get_rate(clk->parent) / div;
1489 }
1490
1491 static int _clk_mmdc_ch1_axi_set_rate(struct clk *clk, unsigned long rate)
1492 {
1493         u32 reg, div;
1494         u32 parent_rate = clk_get_rate(clk->parent);
1495
1496         div = parent_rate / rate;
1497         if (div == 0)
1498                 div++;
1499         if (((parent_rate / div) != rate) || (div > 8))
1500                 return -EINVAL;
1501
1502         reg = __raw_readl(MXC_CCM_CBCDR);
1503         reg &= ~MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK;
1504         reg |= (div - 1) << MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
1505         __raw_writel(reg, MXC_CCM_CBCDR);
1506
1507         if (!WAIT(!(__raw_readl(MXC_CCM_CDHIPR)
1508                 & MXC_CCM_CDHIPR_MMDC_CH1_PODF_BUSY), SPIN_DELAY))
1509                         panic("_clk_mmdc_ch1_axi_set_rate failed\n");
1510
1511         return 0;
1512 }
1513
1514 static unsigned long _clk_mmdc_ch1_axi_round_rate(struct clk *clk,
1515                                                 unsigned long rate)
1516 {
1517         u32 div;
1518         u32 parent_rate = clk_get_rate(clk->parent);
1519
1520         div = parent_rate / rate;
1521
1522         /* Make sure rate is not greater than the maximum value for the clock.
1523          * Also prevent a div of 0.
1524          */
1525         if (div == 0)
1526                 div++;
1527
1528         if (div > 8)
1529                 div = 8;
1530
1531         return parent_rate / div;
1532 }
1533
1534 static struct clk mmdc_ch1_axi_clk[] = {
1535         {
1536         __INIT_CLK_DEBUG(mmdc_ch1_axi_clk)
1537         .id = 0,
1538         .parent = &pll2_pfd_400M,
1539         .enable = _clk_enable,
1540         .disable = _clk_disable,
1541         .enable_reg = MXC_CCM_CCGR3,
1542         .enable_shift = MXC_CCM_CCGRx_CG11_OFFSET,
1543         .secondary = &mmdc_ch1_axi_clk[1],
1544         .get_rate = _clk_mmdc_ch1_axi_get_rate,
1545         .set_rate = _clk_mmdc_ch1_axi_set_rate,
1546         .round_rate = _clk_mmdc_ch1_axi_round_rate,
1547         },
1548         {
1549         .id = 1,
1550         __INIT_CLK_DEBUG(mmdc_ch1_ipg_clk)
1551         .parent = &ipg_clk,
1552         .enable = _clk_enable,
1553         .disable = _clk_disable,
1554         .enable_reg = MXC_CCM_CCGR3,
1555         .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
1556         .secondary = &tzasc2_clk,
1557         },
1558 };
1559
1560 static struct clk ocram_clk = {
1561         __INIT_CLK_DEBUG(ocram_clk)
1562         .id = 0,
1563         .parent = &ahb_clk,
1564         .enable_reg = MXC_CCM_CCGR3,
1565         .enable_shift = MXC_CCM_CCGRx_CG14_OFFSET,
1566         .enable = _clk_enable,
1567         .disable = _clk_disable_inwait,
1568 };
1569
1570 static unsigned long _clk_ipg_perclk_get_rate(struct clk *clk)
1571 {
1572         u32 reg, div;
1573
1574         reg = __raw_readl(MXC_CCM_CSCMR1);
1575         div = ((reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK) >>
1576                         MXC_CCM_CSCMR1_PERCLK_PODF_OFFSET) + 1;
1577
1578         return clk_get_rate(clk->parent) / div;
1579 }
1580
1581 static int _clk_ipg_perclk_set_rate(struct clk *clk, unsigned long rate)
1582 {
1583         u32 reg, div;
1584         u32 parent_rate = clk_get_rate(clk->parent);
1585
1586         div = parent_rate / rate;
1587         if (div == 0)
1588                 div++;
1589         if (((parent_rate / div) != rate) || (div > 64))
1590                 return -EINVAL;
1591
1592         reg = __raw_readl(MXC_CCM_CSCMR1);
1593         reg &= ~MXC_CCM_CSCMR1_PERCLK_PODF_MASK;
1594         reg |= (div - 1) << MXC_CCM_CSCMR1_PERCLK_PODF_OFFSET;
1595         __raw_writel(reg, MXC_CCM_CSCMR1);
1596
1597         return 0;
1598 }
1599
1600
1601 static unsigned long _clk_ipg_perclk_round_rate(struct clk *clk,
1602                                                 unsigned long rate)
1603 {
1604         u32 div;
1605         u32 parent_rate = clk_get_rate(clk->parent);
1606
1607         div = parent_rate / rate;
1608
1609         /* Make sure rate is not greater than the maximum value for the clock.
1610          * Also prevent a div of 0.
1611          */
1612         if (div == 0)
1613                 div++;
1614
1615         if (div > 64)
1616                 div = 64;
1617
1618         return parent_rate / div;
1619 }
1620
1621 static struct clk ipg_perclk = {
1622         __INIT_CLK_DEBUG(ipg_perclk)
1623         .parent = &ipg_clk,
1624         .get_rate = _clk_ipg_perclk_get_rate,
1625         .set_rate = _clk_ipg_perclk_set_rate,
1626         .round_rate = _clk_ipg_perclk_round_rate,
1627 };
1628
1629 static struct clk spba_clk = {
1630         __INIT_CLK_DEBUG(spba_clk)
1631         .parent = &ipg_clk,
1632         .enable_reg = MXC_CCM_CCGR5,
1633         .enable_shift = MXC_CCM_CCGRx_CG6_OFFSET,
1634         .enable = _clk_enable,
1635         .disable = _clk_disable,
1636 };
1637
1638 static struct clk sdma_clk[] = {
1639         {
1640          __INIT_CLK_DEBUG(sdma_clk)
1641          .parent = &ahb_clk,
1642          .enable_reg = MXC_CCM_CCGR5,
1643          .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET,
1644          .enable = _clk_enable,
1645          .disable = _clk_disable,
1646          .secondary = &sdma_clk[1],
1647         },
1648         {
1649          .parent = &mx6per1_clk,
1650 #ifdef CONFIG_SDMA_IRAM
1651          .secondary = &ocram_clk,
1652 #else
1653         .secondary = &mmdc_ch0_axi_clk[0],
1654 #endif
1655         },
1656 };
1657
1658 static int _clk_gpu2d_axi_set_parent(struct clk *clk, struct clk *parent)
1659 {
1660         u32 reg = __raw_readl(MXC_CCM_CBCMR) & ~MXC_CCM_CBCMR_GPU2D_AXI_CLK_SEL;
1661
1662         if (parent == &ahb_clk)
1663                 reg |= MXC_CCM_CBCMR_GPU2D_AXI_CLK_SEL;
1664
1665         __raw_writel(reg, MXC_CCM_CBCMR);
1666
1667         return 0;
1668 }
1669
1670 static struct clk gpu2d_axi_clk = {
1671         __INIT_CLK_DEBUG(gpu2d_axi_clk)
1672         .parent = &axi_clk,
1673         .secondary = &openvg_axi_clk,
1674         .set_parent = _clk_gpu2d_axi_set_parent,
1675 };
1676
1677 static int _clk_gpu3d_axi_set_parent(struct clk *clk, struct clk *parent)
1678 {
1679         u32 reg = __raw_readl(MXC_CCM_CBCMR) & ~MXC_CCM_CBCMR_GPU3D_AXI_CLK_SEL;
1680
1681         if (parent == &ahb_clk)
1682                 reg |= MXC_CCM_CBCMR_GPU3D_AXI_CLK_SEL;
1683
1684         __raw_writel(reg, MXC_CCM_CBCMR);
1685
1686         return 0;
1687 }
1688
1689 static struct clk gpu3d_axi_clk = {
1690         __INIT_CLK_DEBUG(gpu3d_axi_clk)
1691         .parent = &axi_clk,
1692         .secondary = &mmdc_ch0_axi_clk[0],
1693         .set_parent = _clk_gpu3d_axi_set_parent,
1694 };
1695
1696 static int _clk_pcie_axi_set_parent(struct clk *clk, struct clk *parent)
1697 {
1698         u32 reg = __raw_readl(MXC_CCM_CBCMR) & ~MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL;
1699
1700         if (parent == &ahb_clk)
1701                 reg |= MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL;
1702
1703         __raw_writel(reg, MXC_CCM_CBCMR);
1704
1705         return 0;
1706 }
1707
1708 static struct clk pcie_axi_clk = {
1709         __INIT_CLK_DEBUG(pcie_axi_clk)
1710         .parent = &axi_clk,
1711         .set_parent = _clk_pcie_axi_set_parent,
1712 };
1713
1714 static int _clk_vdo_axi_set_parent(struct clk *clk, struct clk *parent)
1715 {
1716         u32 reg = __raw_readl(MXC_CCM_CBCMR) & ~MXC_CCM_CBCMR_VDOAXI_CLK_SEL;
1717
1718         if (parent == &ahb_clk)
1719                 reg |= MXC_CCM_CBCMR_VDOAXI_CLK_SEL;
1720
1721         __raw_writel(reg, MXC_CCM_CBCMR);
1722
1723         return 0;
1724 }
1725
1726 static struct clk vdo_axi_clk = {
1727         __INIT_CLK_DEBUG(vdo_axi_clk)
1728         .parent = &axi_clk,
1729         .enable_reg = MXC_CCM_CCGR6,
1730         .enable_shift = MXC_CCM_CCGRx_CG6_OFFSET,
1731         .enable = _clk_enable,
1732         .disable = _clk_disable,
1733         .set_parent = _clk_vdo_axi_set_parent,
1734 };
1735
1736 static struct clk vdoa_clk = {
1737         __INIT_CLK_DEBUG(vdoa_clk)
1738         .id = 0,
1739         .parent = &axi_clk,
1740         .secondary = &mx6fast1_clk,
1741         .enable_reg = MXC_CCM_CCGR2,
1742         .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
1743         .enable = _clk_enable,
1744         .disable = _clk_disable,
1745 };
1746
1747 static unsigned long _clk_gpt_get_rate(struct clk *clk)
1748 {
1749         u32 reg;
1750         unsigned long rate;
1751
1752         if (mx6q_revision() == IMX_CHIP_REVISION_1_0)
1753                 return clk_get_rate(clk->parent);
1754
1755         rate = mx6_timer_rate();
1756         if (!rate)
1757                 return clk_get_rate(clk->parent);
1758
1759         return rate;
1760 }
1761
1762 static struct clk gpt_clk[] = {
1763         {
1764         __INIT_CLK_DEBUG(gpt_clk)
1765          .parent = &osc_clk,
1766          .id = 0,
1767          .enable_reg = MXC_CCM_CCGR1,
1768          .enable_shift = MXC_CCM_CCGRx_CG10_OFFSET,
1769          .enable = _clk_enable,
1770          .disable = _clk_disable,
1771          .get_rate = _clk_gpt_get_rate,
1772          .secondary = &gpt_clk[1],
1773          },
1774         {
1775         __INIT_CLK_DEBUG(gpt_serial_clk)
1776          .id = 0,
1777          .enable_reg = MXC_CCM_CCGR1,
1778          .enable_shift = MXC_CCM_CCGRx_CG11_OFFSET,
1779          .enable = _clk_enable,
1780          .disable = _clk_disable,
1781          },
1782 };
1783
1784 static unsigned long _clk_iim_get_rate(struct clk *clk)
1785 {
1786         return clk_get_rate(clk->parent);
1787 }
1788
1789 static struct clk iim_clk = {
1790         __INIT_CLK_DEBUG(iim_clk)
1791         .parent = &ipg_clk,
1792         .enable = _clk_enable,
1793         .enable_reg = MXC_CCM_CCGR2,
1794         .enable_shift = MXC_CCM_CCGRx_CG6_OFFSET,
1795         .disable = _clk_disable,
1796         .get_rate = _clk_iim_get_rate,
1797 };
1798
1799 static struct clk i2c_clk[] = {
1800         {
1801         __INIT_CLK_DEBUG(i2c_clk_0)
1802          .id = 0,
1803          .parent = &ipg_perclk,
1804          .enable_reg = MXC_CCM_CCGR2,
1805          .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET,
1806          .enable = _clk_enable,
1807          .disable = _clk_disable,
1808          },
1809         {
1810         __INIT_CLK_DEBUG(i2c_clk_1)
1811          .id = 1,
1812          .parent = &ipg_perclk,
1813          .enable_reg = MXC_CCM_CCGR2,
1814          .enable_shift = MXC_CCM_CCGRx_CG4_OFFSET,
1815          .enable = _clk_enable,
1816          .disable = _clk_disable,
1817          },
1818         {
1819         __INIT_CLK_DEBUG(i2c_clk_2)
1820          .id = 2,
1821          .parent = &ipg_perclk,
1822          .enable_reg = MXC_CCM_CCGR2,
1823          .enable_shift = MXC_CCM_CCGRx_CG5_OFFSET,
1824          .enable = _clk_enable,
1825          .disable = _clk_disable,
1826          },
1827 };
1828
1829 static int _clk_vpu_axi_set_parent(struct clk *clk, struct clk *parent)
1830 {
1831         int mux;
1832         u32 reg = __raw_readl(MXC_CCM_CBCMR)
1833                 & ~MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK;
1834
1835         mux = _get_mux6(parent, &axi_clk, &pll2_pfd_400M,
1836                 &pll2_pfd_352M, NULL, NULL, NULL);
1837
1838         reg |= (mux << MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET);
1839
1840         __raw_writel(reg, MXC_CCM_CBCMR);
1841
1842         return 0;
1843 }
1844
1845 static unsigned long _clk_vpu_axi_get_rate(struct clk *clk)
1846 {
1847         u32 reg, div;
1848
1849         reg = __raw_readl(MXC_CCM_CSCDR1);
1850         div = ((reg & MXC_CCM_CSCDR1_VPU_AXI_PODF_MASK) >>
1851                         MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET) + 1;
1852
1853         return clk_get_rate(clk->parent) / div;
1854 }
1855
1856 static int _clk_vpu_axi_set_rate(struct clk *clk, unsigned long rate)
1857 {
1858         u32 reg, div;
1859         u32 parent_rate = clk_get_rate(clk->parent);
1860
1861         div = parent_rate / rate;
1862         if (div == 0)
1863                 div++;
1864         if (((parent_rate / div) != rate) || (div > 8))
1865                 return -EINVAL;
1866
1867         reg = __raw_readl(MXC_CCM_CSCDR1);
1868         reg &= ~MXC_CCM_CSCDR1_VPU_AXI_PODF_MASK;
1869         reg |= (div - 1) << MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET;
1870         __raw_writel(reg, MXC_CCM_CSCDR1);
1871
1872         return 0;
1873 }
1874
1875 static unsigned long _clk_vpu_axi_round_rate(struct clk *clk,
1876                                                 unsigned long rate)
1877 {
1878         u32 div;
1879         u32 parent_rate = clk_get_rate(clk->parent);
1880
1881         div = parent_rate / rate;
1882
1883         /* Make sure rate is not greater than the maximum value for the clock.
1884          * Also prevent a div of 0.
1885          */
1886         if (div == 0)
1887                 div++;
1888
1889         if (div > 8)
1890                 div = 8;
1891
1892         return parent_rate / div;
1893 }
1894
1895 static struct clk vpu_clk[] = {
1896         {
1897         __INIT_CLK_DEBUG(vpu_clk)
1898         .parent = &axi_clk,
1899         .enable_reg = MXC_CCM_CCGR6,
1900         .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
1901         .enable = _clk_enable,
1902         .disable = _clk_disable,
1903         .set_parent = _clk_vpu_axi_set_parent,
1904         .round_rate = _clk_vpu_axi_round_rate,
1905         .set_rate = _clk_vpu_axi_set_rate,
1906         .get_rate = _clk_vpu_axi_get_rate,
1907         .secondary = &vpu_clk[1],
1908         },
1909         {
1910         .parent =  &mmdc_ch0_axi_clk[0],
1911         .secondary = &vpu_clk[2],
1912         },
1913         {
1914         .parent =  &mx6fast1_clk,
1915         .secondary = &ocram_clk,
1916         },
1917
1918 };
1919
1920 static int _clk_ipu1_set_parent(struct clk *clk, struct clk *parent)
1921 {
1922         int mux;
1923         u32 reg = __raw_readl(MXC_CCM_CSCDR3)
1924                 & ~MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_MASK;
1925
1926         mux = _get_mux6(parent, &mmdc_ch0_axi_clk[0],
1927                 &pll2_pfd_400M, &pll3_120M, &pll3_pfd_540M, NULL, NULL);
1928
1929         reg |= (mux << MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_OFFSET);
1930
1931         __raw_writel(reg, MXC_CCM_CSCDR3);
1932
1933         return 0;
1934 }
1935
1936 static unsigned long _clk_ipu1_get_rate(struct clk *clk)
1937 {
1938         u32 reg, div;
1939
1940         reg = __raw_readl(MXC_CCM_CSCDR3);
1941         div = ((reg & MXC_CCM_CSCDR3_IPU1_HSP_PODF_MASK) >>
1942                         MXC_CCM_CSCDR3_IPU1_HSP_PODF_OFFSET) + 1;
1943
1944         return clk_get_rate(clk->parent) / div;
1945 }
1946
1947 static int _clk_ipu1_set_rate(struct clk *clk, unsigned long rate)
1948 {
1949         u32 reg, div;
1950         u32 parent_rate = clk_get_rate(clk->parent);
1951
1952         div = parent_rate / rate;
1953         if (div == 0)
1954                 div++;
1955         if (((parent_rate / div) != rate) || (div > 8))
1956                 return -EINVAL;
1957
1958         reg = __raw_readl(MXC_CCM_CSCDR3);
1959         reg &= ~MXC_CCM_CSCDR3_IPU1_HSP_PODF_MASK;
1960         reg |= (div - 1) << MXC_CCM_CSCDR3_IPU1_HSP_PODF_OFFSET;
1961         __raw_writel(reg, MXC_CCM_CSCDR3);
1962
1963         return 0;
1964 }
1965
1966 static unsigned long _clk_ipu_round_rate(struct clk *clk,
1967                                                 unsigned long rate)
1968 {
1969         u32 div;
1970         u32 parent_rate = clk_get_rate(clk->parent);
1971
1972         div = parent_rate / rate;
1973
1974         /* Make sure rate is not greater than the maximum value for the clock.
1975          * Also prevent a div of 0.
1976          */
1977         if (div == 0)
1978                 div++;
1979
1980         if (div > 8)
1981                 div = 8;
1982
1983         return parent_rate / div;
1984 }
1985
1986 static struct clk ipu1_clk = {
1987         __INIT_CLK_DEBUG(ipu1_clk)
1988         .parent = &mmdc_ch0_axi_clk[0],
1989         .secondary = &mmdc_ch0_axi_clk[0],
1990         .enable_reg = MXC_CCM_CCGR3,
1991         .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET,
1992         .enable = _clk_enable,
1993         .disable = _clk_disable,
1994         .set_parent = _clk_ipu1_set_parent,
1995         .round_rate = _clk_ipu_round_rate,
1996         .set_rate = _clk_ipu1_set_rate,
1997         .get_rate = _clk_ipu1_get_rate,
1998         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
1999 };
2000
2001 static int _clk_cko1_clk0_set_parent(struct clk *clk, struct clk *parent)
2002 {
2003         u32 sel, reg;
2004
2005         if (parent == &pll3_sw_clk)
2006                 sel = 0;
2007         else if (parent == &pll2_528_bus_main_clk)
2008                 sel = 1;
2009         else if (parent == &pll1_sys_main_clk)
2010                 sel = 2;
2011         else if (parent == &pll5_video_main_clk)
2012                 sel = 3;
2013         else if (parent == &axi_clk)
2014                 sel = 5;
2015         else if (parent == &enfc_clk)
2016                 sel = 6;
2017         else if (parent == &ipu1_di_clk_root)
2018                 sel = 7;
2019         else if (parent == &ipu1_di_clk_root)
2020                 sel = 8;
2021         else if (parent == &ipu2_di_clk_root)
2022                 sel = 9;
2023         else if (parent == &ipu2_di_clk_root)
2024                 sel = 10;
2025         else if (parent == &ahb_clk)
2026                 sel = 11;
2027         else if (parent == &ipg_clk)
2028                 sel = 12;
2029         else if (parent == &ipg_perclk)
2030                 sel = 13;
2031         else if (parent == &ckil_clk)
2032                 sel = 14;
2033         else if (parent == &pll4_audio_main_clk)
2034                 sel = 15;
2035         else
2036                 return -EINVAL;
2037
2038         reg = __raw_readl(MXC_CCM_CCOSR);
2039         reg &= ~MXC_CCM_CCOSR_CKOL_SEL_MASK;
2040         reg |= sel << MXC_CCM_CCOSR_CKOL_SEL_OFFSET;
2041         __raw_writel(reg, MXC_CCM_CCOSR);
2042         return 0;
2043 }
2044
2045 static unsigned long _clk_cko1_round_rate(struct clk *clk,
2046                                                 unsigned long rate)
2047 {
2048         u32 div;
2049         u32 parent_rate = clk_get_rate(clk->parent);
2050
2051         div = parent_rate / rate;
2052
2053         /* Make sure rate is not greater than the maximum value for the clock.
2054          * Also prevent a div of 0.
2055          */
2056         if (div == 0)
2057                 div++;
2058
2059         if (div > 8)
2060                 div = 8;
2061
2062         return parent_rate / div;
2063 }
2064
2065 static int _clk_cko1_set_rate(struct clk *clk, unsigned long rate)
2066 {
2067         u32 reg, div;
2068         u32 parent_rate = clk_get_rate(clk->parent);
2069
2070         div = parent_rate / rate;
2071         if (div == 0)
2072                 div++;
2073         if (((parent_rate / div) != rate) || (div > 8))
2074                 return -EINVAL;
2075
2076         reg = __raw_readl(MXC_CCM_CCOSR);
2077         reg &= ~MXC_CCM_CCOSR_CKOL_DIV_MASK;
2078         reg |= div << MXC_CCM_CCOSR_CKOL_DIV_OFFSET;
2079         __raw_writel(reg, MXC_CCM_CCOSR);
2080
2081         return 0;
2082 }
2083
2084 static unsigned long _clk_cko1_get_rate(struct clk *clk)
2085 {
2086         u32 reg, div;
2087
2088         reg = __raw_readl(MXC_CCM_CCOSR);
2089         div = ((reg & MXC_CCM_CCOSR_CKOL_DIV_MASK) >>
2090                         MXC_CCM_CCOSR_CKOL_DIV_OFFSET) + 1;
2091
2092         return clk_get_rate(clk->parent) / div;
2093 }
2094
2095 static int cko1_clk_enable(struct clk *clk)
2096 {
2097         u32 reg;
2098         reg = __raw_readl(clk->enable_reg);
2099         reg |= clk->enable_shift;
2100         __raw_writel(reg, clk->enable_reg);
2101
2102         return 0;
2103 }
2104
2105 static struct clk cko1_clk0 = {
2106         __INIT_CLK_DEBUG(cko1_clk0)
2107         .parent = &ipg_clk,
2108         .enable_reg = MXC_CCM_CCOSR,
2109         .enable_shift = MXC_CCM_CCOSR_CKOL_EN,
2110         .enable = cko1_clk_enable,
2111         .disable = _clk_disable,
2112         .set_parent = _clk_cko1_clk0_set_parent,
2113         .round_rate = _clk_cko1_round_rate,
2114         .set_rate = _clk_cko1_set_rate,
2115         .get_rate = _clk_cko1_get_rate,
2116 };
2117
2118 static int _clk_ipu2_set_parent(struct clk *clk, struct clk *parent)
2119 {
2120         int mux;
2121         u32 reg = __raw_readl(MXC_CCM_CSCDR3)
2122                 & ~MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_MASK;
2123
2124         mux = _get_mux6(parent, &mmdc_ch0_axi_clk[0],
2125                 &pll2_pfd_400M, &pll3_120M, &pll3_pfd_540M, NULL, NULL);
2126
2127         reg |= (mux << MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_OFFSET);
2128
2129         __raw_writel(reg, MXC_CCM_CSCDR3);
2130
2131         return 0;
2132 }
2133
2134 static unsigned long _clk_ipu2_get_rate(struct clk *clk)
2135 {
2136         u32 reg, div;
2137
2138         reg = __raw_readl(MXC_CCM_CSCDR3);
2139         div = ((reg & MXC_CCM_CSCDR3_IPU2_HSP_PODF_MASK) >>
2140                         MXC_CCM_CSCDR3_IPU2_HSP_PODF_OFFSET) + 1;
2141
2142         return clk_get_rate(clk->parent) / div;
2143 }
2144
2145 static int _clk_ipu2_set_rate(struct clk *clk, unsigned long rate)
2146 {
2147         u32 reg, div;
2148         u32 parent_rate = clk_get_rate(clk->parent);
2149
2150         div = parent_rate / rate;
2151         if (div == 0)
2152                 div++;
2153         if (((parent_rate / div) != rate) || (div > 8))
2154                 return -EINVAL;
2155
2156         reg = __raw_readl(MXC_CCM_CSCDR3);
2157         reg &= ~MXC_CCM_CSCDR3_IPU2_HSP_PODF_MASK;
2158         reg |= (div - 1) << MXC_CCM_CSCDR3_IPU2_HSP_PODF_OFFSET;
2159         __raw_writel(reg, MXC_CCM_CSCDR3);
2160
2161         return 0;
2162 }
2163
2164 static struct clk ipu2_clk = {
2165         __INIT_CLK_DEBUG(ipu2_clk)
2166         .parent = &mmdc_ch0_axi_clk[0],
2167         .secondary = &mmdc_ch0_axi_clk[0],
2168         .enable_reg = MXC_CCM_CCGR3,
2169         .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET,
2170         .enable = _clk_enable,
2171         .disable = _clk_disable,
2172         .set_parent = _clk_ipu2_set_parent,
2173         .round_rate = _clk_ipu_round_rate,
2174         .set_rate = _clk_ipu2_set_rate,
2175         .get_rate = _clk_ipu2_get_rate,
2176         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
2177 };
2178
2179 static struct clk usdhc_dep_clk = {
2180         .parent = &mmdc_ch0_axi_clk[0],
2181         .secondary = &mx6per1_clk,
2182         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
2183         };
2184
2185 static unsigned long _clk_usdhc_round_rate(struct clk *clk,
2186                                                 unsigned long rate)
2187 {
2188         u32 div;
2189         u32 parent_rate = clk_get_rate(clk->parent);
2190
2191         div = parent_rate / rate;
2192
2193         /* Make sure rate is not greater than the maximum value for the clock.
2194          * Also prevent a div of 0.
2195          */
2196         if (div == 0)
2197                 div++;
2198
2199         if (div > 8)
2200                 div = 8;
2201
2202         return parent_rate / div;
2203 }
2204
2205 static int _clk_usdhc1_set_parent(struct clk *clk, struct clk *parent)
2206 {
2207         u32 reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_USDHC1_CLK_SEL;
2208
2209         if (parent == &pll2_pfd_352M)
2210                 reg |= (MXC_CCM_CSCMR1_USDHC1_CLK_SEL);
2211
2212         __raw_writel(reg, MXC_CCM_CSCMR1);
2213
2214         return 0;
2215 }
2216
2217 static unsigned long _clk_usdhc1_get_rate(struct clk *clk)
2218 {
2219         u32 reg, div;
2220
2221         reg = __raw_readl(MXC_CCM_CSCDR1);
2222         div = ((reg & MXC_CCM_CSCDR1_USDHC1_PODF_MASK) >>
2223                         MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET) + 1;
2224
2225         return clk_get_rate(clk->parent) / div;
2226 }
2227
2228 static int _clk_usdhc1_set_rate(struct clk *clk, unsigned long rate)
2229 {
2230         u32 reg, div;
2231         u32 parent_rate = clk_get_rate(clk->parent);
2232
2233         div = parent_rate / rate;
2234         if (div == 0)
2235                 div++;
2236         if (((parent_rate / div) != rate) || (div > 8))
2237                 return -EINVAL;
2238
2239         reg = __raw_readl(MXC_CCM_CSCDR1);
2240         reg &= ~MXC_CCM_CSCDR1_USDHC1_PODF_MASK;
2241         reg |= (div - 1) << MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET;
2242         __raw_writel(reg, MXC_CCM_CSCDR1);
2243
2244         return 0;
2245 }
2246
2247 static struct clk usdhc1_clk = {
2248         __INIT_CLK_DEBUG(usdhc1_clk)
2249         .id = 0,
2250         .parent = &pll2_pfd_400M,
2251         .secondary = &usdhc_dep_clk,
2252         .enable_reg = MXC_CCM_CCGR6,
2253         .enable_shift = MXC_CCM_CCGRx_CG1_OFFSET,
2254         .enable = _clk_enable,
2255         .disable = _clk_disable,
2256         .set_parent = _clk_usdhc1_set_parent,
2257         .round_rate = _clk_usdhc_round_rate,
2258         .set_rate = _clk_usdhc1_set_rate,
2259         .get_rate = _clk_usdhc1_get_rate,
2260         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
2261 };
2262
2263 static int _clk_usdhc2_set_parent(struct clk *clk, struct clk *parent)
2264 {
2265         u32 reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_USDHC2_CLK_SEL;
2266
2267         if (parent == &pll2_pfd_352M)
2268                 reg |= (MXC_CCM_CSCMR1_USDHC2_CLK_SEL);
2269
2270         __raw_writel(reg, MXC_CCM_CSCMR1);
2271
2272         return 0;
2273 }
2274
2275 static unsigned long _clk_usdhc2_get_rate(struct clk *clk)
2276 {
2277         u32 reg, div;
2278
2279         reg = __raw_readl(MXC_CCM_CSCDR1);
2280         div = ((reg & MXC_CCM_CSCDR1_USDHC2_PODF_MASK) >>
2281                         MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET) + 1;
2282
2283         return clk_get_rate(clk->parent) / div;
2284 }
2285
2286 static int _clk_usdhc2_set_rate(struct clk *clk, unsigned long rate)
2287 {
2288         u32 reg, div;
2289         u32 parent_rate = clk_get_rate(clk->parent);
2290
2291         div = parent_rate / rate;
2292         if (div == 0)
2293                 div++;
2294         if (((parent_rate / div) != rate) || (div > 8))
2295                 return -EINVAL;
2296
2297         reg = __raw_readl(MXC_CCM_CSCDR1);
2298         reg &= ~MXC_CCM_CSCDR1_USDHC2_PODF_MASK;
2299         reg |= (div - 1) << MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET;
2300         __raw_writel(reg, MXC_CCM_CSCDR1);
2301
2302         return 0;
2303 }
2304
2305 static struct clk usdhc2_clk = {
2306         __INIT_CLK_DEBUG(usdhc2_clk)
2307         .id = 1,
2308         .parent = &pll2_pfd_400M,
2309         .secondary = &usdhc_dep_clk,
2310         .enable_reg = MXC_CCM_CCGR6,
2311         .enable_shift = MXC_CCM_CCGRx_CG2_OFFSET,
2312         .enable = _clk_enable,
2313         .disable = _clk_disable,
2314         .set_parent = _clk_usdhc2_set_parent,
2315         .round_rate = _clk_usdhc_round_rate,
2316         .set_rate = _clk_usdhc2_set_rate,
2317         .get_rate = _clk_usdhc2_get_rate,
2318         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
2319 };
2320
2321 static int _clk_usdhc3_set_parent(struct clk *clk, struct clk *parent)
2322 {
2323         u32 reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_USDHC3_CLK_SEL;
2324
2325         if (parent == &pll2_pfd_352M)
2326                 reg |= (MXC_CCM_CSCMR1_USDHC3_CLK_SEL);
2327
2328         __raw_writel(reg, MXC_CCM_CSCMR1);
2329
2330         return 0;
2331 }
2332
2333 static unsigned long _clk_usdhc3_get_rate(struct clk *clk)
2334 {
2335         u32 reg, div;
2336
2337         reg = __raw_readl(MXC_CCM_CSCDR1);
2338         div = ((reg & MXC_CCM_CSCDR1_USDHC3_PODF_MASK) >>
2339                         MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET) + 1;
2340
2341         return clk_get_rate(clk->parent) / div;
2342 }
2343
2344 static int _clk_usdhc3_set_rate(struct clk *clk, unsigned long rate)
2345 {
2346         u32 reg, div;
2347         u32 parent_rate = clk_get_rate(clk->parent);
2348
2349         div = parent_rate / rate;
2350         if (div == 0)
2351                 div++;
2352         if (((parent_rate / div) != rate) || (div > 8))
2353                 return -EINVAL;
2354
2355         reg = __raw_readl(MXC_CCM_CSCDR1);
2356         reg &= ~MXC_CCM_CSCDR1_USDHC3_PODF_MASK;
2357         reg |= (div - 1) << MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET;
2358         __raw_writel(reg, MXC_CCM_CSCDR1);
2359
2360         return 0;
2361 }
2362
2363
2364 static struct clk usdhc3_clk = {
2365         __INIT_CLK_DEBUG(usdhc3_clk)
2366         .id = 2,
2367         .parent = &pll2_pfd_400M,
2368         .secondary = &usdhc_dep_clk,
2369         .enable_reg = MXC_CCM_CCGR6,
2370         .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET,
2371         .enable = _clk_enable,
2372         .disable = _clk_disable,
2373         .set_parent = _clk_usdhc3_set_parent,
2374         .round_rate = _clk_usdhc_round_rate,
2375         .set_rate = _clk_usdhc3_set_rate,
2376         .get_rate = _clk_usdhc3_get_rate,
2377         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
2378 };
2379
2380 static int _clk_usdhc4_set_parent(struct clk *clk, struct clk *parent)
2381 {
2382         u32 reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_USDHC4_CLK_SEL;
2383
2384         if (parent == &pll2_pfd_352M)
2385                 reg |= (MXC_CCM_CSCMR1_USDHC4_CLK_SEL);
2386
2387         __raw_writel(reg, MXC_CCM_CSCMR1);
2388
2389         return 0;
2390 }
2391
2392 static unsigned long _clk_usdhc4_get_rate(struct clk *clk)
2393 {
2394         u32 reg, div;
2395
2396         reg = __raw_readl(MXC_CCM_CSCDR1);
2397         div = ((reg & MXC_CCM_CSCDR1_USDHC4_PODF_MASK) >>
2398                         MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET) + 1;
2399
2400         return clk_get_rate(clk->parent) / div;
2401 }
2402
2403 static int _clk_usdhc4_set_rate(struct clk *clk, unsigned long rate)
2404 {
2405         u32 reg, div;
2406         u32 parent_rate = clk_get_rate(clk->parent);
2407
2408         div = parent_rate / rate;
2409         if (div == 0)
2410                 div++;
2411         if (((parent_rate / div) != rate) || (div > 8))
2412                 return -EINVAL;
2413
2414         reg = __raw_readl(MXC_CCM_CSCDR1);
2415         reg &= ~MXC_CCM_CSCDR1_USDHC4_PODF_MASK;
2416         reg |= (div - 1) << MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET;
2417         __raw_writel(reg, MXC_CCM_CSCDR1);
2418
2419         return 0;
2420 }
2421
2422
2423 static struct clk usdhc4_clk = {
2424         __INIT_CLK_DEBUG(usdhc4_clk)
2425         .id = 3,
2426         .parent = &pll2_pfd_400M,
2427         .secondary = &usdhc_dep_clk,
2428         .enable_reg = MXC_CCM_CCGR6,
2429         .enable_shift = MXC_CCM_CCGRx_CG4_OFFSET,
2430         .enable = _clk_enable,
2431         .disable = _clk_disable,
2432         .set_parent = _clk_usdhc4_set_parent,
2433         .round_rate = _clk_usdhc_round_rate,
2434         .set_rate = _clk_usdhc4_set_rate,
2435         .get_rate = _clk_usdhc4_get_rate,
2436         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
2437 };
2438
2439 static unsigned long _clk_ssi_round_rate(struct clk *clk,
2440                                                 unsigned long rate)
2441 {
2442         u32 pre, post;
2443         u32 parent_rate = clk_get_rate(clk->parent);
2444         u32 div = parent_rate / rate;
2445
2446         if (parent_rate % rate)
2447                 div++;
2448
2449         __calc_pre_post_dividers(1 << 6, div, &pre, &post);
2450
2451         return parent_rate / (pre * post);
2452 }
2453
2454 static unsigned long _clk_ssi1_get_rate(struct clk *clk)
2455 {
2456         u32 reg, prediv, podf;
2457
2458         reg = __raw_readl(MXC_CCM_CS1CDR);
2459
2460         prediv = ((reg & MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK)
2461                 >> MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET) + 1;
2462         podf = ((reg & MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK)
2463                 >> MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET) + 1;
2464
2465         return clk_get_rate(clk->parent) / (prediv * podf);
2466 }
2467
2468 static int _clk_ssi1_set_rate(struct clk *clk, unsigned long rate)
2469 {
2470         u32 reg, div, pre, post;
2471         u32 parent_rate = clk_get_rate(clk->parent);
2472
2473         div = parent_rate / rate;
2474         if (div == 0)
2475                 div++;
2476         if (((parent_rate / div) != rate) || div > 512)
2477                 return -EINVAL;
2478
2479         __calc_pre_post_dividers(1 << 6, div, &pre, &post);
2480
2481         reg = __raw_readl(MXC_CCM_CS1CDR);
2482         reg &= ~(MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK |
2483                  MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK);
2484         reg |= (post - 1) << MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET;
2485         reg |= (pre - 1) << MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET;
2486
2487         __raw_writel(reg, MXC_CCM_CS1CDR);
2488
2489         return 0;
2490 }
2491
2492
2493 static int _clk_ssi1_set_parent(struct clk *clk, struct clk *parent)
2494 {
2495         u32 reg, mux;
2496
2497         reg = __raw_readl(MXC_CCM_CSCMR1)
2498                 & ~MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK;
2499
2500         mux = _get_mux6(parent, &pll3_pfd_508M, &pll3_pfd_454M,
2501                         &pll4_audio_main_clk, NULL, NULL, NULL);
2502         reg |= (mux << MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET);
2503
2504         __raw_writel(reg, MXC_CCM_CSCMR1);
2505
2506         return 0;
2507 }
2508
2509 static struct clk ssi1_clk = {
2510         __INIT_CLK_DEBUG(ssi1_clk)
2511         .parent = &pll3_pfd_508M,
2512         .enable_reg = MXC_CCM_CCGR5,
2513         .enable_shift = MXC_CCM_CCGRx_CG9_OFFSET,
2514         .enable = _clk_enable,
2515         .disable = _clk_disable,
2516         .set_parent = _clk_ssi1_set_parent,
2517         .set_rate = _clk_ssi1_set_rate,
2518         .round_rate = _clk_ssi_round_rate,
2519         .get_rate = _clk_ssi1_get_rate,
2520 #ifdef CONFIG_SND_MXC_SOC_IRAM
2521          .secondary = &ocram_clk,
2522 #else
2523          .secondary = &mmdc_ch0_axi_clk[0],
2524 #endif
2525 };
2526
2527 static unsigned long _clk_ssi2_get_rate(struct clk *clk)
2528 {
2529         u32 reg, prediv, podf;
2530
2531         reg = __raw_readl(MXC_CCM_CS2CDR);
2532
2533         prediv = ((reg & MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK)
2534                 >> MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET) + 1;
2535         podf = ((reg & MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK)
2536                 >> MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET) + 1;
2537
2538         return clk_get_rate(clk->parent) / (prediv * podf);
2539 }
2540
2541 static int _clk_ssi2_set_rate(struct clk *clk, unsigned long rate)
2542 {
2543         u32 reg, div, pre, post;
2544         u32 parent_rate = clk_get_rate(clk->parent);
2545
2546         div = parent_rate / rate;
2547         if (div == 0)
2548                 div++;
2549         if (((parent_rate / div) != rate) || div > 512)
2550                 return -EINVAL;
2551
2552         __calc_pre_post_dividers(1 << 6, div, &pre, &post);
2553
2554         reg = __raw_readl(MXC_CCM_CS2CDR);
2555         reg &= ~(MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK |
2556                  MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK);
2557         reg |= (post - 1) << MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET;
2558         reg |= (pre - 1) << MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET;
2559
2560         __raw_writel(reg, MXC_CCM_CS2CDR);
2561
2562         return 0;
2563 }
2564
2565
2566 static int _clk_ssi2_set_parent(struct clk *clk, struct clk *parent)
2567 {
2568         u32 reg, mux;
2569
2570         reg = __raw_readl(MXC_CCM_CSCMR1)
2571                 & ~MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK;
2572
2573         mux = _get_mux6(parent, &pll3_pfd_508M, &pll3_pfd_454M,
2574                         &pll4_audio_main_clk, NULL, NULL, NULL);
2575         reg |= (mux << MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET);
2576
2577         __raw_writel(reg, MXC_CCM_CSCMR1);
2578
2579         return 0;
2580 }
2581
2582 static struct clk ssi2_clk = {
2583         __INIT_CLK_DEBUG(ssi2_clk)
2584         .parent = &pll3_pfd_508M,
2585         .enable_reg = MXC_CCM_CCGR5,
2586         .enable_shift = MXC_CCM_CCGRx_CG10_OFFSET,
2587         .enable = _clk_enable,
2588         .disable = _clk_disable,
2589         .set_parent = _clk_ssi2_set_parent,
2590         .set_rate = _clk_ssi2_set_rate,
2591         .round_rate = _clk_ssi_round_rate,
2592         .get_rate = _clk_ssi2_get_rate,
2593 #ifdef CONFIG_SND_MXC_SOC_IRAM
2594          .secondary = &ocram_clk,
2595 #else
2596          .secondary = &mmdc_ch0_axi_clk[0],
2597 #endif
2598 };
2599
2600 static unsigned long _clk_ssi3_get_rate(struct clk *clk)
2601 {
2602         u32 reg, prediv, podf;
2603
2604         reg = __raw_readl(MXC_CCM_CS1CDR);
2605
2606         prediv = ((reg & MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK)
2607                 >> MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET) + 1;
2608         podf = ((reg & MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK)
2609                 >> MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET) + 1;
2610
2611         return clk_get_rate(clk->parent) / (prediv * podf);
2612 }
2613
2614 static int _clk_ssi3_set_rate(struct clk *clk, unsigned long rate)
2615 {
2616         u32 reg, div, pre, post;
2617         u32 parent_rate = clk_get_rate(clk->parent);
2618
2619         div = parent_rate / rate;
2620         if (div == 0)
2621                 div++;
2622         if (((parent_rate / div) != rate) || div > 512)
2623                 return -EINVAL;
2624
2625         __calc_pre_post_dividers(1 << 6, div, &pre, &post);
2626
2627         reg = __raw_readl(MXC_CCM_CS1CDR);
2628         reg &= ~(MXC_CCM_CS1CDR_SSI3_CLK_PODF_MASK|
2629                  MXC_CCM_CS1CDR_SSI3_CLK_PRED_MASK);
2630         reg |= (post - 1) << MXC_CCM_CS1CDR_SSI3_CLK_PODF_OFFSET;
2631         reg |= (pre - 1) << MXC_CCM_CS1CDR_SSI3_CLK_PRED_OFFSET;
2632
2633         __raw_writel(reg, MXC_CCM_CS1CDR);
2634
2635         return 0;
2636 }
2637
2638
2639 static int _clk_ssi3_set_parent(struct clk *clk, struct clk *parent)
2640 {
2641         u32 reg, mux;
2642
2643         reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_SSI3_CLK_SEL_MASK;
2644
2645         mux = _get_mux6(parent, &pll3_pfd_508M, &pll3_pfd_454M,
2646                                 &pll4_audio_main_clk, NULL, NULL, NULL);
2647         reg |= (mux << MXC_CCM_CSCMR1_SSI3_CLK_SEL_OFFSET);
2648
2649         __raw_writel(reg, MXC_CCM_CSCMR1);
2650
2651         return 0;
2652 }
2653
2654 static struct clk ssi3_clk = {
2655         __INIT_CLK_DEBUG(ssi3_clk)
2656         .parent = &pll3_pfd_508M,
2657         .enable_reg = MXC_CCM_CCGR5,
2658         .enable_shift = MXC_CCM_CCGRx_CG11_OFFSET,
2659         .enable = _clk_enable,
2660         .disable = _clk_disable,
2661         .set_parent = _clk_ssi3_set_parent,
2662         .set_rate = _clk_ssi3_set_rate,
2663         .round_rate = _clk_ssi_round_rate,
2664         .get_rate = _clk_ssi3_get_rate,
2665 #ifdef CONFIG_SND_MXC_SOC_IRAM
2666          .secondary = &ocram_clk,
2667 #else
2668          .secondary = &mmdc_ch0_axi_clk[0],
2669 #endif
2670 };
2671
2672 static unsigned long _clk_ldb_di_round_rate(struct clk *clk,
2673                                                 unsigned long rate)
2674 {
2675         u32 parent_rate = clk_get_rate(clk->parent);
2676
2677         if (rate * 7 <= parent_rate + parent_rate/20)
2678                 return parent_rate / 7;
2679         else
2680                 return 2 * parent_rate / 7;
2681 }
2682
2683 static unsigned long _clk_ldb_di0_get_rate(struct clk *clk)
2684 {
2685         u32 div;
2686
2687         div = __raw_readl(MXC_CCM_CSCMR2) &
2688                 MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
2689
2690         if (div)
2691                 return clk_get_rate(clk->parent) / 7;
2692
2693         return (2 * clk_get_rate(clk->parent)) / 7;
2694 }
2695
2696 static int _clk_ldb_di0_set_rate(struct clk *clk, unsigned long rate)
2697 {
2698         u32 reg, div = 0;
2699         u32 parent_rate = clk_get_rate(clk->parent);
2700
2701         if (rate * 7 <= parent_rate + parent_rate/20) {
2702                 div = 7;
2703                 rate = parent_rate / 7;
2704         } else
2705                 rate = 2 * parent_rate / 7;
2706
2707         reg = __raw_readl(MXC_CCM_CSCMR2);
2708         if (div == 7)
2709                 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
2710         else
2711                 reg &= ~MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
2712
2713         __raw_writel(reg, MXC_CCM_CSCMR2);
2714
2715         return 0;
2716 }
2717
2718 static int _clk_ldb_di0_set_parent(struct clk *clk, struct clk *parent)
2719 {
2720         u32 reg, mux;
2721
2722         reg = __raw_readl(MXC_CCM_CS2CDR)
2723                 & ~MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK;
2724
2725         mux = _get_mux6(parent, &pll5_video_main_clk,
2726                 &pll2_pfd_352M, &pll2_pfd_400M, &pll3_pfd_540M,
2727                 &pll3_usb_otg_main_clk, NULL);
2728         reg |= (mux << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET);
2729
2730         __raw_writel(reg, MXC_CCM_CS2CDR);
2731
2732         return 0;
2733 }
2734
2735 static struct clk ldb_di0_clk = {
2736          __INIT_CLK_DEBUG(ldb_di0_clk)
2737         .id = 0,
2738         .parent = &pll3_pfd_540M,
2739         .enable_reg = MXC_CCM_CCGR3,
2740         .enable_shift = MXC_CCM_CCGRx_CG6_OFFSET,
2741         .enable = _clk_enable,
2742         .disable = _clk_disable,
2743         .set_parent = _clk_ldb_di0_set_parent,
2744         .set_rate = _clk_ldb_di0_set_rate,
2745         .round_rate = _clk_ldb_di_round_rate,
2746         .get_rate = _clk_ldb_di0_get_rate,
2747         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
2748 };
2749
2750 static unsigned long _clk_ldb_di1_get_rate(struct clk *clk)
2751 {
2752         u32 div;
2753
2754         div = __raw_readl(MXC_CCM_CSCMR2) &
2755                 MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
2756
2757         if (div)
2758                 return clk_get_rate(clk->parent) / 7;
2759
2760         return (2 * clk_get_rate(clk->parent)) / 7;
2761 }
2762
2763 static int _clk_ldb_di1_set_rate(struct clk *clk, unsigned long rate)
2764 {
2765         u32 reg, div = 0;
2766         u32 parent_rate = clk_get_rate(clk->parent);
2767
2768         if (rate * 7 <= parent_rate + parent_rate/20) {
2769                 div = 7;
2770                 rate = parent_rate / 7;
2771         } else
2772                 rate = 2 * parent_rate / 7;
2773
2774         reg = __raw_readl(MXC_CCM_CSCMR2);
2775         if (div == 7)
2776                 reg |= MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
2777         else
2778                 reg &= ~MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
2779
2780         __raw_writel(reg, MXC_CCM_CSCMR2);
2781
2782         return 0;
2783 }
2784
2785 static int _clk_ldb_di1_set_parent(struct clk *clk, struct clk *parent)
2786 {
2787         u32 reg, mux;
2788
2789         reg = __raw_readl(MXC_CCM_CS2CDR)
2790                 & ~MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK;
2791
2792         mux = _get_mux6(parent, &pll5_video_main_clk,
2793                 &pll2_pfd_352M, &pll2_pfd_400M, &pll3_pfd_540M,
2794                 &pll3_usb_otg_main_clk, NULL);
2795         reg |= (mux << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
2796
2797         __raw_writel(reg, MXC_CCM_CS2CDR);
2798
2799         return 0;
2800 }
2801
2802 static struct clk ldb_di1_clk = {
2803          __INIT_CLK_DEBUG(ldb_di1_clk)
2804         .id = 0,
2805         .parent = &pll3_pfd_540M,
2806         .enable_reg = MXC_CCM_CCGR3,
2807         .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
2808         .enable = _clk_enable,
2809         .disable = _clk_disable,
2810         .set_parent = _clk_ldb_di1_set_parent,
2811         .set_rate = _clk_ldb_di1_set_rate,
2812         .round_rate = _clk_ldb_di_round_rate,
2813         .get_rate = _clk_ldb_di1_get_rate,
2814         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
2815 };
2816
2817
2818 static unsigned long _clk_ipu_di_round_rate(struct clk *clk,
2819                                                 unsigned long rate)
2820 {
2821         u32 div;
2822         u32 parent_rate = clk_get_rate(clk->parent);
2823
2824         if ((clk->parent == &ldb_di0_clk) ||
2825                 (clk->parent == &ldb_di1_clk))
2826                 return parent_rate;
2827
2828         div = parent_rate / rate;
2829         /* Round to closest divisor */
2830         if ((parent_rate % rate) > (rate / 2))
2831                 div++;
2832
2833         /* Make sure rate is not greater than the maximum value for the clock.
2834          * Also prevent a div of 0.
2835          */
2836         if (div == 0)
2837                 div++;
2838
2839         if (div > 8)
2840                 div = 8;
2841
2842         return parent_rate / div;
2843 }
2844
2845 static unsigned long _clk_ipu1_di0_get_rate(struct clk *clk)
2846 {
2847         u32 reg, div;
2848
2849         if ((clk->parent == &ldb_di0_clk) ||
2850                 (clk->parent == &ldb_di1_clk))
2851                 return clk_get_rate(clk->parent);
2852
2853         reg = __raw_readl(MXC_CCM_CHSCCDR);
2854
2855         div = ((reg & MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK) >>
2856                          MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET) + 1;
2857
2858         return clk_get_rate(clk->parent) / div;
2859 }
2860
2861 static int _clk_ipu1_di0_set_rate(struct clk *clk, unsigned long rate)
2862 {
2863         u32 reg, div;
2864         u32 parent_rate = clk_get_rate(clk->parent);
2865
2866         if ((clk->parent == &ldb_di0_clk) ||
2867                 (clk->parent == &ldb_di1_clk)) {
2868                 if (parent_rate == rate)
2869                         return 0;
2870                 else
2871                         return -EINVAL;
2872         }
2873
2874         div = parent_rate / rate;
2875         if (div == 0)
2876                 div++;
2877         if (((parent_rate / div) != rate) || (div > 8))
2878                 return -EINVAL;
2879
2880         reg = __raw_readl(MXC_CCM_CHSCCDR);
2881         reg &= ~MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK;
2882         reg |= (div - 1) << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET;
2883         __raw_writel(reg, MXC_CCM_CHSCCDR);
2884
2885         return 0;
2886 }
2887
2888
2889 static int _clk_ipu1_di0_set_parent(struct clk *clk, struct clk *parent)
2890 {
2891         u32 reg, mux;
2892
2893         if (parent == &ldb_di0_clk)
2894                 mux = 0x3;
2895         else if (parent == &ldb_di1_clk)
2896                 mux = 0x4;
2897         else {
2898                 reg = __raw_readl(MXC_CCM_CHSCCDR)
2899                         & ~MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK;
2900
2901                 mux = _get_mux6(parent, &mmdc_ch0_axi_clk[0],
2902                                 &pll3_usb_otg_main_clk, &pll5_video_main_clk,
2903                                 &pll2_pfd_352M, &pll2_pfd_400M, &pll3_pfd_540M);
2904                 reg |= (mux << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
2905
2906                 __raw_writel(reg, MXC_CCM_CHSCCDR);
2907
2908                 /* Derive clock from divided pre-muxed ipu1_di0 clock.*/
2909                 mux = 0;
2910         }
2911
2912         reg = __raw_readl(MXC_CCM_CHSCCDR)
2913                 & ~MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK;
2914         __raw_writel(reg | (mux << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET),
2915                 MXC_CCM_CHSCCDR);
2916
2917         return 0;
2918 }
2919
2920 static unsigned long _clk_ipu1_di1_get_rate(struct clk *clk)
2921 {
2922         u32 reg, div;
2923
2924         if ((clk->parent == &ldb_di0_clk) ||
2925                 (clk->parent == &ldb_di1_clk))
2926                 return clk_get_rate(clk->parent);
2927
2928         reg = __raw_readl(MXC_CCM_CHSCCDR);
2929
2930         div = ((reg & MXC_CCM_CHSCCDR_IPU1_DI1_PODF_MASK)
2931                         >> MXC_CCM_CHSCCDR_IPU1_DI1_PODF_OFFSET) + 1;
2932
2933         return clk_get_rate(clk->parent) / div;
2934 }
2935
2936 static int _clk_ipu1_di1_set_rate(struct clk *clk, unsigned long rate)
2937 {
2938         u32 reg, div;
2939         u32 parent_rate = clk_get_rate(clk->parent);
2940
2941         if ((clk->parent == &ldb_di0_clk) ||
2942                 (clk->parent == &ldb_di1_clk)) {
2943                 if (parent_rate == rate)
2944                         return 0;
2945                 else
2946                         return -EINVAL;
2947         }
2948
2949         div = parent_rate / rate;
2950         if (div == 0)
2951                 div++;
2952         if (((parent_rate / div) != rate) || (div > 8))
2953                 return -EINVAL;
2954
2955         reg = __raw_readl(MXC_CCM_CHSCCDR);
2956         reg &= ~MXC_CCM_CHSCCDR_IPU1_DI1_PODF_MASK;
2957         reg |= (div - 1) << MXC_CCM_CHSCCDR_IPU1_DI1_PODF_OFFSET;
2958         __raw_writel(reg, MXC_CCM_CHSCCDR);
2959
2960         return 0;
2961 }
2962
2963
2964 static int _clk_ipu1_di1_set_parent(struct clk *clk, struct clk *parent)
2965 {
2966         u32 reg, mux;
2967
2968         if (parent == &ldb_di0_clk)
2969                 mux = 0x3;
2970         else if (parent == &ldb_di1_clk)
2971                 mux = 0x4;
2972         else {
2973                 reg = __raw_readl(MXC_CCM_CHSCCDR)
2974                         & ~MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_MASK;
2975
2976                 mux = _get_mux6(parent, &mmdc_ch0_axi_clk[0],
2977                                 &pll3_usb_otg_main_clk, &pll5_video_main_clk,
2978                                 &pll2_pfd_352M, &pll2_pfd_400M, &pll3_pfd_540M);
2979                 reg |= (mux << MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_OFFSET);
2980
2981                 __raw_writel(reg, MXC_CCM_CHSCCDR);
2982
2983                 /* Derive clock from divided pre-muxed ipu1_di0 clock.*/
2984                 mux = 0;
2985         }
2986         reg = __raw_readl(MXC_CCM_CHSCCDR)
2987                 & ~MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_MASK;
2988         __raw_writel(reg | (mux << MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET),
2989                 MXC_CCM_CHSCCDR);
2990
2991         return 0;
2992 }
2993
2994 static struct clk ipu1_di_clk[] = {
2995         {
2996          __INIT_CLK_DEBUG(ipu1_di_clk_0)
2997         .id = 0,
2998         .parent = &pll5_video_main_clk,
2999         .enable_reg = MXC_CCM_CCGR3,
3000         .enable_shift = MXC_CCM_CCGRx_CG1_OFFSET,
3001         .enable = _clk_enable,
3002         .disable = _clk_disable,
3003         .set_parent = _clk_ipu1_di0_set_parent,
3004         .set_rate = _clk_ipu1_di0_set_rate,
3005         .round_rate = _clk_ipu_di_round_rate,
3006         .get_rate = _clk_ipu1_di0_get_rate,
3007         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
3008         },
3009         {
3010          __INIT_CLK_DEBUG(ipu1_di_clk_1)
3011         .id = 1,
3012         .parent = &pll5_video_main_clk,
3013         .enable_reg = MXC_CCM_CCGR3,
3014         .enable_shift = MXC_CCM_CCGRx_CG2_OFFSET,
3015         .enable = _clk_enable,
3016         .disable = _clk_disable,
3017         .set_parent = _clk_ipu1_di1_set_parent,
3018         .set_rate = _clk_ipu1_di1_set_rate,
3019         .round_rate = _clk_ipu_di_round_rate,
3020         .get_rate = _clk_ipu1_di1_get_rate,
3021         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
3022         },
3023 };
3024
3025 static unsigned long _clk_ipu2_di0_get_rate(struct clk *clk)
3026 {
3027         u32 reg, div;
3028
3029         if ((clk->parent == &ldb_di0_clk) ||
3030                 (clk->parent == &ldb_di1_clk))
3031                 return clk_get_rate(clk->parent);
3032
3033         reg = __raw_readl(MXC_CCM_CSCDR2);
3034
3035         div = ((reg & MXC_CCM_CSCDR2_IPU2_DI0_PODF_MASK) >>
3036                         MXC_CCM_CSCDR2_IPU2_DI0_PODF_OFFSET) + 1;
3037
3038         return clk_get_rate(clk->parent) / div;
3039 }
3040
3041 static int _clk_ipu2_di0_set_rate(struct clk *clk, unsigned long rate)
3042 {
3043         u32 reg, div;
3044         u32 parent_rate = clk_get_rate(clk->parent);
3045
3046         if ((clk->parent == &ldb_di0_clk) ||
3047                 (clk->parent == &ldb_di1_clk)) {
3048                 if (parent_rate == rate)
3049                         return 0;
3050                 else
3051                         return -EINVAL;
3052         }
3053
3054         div = parent_rate / rate;
3055         if (div == 0)
3056                 div++;
3057         if (((parent_rate / div) != rate) || (div > 8))
3058                 return -EINVAL;
3059
3060         reg = __raw_readl(MXC_CCM_CSCDR2);
3061         reg &= ~MXC_CCM_CSCDR2_IPU2_DI0_PODF_MASK;
3062         reg |= (div - 1) << MXC_CCM_CSCDR2_IPU2_DI0_PODF_OFFSET;
3063         __raw_writel(reg, MXC_CCM_CSCDR2);
3064
3065         return 0;
3066 }
3067
3068 static int _clk_ipu2_di0_set_parent(struct clk *clk, struct clk *parent)
3069 {
3070         u32 reg, mux;
3071
3072         if (parent == &ldb_di0_clk)
3073                 mux = 0x3;
3074         else if (parent == &ldb_di1_clk)
3075                 mux = 0x4;
3076         else {
3077                 reg = __raw_readl(MXC_CCM_CSCDR2)
3078                         & ~MXC_CCM_CSCDR2_IPU2_DI0_PRE_CLK_SEL_MASK;
3079
3080                 mux = _get_mux6(parent, &mmdc_ch0_axi_clk[0],
3081                                 &pll3_usb_otg_main_clk, &pll5_video_main_clk,
3082                                 &pll2_pfd_352M, &pll2_pfd_400M, &pll3_pfd_540M);
3083                 reg |= (mux << MXC_CCM_CSCDR2_IPU2_DI0_PRE_CLK_SEL_OFFSET);
3084
3085                 __raw_writel(reg, MXC_CCM_CSCDR2);
3086
3087                 /* Derive clock from divided pre-muxed ipu2_di0 clock.*/
3088                 mux = 0;
3089         }
3090         reg = __raw_readl(MXC_CCM_CSCDR2)
3091                 & ~MXC_CCM_CSCDR2_IPU2_DI0_CLK_SEL_MASK;
3092         __raw_writel(reg | (mux << MXC_CCM_CSCDR2_IPU2_DI0_CLK_SEL_OFFSET),
3093                 MXC_CCM_CSCDR2);
3094
3095         return 0;
3096 }
3097
3098 static unsigned long _clk_ipu2_di1_get_rate(struct clk *clk)
3099 {
3100         u32 reg, div;
3101
3102         if ((clk->parent == &ldb_di0_clk) ||
3103                 (clk->parent == &ldb_di1_clk))
3104                 return clk_get_rate(clk->parent);
3105
3106         reg = __raw_readl(MXC_CCM_CSCDR2);
3107
3108         div = ((reg & MXC_CCM_CSCDR2_IPU2_DI1_PODF_MASK)
3109                 >> MXC_CCM_CSCDR2_IPU2_DI1_PODF_OFFSET) + 1;
3110
3111         return clk_get_rate(clk->parent) / div;
3112 }
3113
3114 static int _clk_ipu2_di1_set_rate(struct clk *clk, unsigned long rate)
3115 {
3116         u32 reg, div;
3117         u32 parent_rate = clk_get_rate(clk->parent);
3118
3119         if ((clk->parent == &ldb_di0_clk) ||
3120                 (clk->parent == &ldb_di1_clk)) {
3121                 if (parent_rate == rate)
3122                         return 0;
3123                 else
3124                         return -EINVAL;
3125         }
3126
3127         div = parent_rate / rate;
3128         if (div == 0)
3129                 div++;
3130         if (((parent_rate / div) != rate) || (div > 8))
3131                 return -EINVAL;
3132
3133         reg = __raw_readl(MXC_CCM_CSCDR2);
3134         reg &= ~MXC_CCM_CSCDR2_IPU2_DI1_PODF_MASK;
3135         reg |= (div - 1) << MXC_CCM_CSCDR2_IPU2_DI1_PODF_OFFSET;
3136         __raw_writel(reg, MXC_CCM_CSCDR2);
3137
3138         return 0;
3139 }
3140
3141 static int _clk_ipu2_di1_set_parent(struct clk *clk, struct clk *parent)
3142 {
3143         u32 reg, mux;
3144
3145         if (parent == &ldb_di0_clk)
3146                 mux = 0x3;
3147         else if (parent == &ldb_di1_clk)
3148                 mux = 0x4;
3149         else {
3150                 reg = __raw_readl(MXC_CCM_CSCDR2)
3151                         & ~MXC_CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_MASK;
3152
3153                 mux = _get_mux6(parent, &mmdc_ch0_axi_clk[0],
3154                                 &pll3_usb_otg_main_clk, &pll5_video_main_clk,
3155                                 &pll2_pfd_352M, &pll2_pfd_400M, &pll3_pfd_540M);
3156                 reg |= (mux << MXC_CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_OFFSET);
3157
3158                 __raw_writel(reg, MXC_CCM_CSCDR2);
3159
3160                 /* Derive clock from divided pre-muxed ipu1_di0 clock.*/
3161                 mux = 0;
3162         }
3163         reg = __raw_readl(MXC_CCM_CSCDR2)
3164                 & ~MXC_CCM_CSCDR2_IPU2_DI1_CLK_SEL_MASK;
3165         __raw_writel(reg | (mux << MXC_CCM_CSCDR2_IPU2_DI1_CLK_SEL_OFFSET),
3166                 MXC_CCM_CSCDR2);
3167
3168         return 0;
3169 }
3170
3171 static struct clk ipu2_di_clk[] = {
3172         {
3173          __INIT_CLK_DEBUG(ipu2_di_clk_0)
3174         .id = 0,
3175         .parent = &pll5_video_main_clk,
3176         .enable_reg = MXC_CCM_CCGR3,
3177         .enable_shift = MXC_CCM_CCGRx_CG4_OFFSET,
3178         .enable = _clk_enable,
3179         .disable = _clk_disable,
3180         .set_parent = _clk_ipu2_di0_set_parent,
3181         .set_rate = _clk_ipu2_di0_set_rate,
3182         .round_rate = _clk_ipu_di_round_rate,
3183         .get_rate = _clk_ipu2_di0_get_rate,
3184         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
3185         },
3186         {
3187          __INIT_CLK_DEBUG(ipu2_di_clk_1)
3188         .id = 1,
3189         .parent = &pll5_video_main_clk,
3190         .enable_reg = MXC_CCM_CCGR3,
3191         .enable_shift = MXC_CCM_CCGRx_CG5_OFFSET,
3192         .enable = _clk_enable,
3193         .disable = _clk_disable,
3194         .set_parent = _clk_ipu2_di1_set_parent,
3195         .set_rate = _clk_ipu2_di1_set_rate,
3196         .round_rate = _clk_ipu_di_round_rate,
3197         .get_rate = _clk_ipu2_di1_get_rate,
3198         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
3199         },
3200 };
3201
3202 static unsigned long _clk_can_root_round_rate(struct clk *clk,
3203                                                 unsigned long rate)
3204 {
3205         u32 div;
3206         u32 parent_rate = clk_get_rate(clk->parent);
3207
3208         div = parent_rate / rate;
3209
3210         /* Make sure rate is not greater than the maximum value for the clock.
3211          * Also prevent a div of 0.
3212          */
3213         if (div == 0)
3214                 div++;
3215
3216         if (div > 64)
3217                 div = 64;
3218
3219         return parent_rate / div;
3220 }
3221
3222 static int _clk_can_root_set_rate(struct clk *clk, unsigned long rate)
3223 {
3224         u32 reg, div;
3225         u32 parent_rate = clk_get_rate(clk->parent);
3226
3227         div = parent_rate / rate;
3228         if (div == 0)
3229                 div++;
3230         if (((parent_rate / div) != rate) || (div > 64))
3231                 return -EINVAL;
3232
3233         reg = __raw_readl(MXC_CCM_CSCMR2) & MXC_CCM_CSCMR2_CAN_CLK_PODF_MASK;
3234         reg |= ((div - 1) << MXC_CCM_CSCMR2_CAN_CLK_PODF_OFFSET);
3235
3236         __raw_writel(reg, MXC_CCM_CSCMR2);
3237
3238         return 0;
3239 }
3240
3241 static unsigned long _clk_can_root_get_rate(struct clk *clk)
3242 {
3243         u32 reg, div;
3244         unsigned long val;
3245
3246         reg = __raw_readl(MXC_CCM_CSCMR2) & MXC_CCM_CSCMR2_CAN_CLK_PODF_MASK;
3247         div = (reg >> MXC_CCM_CSCMR2_CAN_CLK_PODF_OFFSET) + 1;
3248         val = clk_get_rate(clk->parent) / div;
3249
3250         return val;
3251 }
3252
3253 static struct clk can_clk_root = {
3254          __INIT_CLK_DEBUG(can_clk_root)
3255         .parent = &pll3_60M,
3256         .set_rate = _clk_can_root_set_rate,
3257         .get_rate = _clk_can_root_get_rate,
3258         .round_rate = _clk_can_root_round_rate,
3259 };
3260
3261 static struct clk can2_clk[] = {
3262         {
3263          __INIT_CLK_DEBUG(can2_module_clk)
3264         .id = 0,
3265         .parent = &can_clk_root,
3266         .enable_reg = MXC_CCM_CCGR0,
3267         .enable_shift = MXC_CCM_CCGRx_CG9_OFFSET,
3268         .enable = _clk_enable,
3269         .disable = _clk_disable,
3270         .secondary = &can2_clk[1],
3271         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
3272         },
3273         {
3274          __INIT_CLK_DEBUG(can2_serial_clk)
3275         .id = 1,
3276         .parent = &can_clk_root,
3277         .enable_reg = MXC_CCM_CCGR0,
3278         .enable_shift = MXC_CCM_CCGRx_CG10_OFFSET,
3279         .enable = _clk_enable,
3280         .disable = _clk_disable,
3281         },
3282 };
3283
3284
3285 static struct clk can1_clk[] = {
3286         {
3287          __INIT_CLK_DEBUG(can1_module_clk)
3288         .id = 0,
3289         .parent = &can_clk_root,
3290         .enable_reg = MXC_CCM_CCGR0,
3291         .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
3292         .enable = _clk_enable,
3293         .disable = _clk_disable,
3294         .secondary = &can1_clk[1],
3295         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
3296         },
3297         {
3298          __INIT_CLK_DEBUG(can1_serial_clk)
3299         .id = 1,
3300         .parent = &can_clk_root,
3301         .enable_reg = MXC_CCM_CCGR0,
3302         .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET,
3303         .enable = _clk_enable,
3304         .disable = _clk_disable,
3305         },
3306 };
3307
3308 static unsigned long _clk_spdif_round_rate(struct clk *clk,
3309                                                 unsigned long rate)
3310 {
3311         u32 pre, post;
3312         u32 parent_rate = clk_get_rate(clk->parent);
3313         u32 div = parent_rate / rate;
3314
3315         if (parent_rate % rate)
3316                 div++;
3317
3318         __calc_pre_post_dividers(1 << 3, div, &pre, &post);
3319
3320         return parent_rate / (pre * post);
3321 }
3322
3323 static int _clk_spdif0_set_parent(struct clk *clk, struct clk *parent)
3324 {
3325         u32 reg, mux;
3326
3327         reg = __raw_readl(MXC_CCM_CDCDR)
3328                 & ~MXC_CCM_CDCDR_SPDIF0_CLK_SEL_MASK;
3329
3330         mux = _get_mux6(parent, &pll4_audio_main_clk,
3331                 &pll3_pfd_508M, &pll3_pfd_454M,
3332                 &pll3_sw_clk, NULL, NULL);
3333         reg |= mux << MXC_CCM_CDCDR_SPDIF0_CLK_SEL_OFFSET;
3334
3335         __raw_writel(reg, MXC_CCM_CDCDR);
3336
3337         return 0;
3338 }
3339
3340 static unsigned long _clk_spdif0_get_rate(struct clk *clk)
3341 {
3342         u32 reg, pred, podf;
3343
3344         reg = __raw_readl(MXC_CCM_CDCDR);
3345
3346         pred = ((reg & MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK)
3347                 >> MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET) + 1;
3348         podf = ((reg & MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK)
3349                 >> MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET) + 1;
3350
3351         return clk_get_rate(clk->parent) / (pred * podf);
3352 }
3353
3354 static int _clk_spdif0_set_rate(struct clk *clk, unsigned long rate)
3355 {
3356         u32 reg, div, pre, post;
3357         u32 parent_rate = clk_get_rate(clk->parent);
3358
3359         div = parent_rate / rate;
3360         if (div == 0)
3361                 div++;
3362         if (((parent_rate / div) != rate) || div > 64)
3363                 return -EINVAL;
3364
3365         __calc_pre_post_dividers(1 << 3, div, &pre, &post);
3366
3367         reg = __raw_readl(MXC_CCM_CDCDR);
3368         reg &= ~(MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK|
3369                  MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK);
3370         reg |= (post - 1) << MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET;
3371         reg |= (pre - 1) << MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET;
3372
3373         __raw_writel(reg, MXC_CCM_CDCDR);
3374
3375         return 0;
3376 }
3377
3378 static struct clk spdif0_clk[] = {
3379         {
3380         __INIT_CLK_DEBUG(spdif0_clk_0)
3381         .id = 0,
3382         .parent = &pll3_sw_clk,
3383          .enable = _clk_enable,
3384          .enable_reg = MXC_CCM_CCGR5,
3385          .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
3386          .disable = _clk_disable,
3387          .secondary = &spdif0_clk[1],
3388          .set_rate = _clk_spdif0_set_rate,
3389          .get_rate = _clk_spdif0_get_rate,
3390          .set_parent = _clk_spdif0_set_parent,
3391          .round_rate = _clk_spdif_round_rate,
3392         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
3393         },
3394         {
3395         __INIT_CLK_DEBUG(spdif0_clk_1)
3396          .id = 1,
3397          .parent = &ipg_clk,
3398          .secondary = &spba_clk,
3399          },
3400 };
3401
3402 static unsigned long _clk_esai_round_rate(struct clk *clk,
3403                                                 unsigned long rate)
3404 {
3405         u32 pre, post;
3406         u32 parent_rate = clk_get_rate(clk->parent);
3407         u32 div = parent_rate / rate;
3408
3409         if (parent_rate % rate)
3410                 div++;
3411
3412         __calc_pre_post_dividers(1 << 3, div, &pre, &post);
3413
3414         return parent_rate / (pre * post);
3415 }
3416
3417 static int _clk_esai_set_parent(struct clk *clk, struct clk *parent)
3418 {
3419         u32 reg, mux;
3420
3421         reg = __raw_readl(MXC_CCM_CSCMR2) & ~MXC_CCM_CSCMR2_ESAI_CLK_SEL_MASK;
3422
3423         mux = _get_mux6(parent, &pll4_audio_main_clk, &pll3_pfd_508M,
3424                         &pll3_pfd_454M, &pll3_sw_clk, NULL, NULL);
3425         reg |= mux << MXC_CCM_CSCMR2_ESAI_CLK_SEL_OFFSET;
3426
3427         __raw_writel(reg, MXC_CCM_CSCMR2);
3428
3429         return 0;
3430 }
3431
3432 static unsigned long _clk_esai_get_rate(struct clk *clk)
3433 {
3434         u32 reg, pred, podf;
3435
3436         reg = __raw_readl(MXC_CCM_CS1CDR);
3437
3438         pred = ((reg & MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK)
3439                 >> MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET) + 1;
3440         podf = ((reg & MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK)
3441                 >> MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET) + 1;
3442
3443         return clk_get_rate(clk->parent) / (pred * podf);
3444 }
3445
3446 static int _clk_esai_set_rate(struct clk *clk, unsigned long rate)
3447 {
3448         u32 reg, div, pre, post;
3449         u32 parent_rate = clk_get_rate(clk->parent);
3450
3451         div = parent_rate / rate;
3452         if (div == 0)
3453                 div++;
3454         if (((parent_rate / div) != rate) || div > 64)
3455                 return -EINVAL;
3456
3457         __calc_pre_post_dividers(1 << 3, div, &pre, &post);
3458
3459         reg = __raw_readl(MXC_CCM_CS1CDR);
3460         reg &= ~(MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK|
3461                  MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK);
3462         reg |= (post - 1) << MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET;
3463         reg |= (pre - 1) << MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET;
3464
3465         __raw_writel(reg, MXC_CCM_CS1CDR);
3466
3467         return 0;
3468 }
3469
3470 static struct clk esai_clk = {
3471         __INIT_CLK_DEBUG(esai_clk)
3472          .id = 0,
3473          .parent = &pll3_sw_clk,
3474          .secondary = &spba_clk,
3475          .enable_reg = MXC_CCM_CCGR1,
3476          .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET,
3477          .enable = _clk_enable,
3478          .disable = _clk_disable,
3479          .set_rate = _clk_esai_set_rate,
3480          .get_rate = _clk_esai_get_rate,
3481          .set_parent = _clk_esai_set_parent,
3482          .round_rate = _clk_esai_round_rate,
3483 };
3484
3485 static int _clk_enet_enable(struct clk *clk)
3486 {
3487         unsigned int reg;
3488
3489         /* Enable ENET ref clock */
3490         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
3491         reg &= ~ANADIG_PLL_BYPASS;
3492         reg |= ANADIG_PLL_ENABLE;
3493         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
3494
3495         _clk_enable(clk);
3496         return 0;
3497 }
3498
3499 static void _clk_enet_disable(struct clk *clk)
3500 {
3501         unsigned int reg;
3502
3503         _clk_disable(clk);
3504
3505         /* Enable ENET ref clock */
3506         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
3507         reg |= ANADIG_PLL_BYPASS;
3508         reg &= ~ANADIG_PLL_ENABLE;
3509         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
3510 }
3511
3512 static int _clk_enet_set_rate(struct clk *clk, unsigned long rate)
3513 {
3514         unsigned int reg, div = 1;
3515
3516         switch (rate) {
3517         case 25000000:
3518                 div = 0;
3519                 break;
3520         case 50000000:
3521                 div = 1;
3522                 break;
3523         case 100000000:
3524                 div = 2;
3525                 break;
3526         case 125000000:
3527                 div = 3;
3528                 break;
3529         default:
3530                 return -EINVAL;
3531         }
3532         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
3533         reg &= ~ANADIG_PLL_ENET_DIV_SELECT_MASK;
3534         reg |= (div << ANADIG_PLL_ENET_DIV_SELECT_OFFSET);
3535         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
3536
3537         return 0;
3538 }
3539
3540 static unsigned long _clk_enet_get_rate(struct clk *clk)
3541 {
3542         unsigned int div;
3543
3544         div = (__raw_readl(PLL8_ENET_BASE_ADDR))
3545                 & ANADIG_PLL_ENET_DIV_SELECT_MASK;
3546
3547         switch (div) {
3548         case 0:
3549                 div = 20;
3550                 break;
3551         case 1:
3552                 div = 10;
3553                 break;
3554         case 3:
3555                 div = 5;
3556                 break;
3557         case 4:
3558                 div = 4;
3559                 break;
3560         }
3561
3562         return 500000000 / div;
3563 }
3564
3565 static struct clk enet_clk[] = {
3566         {
3567         __INIT_CLK_DEBUG(enet_clk)
3568          .id = 0,
3569          .parent = &pll8_enet_main_clk,
3570          .enable_reg = MXC_CCM_CCGR1,
3571          .enable_shift = MXC_CCM_CCGRx_CG5_OFFSET,
3572          .enable = _clk_enet_enable,
3573          .disable = _clk_enet_disable,
3574          .set_rate = _clk_enet_set_rate,
3575          .get_rate = _clk_enet_get_rate,
3576         .secondary = &enet_clk[1],
3577         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
3578         },
3579         {
3580         .parent = &mmdc_ch0_axi_clk[0],
3581         .secondary = &mx6per1_clk,
3582         },
3583 };
3584
3585 static struct clk ecspi_clk[] = {
3586         {
3587         __INIT_CLK_DEBUG(ecspi0_clk)
3588         .id = 0,
3589         .parent = &pll3_60M,
3590         .secondary = &spba_clk,
3591         .enable_reg = MXC_CCM_CCGR1,
3592         .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET,
3593         .enable = _clk_enable,
3594         .disable = _clk_disable,
3595         },
3596         {
3597         __INIT_CLK_DEBUG(ecspi1_clk)
3598         .id = 1,
3599         .parent = &pll3_60M,
3600         .secondary = &spba_clk,
3601         .enable_reg = MXC_CCM_CCGR1,
3602         .enable_shift = MXC_CCM_CCGRx_CG1_OFFSET,
3603         .enable = _clk_enable,
3604         .disable = _clk_disable,
3605         },
3606         {
3607         __INIT_CLK_DEBUG(ecspi2_clk)
3608         .id = 2,
3609         .parent = &pll3_60M,
3610         .secondary = &spba_clk,
3611         .enable_reg = MXC_CCM_CCGR1,
3612         .enable_shift = MXC_CCM_CCGRx_CG2_OFFSET,
3613         .enable = _clk_enable,
3614         .disable = _clk_disable,
3615         },
3616         {
3617         __INIT_CLK_DEBUG(ecspi3_clk)
3618         .id = 3,
3619         .parent = &pll3_60M,
3620         .secondary = &spba_clk,
3621         .enable_reg = MXC_CCM_CCGR1,
3622         .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET,
3623         .enable = _clk_enable,
3624         .disable = _clk_disable,
3625         },
3626         {
3627         __INIT_CLK_DEBUG(ecspi4_clk)
3628         .id = 4,
3629         .parent = &pll3_60M,
3630         .secondary = &spba_clk,
3631         .enable_reg = MXC_CCM_CCGR1,
3632         .enable_shift = MXC_CCM_CCGRx_CG4_OFFSET,
3633         .enable = _clk_enable,
3634         .disable = _clk_disable,
3635         },
3636 };
3637
3638 static unsigned long _clk_emi_slow_round_rate(struct clk *clk,
3639                                                 unsigned long rate)
3640 {
3641         u32 div;
3642         u32 parent_rate = clk_get_rate(clk->parent);
3643
3644         div = parent_rate / rate;
3645
3646         /* Make sure rate is not greater than the maximum value for the clock.
3647          * Also prevent a div of 0.
3648          */
3649         if (div == 0)
3650                 div++;
3651
3652         if (div > 8)
3653                 div = 8;
3654
3655         return parent_rate / div;
3656 }
3657
3658 static int _clk_emi_slow_set_parent(struct clk *clk, struct clk *parent)
3659 {
3660         int mux;
3661         u32 reg = __raw_readl(MXC_CCM_CSCMR1)
3662                 & ~MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK;
3663
3664         mux = _get_mux6(parent, &axi_clk, &pll3_usb_otg_main_clk,
3665                                 &pll2_pfd_400M, &pll2_pfd_352M, NULL, NULL);
3666         reg |= (mux << MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET);
3667         __raw_writel(reg, MXC_CCM_CSCMR1);
3668
3669         return 0;
3670 }
3671
3672 static unsigned long _clk_emi_slow_get_rate(struct clk *clk)
3673 {
3674         u32 reg, div;
3675
3676         reg = __raw_readl(MXC_CCM_CSCMR1);
3677         div = ((reg & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK) >>
3678                         MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET) + 1;
3679
3680         return clk_get_rate(clk->parent) / div;
3681 }
3682
3683 static int _clk_emi_slow_set_rate(struct clk *clk, unsigned long rate)
3684 {
3685         u32 reg, div;
3686         u32 parent_rate = clk_get_rate(clk->parent);
3687
3688         div = parent_rate / rate;
3689         if (div == 0)
3690                 div++;
3691         if (((parent_rate / div) != rate) || (div > 8))
3692                 return -EINVAL;
3693
3694         reg = __raw_readl(MXC_CCM_CSCMR1);
3695         reg &= ~MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK;
3696         reg |= (div - 1) << MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET;
3697         __raw_writel(reg, MXC_CCM_CSCMR1);
3698
3699         return 0;
3700 }
3701
3702 static struct clk emi_slow_clk = {
3703         __INIT_CLK_DEBUG(emi_slow_clk)
3704          .id = 0,
3705          .parent = &axi_clk,
3706          .enable_reg = MXC_CCM_CCGR6,
3707          .enable_shift = MXC_CCM_CCGRx_CG5_OFFSET,
3708          .enable = _clk_enable,
3709          .disable = _clk_disable,
3710          .set_rate = _clk_emi_slow_set_rate,
3711          .get_rate = _clk_emi_slow_get_rate,
3712          .round_rate = _clk_emi_slow_round_rate,
3713          .set_parent = _clk_emi_slow_set_parent,
3714 };
3715
3716 static unsigned long _clk_emi_round_rate(struct clk *clk,
3717                                                 unsigned long rate)
3718 {
3719         u32 div;
3720         u32 parent_rate = clk_get_rate(clk->parent);
3721
3722         div = parent_rate / rate;
3723
3724         /* Make sure rate is not greater than the maximum value for the clock.
3725          * Also prevent a div of 0.
3726          */
3727         if (div == 0)
3728                 div++;
3729
3730         if (div > 8)
3731                 div = 8;
3732
3733         return parent_rate / div;
3734 }
3735
3736 static int _clk_emi_set_parent(struct clk *clk, struct clk *parent)
3737 {
3738         int mux;
3739         u32 reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_ACLK_EMI_MASK;
3740
3741         mux = _get_mux6(parent, &axi_clk, &pll3_usb_otg_main_clk,
3742                         &pll2_pfd_400M, &pll2_pfd_352M, NULL, NULL);
3743         reg |= (mux << MXC_CCM_CSCMR1_ACLK_EMI_OFFSET);
3744         __raw_writel(reg, MXC_CCM_CSCMR1);
3745
3746         return 0;
3747 }
3748
3749 static unsigned long _clk_emi_get_rate(struct clk *clk)
3750 {
3751         u32 reg, div;
3752
3753         reg = __raw_readl(MXC_CCM_CSCMR1);
3754         div = ((reg & MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK) >>
3755                         MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET) + 1;
3756
3757         return clk_get_rate(clk->parent) / div;
3758 }
3759
3760 static int _clk_emi_set_rate(struct clk *clk, unsigned long rate)
3761 {
3762         u32 reg, div;
3763         u32 parent_rate = clk_get_rate(clk->parent);
3764
3765         div = parent_rate / rate;
3766         if (div == 0)
3767                 div++;
3768         if (((parent_rate / div) != rate) || (div > 8))
3769                 return -EINVAL;
3770
3771         reg = __raw_readl(MXC_CCM_CSCMR1);
3772         reg &= ~MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK;
3773         reg |= (div - 1) << MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET;
3774         __raw_writel(reg, MXC_CCM_CSCMR1);
3775
3776         return 0;
3777 }
3778
3779 static struct clk emi_clk = {
3780         __INIT_CLK_DEBUG(emi_clk)
3781          .id = 0,
3782          .parent = &axi_clk,
3783          .set_rate = _clk_emi_set_rate,
3784          .get_rate = _clk_emi_get_rate,
3785          .round_rate = _clk_emi_round_rate,
3786          .set_parent = _clk_emi_set_parent,
3787 };
3788
3789 static unsigned long _clk_enfc_round_rate(struct clk *clk,
3790                                                 unsigned long rate)
3791 {
3792         u32 pre, post;
3793         u32 parent_rate = clk_get_rate(clk->parent);
3794         u32 div = parent_rate / rate;
3795
3796         if (parent_rate % rate)
3797                 div++;
3798
3799         __calc_pre_post_dividers(1 << 6, div, &pre, &post);
3800
3801         return parent_rate / (pre * post);
3802 }
3803
3804 static int _clk_enfc_set_parent(struct clk *clk, struct clk *parent)
3805 {
3806         u32 reg, mux;
3807
3808         reg = __raw_readl(MXC_CCM_CS2CDR)
3809                 & ~MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK;
3810
3811         mux = _get_mux6(parent, &pll2_pfd_352M,
3812                 &pll2_528_bus_main_clk, &pll3_usb_otg_main_clk,
3813                 &pll2_pfd_400M, NULL, NULL);
3814         reg |= mux << MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET;
3815
3816         __raw_writel(reg, MXC_CCM_CS2CDR);
3817
3818         return 0;
3819 }
3820
3821 static unsigned long _clk_enfc_get_rate(struct clk *clk)
3822 {
3823         u32 reg, pred, podf;
3824
3825         reg = __raw_readl(MXC_CCM_CS2CDR);
3826
3827         pred = ((reg & MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK)
3828                 >> MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET) + 1;
3829         podf = ((reg & MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK)
3830                 >> MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET) + 1;
3831
3832         return clk_get_rate(clk->parent) / (pred * podf);
3833 }
3834
3835 static int _clk_enfc_set_rate(struct clk *clk, unsigned long rate)
3836 {
3837         u32 reg, div, pre, post;
3838         u32 parent_rate = clk_get_rate(clk->parent);
3839
3840         div = parent_rate / rate;
3841         if (div == 0)
3842                 div++;
3843         if (((parent_rate / div) != rate) || div > 512)
3844                 return -EINVAL;
3845
3846         __calc_pre_post_dividers(1 << 6, div, &pre, &post);
3847
3848         reg = __raw_readl(MXC_CCM_CS2CDR);
3849         reg &= ~(MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK|
3850                  MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK);
3851         reg |= (post - 1) << MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET;
3852         reg |= (pre - 1) << MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET;
3853
3854         __raw_writel(reg, MXC_CCM_CS2CDR);
3855
3856         return 0;
3857 }
3858
3859 static struct clk enfc_clk = {
3860         __INIT_CLK_DEBUG(enfc_clk)
3861          .id = 0,
3862          .parent = &pll2_pfd_352M,
3863          .enable_reg = MXC_CCM_CCGR2,
3864          .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
3865          .enable = _clk_enable,
3866          .disable = _clk_disable,
3867          .set_rate = _clk_enfc_set_rate,
3868          .get_rate = _clk_enfc_get_rate,
3869          .round_rate = _clk_enfc_round_rate,
3870          .set_parent = _clk_enfc_set_parent,
3871 };
3872
3873 static unsigned long _clk_uart_round_rate(struct clk *clk,
3874                                                 unsigned long rate)
3875 {
3876         u32 div;
3877         u32 parent_rate = clk_get_rate(clk->parent);
3878
3879         div = parent_rate / rate;
3880
3881         /* Make sure rate is not greater than the maximum value for the clock.
3882          * Also prevent a div of 0.
3883          */
3884         if (div == 0)
3885                 div++;
3886
3887         if (div > 64)
3888                 div = 64;
3889
3890         return parent_rate / div;
3891 }
3892
3893 static int _clk_uart_set_rate(struct clk *clk, unsigned long rate)
3894 {
3895         u32 reg, div;
3896         u32 parent_rate = clk_get_rate(clk->parent);
3897
3898         div = parent_rate / rate;
3899         if (div == 0)
3900                 div++;
3901         if (((parent_rate / div) != rate) || (div > 64))
3902                 return -EINVAL;
3903
3904         reg = __raw_readl(MXC_CCM_CSCDR1) & MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
3905         reg |= ((div - 1) << MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET);
3906
3907         __raw_writel(reg, MXC_CCM_CSCDR1);
3908
3909         return 0;
3910 }
3911
3912 static unsigned long _clk_uart_get_rate(struct clk *clk)
3913 {
3914         u32 reg, div;
3915         unsigned long val;
3916
3917         reg = __raw_readl(MXC_CCM_CSCDR1) & MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
3918         div = (reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET) + 1;
3919         val = clk_get_rate(clk->parent) / div;
3920
3921         return val;
3922 }
3923
3924 static struct clk uart_clk[] = {
3925         {
3926         __INIT_CLK_DEBUG(uart_clk)
3927          .id = 0,
3928          .parent = &pll3_80M,
3929          .enable_reg = MXC_CCM_CCGR5,
3930          .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET,
3931          .enable = _clk_enable,
3932          .disable = _clk_disable,
3933          .secondary = &uart_clk[1],
3934          .set_rate = _clk_uart_set_rate,
3935          .get_rate = _clk_uart_get_rate,
3936          .round_rate = _clk_uart_round_rate,
3937         },
3938         {
3939         __INIT_CLK_DEBUG(uart_serial_clk)
3940          .id = 1,
3941          .enable_reg = MXC_CCM_CCGR5,
3942          .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
3943          .enable = _clk_enable,
3944          .disable = _clk_disable,
3945         },
3946 };
3947
3948 static unsigned long _clk_hsi_tx_round_rate(struct clk *clk,
3949                                                 unsigned long rate)
3950 {
3951         u32 div;
3952         u32 parent_rate = clk_get_rate(clk->parent);
3953
3954         div = parent_rate / rate;
3955
3956         /* Make sure rate is not greater than the maximum value for the clock.
3957          * Also prevent a div of 0.
3958          */
3959         if (div == 0)
3960                 div++;
3961
3962         if (div > 8)
3963                 div = 8;
3964
3965         return parent_rate / div;
3966 }
3967
3968 static int _clk_hsi_tx_set_parent(struct clk *clk, struct clk *parent)
3969 {
3970         u32 reg = __raw_readl(MXC_CCM_CDCDR) & ~MXC_CCM_CDCDR_HSI_TX_CLK_SEL;
3971
3972         if (parent == &pll2_pfd_400M)
3973                 reg |= (MXC_CCM_CDCDR_HSI_TX_CLK_SEL);
3974
3975         __raw_writel(reg, MXC_CCM_CDCDR);
3976
3977         return 0;
3978 }
3979
3980 static unsigned long _clk_hsi_tx_get_rate(struct clk *clk)
3981 {
3982         u32 reg, div;
3983
3984         reg = __raw_readl(MXC_CCM_CDCDR);
3985         div = ((reg & MXC_CCM_CDCDR_HSI_TX_PODF_MASK) >>
3986                         MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET) + 1;
3987
3988         return clk_get_rate(clk->parent) / div;
3989 }
3990
3991 static int _clk_hsi_tx_set_rate(struct clk *clk, unsigned long rate)
3992 {
3993         u32 reg, div;
3994         u32 parent_rate = clk_get_rate(clk->parent);
3995
3996         div = parent_rate / rate;
3997         if (div == 0)
3998                 div++;
3999         if (((parent_rate / div) != rate) || (div > 8))
4000                 return -EINVAL;
4001
4002         reg = __raw_readl(MXC_CCM_CDCDR);
4003         reg &= ~MXC_CCM_CDCDR_HSI_TX_PODF_MASK;
4004         reg |= (div - 1) << MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET;
4005         __raw_writel(reg, MXC_CCM_CDCDR);
4006
4007         return 0;
4008 }
4009
4010 static struct clk hsi_tx_clk[] = {
4011         {
4012          __INIT_CLK_DEBUG(hsi_tx_clk)
4013         .id = 0,
4014          .parent = &pll2_pfd_400M,
4015         .enable_reg = MXC_CCM_CCGR3,
4016         .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET,
4017         .enable = _clk_enable,
4018         .disable = _clk_disable,
4019         .set_parent = _clk_hsi_tx_set_parent,
4020         .round_rate = _clk_hsi_tx_round_rate,
4021         .set_rate = _clk_hsi_tx_set_rate,
4022         .get_rate = _clk_hsi_tx_get_rate,
4023          .secondary = &hsi_tx_clk[1],
4024         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
4025         },
4026         {
4027         .parent = &mx6per1_clk,
4028         .secondary = &mx6per2_clk,
4029          },
4030 };
4031
4032 static struct clk mipi_pllref_clk = {
4033          __INIT_CLK_DEBUG(mipi_pllref_clk)
4034         .id = 0,
4035         .parent = &pll3_pfd_540M,
4036         .enable_reg = MXC_CCM_CCGR3,
4037         .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET,
4038         .enable = _clk_enable,
4039         .disable = _clk_disable,
4040 };
4041
4042 static struct clk hdmi_clk[] = {
4043         {
4044          __INIT_CLK_DEBUG(hdmi_isfr_clk)
4045         .id = 0,
4046         .parent = &pll3_pfd_540M,
4047         .enable_reg = MXC_CCM_CCGR2,
4048         .enable_shift = MXC_CCM_CCGRx_CG2_OFFSET,
4049         .enable = _clk_enable,
4050         .disable = _clk_disable,
4051         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
4052         },
4053         {
4054          __INIT_CLK_DEBUG(hdmi_iahb_clk)
4055         .id = 1,
4056          .parent = &ahb_clk,
4057         .enable_reg = MXC_CCM_CCGR2,
4058         .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET,
4059         .enable = _clk_enable,
4060         .disable = _clk_disable,
4061         },
4062 };
4063
4064 static struct clk caam_clk[] = {
4065         {
4066          __INIT_CLK_DEBUG(caam_mem_clk)
4067         .id = 0,
4068         .enable_reg = MXC_CCM_CCGR0,
4069         .enable_shift = MXC_CCM_CCGRx_CG4_OFFSET,
4070         .enable = _clk_enable,
4071         .disable = _clk_disable,
4072         .secondary = &caam_clk[1],
4073         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
4074         },
4075         {
4076          __INIT_CLK_DEBUG(caam_aclk_clk)
4077         .id = 1,
4078         .enable_reg = MXC_CCM_CCGR0,
4079         .enable_shift = MXC_CCM_CCGRx_CG5_OFFSET,
4080         .enable = _clk_enable,
4081         .disable = _clk_disable,
4082         .secondary = &caam_clk[2],
4083         },
4084         {
4085          __INIT_CLK_DEBUG(caam_ipg_clk)
4086         .id = 2,
4087         .enable_reg = MXC_CCM_CCGR0,
4088         .enable_shift = MXC_CCM_CCGRx_CG4_OFFSET,
4089         .enable = _clk_enable,
4090         .disable = _clk_disable,
4091         .parent = &mmdc_ch0_axi_clk[0],
4092         .secondary = &mx6per1_clk,
4093         },
4094 };
4095
4096 static int _clk_asrc_serial_set_parent(struct clk *clk, struct clk *parent)
4097 {
4098         u32 reg, mux;
4099
4100         reg = __raw_readl(MXC_CCM_CDCDR) & ~MXC_CCM_CDCDR_SPDIF1_CLK_SEL_MASK;
4101
4102         mux = _get_mux6(parent, &pll4_audio_main_clk, &pll3_pfd_508M,
4103                         &pll3_pfd_454M, &pll3_sw_clk, NULL, NULL);
4104         reg |= mux << MXC_CCM_CDCDR_SPDIF1_CLK_SEL_OFFSET;
4105
4106         __raw_writel(reg, MXC_CCM_CDCDR);
4107
4108         return 0;
4109 }
4110
4111 static unsigned long _clk_asrc_serial_get_rate(struct clk *clk)
4112 {
4113         u32 reg, pred, podf;
4114
4115         reg = __raw_readl(MXC_CCM_CDCDR);
4116
4117         pred = ((reg & MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK)
4118                 >> MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET) + 1;
4119         podf = ((reg & MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK)
4120                 >> MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET) + 1;
4121
4122         return clk_get_rate(clk->parent) / (pred * podf);
4123 }
4124
4125 static int _clk_asrc_serial_set_rate(struct clk *clk, unsigned long rate)
4126 {
4127         u32 reg, div, pre, post;
4128         u32 parent_rate = clk_get_rate(clk->parent);
4129
4130         div = parent_rate / rate;
4131         if (div == 0)
4132                 div++;
4133         if (((parent_rate / div) != rate) || div > 64)
4134                 return -EINVAL;
4135
4136         __calc_pre_post_dividers(1 << 3, div, &pre, &post);
4137
4138         reg = __raw_readl(MXC_CCM_CDCDR);
4139         reg &= ~(MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK|
4140                  MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK);
4141         reg |= (post - 1) << MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET;
4142         reg |= (pre - 1) << MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET;
4143
4144         __raw_writel(reg, MXC_CCM_CDCDR);
4145
4146         return 0;
4147 }
4148
4149 static unsigned long _clk_asrc_serial_round_rate(struct clk *clk,
4150                                                 unsigned long rate)
4151 {
4152         u32 pre, post;
4153         u32 parent_rate = clk_get_rate(clk->parent);
4154         u32 div = parent_rate / rate;
4155
4156         if (parent_rate % rate)
4157                 div++;
4158
4159         __calc_pre_post_dividers(1 << 3, div, &pre, &post);
4160
4161         return parent_rate / (pre * post);
4162 }
4163
4164 static struct clk asrc_clk[] = {
4165         {
4166         __INIT_CLK_DEBUG(asrc_clk)
4167         .id = 0,
4168         .parent = &pll4_audio_main_clk,
4169         .enable_reg = MXC_CCM_CCGR0,
4170         .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET,
4171         .enable = _clk_enable,
4172         .disable = _clk_disable,
4173         .secondary = &spba_clk,
4174         },
4175         {
4176         /*In the MX6 spec, asrc_serial_clk is listed as SPDIF1 clk
4177          * This clock can never be gated and does  not have any
4178          * CCGR bits associated with it.
4179          */
4180         __INIT_CLK_DEBUG(asrc_serial_clk)
4181         .id = 1,
4182         .parent = &pll3_sw_clk,
4183          .set_rate = _clk_asrc_serial_set_rate,
4184          .get_rate = _clk_asrc_serial_get_rate,
4185          .set_parent = _clk_asrc_serial_set_parent,
4186          .round_rate = _clk_asrc_serial_round_rate,
4187         },
4188 };
4189
4190 static struct clk apbh_dma_clk = {
4191         __INIT_CLK_DEBUG(apbh_dma_clk)
4192         .parent = &usdhc3_clk,
4193         .secondary = &mx6per1_clk,
4194         .enable = _clk_enable,
4195         .disable = _clk_disable_inwait,
4196         .enable_reg = MXC_CCM_CCGR0,
4197         .enable_shift = MXC_CCM_CCGRx_CG2_OFFSET,
4198 };
4199
4200 static struct clk aips_tz2_clk = {
4201         __INIT_CLK_DEBUG(aips_tz2_clk)
4202         .parent = &ahb_clk,
4203         .enable_reg = MXC_CCM_CCGR0,
4204         .enable_shift = MXC_CCM_CCGRx_CG1_OFFSET,
4205         .enable = _clk_enable,
4206         .disable = _clk_disable_inwait,
4207 };
4208
4209 static struct clk aips_tz1_clk = {
4210         __INIT_CLK_DEBUG(aips_tz1_clk)
4211         .parent = &ahb_clk,
4212         .enable_reg = MXC_CCM_CCGR0,
4213         .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET,
4214         .enable = _clk_enable,
4215         .disable = _clk_disable_inwait,
4216 };
4217
4218
4219 static struct clk openvg_axi_clk = {
4220         __INIT_CLK_DEBUG(openvg_axi_clk)
4221         .parent = &gpu2d_axi_clk,
4222         .enable = _clk_enable,
4223         .enable_reg = MXC_CCM_CCGR3,
4224         .enable_shift = MXC_CCM_CCGRx_CG15_OFFSET,
4225         .disable = _clk_disable,
4226         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
4227 };
4228
4229 static unsigned long _clk_gpu3d_core_round_rate(struct clk *clk,
4230                                                 unsigned long rate)
4231 {
4232         u32 div;
4233         u32 parent_rate = clk_get_rate(clk->parent);
4234
4235         div = parent_rate / rate;
4236
4237         /* Make sure rate is not greater than the maximum value for the clock.
4238          * Also prevent a div of 0.
4239          */
4240         if (div == 0)
4241                 div++;
4242
4243         if (div > 8)
4244                 div = 8;
4245
4246         return parent_rate / div;
4247 }
4248
4249 static int _clk_gpu3d_core_set_parent(struct clk *clk, struct clk *parent)
4250 {
4251         int mux;
4252         u32 reg = __raw_readl(MXC_CCM_CBCMR)
4253                 & ~MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK;
4254
4255         mux = _get_mux6(parent, &mmdc_ch0_axi_clk[0],
4256                 &pll3_usb_otg_main_clk,
4257                 &pll2_pfd_594M, &pll2_pfd_400M, NULL, NULL);
4258         reg |= (mux << MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET);
4259         __raw_writel(reg, MXC_CCM_CBCMR);
4260
4261         return 0;
4262 }
4263
4264 static unsigned long _clk_gpu3d_core_get_rate(struct clk *clk)
4265 {
4266         u32 reg, div;
4267
4268         reg = __raw_readl(MXC_CCM_CBCMR);
4269         div = ((reg & MXC_CCM_CBCMR_GPU3D_CORE_PODF_MASK) >>
4270                         MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET) + 1;
4271
4272         return clk_get_rate(clk->parent) / div;
4273 }
4274
4275 static int _clk_gpu3d_core_set_rate(struct clk *clk, unsigned long rate)
4276 {
4277         u32 reg, div;
4278         u32 parent_rate = clk_get_rate(clk->parent);
4279
4280         div = parent_rate / rate;
4281         if (div == 0)
4282                 div++;
4283         if (div > 8)
4284                 div = 8;
4285
4286         reg = __raw_readl(MXC_CCM_CBCMR);
4287         reg &= ~MXC_CCM_CBCMR_GPU3D_CORE_PODF_MASK;
4288         reg |= (div - 1) << MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET;
4289         __raw_writel(reg, MXC_CCM_CBCMR);
4290
4291         return 0;
4292 }
4293
4294 static struct clk gpu3d_core_clk[] = {
4295         {
4296         __INIT_CLK_DEBUG(gpu3d_core_clk)
4297         .parent = &pll2_pfd_594M,
4298         .enable = _clk_enable,
4299         .enable_reg = MXC_CCM_CCGR1,
4300         .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
4301         .disable = _clk_disable,
4302         .set_parent = _clk_gpu3d_core_set_parent,
4303         .set_rate = _clk_gpu3d_core_set_rate,
4304         .get_rate = _clk_gpu3d_core_get_rate,
4305         .round_rate = _clk_gpu3d_core_round_rate,
4306         .secondary = &gpu3d_core_clk[1],
4307         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
4308         },
4309         {
4310         .parent = &gpu3d_axi_clk,
4311         .secondary = &mx6fast1_clk,
4312         },
4313 };
4314
4315 static unsigned long _clk_gpu2d_core_round_rate(struct clk *clk,
4316                                                 unsigned long rate)
4317 {
4318         u32 div;
4319         u32 parent_rate = clk_get_rate(clk->parent);
4320
4321         div = parent_rate / rate;
4322
4323         /* Make sure rate is not greater than the maximum value for the clock.
4324          * Also prevent a div of 0.
4325          */
4326         if (div == 0)
4327                 div++;
4328
4329         if (div > 8)
4330                 div = 8;
4331
4332         return parent_rate / div;
4333 }
4334
4335 static int _clk_gpu2d_core_set_parent(struct clk *clk, struct clk *parent)
4336 {
4337         int mux;
4338         u32 reg = __raw_readl(MXC_CCM_CBCMR) &
4339                                 ~MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK;
4340
4341         mux = _get_mux6(parent, &axi_clk, &pll3_usb_otg_main_clk,
4342                 &pll2_pfd_352M, &pll2_pfd_400M, NULL, NULL);
4343         reg |= (mux << MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET);
4344         __raw_writel(reg, MXC_CCM_CBCMR);
4345
4346         return 0;
4347 }
4348
4349 static unsigned long _clk_gpu2d_core_get_rate(struct clk *clk)
4350 {
4351         u32 reg, div;
4352
4353         reg = __raw_readl(MXC_CCM_CBCMR);
4354         div = ((reg & MXC_CCM_CBCMR_GPU2D_CORE_PODF_MASK) >>
4355                         MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET) + 1;
4356
4357         return clk_get_rate(clk->parent) / div;
4358 }
4359
4360 static int _clk_gpu2d_core_set_rate(struct clk *clk, unsigned long rate)
4361 {
4362         u32 reg, div;
4363         u32 parent_rate = clk_get_rate(clk->parent);
4364
4365         div = parent_rate / rate;
4366         if (div == 0)
4367                 div++;
4368         if (((parent_rate / div) != rate) || (div > 8))
4369                 return -EINVAL;
4370
4371         reg = __raw_readl(MXC_CCM_CBCMR);
4372         reg &= ~MXC_CCM_CBCMR_GPU2D_CORE_PODF_MASK;
4373         reg |= (div - 1) << MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET;
4374         __raw_writel(reg, MXC_CCM_CBCMR);
4375
4376         return 0;
4377 }
4378 static struct clk gpu2d_core_clk[] = {
4379         {
4380         __INIT_CLK_DEBUG(gpu2d_core_clk)
4381         .parent = &pll2_pfd_352M,
4382         .enable = _clk_enable,
4383         .enable_reg = MXC_CCM_CCGR1,
4384         .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET,
4385         .disable = _clk_disable,
4386         .set_parent = _clk_gpu2d_core_set_parent,
4387         .set_rate = _clk_gpu2d_core_set_rate,
4388         .get_rate = _clk_gpu2d_core_get_rate,
4389         .round_rate = _clk_gpu2d_core_round_rate,
4390         .secondary = &gpu2d_core_clk[1],
4391         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
4392         },
4393         {
4394         .parent = &gpu2d_axi_clk,
4395         .secondary = &mx6fast1_clk,
4396         },
4397 };
4398
4399 static unsigned long _clk_gpu3d_shader_round_rate(struct clk *clk,
4400                                                 unsigned long rate)
4401 {
4402         u32 div;
4403         u32 parent_rate = clk_get_rate(clk->parent);
4404
4405         div = parent_rate / rate;
4406
4407         /* Make sure rate is not greater than the maximum value for the clock.
4408          * Also prevent a div of 0.
4409          */
4410         if (div == 0)
4411                 div++;
4412
4413         if (div > 8)
4414                 div = 8;
4415
4416         return parent_rate / div;
4417 }
4418
4419 static int _clk_gpu3d_shader_set_parent(struct clk *clk, struct clk *parent)
4420 {
4421         int mux;
4422         u32 reg = __raw_readl(MXC_CCM_CBCMR)
4423                 & ~MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_MASK;
4424
4425         mux = _get_mux6(parent, &mmdc_ch0_axi_clk[0],
4426                 &pll3_usb_otg_main_clk,
4427                 &pll2_pfd_594M, &pll3_pfd_720M, NULL, NULL);
4428         reg |= (mux << MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET);
4429         __raw_writel(reg, MXC_CCM_CBCMR);
4430
4431         return 0;
4432 }
4433
4434 static unsigned long _clk_gpu3d_shader_get_rate(struct clk *clk)
4435 {
4436         u32 reg, div;
4437
4438         reg = __raw_readl(MXC_CCM_CBCMR);
4439         div = ((reg & MXC_CCM_CBCMR_GPU3D_SHADER_PODF_MASK) >>
4440                         MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET) + 1;
4441
4442         return clk_get_rate(clk->parent) / div;
4443 }
4444
4445 static int _clk_gpu3d_shader_set_rate(struct clk *clk, unsigned long rate)
4446 {
4447         u32 reg, div;
4448         u32 parent_rate = clk_get_rate(clk->parent);
4449
4450         div = parent_rate / rate;
4451         if (div == 0)
4452                 div++;
4453         if (div > 8)
4454                 div = 8;
4455
4456         reg = __raw_readl(MXC_CCM_CBCMR);
4457         reg &= ~MXC_CCM_CBCMR_GPU3D_SHADER_PODF_MASK;
4458         reg |= (div - 1) << MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET;
4459         __raw_writel(reg, MXC_CCM_CBCMR);
4460
4461         return 0;
4462 }
4463
4464
4465 static struct clk gpu3d_shader_clk = {
4466         __INIT_CLK_DEBUG(gpu3d_shader_clk)
4467         .parent = &pll3_pfd_720M,
4468         .secondary = &mmdc_ch0_axi_clk[0],
4469         .enable = _clk_enable,
4470         .enable_reg = MXC_CCM_CCGR1,
4471         .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
4472         .disable = _clk_disable,
4473         .set_parent = _clk_gpu3d_shader_set_parent,
4474         .set_rate = _clk_gpu3d_shader_set_rate,
4475         .get_rate = _clk_gpu3d_shader_get_rate,
4476         .round_rate = _clk_gpu3d_shader_round_rate,
4477         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
4478 };
4479
4480 /* set the parent by the ipcg table */
4481 static struct clk gpmi_nand_clk[] = {
4482         {       /* gpmi_io_clk */
4483         __INIT_CLK_DEBUG(gpmi_io_clk)
4484         .parent = &enfc_clk,
4485         .secondary = &gpmi_nand_clk[1],
4486         .enable = _clk_enable,
4487         .enable_reg = MXC_CCM_CCGR4,
4488         .enable_shift = MXC_CCM_CCGRx_CG14_OFFSET,
4489         .disable = _clk_disable,
4490         },
4491         {       /* gpmi_apb_clk */
4492         __INIT_CLK_DEBUG(gpmi_apb_clk)
4493         .parent = &usdhc3_clk,
4494         .secondary = &gpmi_nand_clk[2],
4495         .enable = _clk_enable,
4496         .enable_reg = MXC_CCM_CCGR4,
4497         .enable_shift = MXC_CCM_CCGRx_CG15_OFFSET,
4498         .disable = _clk_disable,
4499         },
4500         {       /* bch_clk */
4501         __INIT_CLK_DEBUG(gpmi_bch_clk)
4502         .parent = &usdhc4_clk,
4503         .secondary = &gpmi_nand_clk[3],
4504         .enable = _clk_enable,
4505         .enable_reg = MXC_CCM_CCGR4,
4506         .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
4507         .disable = _clk_disable,
4508         },
4509         {       /* bch_apb_clk */
4510         __INIT_CLK_DEBUG(gpmi_bch_apb_clk)
4511         .parent = &usdhc3_clk,
4512         .secondary = &gpmi_nand_clk[4],
4513         .enable = _clk_enable,
4514         .enable_reg = MXC_CCM_CCGR4,
4515         .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET,
4516         .disable = _clk_disable,
4517         },
4518         {       /* bch relative clk */
4519         __INIT_CLK_DEBUG(pl301_mx6qperl_bch)
4520         .parent = &mx6per1_clk,
4521         .secondary = &mmdc_ch0_axi_clk[0],
4522         },
4523 };
4524
4525 static struct clk pwm_clk[] = {
4526         {
4527         __INIT_CLK_DEBUG(pwm_clk_0)
4528          .parent = &ipg_perclk,
4529          .id = 0,
4530          .enable_reg = MXC_CCM_CCGR4,
4531          .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET,
4532          .enable = _clk_enable,
4533          .disable = _clk_disable,
4534          },
4535         {
4536         __INIT_CLK_DEBUG(pwm_clk_1)
4537          .parent = &ipg_perclk,
4538          .id = 1,
4539          .enable_reg = MXC_CCM_CCGR4,
4540          .enable_shift = MXC_CCM_CCGRx_CG9_OFFSET,
4541          .enable = _clk_enable,
4542          .disable = _clk_disable,
4543          },
4544         {
4545         __INIT_CLK_DEBUG(pwm_clk_2)
4546          .parent = &ipg_perclk,
4547          .id = 2,
4548          .enable_reg = MXC_CCM_CCGR4,
4549          .enable_shift = MXC_CCM_CCGRx_CG10_OFFSET,
4550          .enable = _clk_enable,
4551          .disable = _clk_disable,
4552          },
4553         {
4554         __INIT_CLK_DEBUG(pwm_clk_3)
4555          .parent = &ipg_perclk,
4556          .id = 3,
4557          .enable_reg = MXC_CCM_CCGR4,
4558          .enable_shift = MXC_CCM_CCGRx_CG11_OFFSET,
4559          .enable = _clk_enable,
4560          .disable = _clk_disable,
4561          },
4562 };
4563
4564 static int _clk_pcie_enable(struct clk *clk)
4565 {
4566         unsigned int reg;
4567
4568         /* Enable SATA ref clock */
4569         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
4570         reg |= ANADIG_PLL_ENET_EN_PCIE;
4571         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
4572
4573         _clk_enable(clk);
4574
4575         return 0;
4576 }
4577
4578 static void _clk_pcie_disable(struct clk *clk)
4579 {
4580         unsigned int reg;
4581
4582         _clk_disable(clk);
4583
4584         /* Disable SATA ref clock */
4585         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
4586         reg &= ~ANADIG_PLL_ENET_EN_PCIE;
4587         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
4588 }
4589
4590 static struct clk pcie_clk[] = {
4591         {
4592         __INIT_CLK_DEBUG(pcie_clk)
4593         .parent = &pcie_axi_clk,
4594         .enable = _clk_pcie_enable,
4595         .disable = _clk_pcie_disable,
4596         .enable_reg = MXC_CCM_CCGR4,
4597         .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET,
4598         .secondary = &pcie_clk[1],
4599         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
4600         },
4601         {
4602         .parent = &mmdc_ch0_axi_clk[0],
4603         .secondary = &mx6fast1_clk,
4604         },
4605 };
4606
4607 static int _clk_sata_enable(struct clk *clk)
4608 {
4609         unsigned int reg;
4610
4611         /* Clear Power Down and Enable PLLs */
4612         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
4613         reg &= ~ANADIG_PLL_ENET_POWER_DOWN;
4614         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
4615
4616         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
4617         reg |= ANADIG_PLL_ENET_EN;
4618         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
4619
4620         /* Waiting for the PLL is locked */
4621         if (!WAIT(ANADIG_PLL_ENET_LOCK & __raw_readl(PLL8_ENET_BASE_ADDR),
4622                                 SPIN_DELAY))
4623                 panic("pll8 lock failed\n");
4624
4625         /* Disable the bypass */
4626         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
4627         reg &= ~ANADIG_PLL_ENET_BYPASS;
4628         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
4629
4630         /* Enable SATA ref clock */
4631         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
4632         reg |= ANADIG_PLL_ENET_EN_SATA;
4633         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
4634
4635         _clk_enable(clk);
4636
4637         return 0;
4638 }
4639
4640 static void _clk_sata_disable(struct clk *clk)
4641 {
4642         unsigned int reg;
4643
4644         _clk_disable(clk);
4645
4646         /* Disable SATA ref clock */
4647         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
4648         reg &= ~ANADIG_PLL_ENET_EN_SATA;
4649         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
4650 }
4651
4652 static struct clk sata_clk[] = {
4653         {
4654         __INIT_CLK_DEBUG(sata_clk)
4655         .parent = &ipg_clk,
4656         .enable = _clk_sata_enable,
4657         .enable_reg = MXC_CCM_CCGR5,
4658         .enable_shift = MXC_CCM_CCGRx_CG2_OFFSET,
4659         .disable = _clk_sata_disable,
4660         .secondary = &sata_clk[1],
4661         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
4662         },
4663         {
4664         .parent = &mmdc_ch0_axi_clk[0],
4665         .secondary = &mx6per1_clk,
4666         }
4667 };
4668
4669 static struct clk usboh3_clk[] = {
4670         {
4671         __INIT_CLK_DEBUG(usboh3_clk)
4672         .parent = &ahb_clk,
4673         .enable = _clk_enable,
4674         .enable_reg = MXC_CCM_CCGR6,
4675         .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET,
4676         .disable = _clk_disable,
4677         .secondary = &usboh3_clk[1],
4678         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
4679         },
4680         {
4681         .parent = &mmdc_ch0_axi_clk[0],
4682         .secondary = &mx6per1_clk,
4683         },
4684 };
4685
4686 static struct clk mlb150_clk = {
4687         __INIT_CLK_DEBUG(mlb150_clk)
4688         .id = 0,
4689         .parent = &ipg_clk,
4690         .enable_reg = MXC_CCM_CCGR3,
4691         .enable_shift = MXC_CCM_CCGRx_CG9_OFFSET,
4692         .enable = _clk_enable,
4693         .disable = _clk_disable,
4694 };
4695
4696 static int _clk_enable1(struct clk *clk)
4697 {
4698         u32 reg;
4699         reg = __raw_readl(clk->enable_reg);
4700         reg |= 1 << clk->enable_shift;
4701         __raw_writel(reg, clk->enable_reg);
4702
4703         return 0;
4704 }
4705
4706 static void _clk_disable1(struct clk *clk)
4707 {
4708         u32 reg;
4709         reg = __raw_readl(clk->enable_reg);
4710         reg &= ~(1 << clk->enable_shift);
4711         __raw_writel(reg, clk->enable_reg);
4712 }
4713
4714 static int _clk_clko_set_parent(struct clk *clk, struct clk *parent)
4715 {
4716         u32 sel, reg;
4717
4718         if (parent == &pll3_usb_otg_main_clk)
4719                 sel = 0;
4720         else if (parent == &pll2_528_bus_main_clk)
4721                 sel = 1;
4722         else if (parent == &pll1_sys_main_clk)
4723                 sel = 2;
4724         else if (parent == &pll5_video_main_clk)
4725                 sel = 3;
4726         else if (parent == &axi_clk)
4727                 sel = 5;
4728         else if (parent == &enfc_clk)
4729                 sel = 6;
4730         else if (parent == &ipu1_di_clk[0])
4731                 sel = 7;
4732         else if (parent == &ipu1_di_clk[1])
4733                 sel = 8;
4734         else if (parent == &ipu2_di_clk[0])
4735                 sel = 9;
4736         else if (parent == &ipu2_di_clk[1])
4737                 sel = 10;
4738         else if (parent == &ahb_clk)
4739                 sel = 11;
4740         else if (parent == &ipg_clk)
4741                 sel = 12;
4742         else if (parent == &ipg_perclk)
4743                 sel = 13;
4744         else if (parent == &ckil_clk)
4745                 sel = 14;
4746         else if (parent == &pll4_audio_main_clk)
4747                 sel = 15;
4748         else
4749                 return -EINVAL;
4750
4751         reg = __raw_readl(MXC_CCM_CCOSR);
4752         reg &= ~MXC_CCM_CCOSR_CKOL_SEL_MASK;
4753         reg |= sel << MXC_CCM_CCOSR_CKOL_SEL_OFFSET;
4754         __raw_writel(reg, MXC_CCM_CCOSR);
4755         return 0;
4756 }
4757
4758 static unsigned long _clk_clko_get_rate(struct clk *clk)
4759 {
4760         u32 reg = __raw_readl(MXC_CCM_CCOSR);
4761         u32 div = ((reg & MXC_CCM_CCOSR_CKOL_DIV_MASK) >>
4762                         MXC_CCM_CCOSR_CKOL_DIV_OFFSET) + 1;
4763         return clk_get_rate(clk->parent) / div;
4764 }
4765
4766 static int _clk_clko_set_rate(struct clk *clk, unsigned long rate)
4767 {
4768         u32 reg;
4769         u32 parent_rate = clk_get_rate(clk->parent);
4770         u32 div = parent_rate / rate;
4771
4772         if (div == 0)
4773                 div++;
4774         if (((parent_rate / div) != rate) || (div > 8))
4775                 return -EINVAL;
4776
4777         reg = __raw_readl(MXC_CCM_CCOSR);
4778         reg &= ~MXC_CCM_CCOSR_CKOL_DIV_MASK;
4779         reg |= (div - 1) << MXC_CCM_CCOSR_CKOL_DIV_OFFSET;
4780         __raw_writel(reg, MXC_CCM_CCOSR);
4781         return 0;
4782 }
4783
4784 static unsigned long _clk_clko_round_rate(struct clk *clk,
4785                                                 unsigned long rate)
4786 {
4787         u32 parent_rate = clk_get_rate(clk->parent);
4788         u32 div = parent_rate / rate;
4789
4790         /* Make sure rate is not greater than the maximum value for the clock.
4791          * Also prevent a div of 0.
4792          */
4793         if (div == 0)
4794                 div++;
4795         if (div > 8)
4796                 div = 8;
4797         return parent_rate / div;
4798 }
4799
4800 static int _clk_clko2_set_parent(struct clk *clk, struct clk *parent)
4801 {
4802         u32 sel, reg;
4803
4804         if (parent == &mmdc_ch0_axi_clk[0])
4805                 sel = 0;
4806         else if (parent == &mmdc_ch1_axi_clk[0])
4807                 sel = 1;
4808         else if (parent == &usdhc4_clk)
4809                 sel = 2;
4810         else if (parent == &usdhc1_clk)
4811                 sel = 3;
4812         else if (parent == &gpu2d_axi_clk)
4813                 sel = 4;
4814         else if (parent == &ecspi_clk[0])
4815                 sel = 6;
4816         else if (parent == &gpu3d_axi_clk)
4817                 sel = 7;
4818         else if (parent == &usdhc3_clk)
4819                 sel = 8;
4820         else if (parent == &pcie_clk[0])
4821                 sel = 9;
4822         else if (parent == &ipu1_clk)
4823                 sel = 11;
4824         else if (parent == &ipu2_clk)
4825                 sel = 12;
4826         else if (parent == &vdo_axi_clk)
4827                 sel = 13;
4828         else if (parent == &osc_clk)
4829                 sel = 14;
4830         else if (parent == &gpu2d_core_clk[0])
4831                 sel = 15;
4832         else if (parent == &gpu3d_core_clk[0])
4833                 sel = 16;
4834         else if (parent == &usdhc2_clk)
4835                 sel = 17;
4836         else if (parent == &ssi1_clk)
4837                 sel = 18;
4838         else if (parent == &ssi2_clk)
4839                 sel = 19;
4840         else if (parent == &ssi3_clk)
4841                 sel = 20;
4842         else if (parent == &gpu3d_shader_clk)
4843                 sel = 21;
4844         else if (parent == &can_clk_root)
4845                 sel = 23;
4846         else if (parent == &ldb_di0_clk)
4847                 sel = 24;
4848         else if (parent == &ldb_di1_clk)
4849                 sel = 25;
4850         else if (parent == &esai_clk)
4851                 sel = 26;
4852         else if (parent == &uart_clk[0])
4853                 sel = 28;
4854         else if (parent == &spdif0_clk[0])
4855                 sel = 29;
4856         else if (parent == &hsi_tx_clk[0])
4857                 sel = 31;
4858         else
4859                 return -EINVAL;
4860
4861         reg = __raw_readl(MXC_CCM_CCOSR);
4862         reg &= ~MXC_CCM_CCOSR_CKO2_SEL_MASK;
4863         reg |= sel << MXC_CCM_CCOSR_CKO2_SEL_OFFSET;
4864         __raw_writel(reg, MXC_CCM_CCOSR);
4865         return 0;
4866 }
4867
4868 static unsigned long _clk_clko2_get_rate(struct clk *clk)
4869 {
4870         u32 reg = __raw_readl(MXC_CCM_CCOSR);
4871         u32 div = ((reg & MXC_CCM_CCOSR_CKO2_DIV_MASK) >>
4872                         MXC_CCM_CCOSR_CKO2_DIV_OFFSET) + 1;
4873         return clk_get_rate(clk->parent) / div;
4874 }
4875
4876 static int _clk_clko2_set_rate(struct clk *clk, unsigned long rate)
4877 {
4878         u32 reg;
4879         u32 parent_rate = clk_get_rate(clk->parent);
4880         u32 div = parent_rate / rate;
4881
4882         if (div == 0)
4883                 div++;
4884         if (((parent_rate / div) != rate) || (div > 8))
4885                 return -EINVAL;
4886
4887         reg = __raw_readl(MXC_CCM_CCOSR);
4888         reg &= ~MXC_CCM_CCOSR_CKO2_DIV_MASK;
4889         reg |= (div - 1) << MXC_CCM_CCOSR_CKO2_DIV_OFFSET;
4890         __raw_writel(reg, MXC_CCM_CCOSR);
4891         return 0;
4892 }
4893
4894 static struct clk clko_clk = {
4895         __INIT_CLK_DEBUG(clko_clk)
4896         .parent = &pll2_528_bus_main_clk,
4897         .enable = _clk_enable1,
4898         .enable_reg = MXC_CCM_CCOSR,
4899         .enable_shift = MXC_CCM_CCOSR_CKOL_EN_OFFSET,
4900         .disable = _clk_disable1,
4901         .set_parent = _clk_clko_set_parent,
4902         .set_rate = _clk_clko_set_rate,
4903         .get_rate = _clk_clko_get_rate,
4904         .round_rate = _clk_clko_round_rate,
4905 };
4906
4907 static struct clk clko2_clk = {
4908         __INIT_CLK_DEBUG(clko2_clk)
4909         .parent = &usdhc4_clk,
4910         .enable = _clk_enable1,
4911         .enable_reg = MXC_CCM_CCOSR,
4912         .enable_shift = MXC_CCM_CCOSR_CKO2_EN_OFFSET,
4913         .disable = _clk_disable1,
4914         .set_parent = _clk_clko2_set_parent,
4915         .set_rate = _clk_clko2_set_rate,
4916         .get_rate = _clk_clko2_get_rate,
4917         .round_rate = _clk_clko_round_rate,
4918 };
4919
4920 static struct clk perfmon0_clk = {
4921         __INIT_CLK_DEBUG(perfmon0_clk)
4922         .parent = &mmdc_ch0_axi_clk[0],
4923         .enable = _clk_enable1,
4924         .enable_reg = MXC_CCM_CCGR4,
4925         .enable_shift = MXC_CCM_CCGRx_CG1_OFFSET,
4926         .disable = _clk_disable1,
4927 };
4928
4929 static struct clk perfmon1_clk = {
4930         __INIT_CLK_DEBUG(perfmon1_clk)
4931         .parent = &ipu1_clk,
4932         .enable = _clk_enable1,
4933         .enable_reg = MXC_CCM_CCGR4,
4934         .enable_shift = MXC_CCM_CCGRx_CG2_OFFSET,
4935         .disable = _clk_disable1,
4936 };
4937
4938 static struct clk perfmon2_clk = {
4939         __INIT_CLK_DEBUG(perfmon2_clk)
4940         .parent = &mmdc_ch0_axi_clk[0],
4941         .enable = _clk_enable1,
4942         .enable_reg = MXC_CCM_CCGR4,
4943         .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET,
4944         .disable = _clk_disable1,
4945 };
4946
4947 static struct clk dummy_clk = {
4948         .id = 0,
4949 };
4950
4951 #define _REGISTER_CLOCK(d, n, c) \
4952         { \
4953                 .dev_id = d, \
4954                 .con_id = n, \
4955                 .clk = &c, \
4956         }
4957
4958
4959 static struct clk_lookup lookups[] = {
4960         _REGISTER_CLOCK(NULL, "osc", osc_clk),
4961         _REGISTER_CLOCK(NULL, "ckih", ckih_clk),
4962         _REGISTER_CLOCK(NULL, "ckih2", ckih2_clk),
4963         _REGISTER_CLOCK(NULL, "ckil", ckil_clk),
4964         _REGISTER_CLOCK(NULL, "pll1_main_clk", pll1_sys_main_clk),
4965         _REGISTER_CLOCK(NULL, "pll1_sw_clk", pll1_sw_clk),
4966         _REGISTER_CLOCK(NULL, "pll2", pll2_528_bus_main_clk),
4967         _REGISTER_CLOCK(NULL, "pll2_pfd_400M", pll2_pfd_400M),
4968         _REGISTER_CLOCK(NULL, "pll2_pfd_352M", pll2_pfd_352M),
4969         _REGISTER_CLOCK(NULL, "pll2_pfd_594M", pll2_pfd_594M),
4970         _REGISTER_CLOCK(NULL, "pll2_200M", pll2_200M),
4971         _REGISTER_CLOCK(NULL, "pll3_main_clk", pll3_usb_otg_main_clk),
4972         _REGISTER_CLOCK(NULL, "pll3_pfd_508M", pll3_pfd_508M),
4973         _REGISTER_CLOCK(NULL, "pll3_pfd_454M", pll3_pfd_454M),
4974         _REGISTER_CLOCK(NULL, "pll3_pfd_720M", pll3_pfd_720M),
4975         _REGISTER_CLOCK(NULL, "pll3_pfd_540M", pll3_pfd_540M),
4976         _REGISTER_CLOCK(NULL, "pll3_sw_clk", pll3_sw_clk),
4977         _REGISTER_CLOCK(NULL, "pll3_120M", pll3_120M),
4978         _REGISTER_CLOCK(NULL, "pll3_120M", pll3_80M),
4979         _REGISTER_CLOCK(NULL, "pll3_120M", pll3_60M),
4980         _REGISTER_CLOCK(NULL, "pll4", pll4_audio_main_clk),
4981         _REGISTER_CLOCK(NULL, "pll5", pll5_video_main_clk),
4982         _REGISTER_CLOCK(NULL, "pll6", pll6_mlb150_main_clk),
4983         _REGISTER_CLOCK(NULL, "pll3", pll7_usb_host_main_clk),
4984         _REGISTER_CLOCK(NULL, "pll4", pll8_enet_main_clk),
4985         _REGISTER_CLOCK(NULL, "cpu_clk", cpu_clk),
4986         _REGISTER_CLOCK(NULL, "periph_clk", periph_clk),
4987         _REGISTER_CLOCK(NULL, "axi_clk", axi_clk),
4988         _REGISTER_CLOCK(NULL, "mmdc_ch0_axi", mmdc_ch0_axi_clk[0]),
4989         _REGISTER_CLOCK(NULL, "mmdc_ch1_axi", mmdc_ch1_axi_clk[0]),
4990         _REGISTER_CLOCK(NULL, "ahb", ahb_clk),
4991         _REGISTER_CLOCK(NULL, "ipg_clk", ipg_clk),
4992         _REGISTER_CLOCK(NULL, "ipg_perclk", ipg_perclk),
4993         _REGISTER_CLOCK(NULL, "spba", spba_clk),
4994         _REGISTER_CLOCK("imx-sdma", NULL, sdma_clk[0]),
4995         _REGISTER_CLOCK(NULL, "gpu2d_axi_clk", gpu2d_axi_clk),
4996         _REGISTER_CLOCK(NULL, "gpu3d_axi_clk", gpu3d_axi_clk),
4997         _REGISTER_CLOCK(NULL, "pcie_axi_clk", pcie_axi_clk),
4998         _REGISTER_CLOCK(NULL, "vdo_axi_clk", vdo_axi_clk),
4999         _REGISTER_CLOCK(NULL, "iim_clk", iim_clk),
5000         _REGISTER_CLOCK(NULL, "i2c_clk", i2c_clk[0]),
5001         _REGISTER_CLOCK("imx-i2c.1", NULL, i2c_clk[1]),
5002         _REGISTER_CLOCK("imx-i2c.2", NULL, i2c_clk[2]),
5003         _REGISTER_CLOCK(NULL, "vpu_clk", vpu_clk[0]),
5004         _REGISTER_CLOCK(NULL, "ipu1_clk", ipu1_clk),
5005         _REGISTER_CLOCK(NULL, "ipu2_clk", ipu2_clk),
5006         _REGISTER_CLOCK(NULL, "cko1_clk0", cko1_clk0),
5007         _REGISTER_CLOCK("sdhci-esdhc-imx.0", NULL, usdhc1_clk),
5008         _REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL, usdhc2_clk),
5009         _REGISTER_CLOCK("sdhci-esdhc-imx.2", NULL, usdhc3_clk),
5010         _REGISTER_CLOCK("sdhci-esdhc-imx.3", NULL, usdhc4_clk),
5011         _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk),
5012         _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk),
5013         _REGISTER_CLOCK("imx-ssi.2", NULL, ssi3_clk),
5014         _REGISTER_CLOCK(NULL, "ipu1_di0_clk", ipu1_di_clk[0]),
5015         _REGISTER_CLOCK(NULL, "ipu1_di1_clk", ipu1_di_clk[1]),
5016         _REGISTER_CLOCK(NULL, "ipu2_di0_clk", ipu2_di_clk[0]),
5017         _REGISTER_CLOCK(NULL, "ipu2_di1_clk", ipu2_di_clk[1]),
5018         _REGISTER_CLOCK(NULL, "can_root_clk", can_clk_root),
5019         _REGISTER_CLOCK("imx6q-flexcan.0", NULL, can1_clk[0]),
5020         _REGISTER_CLOCK("imx6q-flexcan.1", NULL, can2_clk[0]),
5021         _REGISTER_CLOCK(NULL, "ldb_di0_clk", ldb_di0_clk),
5022         _REGISTER_CLOCK(NULL, "ldb_di1_clk", ldb_di1_clk),
5023         _REGISTER_CLOCK("mxc_spdif.0", NULL, spdif0_clk[0]),
5024         _REGISTER_CLOCK(NULL, "esai_clk", esai_clk),
5025         _REGISTER_CLOCK("imx6q-ecspi.0", NULL, ecspi_clk[0]),
5026         _REGISTER_CLOCK("imx6q-ecspi.1", NULL, ecspi_clk[1]),
5027         _REGISTER_CLOCK("imx6q-ecspi.2", NULL, ecspi_clk[2]),
5028         _REGISTER_CLOCK("imx6q-ecspi.3", NULL, ecspi_clk[3]),
5029         _REGISTER_CLOCK("imx6q-ecspi.4", NULL, ecspi_clk[4]),
5030         _REGISTER_CLOCK(NULL, "emi_slow_clk", emi_slow_clk),
5031         _REGISTER_CLOCK(NULL, "emi_clk", emi_clk),
5032         _REGISTER_CLOCK(NULL, "enfc_clk", enfc_clk),
5033         _REGISTER_CLOCK("imx-uart.0", NULL, uart_clk[0]),
5034         _REGISTER_CLOCK("imx-uart.1", NULL, uart_clk[0]),
5035         _REGISTER_CLOCK("imx-uart.2", NULL, uart_clk[0]),
5036         _REGISTER_CLOCK("imx-uart.3", NULL, uart_clk[0]),
5037         _REGISTER_CLOCK(NULL, "hsi_tx", hsi_tx_clk[0]),
5038         _REGISTER_CLOCK(NULL, "caam_clk", caam_clk[0]),
5039         _REGISTER_CLOCK(NULL, "asrc_clk", asrc_clk[0]),
5040         _REGISTER_CLOCK(NULL, "asrc_serial_clk", asrc_clk[1]),
5041         _REGISTER_CLOCK("mxs-dma-apbh", NULL, apbh_dma_clk),
5042         _REGISTER_CLOCK(NULL, "openvg_axi_clk", openvg_axi_clk),
5043         _REGISTER_CLOCK(NULL, "gpu3d_clk", gpu3d_core_clk[0]),
5044         _REGISTER_CLOCK(NULL, "gpu2d_clk", gpu2d_core_clk[0]),
5045         _REGISTER_CLOCK(NULL, "gpu3d_shader_clk", gpu3d_shader_clk),
5046         _REGISTER_CLOCK(NULL, "gpt", gpt_clk[0]),
5047         _REGISTER_CLOCK("imx6q-gpmi-nand.0", NULL, gpmi_nand_clk[0]),
5048         _REGISTER_CLOCK(NULL, "gpmi-apb", gpmi_nand_clk[1]),
5049         _REGISTER_CLOCK(NULL, "bch", gpmi_nand_clk[2]),
5050         _REGISTER_CLOCK(NULL, "bch-apb", gpmi_nand_clk[3]),
5051         _REGISTER_CLOCK(NULL, "pl301_mx6qperl-bch", gpmi_nand_clk[4]),
5052         _REGISTER_CLOCK("mxc_pwm.0", NULL, pwm_clk[0]),
5053         _REGISTER_CLOCK("mxc_pwm.1", NULL, pwm_clk[1]),
5054         _REGISTER_CLOCK("mxc_pwm.2", NULL, pwm_clk[2]),
5055         _REGISTER_CLOCK("mxc_pwm.3", NULL, pwm_clk[3]),
5056         _REGISTER_CLOCK(NULL, "pcie_clk", pcie_clk[0]),
5057         _REGISTER_CLOCK("fec.0", NULL, enet_clk[0]),
5058         _REGISTER_CLOCK(NULL, "imx_sata_clk", sata_clk[0]),
5059         _REGISTER_CLOCK(NULL, "usboh3_clk", usboh3_clk[0]),
5060         _REGISTER_CLOCK(NULL, "usb_phy1_clk", usb_phy1_clk),
5061         _REGISTER_CLOCK(NULL, "usb_phy3_clk", usb_phy3_clk),
5062         _REGISTER_CLOCK(NULL, "usb_phy4_clk", usb_phy4_clk),
5063         _REGISTER_CLOCK("imx2-wdt.0", NULL, dummy_clk),
5064         _REGISTER_CLOCK("imx2-wdt.1", NULL, dummy_clk),
5065         _REGISTER_CLOCK(NULL, "hdmi_isfr_clk", hdmi_clk[0]),
5066         _REGISTER_CLOCK(NULL, "hdmi_iahb_clk", hdmi_clk[1]),
5067         _REGISTER_CLOCK(NULL, "mipi_pllref_clk", mipi_pllref_clk),
5068         _REGISTER_CLOCK(NULL, NULL, vdoa_clk),
5069         _REGISTER_CLOCK(NULL, NULL, aips_tz2_clk),
5070         _REGISTER_CLOCK(NULL, NULL, aips_tz1_clk),
5071         _REGISTER_CLOCK(NULL, "clko_clk", clko_clk),
5072         _REGISTER_CLOCK(NULL, "clko2_clk", clko2_clk),
5073         _REGISTER_CLOCK("mxs-perfmon.0", "perfmon", perfmon0_clk),
5074         _REGISTER_CLOCK("mxs-perfmon.1", "perfmon", perfmon1_clk),
5075         _REGISTER_CLOCK("mxs-perfmon.2", "perfmon", perfmon2_clk),
5076         _REGISTER_CLOCK(NULL, "mlb150_clk", mlb150_clk),
5077 };
5078
5079 static void clk_tree_init(void)
5080
5081 {
5082         unsigned int reg;
5083
5084         reg = __raw_readl(MMDC_MDMISC_OFFSET);
5085         if ((reg & MMDC_MDMISC_DDR_TYPE_MASK) ==
5086                 (0x1 << MMDC_MDMISC_DDR_TYPE_OFFSET)) {
5087                 clk_set_parent(&periph_clk, &pll2_pfd_400M);
5088                 printk(KERN_INFO "Set periph_clk's parent to pll2_pfd_400M!\n");
5089         }
5090 }
5091
5092
5093 int __init mx6_clocks_init(unsigned long ckil, unsigned long osc,
5094         unsigned long ckih1, unsigned long ckih2)
5095 {
5096         __iomem void *base;
5097         int i;
5098
5099         external_low_reference = ckil;
5100         external_high_reference = ckih1;
5101         ckih2_reference = ckih2;
5102         oscillator_reference = osc;
5103
5104         apll_base = ioremap(ANATOP_BASE_ADDR, SZ_4K);
5105
5106         for (i = 0; i < ARRAY_SIZE(lookups); i++) {
5107                 clkdev_add(&lookups[i]);
5108                 clk_debug_register(lookups[i].clk);
5109         }
5110
5111         /* Disable un-necessary PFDs & PLLs */
5112
5113         /* keep correct count. */
5114         clk_enable(&cpu_clk);
5115         clk_enable(&periph_clk);
5116
5117         clk_tree_init();
5118
5119         if (pll2_pfd_400M.usecount == 0 && cpu_is_mx6q())
5120                 pll2_pfd_400M.disable(&pll2_pfd_400M);
5121         pll2_pfd_352M.disable(&pll2_pfd_352M);
5122         pll2_pfd_594M.disable(&pll2_pfd_594M);
5123
5124 #if !defined(CONFIG_FEC_1588)
5125         pll3_pfd_454M.disable(&pll3_pfd_454M);
5126         pll3_pfd_508M.disable(&pll3_pfd_508M);
5127         pll3_pfd_540M.disable(&pll3_pfd_540M);
5128         pll3_pfd_720M.disable(&pll3_pfd_720M);
5129
5130         pll3_usb_otg_main_clk.disable(&pll3_usb_otg_main_clk);
5131 #endif
5132         pll4_audio_main_clk.disable(&pll4_audio_main_clk);
5133         pll5_video_main_clk.disable(&pll5_video_main_clk);
5134         pll6_mlb150_main_clk.disable(&pll6_mlb150_main_clk);
5135         pll7_usb_host_main_clk.disable(&pll7_usb_host_main_clk);
5136         pll8_enet_main_clk.disable(&pll8_enet_main_clk);
5137
5138         sata_clk[0].disable(&sata_clk[0]);
5139         pcie_clk[0].disable(&pcie_clk[0]);
5140
5141         /* Initialize Audio and Video PLLs to valid frequency (650MHz). */
5142         clk_set_rate(&pll4_audio_main_clk, 650000000);
5143         clk_set_rate(&pll5_video_main_clk, 650000000);
5144
5145         clk_set_parent(&ipu1_di_clk[0], &pll5_video_main_clk);
5146         clk_set_parent(&ipu1_di_clk[1], &pll5_video_main_clk);
5147         clk_set_parent(&ipu2_di_clk[0], &pll5_video_main_clk);
5148         clk_set_parent(&ipu2_di_clk[1], &pll5_video_main_clk);
5149
5150         clk_set_parent(&cko1_clk0, &ipg_clk);
5151         clk_set_rate(&cko1_clk0, 22000000);
5152         clk_enable(&cko1_clk0);
5153
5154         clk_set_parent(&emi_clk, &pll2_pfd_400M);
5155         clk_set_rate(&emi_clk, 200000000);
5156
5157         clk_set_parent(&gpu3d_shader_clk, &pll2_pfd_594M);
5158         clk_set_rate(&gpu3d_shader_clk, 594000000);
5159         clk_set_parent(&gpu3d_core_clk[0], &mmdc_ch0_axi_clk[0]);
5160         clk_set_rate(&gpu3d_core_clk[0], 528000000);
5161
5162         /* PCLK camera - J5 */
5163         clk_set_parent(&clko2_clk, &osc_clk);
5164         clk_set_rate(&clko2_clk, 2400000);
5165
5166         /*
5167          * FIXME: asrc needs to use asrc_serial(spdif1) clock to do sample
5168          * rate convertion and this clock frequency can not be too high, set
5169          * it to the minimum value 7.5Mhz to make asrc work properly.
5170          */
5171         clk_set_parent(&asrc_clk[1], &pll3_sw_clk);
5172         clk_set_rate(&asrc_clk[1], 7500000);
5173
5174         /* set the GPMI clock to default frequency : 20MHz */
5175         clk_set_rate(&enfc_clk, enfc_clk.round_rate(&enfc_clk, 20000000));
5176
5177         mx6_cpu_op_init();
5178         cpu_op_tbl = get_cpu_op(&cpu_op_nr);
5179
5180         /* Gate off all possible clocks */
5181         if (mxc_jtag_enabled) {
5182                 __raw_writel(3 << MXC_CCM_CCGRx_CG11_OFFSET |
5183                              3 << MXC_CCM_CCGRx_CG2_OFFSET |
5184                              3 << MXC_CCM_CCGRx_CG1_OFFSET |
5185                              3 << MXC_CCM_CCGRx_CG0_OFFSET, MXC_CCM_CCGR0);
5186         } else {
5187                 __raw_writel(1 << MXC_CCM_CCGRx_CG11_OFFSET |
5188                              3 << MXC_CCM_CCGRx_CG2_OFFSET |
5189                              3 << MXC_CCM_CCGRx_CG1_OFFSET |
5190                              3 << MXC_CCM_CCGRx_CG0_OFFSET, MXC_CCM_CCGR0);
5191         }
5192         __raw_writel(3 << MXC_CCM_CCGRx_CG10_OFFSET, MXC_CCM_CCGR1);
5193         __raw_writel(1 << MXC_CCM_CCGRx_CG12_OFFSET |
5194                      1 << MXC_CCM_CCGRx_CG11_OFFSET |
5195                      3 << MXC_CCM_CCGRx_CG10_OFFSET |
5196                      3 << MXC_CCM_CCGRx_CG9_OFFSET |
5197                      3 << MXC_CCM_CCGRx_CG8_OFFSET, MXC_CCM_CCGR2);
5198         __raw_writel(1 << MXC_CCM_CCGRx_CG14_OFFSET |
5199                      3 << MXC_CCM_CCGRx_CG13_OFFSET |
5200                      3 << MXC_CCM_CCGRx_CG12_OFFSET |
5201                      3 << MXC_CCM_CCGRx_CG11_OFFSET |
5202                      3 << MXC_CCM_CCGRx_CG10_OFFSET, MXC_CCM_CCGR3);
5203         __raw_writel(3 << MXC_CCM_CCGRx_CG7_OFFSET |
5204                         1 << MXC_CCM_CCGRx_CG6_OFFSET |
5205                         1 << MXC_CCM_CCGRx_CG4_OFFSET, MXC_CCM_CCGR4);
5206         __raw_writel(1 << MXC_CCM_CCGRx_CG0_OFFSET, MXC_CCM_CCGR5);
5207
5208         __raw_writel(0, MXC_CCM_CCGR6);
5209
5210         /* Lower the ipg_perclk frequency to 8.25MHz. */
5211         clk_set_rate(&ipg_perclk, 8250000);
5212
5213         /* S/PDIF */
5214         clk_set_parent(&spdif0_clk[0], &pll3_pfd_454M);
5215
5216         if (mx6q_revision() == IMX_CHIP_REVISION_1_0) {
5217                 gpt_clk[0].parent = &ipg_perclk;
5218                 gpt_clk[0].get_rate = NULL;
5219                 }
5220
5221         base = ioremap(GPT_BASE_ADDR, SZ_4K);
5222         mxc_timer_init(&gpt_clk[0], base, MXC_INT_GPT);
5223
5224         lp_high_freq = 0;
5225         lp_med_freq = 0;
5226
5227         return 0;
5228
5229 }