arch/arm/mach-mx6/clock.c

   1
   2 /*
   3  * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
   4  */
   5
   6 /*
   7  * The code contained herein is licensed under the GNU General Public
   8  * License. You may obtain a copy of the GNU General Public License
   9  * Version 2 or later at the following locations:
  10  *
  11  * http://www.opensource.org/licenses/gpl-license.html
  12  * http://www.gnu.org/copyleft/gpl.html
  13  */
  14
  15 #include <linux/kernel.h>
  16 #include <linux/init.h>
  17 #include <linux/types.h>
  18 #include <linux/time.h>
  19 #include <linux/hrtimer.h>
  20 #include <linux/mm.h>
  21 #include <linux/errno.h>
  22 #include <linux/delay.h>
  23 #include <linux/clk.h>
  24 #include <linux/io.h>
  25 #include <linux/clkdev.h>
  26 #include <asm/div64.h>
  27 #include <mach/hardware.h>
  28 #include <mach/common.h>
  29 #include <mach/clock.h>
  30 #include <mach/mxc_dvfs.h>
  31 #include "crm_regs.h"
  32 #include "cpu_op-mx6.h"
  33
  34 #ifdef CONFIG_CLK_DEBUG
  35 #define __INIT_CLK_DEBUG(n)     .name = #n,
  36 #else
  37 #define __INIT_CLK_DEBUG(n)
  38 #endif
  39
  40 extern u32 arm_max_freq;
  41 extern int mxc_jtag_enabled;
  42 extern struct cpu_op *(*get_cpu_op)(int *op);
  43 extern int mx6_set_cpu_voltage(u32 cpu_volt);
  44
  45 extern int lp_high_freq;
  46 extern int lp_med_freq;
  47
  48 void __iomem *apll_base;
  49 static struct clk pll1_sys_main_clk;
  50 static struct clk pll2_528_bus_main_clk;
  51 static struct clk pll2_pfd_400M;
  52 static struct clk pll3_usb_otg_main_clk;
  53 static struct clk pll4_audio_main_clk;
  54 static struct clk pll5_video_main_clk;
  55 static struct clk pll6_MLB_main_clk;
  56 static struct clk pll7_usb_host_main_clk;
  57 static struct clk pll8_enet_main_clk;
  58 static struct clk apbh_dma_clk;
  59 static struct clk openvg_axi_clk;
  60 static struct clk enfc_clk;
  61 static struct clk ipu1_di_clk_root;
  62 static struct clk ipu2_di_clk_root;
  63 static struct clk usdhc3_clk;
  64
  65 static struct cpu_op *cpu_op_tbl;
  66 static int cpu_op_nr;
  67
  68 #define SPIN_DELAY      1200000 /* in nanoseconds */
  69
  70 #define AUDIO_VIDEO_MIN_CLK_FREQ        650000000
  71 #define AUDIO_VIDEO_MAX_CLK_FREQ        1300000000
  72
  73 /* We need to check the exp status again after timer expiration,
  74  * as there might be interrupt coming between the first time exp
  75  * and the time reading, then the time reading may be several ms
  76  * after the exp checking due to the irq handle, so we need to
  77  * check it to make sure the exp return the right value after
  78  * timer expiration. */
  79 #define WAIT(exp, timeout) \
  80 ({ \
  81         struct timespec nstimeofday; \
  82         struct timespec curtime; \
  83         int result = 1; \
  84         getnstimeofday(&nstimeofday); \
  85         while (!(exp)) { \
  86                 getnstimeofday(&curtime); \
  87                 if ((curtime.tv_nsec - nstimeofday.tv_nsec) > (timeout)) { \
  88                         if (!(exp)) \
  89                                 result = 0; \
  90                         break; \
  91                 } \
  92         } \
  93         result; \
  94 })
  95
  96 /* External clock values passed-in by the board code */
  97 static unsigned long external_high_reference, external_low_reference;
  98 static unsigned long oscillator_reference, ckih2_reference;
  99
 100 static void __calc_pre_post_dividers(u32 max_podf, u32 div, u32 *pre, u32 *post)
 101 {
 102         u32 min_pre, temp_pre, old_err, err;
 103
 104         /* Some of the podfs are 3 bits while others are 6 bits.
 105           * Handle both cases here.
 106           */
 107         if (div >= 512 && (max_podf == 64)) {
 108                 /* For pre = 3bits and podf = 6 bits, max divider is 512. */
 109                 *pre = 8;
 110                 *post = 64;
 111         } else if (div >= 64 && (max_podf == 8)) {
 112                 /* For pre = 3bits and podf = 3 bits, max divider is 64. */
 113                 *pre = 8;
 114                 *post = 8;
 115         } else if (div >= 8) {
 116                 /* Find the minimum pre-divider for a max podf */
 117                 if (max_podf == 64)
 118                         min_pre = (div - 1) / (1 << 6) + 1;
 119                 else
 120                         min_pre = (div - 1) / (1 << 3) + 1;
 121                 old_err = 8;
 122                 /* Now loop through to find the max pre-divider. */
 123                 for (temp_pre = 8; temp_pre >= min_pre; temp_pre--) {
 124                         err = div % temp_pre;
 125                         if (err == 0) {
 126                                 *pre = temp_pre;
 127                                 break;
 128                         }
 129                         err = temp_pre - err;
 130                         if (err < old_err) {
 131                                 old_err = err;
 132                                 *pre = temp_pre;
 133                         }
 134                 }
 135                 *post = (div + *pre - 1) / *pre;
 136         } else if (div < 8) {
 137                 *pre = div;
 138                 *post = 1;
 139         }
 140 }
 141
 142 static int _clk_enable(struct clk *clk)
 143 {
 144         u32 reg;
 145         reg = __raw_readl(clk->enable_reg);
 146         reg |= MXC_CCM_CCGRx_CG_MASK << clk->enable_shift;
 147         __raw_writel(reg, clk->enable_reg);
 148
 149         if (clk->flags & AHB_HIGH_SET_POINT)
 150                 lp_high_freq++;
 151         else if (clk->flags & AHB_MED_SET_POINT)
 152                 lp_med_freq++;
 153
 154         return 0;
 155 }
 156
 157 static void _clk_disable(struct clk *clk)
 158 {
 159         u32 reg;
 160         reg = __raw_readl(clk->enable_reg);
 161         reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift);
 162         __raw_writel(reg, clk->enable_reg);
 163
 164         if (clk->flags & AHB_HIGH_SET_POINT)
 165                 lp_high_freq--;
 166         else if (clk->flags & AHB_MED_SET_POINT)
 167                 lp_med_freq--;
 168 }
 169
 170 static void _clk_disable_inwait(struct clk *clk)
 171 {
 172         u32 reg;
 173         reg = __raw_readl(clk->enable_reg);
 174         reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift);
 175         reg |= 1 << clk->enable_shift;
 176         __raw_writel(reg, clk->enable_reg);
 177 }
 178
 179 /*
 180  * For the 4-to-1 muxed input clock
 181  */
 182 static inline u32 _get_mux(struct clk *parent, struct clk *m0,
 183                            struct clk *m1, struct clk *m2, struct clk *m3)
 184 {
 185         if (parent == m0)
 186                 return 0;
 187         else if (parent == m1)
 188                 return 1;
 189         else if (parent == m2)
 190                 return 2;
 191         else if (parent == m3)
 192                 return 3;
 193         else
 194                 BUG();
 195
 196         return 0;
 197 }
 198
 199 static inline void __iomem *_get_pll_base(struct clk *pll)
 200 {
 201         if (pll == &pll1_sys_main_clk)
 202                 return PLL1_SYS_BASE_ADDR;
 203         else if (pll == &pll2_528_bus_main_clk)
 204                 return PLL2_528_BASE_ADDR;
 205         else if (pll == &pll3_usb_otg_main_clk)
 206                 return PLL3_480_USB1_BASE_ADDR;
 207         else if (pll == &pll4_audio_main_clk)
 208                 return PLL4_AUDIO_BASE_ADDR;
 209         else if (pll == &pll5_video_main_clk)
 210                 return PLL5_VIDEO_BASE_ADDR;
 211         else if (pll == &pll6_MLB_main_clk)
 212                 return PLL6_MLB_BASE_ADDR;
 213         else if (pll == &pll7_usb_host_main_clk)
 214                 return PLL7_480_USB2_BASE_ADDR;
 215         else if (pll == &pll8_enet_main_clk)
 216                 return PLL8_ENET_BASE_ADDR;
 217         else
 218                 BUG();
 219         return NULL;
 220 }
 221
 222
 223 /*
 224  * For the 6-to-1 muxed input clock
 225  */
 226 static inline u32 _get_mux6(struct clk *parent, struct clk *m0, struct clk *m1,
 227                             struct clk *m2, struct clk *m3, struct clk *m4,
 228                             struct clk *m5)
 229 {
 230         if (parent == m0)
 231                 return 0;
 232         else if (parent == m1)
 233                 return 1;
 234         else if (parent == m2)
 235                 return 2;
 236         else if (parent == m3)
 237                 return 3;
 238         else if (parent == m4)
 239                 return 4;
 240         else if (parent == m5)
 241                 return 5;
 242         else
 243                 BUG();
 244
 245         return 0;
 246 }
 247 static unsigned long get_high_reference_clock_rate(struct clk *clk)
 248 {
 249         return external_high_reference;
 250 }
 251
 252 static unsigned long get_low_reference_clock_rate(struct clk *clk)
 253 {
 254         return external_low_reference;
 255 }
 256
 257 static unsigned long get_oscillator_reference_clock_rate(struct clk *clk)
 258 {
 259         return oscillator_reference;
 260 }
 261
 262 static unsigned long get_ckih2_reference_clock_rate(struct clk *clk)
 263 {
 264         return ckih2_reference;
 265 }
 266
 267 /* External high frequency clock */
 268 static struct clk ckih_clk = {
 269         __INIT_CLK_DEBUG(ckih_clk)
 270         .get_rate = get_high_reference_clock_rate,
 271 };
 272
 273 static struct clk ckih2_clk = {
 274         __INIT_CLK_DEBUG(ckih2_clk)
 275         .get_rate = get_ckih2_reference_clock_rate,
 276 };
 277
 278 static struct clk osc_clk = {
 279         __INIT_CLK_DEBUG(osc_clk)
 280         .get_rate = get_oscillator_reference_clock_rate,
 281 };
 282
 283 /* External low frequency (32kHz) clock */
 284 static struct clk ckil_clk = {
 285         __INIT_CLK_DEBUG(ckil_clk)
 286         .get_rate = get_low_reference_clock_rate,
 287 };
 288
 289 static unsigned long pfd_round_rate(struct clk *clk, unsigned long rate)
 290 {
 291         u32 frac;
 292         u64 tmp;
 293
 294         tmp = (u64)clk_get_rate(clk->parent) * 18;
 295         tmp += rate/2;
 296         do_div(tmp, rate);
 297         frac = tmp;
 298         frac = frac < 12 ? 12 : frac;
 299         frac = frac > 35 ? 35 : frac;
 300         tmp = (u64)clk_get_rate(clk->parent) * 18;
 301         do_div(tmp, frac);
 302         return tmp;
 303 }
 304
 305 static unsigned long pfd_get_rate(struct clk *clk)
 306 {
 307         u32 frac;
 308         u64 tmp;
 309         tmp = (u64)clk_get_rate(clk->parent) * 18;
 310
 311         if (apbh_dma_clk.usecount == 0)
 312                 apbh_dma_clk.enable(&apbh_dma_clk);
 313
 314         frac = (__raw_readl(clk->enable_reg) >> clk->enable_shift) &
 315                         ANADIG_PFD_FRAC_MASK;
 316
 317         do_div(tmp, frac);
 318
 319         return tmp;
 320 }
 321
 322 static int pfd_set_rate(struct clk *clk, unsigned long rate)
 323 {
 324         u32 frac;
 325         u64 tmp;
 326         tmp = (u64)clk_get_rate(clk->parent) * 18;
 327
 328         if (apbh_dma_clk.usecount == 0)
 329                 apbh_dma_clk.enable(&apbh_dma_clk);
 330
 331         /* Round up the divider so that we don't set a rate
 332           * higher than what is requested. */
 333         tmp += rate/2;
 334         do_div(tmp, rate);
 335         frac = tmp;
 336         frac = frac < 12 ? 12 : frac;
 337         frac = frac > 35 ? 35 : frac;
 338         /* clear clk frac bits */
 339         __raw_writel(ANADIG_PFD_FRAC_MASK << clk->enable_shift,
 340                         (int)clk->enable_reg + 8);
 341         /* set clk frac bits */
 342         __raw_writel(frac << clk->enable_shift,
 343                         (int)clk->enable_reg + 4);
 344
 345         tmp = (u64)clk_get_rate(clk->parent) * 18;
 346         do_div(tmp, frac);
 347
 348         if (apbh_dma_clk.usecount == 0)
 349                 apbh_dma_clk.disable(&apbh_dma_clk);
 350         return 0;
 351 }
 352
 353 static int _clk_pfd_enable(struct clk *clk)
 354 {
 355         if (apbh_dma_clk.usecount == 0)
 356                 apbh_dma_clk.enable(&apbh_dma_clk);
 357
 358         /* clear clk gate bit */
 359         __raw_writel((1 << (clk->enable_shift + 7)),
 360                         (int)clk->enable_reg + 8);
 361
 362         if (apbh_dma_clk.usecount == 0)
 363                 apbh_dma_clk.disable(&apbh_dma_clk);
 364
 365         return 0;
 366 }
 367
 368 static void _clk_pfd_disable(struct clk *clk)
 369 {
 370         if (apbh_dma_clk.usecount == 0)
 371                 apbh_dma_clk.enable(&apbh_dma_clk);
 372
 373         /* set clk gate bit */
 374         __raw_writel((1 << (clk->enable_shift + 7)),
 375                         (int)clk->enable_reg + 4);
 376
 377         if (apbh_dma_clk.usecount == 0)
 378                 apbh_dma_clk.disable(&apbh_dma_clk);
 379 }
 380
 381 static int _clk_pll_enable(struct clk *clk)
 382 {
 383         unsigned int reg;
 384         void __iomem *pllbase;
 385
 386         pllbase = _get_pll_base(clk);
 387
 388         reg = __raw_readl(pllbase);
 389         reg &= ~ANADIG_PLL_BYPASS;
 390         reg &= ~ANADIG_PLL_POWER_DOWN;
 391
 392         /* The 480MHz PLLs have the opposite definition for power bit. */
 393         if (clk == &pll3_usb_otg_main_clk || clk == &pll7_usb_host_main_clk)
 394                 reg |= ANADIG_PLL_POWER_DOWN;
 395
 396         __raw_writel(reg, pllbase);
 397
 398         /* Wait for PLL to lock */
 399         if (!WAIT(__raw_readl(pllbase) & ANADIG_PLL_LOCK,
 400                                 SPIN_DELAY))
 401                 panic("pll enable failed\n");
 402
 403         /* Enable the PLL output now*/
 404         reg = __raw_readl(pllbase);
 405         reg |= ANADIG_PLL_ENABLE;
 406         __raw_writel(reg, pllbase);
 407
 408         return 0;
 409 }
 410
 411 static void _clk_pll_disable(struct clk *clk)
 412 {
 413         unsigned int reg;
 414         void __iomem *pllbase;
 415
 416         pllbase = _get_pll_base(clk);
 417
 418         reg = __raw_readl(pllbase);
 419         reg |= ANADIG_PLL_BYPASS;
 420         reg &= ~ANADIG_PLL_ENABLE;
 421
 422         __raw_writel(reg, pllbase);
 423 }
 424
 425 static unsigned long  _clk_pll1_main_get_rate(struct clk *clk)
 426 {
 427         unsigned int div;
 428         unsigned long val;
 429
 430         div = __raw_readl(PLL1_SYS_BASE_ADDR) & ANADIG_PLL_SYS_DIV_SELECT_MASK;
 431         val = (clk_get_rate(clk->parent) * div) / 2;
 432         return val;
 433 }
 434
 435 static int _clk_pll1_main_set_rate(struct clk *clk, unsigned long rate)
 436 {
 437         unsigned int reg,  div;
 438
 439         if (rate < AUDIO_VIDEO_MIN_CLK_FREQ || rate > AUDIO_VIDEO_MAX_CLK_FREQ)
 440                 return -EINVAL;
 441
 442         div = (rate * 2) / clk_get_rate(clk->parent) ;
 443
 444         reg = __raw_readl(PLL1_SYS_BASE_ADDR) & ~ANADIG_PLL_SYS_DIV_SELECT_MASK;
 445         reg |= div;
 446         __raw_writel(reg, PLL1_SYS_BASE_ADDR);
 447
 448         return 0;
 449 }
 450
 451 static struct clk pll1_sys_main_clk = {
 452         __INIT_CLK_DEBUG(pll1_sys_main_clk)
 453         .parent = &osc_clk,
 454         .get_rate = _clk_pll1_main_get_rate,
 455         .set_rate = _clk_pll1_main_set_rate,
 456         .enable = _clk_pll_enable,
 457         .disable = _clk_pll_disable,
 458 };
 459
 460 static int _clk_pll1_sw_set_parent(struct clk *clk, struct clk *parent)
 461 {
 462         u32 reg;
 463
 464         reg = __raw_readl(MXC_CCM_CCSR);
 465
 466         if (parent == &pll1_sys_main_clk) {
 467                 reg &= ~MXC_CCM_CCSR_PLL1_SW_CLK_SEL;
 468                 __raw_writel(reg, MXC_CCM_CCSR);
 469                 /* Set the step_clk parent to be lp_apm, to save power. */
 470                 reg = __raw_readl(MXC_CCM_CCSR);
 471                 reg = (reg & ~MXC_CCM_CCSR_STEP_SEL);
 472         } else {
 473                 /* Set STEP_CLK to be the parent*/
 474                 if (parent == &osc_clk) {
 475                         /* Set STEP_CLK to be sourced from LPAPM. */
 476                         reg = __raw_readl(MXC_CCM_CCSR);
 477                         reg = (reg & ~MXC_CCM_CCSR_STEP_SEL);
 478                         __raw_writel(reg, MXC_CCM_CCSR);
 479                 } else {
 480                         /* Set STEP_CLK to be sourced from PLL2-PDF (400MHz). */
 481                         reg = __raw_readl(MXC_CCM_CCSR);
 482                         reg |= MXC_CCM_CCSR_STEP_SEL;
 483                         __raw_writel(reg, MXC_CCM_CCSR);
 484
 485                 }
 486                 reg = __raw_readl(MXC_CCM_CCSR);
 487                 reg |= MXC_CCM_CCSR_PLL1_SW_CLK_SEL;
 488         }
 489         __raw_writel(reg, MXC_CCM_CCSR);
 490         return 0;
 491 }
 492
 493 static unsigned long _clk_pll1_sw_get_rate(struct clk *clk)
 494 {
 495         return clk_get_rate(clk->parent);
 496 }
 497
 498 static struct clk pll1_sw_clk = {
 499         __INIT_CLK_DEBUG(pll1_sw_clk)
 500         .parent = &pll1_sys_main_clk,
 501         .set_parent = _clk_pll1_sw_set_parent,
 502         .get_rate = _clk_pll1_sw_get_rate,
 503 };
 504
 505 static unsigned long _clk_pll2_main_get_rate(struct clk *clk)
 506 {
 507         unsigned int div;
 508         unsigned long val;
 509
 510         div = __raw_readl(PLL2_528_BASE_ADDR) & ANADIG_PLL_528_DIV_SELECT;
 511
 512         if (div == 1)
 513                 val = clk_get_rate(clk->parent) * 22;
 514
 515         else
 516                 val = clk_get_rate(clk->parent) * 20;
 517
 518         return val;
 519 }
 520
 521 static int _clk_pll2_main_set_rate(struct clk *clk, unsigned long rate)
 522 {
 523         unsigned int reg,  div;
 524
 525         if (rate == 528000000)
 526                 div = 1;
 527         else if (rate == 480000000)
 528                 div = 0;
 529         else
 530                 return -EINVAL;
 531
 532         reg = __raw_readl(PLL2_528_BASE_ADDR);
 533         reg &= ~ANADIG_PLL_528_DIV_SELECT;
 534         reg |= div;
 535         __raw_writel(reg, PLL2_528_BASE_ADDR);
 536
 537         return 0;
 538 }
 539
 540 static struct clk pll2_528_bus_main_clk = {
 541         __INIT_CLK_DEBUG(pll2_528_bus_main_clk)
 542         .parent = &osc_clk,
 543         .get_rate = _clk_pll2_main_get_rate,
 544         .set_rate = _clk_pll2_main_set_rate,
 545         .enable = _clk_pll_enable,
 546         .disable = _clk_pll_disable,
 547 };
 548
 549 static struct clk pll2_pfd_400M = {
 550         __INIT_CLK_DEBUG(pll2_pfd_400M)
 551         .parent = &pll2_528_bus_main_clk,
 552         .enable_reg = (void *)PFD_528_BASE_ADDR,
 553         .enable_shift = ANADIG_PFD2_FRAC_OFFSET,
 554         .enable = _clk_pfd_enable,
 555         .disable = _clk_pfd_disable,
 556         .get_rate = pfd_get_rate,
 557         .set_rate = pfd_set_rate,
 558         .get_rate = pfd_get_rate,
 559         .round_rate = pfd_round_rate,
 560 };
 561
 562 static struct clk pll2_pfd_352M = {
 563         __INIT_CLK_DEBUG(pll2_pfd_352M)
 564         .parent = &pll2_528_bus_main_clk,
 565         .enable_reg = (void *)PFD_528_BASE_ADDR,
 566         .enable_shift = ANADIG_PFD0_FRAC_OFFSET,
 567         .enable = _clk_pfd_enable,
 568         .disable = _clk_pfd_disable,
 569         .set_rate = pfd_set_rate,
 570         .get_rate = pfd_get_rate,
 571         .round_rate = pfd_round_rate,
 572 };
 573
 574 static struct clk pll2_pfd_594M = {
 575         __INIT_CLK_DEBUG(pll2_pfd_594M)
 576         .parent = &pll2_528_bus_main_clk,
 577         .enable_reg = (void *)PFD_528_BASE_ADDR,
 578         .enable_shift = ANADIG_PFD1_FRAC_OFFSET,
 579         .enable = _clk_pfd_enable,
 580         .disable = _clk_pfd_disable,
 581         .set_rate = pfd_set_rate,
 582         .get_rate = pfd_get_rate,
 583         .round_rate = pfd_round_rate,
 584 };
 585
 586 static unsigned long _clk_pll2_200M_get_rate(struct clk *clk)
 587 {
 588         return clk_get_rate(clk->parent) / 2;
 589 }
 590
 591 static struct clk pll2_200M = {
 592         __INIT_CLK_DEBUG(pll2_200M)
 593         .parent = &pll2_pfd_400M,
 594         .get_rate = _clk_pll2_200M_get_rate,
 595 };
 596
 597 static unsigned long _clk_pll3_usb_otg_get_rate(struct clk *clk)
 598 {
 599         unsigned int div;
 600         unsigned long val;
 601
 602         div = __raw_readl(PLL3_480_USB1_BASE_ADDR)
 603                 & ANADIG_PLL_480_DIV_SELECT_MASK;
 604
 605         if (div == 1)
 606                 val = clk_get_rate(clk->parent) * 22;
 607         else
 608                 val = clk_get_rate(clk->parent) * 20;
 609         return val;
 610 }
 611
 612 static int _clk_pll3_usb_otg_set_rate(struct clk *clk, unsigned long rate)
 613 {
 614         unsigned int reg,  div;
 615
 616         if (rate == 528000000)
 617                 div = 1;
 618         else if (rate == 480000000)
 619                 div = 0;
 620         else
 621                 return -EINVAL;
 622
 623         reg = __raw_readl(PLL3_480_USB1_BASE_ADDR);
 624         reg &= ~ANADIG_PLL_480_DIV_SELECT_MASK;
 625         reg |= div;
 626         __raw_writel(reg, PLL3_480_USB1_BASE_ADDR);
 627
 628         return 0;
 629 }
 630
 631
 632 /* same as pll3_main_clk. These two clocks should always be the same */
 633 static struct clk pll3_usb_otg_main_clk = {
 634         __INIT_CLK_DEBUG(pll3_usb_otg_main_clk)
 635         .parent = &osc_clk,
 636         .enable = _clk_pll_enable,
 637         .disable = _clk_pll_disable,
 638         .set_rate = _clk_pll3_usb_otg_set_rate,
 639         .get_rate = _clk_pll3_usb_otg_get_rate,
 640 };
 641
 642 /* for USB OTG */
 643 static struct clk usb_phy1_clk = {
 644         __INIT_CLK_DEBUG(usb_phy1_clk)
 645         .parent = &pll3_usb_otg_main_clk,
 646         .set_rate = _clk_pll3_usb_otg_set_rate,
 647         .get_rate = _clk_pll3_usb_otg_get_rate,
 648 };
 649
 650 /* For HSIC port 1 */
 651 static struct clk usb_phy3_clk = {
 652         __INIT_CLK_DEBUG(usb_phy3_clk)
 653         .parent = &pll3_usb_otg_main_clk,
 654         .set_rate = _clk_pll3_usb_otg_set_rate,
 655         .get_rate = _clk_pll3_usb_otg_get_rate,
 656 };
 657
 658 /* For HSIC port 2 */
 659 static struct clk usb_phy4_clk = {
 660         __INIT_CLK_DEBUG(usb_phy4_clk)
 661         .parent = &pll3_usb_otg_main_clk,
 662         .set_rate = _clk_pll3_usb_otg_set_rate,
 663         .get_rate = _clk_pll3_usb_otg_get_rate,
 664 };
 665
 666 static struct clk pll3_pfd_508M = {
 667         __INIT_CLK_DEBUG(pll3_pfd_508M)
 668         .parent = &pll3_usb_otg_main_clk,
 669         .enable_reg = (void *)PFD_480_BASE_ADDR,
 670         .enable_shift = ANADIG_PFD2_FRAC_OFFSET,
 671         .enable = _clk_pfd_enable,
 672         .disable = _clk_pfd_disable,
 673         .set_rate = pfd_set_rate,
 674         .get_rate = pfd_get_rate,
 675         .round_rate = pfd_round_rate,
 676 };
 677
 678 static struct clk pll3_pfd_454M = {
 679         __INIT_CLK_DEBUG(pll3_pfd_454M)
 680         .parent = &pll3_usb_otg_main_clk,
 681         .enable_reg = (void *)PFD_480_BASE_ADDR,
 682         .enable_shift = ANADIG_PFD3_FRAC_OFFSET,
 683         .enable = _clk_pfd_enable,
 684         .disable = _clk_pfd_disable,
 685         .set_rate = pfd_set_rate,
 686         .get_rate = pfd_get_rate,
 687         .round_rate = pfd_round_rate,
 688 };
 689
 690 static struct clk pll3_pfd_720M = {
 691         __INIT_CLK_DEBUG(pll3_pfd_720M)
 692         .parent = &pll3_usb_otg_main_clk,
 693         .enable_reg = (void *)PFD_480_BASE_ADDR,
 694         .enable_shift = ANADIG_PFD0_FRAC_OFFSET,
 695         .enable = _clk_pfd_enable,
 696         .disable = _clk_pfd_disable,
 697         .set_rate = pfd_set_rate,
 698         .get_rate = pfd_get_rate,
 699         .round_rate = pfd_round_rate,
 700 };
 701
 702 static struct clk pll3_pfd_540M = {
 703         __INIT_CLK_DEBUG(pll3_pfd_540M)
 704         .parent = &pll3_usb_otg_main_clk,
 705         .enable_reg = (void *)PFD_480_BASE_ADDR,
 706         .enable_shift = ANADIG_PFD1_FRAC_OFFSET,
 707         .enable = _clk_pfd_enable,
 708         .disable = _clk_pfd_disable,
 709         .set_rate = pfd_set_rate,
 710         .get_rate = pfd_get_rate,
 711         .round_rate = pfd_round_rate,
 712         .get_rate = pfd_get_rate,
 713 };
 714
 715 static unsigned long _clk_pll3_sw_get_rate(struct clk *clk)
 716 {
 717         return clk_get_rate(clk->parent);
 718 }
 719
 720 /* same as pll3_main_clk. These two clocks should always be the same */
 721 static struct clk pll3_sw_clk = {
 722         __INIT_CLK_DEBUG(pll3_sw_clk)
 723         .parent = &pll3_usb_otg_main_clk,
 724         .get_rate = _clk_pll3_sw_get_rate,
 725 };
 726
 727 static unsigned long _clk_pll3_120M_get_rate(struct clk *clk)
 728 {
 729         return clk_get_rate(clk->parent) / 4;
 730 }
 731
 732 static struct clk pll3_120M = {
 733         __INIT_CLK_DEBUG(pll3_120M)
 734         .parent = &pll3_sw_clk,
 735         .get_rate = _clk_pll3_120M_get_rate,
 736 };
 737
 738 static unsigned long _clk_pll3_80M_get_rate(struct clk *clk)
 739 {
 740         return clk_get_rate(clk->parent) / 6;
 741 }
 742
 743 static struct clk pll3_80M = {
 744         __INIT_CLK_DEBUG(pll3_80M)
 745         .parent = &pll3_sw_clk,
 746         .get_rate = _clk_pll3_80M_get_rate,
 747 };
 748
 749 static unsigned long _clk_pll3_60M_get_rate(struct clk *clk)
 750 {
 751         return clk_get_rate(clk->parent) / 8;
 752 }
 753
 754 static struct clk pll3_60M = {
 755         __INIT_CLK_DEBUG(pll3_60M)
 756         .parent = &pll3_sw_clk,
 757         .get_rate = _clk_pll3_60M_get_rate,
 758 };
 759
 760 static unsigned long  _clk_audio_video_get_rate(struct clk *clk)
 761 {
 762         unsigned int div, mfn, mfd;
 763         unsigned long rate;
 764         unsigned int parent_rate = clk_get_rate(clk->parent);
 765         void __iomem *pllbase;
 766
 767         if (clk == &pll4_audio_main_clk)
 768                 pllbase = PLL4_AUDIO_BASE_ADDR;
 769         else
 770                 pllbase = PLL5_VIDEO_BASE_ADDR;
 771
 772         div = __raw_readl(pllbase) & ANADIG_PLL_SYS_DIV_SELECT_MASK;
 773         mfn = __raw_readl(pllbase + PLL_NUM_DIV_OFFSET);
 774         mfd = __raw_readl(pllbase + PLL_DENOM_DIV_OFFSET);
 775
 776         rate = (parent_rate * div) + ((parent_rate / mfd) * mfn);
 777
 778         return rate;
 779 }
 780
 781 static int _clk_audio_video_set_rate(struct clk *clk, unsigned long rate)
 782 {
 783         unsigned int reg,  div;
 784         unsigned int mfn, mfd = 1000000;
 785         s64 temp64;
 786         unsigned int parent_rate = clk_get_rate(clk->parent);
 787         void __iomem *pllbase;
 788
 789         if ((rate < AUDIO_VIDEO_MIN_CLK_FREQ) ||
 790                 (rate > AUDIO_VIDEO_MAX_CLK_FREQ))
 791                 return -EINVAL;
 792
 793         if (clk == &pll4_audio_main_clk)
 794                 pllbase = PLL4_AUDIO_BASE_ADDR;
 795         else
 796                 pllbase = PLL5_VIDEO_BASE_ADDR;
 797
 798         div = rate / parent_rate ;
 799         temp64 = (u64) (rate - (div * parent_rate));
 800         temp64 *= mfd;
 801         do_div(temp64, parent_rate);
 802         mfn = temp64;
 803
 804         reg = __raw_readl(pllbase) & ~ANADIG_PLL_SYS_DIV_SELECT_MASK;
 805         reg |= div;
 806         __raw_writel(reg, pllbase);
 807         __raw_writel(mfn, pllbase + PLL_NUM_DIV_OFFSET);
 808         __raw_writel(mfd, pllbase + PLL_DENOM_DIV_OFFSET);
 809
 810         return 0;
 811 }
 812
 813 static unsigned long _clk_audio_video_round_rate(struct clk *clk,
 814                                                 unsigned long rate)
 815 {
 816         if (rate < AUDIO_VIDEO_MIN_CLK_FREQ)
 817                 return AUDIO_VIDEO_MIN_CLK_FREQ;
 818
 819         if (rate > AUDIO_VIDEO_MAX_CLK_FREQ)
 820                 return AUDIO_VIDEO_MAX_CLK_FREQ;
 821
 822         return rate;
 823 }
 824
 825
 826 static struct clk pll4_audio_main_clk = {
 827         __INIT_CLK_DEBUG(pll4_audio_main_clk)
 828         .parent = &osc_clk,
 829         .enable = _clk_pll_enable,
 830         .disable = _clk_pll_disable,
 831         .set_rate = _clk_audio_video_set_rate,
 832         .get_rate = _clk_audio_video_get_rate,
 833         .round_rate = _clk_audio_video_round_rate,
 834 };
 835
 836
 837 static struct clk pll5_video_main_clk = {
 838         __INIT_CLK_DEBUG(pll5_video_main_clk)
 839         .parent = &osc_clk,
 840         .enable = _clk_pll_enable,
 841         .disable = _clk_pll_disable,
 842         .set_rate = _clk_audio_video_set_rate,
 843         .get_rate = _clk_audio_video_get_rate,
 844         .round_rate = _clk_audio_video_round_rate,
 845 };
 846
 847 static struct clk pll6_MLB_main_clk = {
 848         __INIT_CLK_DEBUG(pll6_MLB_main_clk)
 849         .parent = &osc_clk,
 850         .enable = _clk_pll_enable,
 851         .disable = _clk_pll_disable,
 852 };
 853
 854 static unsigned long _clk_pll7_usb_otg_get_rate(struct clk *clk)
 855 {
 856         unsigned int div;
 857         unsigned long val;
 858
 859         div = __raw_readl(PLL7_480_USB2_BASE_ADDR)
 860                 & ANADIG_PLL_480_DIV_SELECT_MASK;
 861
 862         if (div == 1)
 863                 val = clk_get_rate(clk->parent) * 22;
 864         else
 865                 val = clk_get_rate(clk->parent) * 20;
 866         return val;
 867 }
 868
 869 static int _clk_pll7_usb_otg_set_rate(struct clk *clk, unsigned long rate)
 870 {
 871         unsigned int reg,  div;
 872
 873         if (rate == 528000000)
 874                 div = 1;
 875         else if (rate == 480000000)
 876                 div = 0;
 877         else
 878                 return -EINVAL;
 879
 880         reg = __raw_readl(PLL7_480_USB2_BASE_ADDR);
 881         reg &= ~ANADIG_PLL_480_DIV_SELECT_MASK;
 882         reg |= div;
 883         __raw_writel(reg, PLL7_480_USB2_BASE_ADDR);
 884
 885         return 0;
 886 }
 887
 888 static struct clk pll7_usb_host_main_clk = {
 889         __INIT_CLK_DEBUG(pll7_usb_host_main_clk)
 890         .parent = &osc_clk,
 891         .enable = _clk_pll_enable,
 892         .disable = _clk_pll_disable,
 893         .set_rate = _clk_pll7_usb_otg_set_rate,
 894         .get_rate = _clk_pll7_usb_otg_get_rate,
 895
 896 };
 897
 898 static struct clk pll8_enet_main_clk = {
 899         __INIT_CLK_DEBUG(pll8_enet_main_clk)
 900         .parent = &osc_clk,
 901         .enable = _clk_pll_enable,
 902         .disable = _clk_pll_disable,
 903 };
 904
 905 static unsigned long _clk_arm_get_rate(struct clk *clk)
 906 {
 907         u32 cacrr, div;
 908
 909         cacrr = __raw_readl(MXC_CCM_CACRR);
 910         div = (cacrr & MXC_CCM_CACRR_ARM_PODF_MASK) + 1;
 911         return clk_get_rate(clk->parent) / div;
 912 }
 913
 914 static int _clk_arm_set_rate(struct clk *clk, unsigned long rate)
 915 {
 916         int i;
 917         u32 div;
 918         u32 parent_rate;
 919
 920
 921         for (i = 0; i < cpu_op_nr; i++) {
 922                 if (rate == cpu_op_tbl[i].cpu_rate)
 923                         break;
 924         }
 925         if (i >= cpu_op_nr)
 926                 return -EINVAL;
 927
 928         if (cpu_op_tbl[i].pll_rate != clk_get_rate(&pll1_sys_main_clk)) {
 929                 /* Change the PLL1 rate. */
 930                 if (pll2_pfd_400M.usecount != 0)
 931                         pll1_sw_clk.set_parent(&pll1_sw_clk, &pll2_pfd_400M);
 932                 else
 933                         pll1_sw_clk.set_parent(&pll1_sw_clk, &osc_clk);
 934                 pll1_sys_main_clk.set_rate(&pll1_sys_main_clk, cpu_op_tbl[i].pll_rate);
 935                 pll1_sw_clk.set_parent(&pll1_sw_clk, &pll1_sys_main_clk);
 936         }
 937
 938         parent_rate = clk_get_rate(clk->parent);
 939         div = parent_rate / rate;
 940
 941         if (div == 0)
 942                 div = 1;
 943
 944         if ((parent_rate / div) > rate)
 945                 div++;
 946
 947         if (div > 8)
 948                 return -1;
 949
 950         __raw_writel(div - 1, MXC_CCM_CACRR);
 951
 952         return 0;
 953 }
 954
 955 static struct clk cpu_clk = {
 956         __INIT_CLK_DEBUG(cpu_clk)
 957         .parent = &pll1_sw_clk,
 958         .set_rate = _clk_arm_set_rate,
 959         .get_rate = _clk_arm_get_rate,
 960 };
 961
 962 static int _clk_periph_set_parent(struct clk *clk, struct clk *parent)
 963 {
 964         u32 reg;
 965         int mux;
 966
 967         mux = _get_mux6(parent, &pll2_528_bus_main_clk, &pll2_pfd_400M,
 968                 &pll2_pfd_352M, &pll2_200M, &pll3_sw_clk, &osc_clk);
 969
 970         if (mux <= 3) {
 971                 /* Set the pre_periph_clk multiplexer */
 972                 reg = __raw_readl(MXC_CCM_CBCMR);
 973                 reg &= ~MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK;
 974                 reg |= mux << MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET;
 975                 __raw_writel(reg, MXC_CCM_CBCMR);
 976
 977                 /* Set the periph_clk_sel multiplexer. */
 978                 reg = __raw_readl(MXC_CCM_CBCDR);
 979                 reg &= ~MXC_CCM_CBCDR_PERIPH_CLK_SEL;
 980                 __raw_writel(reg, MXC_CCM_CBCDR);
 981         } else {
 982                 reg = __raw_readl(MXC_CCM_CBCDR);
 983                 /* Set the periph_clk2_podf divider to divide by 1. */
 984                 reg &= ~MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK;
 985                 __raw_writel(reg, MXC_CCM_CBCDR);
 986
 987                 /* Set the periph_clk2_sel mux. */
 988                 reg = __raw_readl(MXC_CCM_CBCMR);
 989                 reg &= ~MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK;
 990                 reg |= ((mux - 4) << MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET);
 991                 __raw_writel(reg, MXC_CCM_CBCMR);
 992
 993                 while (__raw_readl(MXC_CCM_CDHIPR))
 994                         ;
 995
 996                 reg = __raw_readl(MXC_CCM_CBCDR);
 997                 /* Set periph_clk_sel to select periph_clk2. */
 998                 reg |= MXC_CCM_CBCDR_PERIPH_CLK_SEL;
 999                 __raw_writel(reg, MXC_CCM_CBCDR);
1000         }
1001
1002         if (!WAIT(!(__raw_readl(MXC_CCM_CDHIPR)
1003              & MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY), SPIN_DELAY))
1004                 panic("_clk_periph_set_parent failed\n");
1005
1006         return 0;
1007 }
1008
1009 static unsigned long _clk_periph_get_rate(struct clk *clk)
1010 {
1011         u32 div = 1;
1012         u32 reg;
1013         unsigned long val;
1014
1015         if ((clk->parent == &pll3_sw_clk) || (clk->parent == &osc_clk)) {
1016                 reg = __raw_readl(MXC_CCM_CBCDR)
1017                         & MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK;
1018                 div = (reg >> MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET) + 1;
1019         }
1020         val = clk_get_rate(clk->parent) / div;
1021         return val;
1022 }
1023
1024 static struct clk periph_clk = {
1025         __INIT_CLK_DEBUG(periph_clk)
1026         .parent = &pll2_528_bus_main_clk,
1027         .set_parent = _clk_periph_set_parent,
1028         .get_rate = _clk_periph_get_rate,
1029 };
1030
1031 static unsigned long _clk_axi_get_rate(struct clk *clk)
1032 {
1033         u32 div, reg;
1034         unsigned long val;
1035
1036         reg = __raw_readl(MXC_CCM_CBCDR) & MXC_CCM_CBCDR_AXI_PODF_MASK;
1037         div = (reg >> MXC_CCM_CBCDR_AXI_PODF_OFFSET);
1038
1039         val = clk_get_rate(clk->parent) / (div + 1);
1040         return val;
1041 }
1042
1043 static int _clk_axi_set_rate(struct clk *clk, unsigned long rate)
1044 {
1045         u32 reg, div;
1046         u32 parent_rate = clk_get_rate(clk->parent);
1047
1048         div = parent_rate / rate;
1049
1050         if (div == 0)
1051                 div++;
1052         if (((parent_rate / div) != rate) || (div > 8))
1053                 return -EINVAL;
1054
1055         reg = __raw_readl(MXC_CCM_CBCDR);
1056         reg &= ~MXC_CCM_CBCDR_AXI_PODF_MASK;
1057         reg |= (div - 1) << MXC_CCM_CBCDR_AXI_PODF_OFFSET;
1058         __raw_writel(reg, MXC_CCM_CBCDR);
1059
1060         if (!WAIT(!(__raw_readl(MXC_CCM_CDHIPR)
1061              & MXC_CCM_CDHIPR_AXI_PODF_BUSY), SPIN_DELAY))
1062                 panic("pll _clk_axi_a_set_rate failed\n");
1063
1064         return 0;
1065 }
1066
1067 static unsigned long _clk_axi_round_rate(struct clk *clk,
1068                                                 unsigned long rate)
1069 {
1070         u32 div;
1071         u32 parent_rate = clk_get_rate(clk->parent);
1072
1073         div = parent_rate / rate;
1074
1075         /* Make sure rate is not greater than the maximum
1076          * value for the clock.
1077          * Also prevent a div of 0.
1078          */
1079
1080         if (div > 8)
1081                 div = 8;
1082         else if (div == 0)
1083                 div++;
1084
1085         return parent_rate / div;
1086 }
1087
1088 static int _clk_axi_set_parent(struct clk *clk, struct clk *parent)
1089 {
1090         u32 reg;
1091         int mux;
1092
1093         mux = _get_mux6(parent, &periph_clk, &pll2_pfd_400M,
1094                                 &pll3_pfd_540M, NULL, NULL, NULL);
1095
1096         if (mux == 0) {
1097                 /* Set the AXI_SEL mux */
1098                 reg = __raw_readl(MXC_CCM_CBCDR) & ~MXC_CCM_CBCDR_AXI_SEL;
1099                 __raw_writel(reg, MXC_CCM_CBCDR);
1100         } else {
1101                 /* Set the AXI_ALT_SEL mux. */
1102                 reg = __raw_readl(MXC_CCM_CBCDR)
1103                         & ~MXC_CCM_CBCDR_AXI_ALT_SEL_MASK;
1104                 reg = ((mux - 1) << MXC_CCM_CBCDR_AXI_ALT_SEL_OFFSET);
1105                 __raw_writel(reg, MXC_CCM_CBCDR);
1106
1107                 /* Set the AXI_SEL mux */
1108                 reg = __raw_readl(MXC_CCM_CBCDR) & ~MXC_CCM_CBCDR_AXI_SEL;
1109                 reg |= MXC_CCM_CBCDR_AXI_SEL;
1110                 __raw_writel(reg, MXC_CCM_CBCDR);
1111         }
1112         return 0;
1113 }
1114
1115 static struct clk axi_clk = {
1116         __INIT_CLK_DEBUG(axi_clk)
1117         .parent = &periph_clk,
1118         .set_parent = _clk_axi_set_parent,
1119         .set_rate = _clk_axi_set_rate,
1120         .get_rate = _clk_axi_get_rate,
1121         .round_rate = _clk_axi_round_rate,
1122 };
1123
1124 static unsigned long _clk_ahb_get_rate(struct clk *clk)
1125 {
1126         u32 reg, div;
1127
1128         reg = __raw_readl(MXC_CCM_CBCDR);
1129         div = ((reg & MXC_CCM_CBCDR_AHB_PODF_MASK) >>
1130                MXC_CCM_CBCDR_AHB_PODF_OFFSET) + 1;
1131
1132         return clk_get_rate(clk->parent) / div;
1133 }
1134
1135 static int _clk_ahb_set_rate(struct clk *clk, unsigned long rate)
1136 {
1137         u32 reg, div;
1138         u32 parent_rate = clk_get_rate(clk->parent);
1139
1140         div = parent_rate / rate;
1141         if (div == 0)
1142                 div++;
1143         if (((parent_rate / div) != rate) || (div > 8))
1144                 return -EINVAL;
1145
1146         reg = __raw_readl(MXC_CCM_CBCDR);
1147         reg &= ~MXC_CCM_CBCDR_AHB_PODF_MASK;
1148         reg |= (div - 1) << MXC_CCM_CBCDR_AHB_PODF_OFFSET;
1149         __raw_writel(reg, MXC_CCM_CBCDR);
1150
1151         if (!WAIT(!(__raw_readl(MXC_CCM_CDHIPR) & MXC_CCM_CDHIPR_AHB_PODF_BUSY),
1152                                 SPIN_DELAY))
1153                         panic("_clk_ahb_set_rate failed\n");
1154
1155         return 0;
1156 }
1157
1158 static unsigned long _clk_ahb_round_rate(struct clk *clk,
1159                                                 unsigned long rate)
1160 {
1161         u32 div;
1162         u32 parent_rate = clk_get_rate(clk->parent);
1163
1164         div = parent_rate / rate;
1165
1166         /* Make sure rate is not greater than the maximum value for the clock.
1167          * Also prevent a div of 0.
1168          */
1169         if (div == 0)
1170                 div++;
1171
1172         if (div > 8)
1173                 div = 8;
1174
1175         return parent_rate / div;
1176 }
1177
1178 static struct clk ahb_clk = {
1179         __INIT_CLK_DEBUG(ahb_clk)
1180         .parent = &periph_clk,
1181         .get_rate = _clk_ahb_get_rate,
1182         .set_rate = _clk_ahb_set_rate,
1183         .round_rate = _clk_ahb_round_rate,
1184 };
1185
1186 static unsigned long _clk_ipg_get_rate(struct clk *clk)
1187 {
1188         u32 reg, div;
1189
1190         reg = __raw_readl(MXC_CCM_CBCDR);
1191         div = ((reg & MXC_CCM_CBCDR_IPG_PODF_MASK) >>
1192                 MXC_CCM_CBCDR_IPG_PODF_OFFSET) + 1;
1193
1194         return clk_get_rate(clk->parent) / div;
1195 }
1196
1197
1198 static struct clk ipg_clk = {
1199         __INIT_CLK_DEBUG(ipg_clk)
1200         .parent = &ahb_clk,
1201         .get_rate = _clk_ipg_get_rate,
1202 };
1203
1204 static struct clk tzasc1_clk = {
1205         __INIT_CLK_DEBUG(tzasc1_clk)
1206         .id = 0,
1207         .parent = &ipg_clk,
1208         .enable_reg = MXC_CCM_CCGR2,
1209         .enable_shift = MXC_CCM_CCGRx_CG11_OFFSET,
1210         .enable = _clk_enable,
1211         .disable = _clk_disable_inwait,
1212 };
1213
1214 static struct clk tzasc2_clk = {
1215         __INIT_CLK_DEBUG(tzasc2_clk)
1216         .id = 0,
1217         .parent = &ipg_clk,
1218         .enable_reg = MXC_CCM_CCGR2,
1219         .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET,
1220         .enable = _clk_enable,
1221         .disable = _clk_disable_inwait,
1222 };
1223
1224 static struct clk mx6fast1_clk = {
1225         __INIT_CLK_DEBUG(mx6fast1_clk)
1226         .id = 0,
1227         .parent = &ahb_clk,
1228         .enable_reg = MXC_CCM_CCGR4,
1229         .enable_shift = MXC_CCM_CCGRx_CG4_OFFSET,
1230         .enable = _clk_enable,
1231         .disable = _clk_disable_inwait,
1232 };
1233
1234 static struct clk mx6per1_clk = {
1235         __INIT_CLK_DEBUG(mx6per1_clk)
1236         .id = 0,
1237         .parent = &ahb_clk,
1238         .secondary = &mx6fast1_clk,
1239         .enable_reg = MXC_CCM_CCGR4,
1240         .enable_shift = MXC_CCM_CCGRx_CG6_OFFSET,
1241         .enable = _clk_enable,
1242         .disable = _clk_disable_inwait,
1243 };
1244
1245 static struct clk mx6per2_clk = {
1246         __INIT_CLK_DEBUG(mx6per2_clk)
1247         .id = 0,
1248         .parent = &ahb_clk,
1249         .enable_reg = MXC_CCM_CCGR4,
1250         .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
1251         .enable = _clk_enable,
1252         .disable = _clk_disable_inwait,
1253 };
1254
1255 static unsigned long _clk_mmdc_ch0_axi_get_rate(struct clk *clk)
1256 {
1257         u32 reg, div;
1258
1259         reg = __raw_readl(MXC_CCM_CBCDR);
1260         div = ((reg & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
1261                         MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET) + 1;
1262
1263         return clk_get_rate(clk->parent) / div;
1264 }
1265
1266 static int _clk_mmdc_ch0_axi_set_rate(struct clk *clk, unsigned long rate)
1267 {
1268         u32 reg, div;
1269         u32 parent_rate = clk_get_rate(clk->parent);
1270
1271         div = parent_rate / rate;
1272         if (div == 0)
1273                 div++;
1274         if (((parent_rate / div) != rate) || (div > 8))
1275                 return -EINVAL;
1276
1277         reg = __raw_readl(MXC_CCM_CBCDR);
1278         reg &= ~MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK;
1279         reg |= (div - 1) << MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
1280         __raw_writel(reg, MXC_CCM_CBCDR);
1281
1282         if (!WAIT(!(__raw_readl(MXC_CCM_CDHIPR)
1283                 & MXC_CCM_CDHIPR_MMDC_CH0_PODF_BUSY),
1284                                 SPIN_DELAY))
1285                         panic("_clk_mmdc_ch0_axi_set_rate failed\n");
1286
1287         return 0;
1288 }
1289
1290 static unsigned long _clk_mmdc_ch0_axi_round_rate(struct clk *clk,
1291                                                 unsigned long rate)
1292 {
1293         u32 div;
1294         u32 parent_rate = clk_get_rate(clk->parent);
1295
1296         div = parent_rate / rate;
1297
1298         /* Make sure rate is not greater than the maximum value for the clock.
1299          * Also prevent a div of 0.
1300          */
1301         if (div == 0)
1302                 div++;
1303
1304         if (div > 8)
1305                 div = 8;
1306
1307         return parent_rate / div;
1308 }
1309
1310 static struct clk mmdc_ch0_axi_clk[] = {
1311         {
1312         __INIT_CLK_DEBUG(mmdc_ch0_axi_clk)
1313         .id = 0,
1314         .parent = &periph_clk,
1315         .enable = _clk_enable,
1316         .disable = _clk_disable_inwait,
1317         .enable_reg = MXC_CCM_CCGR3,
1318         .enable_shift = MXC_CCM_CCGRx_CG10_OFFSET,
1319         .secondary = &mmdc_ch0_axi_clk[1],
1320         .get_rate = _clk_mmdc_ch0_axi_get_rate,
1321         .set_rate = _clk_mmdc_ch0_axi_set_rate,
1322         .round_rate = _clk_mmdc_ch0_axi_round_rate,
1323         },
1324         {
1325         __INIT_CLK_DEBUG(mmdc_ch0_ipg_clk)
1326         .id = 0,
1327         .parent = &ipg_clk,
1328         .enable = _clk_enable,
1329         .disable = _clk_disable_inwait,
1330         .enable_reg = MXC_CCM_CCGR3,
1331         .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET,
1332         .secondary = &tzasc1_clk,
1333         },
1334 };
1335
1336 static unsigned long _clk_mmdc_ch1_axi_get_rate(struct clk *clk)
1337 {
1338         u32 reg, div;
1339
1340         reg = __raw_readl(MXC_CCM_CBCDR);
1341         div = ((reg & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) >>
1342                         MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET) + 1;
1343
1344         return clk_get_rate(clk->parent) / div;
1345 }
1346
1347 static int _clk_mmdc_ch1_axi_set_rate(struct clk *clk, unsigned long rate)
1348 {
1349         u32 reg, div;
1350         u32 parent_rate = clk_get_rate(clk->parent);
1351
1352         div = parent_rate / rate;
1353         if (div == 0)
1354                 div++;
1355         if (((parent_rate / div) != rate) || (div > 8))
1356                 return -EINVAL;
1357
1358         reg = __raw_readl(MXC_CCM_CBCDR);
1359         reg &= ~MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK;
1360         reg |= (div - 1) << MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
1361         __raw_writel(reg, MXC_CCM_CBCDR);
1362
1363         if (!WAIT(!(__raw_readl(MXC_CCM_CDHIPR)
1364                 & MXC_CCM_CDHIPR_MMDC_CH1_PODF_BUSY), SPIN_DELAY))
1365                         panic("_clk_mmdc_ch1_axi_set_rate failed\n");
1366
1367         return 0;
1368 }
1369
1370 static unsigned long _clk_mmdc_ch1_axi_round_rate(struct clk *clk,
1371                                                 unsigned long rate)
1372 {
1373         u32 div;
1374         u32 parent_rate = clk_get_rate(clk->parent);
1375
1376         div = parent_rate / rate;
1377
1378         /* Make sure rate is not greater than the maximum value for the clock.
1379          * Also prevent a div of 0.
1380          */
1381         if (div == 0)
1382                 div++;
1383
1384         if (div > 8)
1385                 div = 8;
1386
1387         return parent_rate / div;
1388 }
1389
1390 static struct clk mmdc_ch1_axi_clk[] = {
1391         {
1392         __INIT_CLK_DEBUG(mmdc_ch1_axi_clk)
1393         .id = 0,
1394         .parent = &pll2_pfd_400M,
1395         .enable = _clk_enable,
1396         .disable = _clk_disable,
1397         .enable_reg = MXC_CCM_CCGR3,
1398         .enable_shift = MXC_CCM_CCGRx_CG11_OFFSET,
1399         .secondary = &mmdc_ch1_axi_clk[1],
1400         .get_rate = _clk_mmdc_ch1_axi_get_rate,
1401         .set_rate = _clk_mmdc_ch1_axi_set_rate,
1402         .round_rate = _clk_mmdc_ch1_axi_round_rate,
1403         },
1404         {
1405         .id = 1,
1406         __INIT_CLK_DEBUG(mmdc_ch1_ipg_clk)
1407         .parent = &ipg_clk,
1408         .enable = _clk_enable,
1409         .disable = _clk_disable,
1410         .enable_reg = MXC_CCM_CCGR3,
1411         .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
1412         .secondary = &tzasc2_clk,
1413         },
1414 };
1415
1416 static struct clk ocram_clk = {
1417         __INIT_CLK_DEBUG(ocram_clk)
1418         .id = 0,
1419         .parent = &ahb_clk,
1420         .enable_reg = MXC_CCM_CCGR3,
1421         .enable_shift = MXC_CCM_CCGRx_CG14_OFFSET,
1422         .enable = _clk_enable,
1423         .disable = _clk_disable_inwait,
1424 };
1425
1426 static unsigned long _clk_ipg_perclk_get_rate(struct clk *clk)
1427 {
1428         u32 reg, div;
1429
1430         reg = __raw_readl(MXC_CCM_CSCMR1);
1431         div = ((reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK) >>
1432                         MXC_CCM_CSCMR1_PERCLK_PODF_OFFSET) + 1;
1433
1434         return clk_get_rate(clk->parent) / div;
1435 }
1436
1437 static int _clk_ipg_perclk_set_rate(struct clk *clk, unsigned long rate)
1438 {
1439         u32 reg, div;
1440         u32 parent_rate = clk_get_rate(clk->parent);
1441
1442         div = parent_rate / rate;
1443         if (div == 0)
1444                 div++;
1445         if (((parent_rate / div) != rate) || (div > 64))
1446                 return -EINVAL;
1447
1448         reg = __raw_readl(MXC_CCM_CSCMR1);
1449         reg &= ~MXC_CCM_CSCMR1_PERCLK_PODF_MASK;
1450         reg |= (div - 1) << MXC_CCM_CSCMR1_PERCLK_PODF_OFFSET;
1451         __raw_writel(reg, MXC_CCM_CSCMR1);
1452
1453         return 0;
1454 }
1455
1456
1457 static unsigned long _clk_ipg_perclk_round_rate(struct clk *clk,
1458                                                 unsigned long rate)
1459 {
1460         u32 div;
1461         u32 parent_rate = clk_get_rate(clk->parent);
1462
1463         div = parent_rate / rate;
1464
1465         /* Make sure rate is not greater than the maximum value for the clock.
1466          * Also prevent a div of 0.
1467          */
1468         if (div == 0)
1469                 div++;
1470
1471         if (div > 64)
1472                 div = 64;
1473
1474         return parent_rate / div;
1475 }
1476
1477 static struct clk ipg_perclk = {
1478         __INIT_CLK_DEBUG(ipg_perclk)
1479         .parent = &ipg_clk,
1480         .get_rate = _clk_ipg_perclk_get_rate,
1481         .set_rate = _clk_ipg_perclk_set_rate,
1482         .round_rate = _clk_ipg_perclk_round_rate,
1483 };
1484
1485 static struct clk spba_clk = {
1486         __INIT_CLK_DEBUG(spba_clk)
1487         .parent = &ipg_clk,
1488         .enable_reg = MXC_CCM_CCGR5,
1489         .enable_shift = MXC_CCM_CCGRx_CG6_OFFSET,
1490         .enable = _clk_enable,
1491         .disable = _clk_disable,
1492 };
1493
1494 static struct clk sdma_clk[] = {
1495         {
1496          __INIT_CLK_DEBUG(sdma_clk)
1497          .parent = &ahb_clk,
1498          .enable_reg = MXC_CCM_CCGR5,
1499          .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET,
1500          .enable = _clk_enable,
1501          .disable = _clk_disable,
1502          .secondary = &sdma_clk[1],
1503         },
1504         {
1505          .parent = &mx6per1_clk,
1506 #ifdef CONFIG_SDMA_IRAM
1507          .secondary = &ocram_clk,
1508 #else
1509         .secondary = &mmdc_ch0_axi_clk[0],
1510 #endif
1511         },
1512 };
1513
1514 static int _clk_gpu2d_axi_set_parent(struct clk *clk, struct clk *parent)
1515 {
1516         u32 reg = __raw_readl(MXC_CCM_CBCMR) & ~MXC_CCM_CBCMR_GPU2D_AXI_CLK_SEL;
1517
1518         if (parent == &ahb_clk)
1519                 reg |= MXC_CCM_CBCMR_GPU2D_AXI_CLK_SEL;
1520
1521         __raw_writel(reg, MXC_CCM_CBCMR);
1522
1523         return 0;
1524 }
1525
1526 static struct clk gpu2d_axi_clk = {
1527         __INIT_CLK_DEBUG(gpu2d_axi_clk)
1528         .parent = &axi_clk,
1529         .secondary = &openvg_axi_clk,
1530         .set_parent = _clk_gpu2d_axi_set_parent,
1531 };
1532
1533 static int _clk_gpu3d_axi_set_parent(struct clk *clk, struct clk *parent)
1534 {
1535         u32 reg = __raw_readl(MXC_CCM_CBCMR) & ~MXC_CCM_CBCMR_GPU3D_AXI_CLK_SEL;
1536
1537         if (parent == &ahb_clk)
1538                 reg |= MXC_CCM_CBCMR_GPU3D_AXI_CLK_SEL;
1539
1540         __raw_writel(reg, MXC_CCM_CBCMR);
1541
1542         return 0;
1543 }
1544
1545 static struct clk gpu3d_axi_clk = {
1546         __INIT_CLK_DEBUG(gpu3d_axi_clk)
1547         .parent = &axi_clk,
1548         .secondary = &mmdc_ch0_axi_clk[0],
1549         .set_parent = _clk_gpu3d_axi_set_parent,
1550 };
1551
1552 static int _clk_pcie_axi_set_parent(struct clk *clk, struct clk *parent)
1553 {
1554         u32 reg = __raw_readl(MXC_CCM_CBCMR) & ~MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL;
1555
1556         if (parent == &ahb_clk)
1557                 reg |= MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL;
1558
1559         __raw_writel(reg, MXC_CCM_CBCMR);
1560
1561         return 0;
1562 }
1563
1564 static struct clk pcie_axi_clk = {
1565         __INIT_CLK_DEBUG(pcie_axi_clk)
1566         .parent = &axi_clk,
1567         .set_parent = _clk_pcie_axi_set_parent,
1568 };
1569
1570 static int _clk_vdo_axi_set_parent(struct clk *clk, struct clk *parent)
1571 {
1572         u32 reg = __raw_readl(MXC_CCM_CBCMR) & ~MXC_CCM_CBCMR_VDOAXI_CLK_SEL;
1573
1574         if (parent == &ahb_clk)
1575                 reg |= MXC_CCM_CBCMR_VDOAXI_CLK_SEL;
1576
1577         __raw_writel(reg, MXC_CCM_CBCMR);
1578
1579         return 0;
1580 }
1581
1582 static struct clk vdo_axi_clk = {
1583         __INIT_CLK_DEBUG(vdo_axi_clk)
1584         .parent = &axi_clk,
1585         .enable_reg = MXC_CCM_CCGR6,
1586         .enable_shift = MXC_CCM_CCGRx_CG6_OFFSET,
1587         .enable = _clk_enable,
1588         .disable = _clk_disable,
1589         .set_parent = _clk_vdo_axi_set_parent,
1590 };
1591
1592 static struct clk vdoa_clk = {
1593         __INIT_CLK_DEBUG(vdoa_clk)
1594         .id = 0,
1595         .parent = &axi_clk,
1596         .secondary = &mx6fast1_clk,
1597         .enable_reg = MXC_CCM_CCGR2,
1598         .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
1599         .enable = _clk_enable,
1600         .disable = _clk_disable,
1601 };
1602
1603 static struct clk gpt_clk[] = {
1604         {
1605         __INIT_CLK_DEBUG(gpt_clk)
1606          .parent = &ipg_perclk,
1607          .id = 0,
1608          .enable_reg = MXC_CCM_CCGR1,
1609          .enable_shift = MXC_CCM_CCGRx_CG10_OFFSET,
1610          .enable = _clk_enable,
1611          .disable = _clk_disable,
1612          .secondary = &gpt_clk[1],
1613          },
1614         {
1615         __INIT_CLK_DEBUG(gpt_serial_clk)
1616          .id = 0,
1617          .enable_reg = MXC_CCM_CCGR1,
1618          .enable_shift = MXC_CCM_CCGRx_CG11_OFFSET,
1619          .enable = _clk_enable,
1620          .disable = _clk_disable,
1621          },
1622 };
1623
1624 static unsigned long _clk_iim_get_rate(struct clk *clk)
1625 {
1626         return clk_get_rate(clk->parent);
1627 }
1628
1629 static struct clk iim_clk = {
1630         __INIT_CLK_DEBUG(iim_clk)
1631         .parent = &ipg_clk,
1632         .enable = _clk_enable,
1633         .enable_reg = MXC_CCM_CCGR2,
1634         .enable_shift = MXC_CCM_CCGRx_CG6_OFFSET,
1635         .disable = _clk_disable,
1636         .get_rate = _clk_iim_get_rate,
1637 };
1638
1639 static struct clk i2c_clk[] = {
1640         {
1641         __INIT_CLK_DEBUG(i2c_clk_0)
1642          .id = 0,
1643          .parent = &ipg_perclk,
1644          .enable_reg = MXC_CCM_CCGR2,
1645          .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET,
1646          .enable = _clk_enable,
1647          .disable = _clk_disable,
1648          },
1649         {
1650         __INIT_CLK_DEBUG(i2c_clk_1)
1651          .id = 1,
1652          .parent = &ipg_perclk,
1653          .enable_reg = MXC_CCM_CCGR2,
1654          .enable_shift = MXC_CCM_CCGRx_CG4_OFFSET,
1655          .enable = _clk_enable,
1656          .disable = _clk_disable,
1657          },
1658         {
1659         __INIT_CLK_DEBUG(i2c_clk_2)
1660          .id = 2,
1661          .parent = &ipg_perclk,
1662          .enable_reg = MXC_CCM_CCGR2,
1663          .enable_shift = MXC_CCM_CCGRx_CG5_OFFSET,
1664          .enable = _clk_enable,
1665          .disable = _clk_disable,
1666          },
1667 };
1668
1669 static int _clk_vpu_axi_set_parent(struct clk *clk, struct clk *parent)
1670 {
1671         int mux;
1672         u32 reg = __raw_readl(MXC_CCM_CBCMR)
1673                 & ~MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK;
1674
1675         mux = _get_mux6(parent, &axi_clk, &pll2_pfd_400M,
1676                 &pll2_pfd_352M, NULL, NULL, NULL);
1677
1678         reg |= (mux << MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET);
1679
1680         __raw_writel(reg, MXC_CCM_CBCMR);
1681
1682         return 0;
1683 }
1684
1685 static unsigned long _clk_vpu_axi_get_rate(struct clk *clk)
1686 {
1687         u32 reg, div;
1688
1689         reg = __raw_readl(MXC_CCM_CSCDR1);
1690         div = ((reg & MXC_CCM_CSCDR1_VPU_AXI_PODF_MASK) >>
1691                         MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET) + 1;
1692
1693         return clk_get_rate(clk->parent) / div;
1694 }
1695
1696 static int _clk_vpu_axi_set_rate(struct clk *clk, unsigned long rate)
1697 {
1698         u32 reg, div;
1699         u32 parent_rate = clk_get_rate(clk->parent);
1700
1701         div = parent_rate / rate;
1702         if (div == 0)
1703                 div++;
1704         if (((parent_rate / div) != rate) || (div > 8))
1705                 return -EINVAL;
1706
1707         reg = __raw_readl(MXC_CCM_CSCDR1);
1708         reg &= ~MXC_CCM_CSCDR1_VPU_AXI_PODF_MASK;
1709         reg |= (div - 1) << MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET;
1710         __raw_writel(reg, MXC_CCM_CSCDR1);
1711
1712         return 0;
1713 }
1714
1715 static unsigned long _clk_vpu_axi_round_rate(struct clk *clk,
1716                                                 unsigned long rate)
1717 {
1718         u32 div;
1719         u32 parent_rate = clk_get_rate(clk->parent);
1720
1721         div = parent_rate / rate;
1722
1723         /* Make sure rate is not greater than the maximum value for the clock.
1724          * Also prevent a div of 0.
1725          */
1726         if (div == 0)
1727                 div++;
1728
1729         if (div > 8)
1730                 div = 8;
1731
1732         return parent_rate / div;
1733 }
1734
1735 static struct clk vpu_clk[] = {
1736         {
1737         __INIT_CLK_DEBUG(vpu_clk)
1738         .parent = &axi_clk,
1739         .enable_reg = MXC_CCM_CCGR6,
1740         .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
1741         .enable = _clk_enable,
1742         .disable = _clk_disable,
1743         .set_parent = _clk_vpu_axi_set_parent,
1744         .round_rate = _clk_vpu_axi_round_rate,
1745         .set_rate = _clk_vpu_axi_set_rate,
1746         .get_rate = _clk_vpu_axi_get_rate,
1747         .secondary = &vpu_clk[1],
1748         },
1749         {
1750         .parent =  &mmdc_ch0_axi_clk[0],
1751         .secondary = &vpu_clk[2],
1752         },
1753         {
1754         .parent =  &mx6fast1_clk,
1755         .secondary = &ocram_clk,
1756         },
1757
1758 };
1759
1760 static int _clk_ipu1_set_parent(struct clk *clk, struct clk *parent)
1761 {
1762         int mux;
1763         u32 reg = __raw_readl(MXC_CCM_CSCDR3)
1764                 & ~MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_MASK;
1765
1766         mux = _get_mux6(parent, &mmdc_ch0_axi_clk[0],
1767                 &pll2_pfd_400M, &pll3_120M, &pll3_pfd_540M, NULL, NULL);
1768
1769         reg |= (mux << MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_OFFSET);
1770
1771         __raw_writel(reg, MXC_CCM_CSCDR3);
1772
1773         return 0;
1774 }
1775
1776 static unsigned long _clk_ipu1_get_rate(struct clk *clk)
1777 {
1778         u32 reg, div;
1779
1780         reg = __raw_readl(MXC_CCM_CSCDR3);
1781         div = ((reg & MXC_CCM_CSCDR3_IPU1_HSP_PODF_MASK) >>
1782                         MXC_CCM_CSCDR3_IPU1_HSP_PODF_OFFSET) + 1;
1783
1784         return clk_get_rate(clk->parent) / div;
1785 }
1786
1787 static int _clk_ipu1_set_rate(struct clk *clk, unsigned long rate)
1788 {
1789         u32 reg, div;
1790         u32 parent_rate = clk_get_rate(clk->parent);
1791
1792         div = parent_rate / rate;
1793         if (div == 0)
1794                 div++;
1795         if (((parent_rate / div) != rate) || (div > 8))
1796                 return -EINVAL;
1797
1798         reg = __raw_readl(MXC_CCM_CSCDR3);
1799         reg &= ~MXC_CCM_CSCDR3_IPU1_HSP_PODF_MASK;
1800         reg |= (div - 1) << MXC_CCM_CSCDR3_IPU1_HSP_PODF_OFFSET;
1801         __raw_writel(reg, MXC_CCM_CSCDR3);
1802
1803         return 0;
1804 }
1805
1806 static unsigned long _clk_ipu_round_rate(struct clk *clk,
1807                                                 unsigned long rate)
1808 {
1809         u32 div;
1810         u32 parent_rate = clk_get_rate(clk->parent);
1811
1812         div = parent_rate / rate;
1813
1814         /* Make sure rate is not greater than the maximum value for the clock.
1815          * Also prevent a div of 0.
1816          */
1817         if (div == 0)
1818                 div++;
1819
1820         if (div > 8)
1821                 div = 8;
1822
1823         return parent_rate / div;
1824 }
1825
1826 static struct clk ipu1_clk = {
1827         __INIT_CLK_DEBUG(ipu1_clk)
1828         .parent = &mmdc_ch0_axi_clk[0],
1829         .secondary = &mmdc_ch0_axi_clk[0],
1830         .enable_reg = MXC_CCM_CCGR3,
1831         .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET,
1832         .enable = _clk_enable,
1833         .disable = _clk_disable,
1834         .set_parent = _clk_ipu1_set_parent,
1835         .round_rate = _clk_ipu_round_rate,
1836         .set_rate = _clk_ipu1_set_rate,
1837         .get_rate = _clk_ipu1_get_rate,
1838         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
1839 };
1840
1841 static int _clk_cko1_clk0_set_parent(struct clk *clk, struct clk *parent)
1842 {
1843         u32 sel, reg;
1844
1845         if (parent == &pll3_sw_clk)
1846                 sel = 0;
1847         else if (parent == &pll2_528_bus_main_clk)
1848                 sel = 1;
1849         else if (parent == &pll1_sys_main_clk)
1850                 sel = 2;
1851         else if (parent == &pll5_video_main_clk)
1852                 sel = 3;
1853         else if (parent == &axi_clk)
1854                 sel = 5;
1855         else if (parent == &enfc_clk)
1856                 sel = 6;
1857         else if (parent == &ipu1_di_clk_root)
1858                 sel = 7;
1859         else if (parent == &ipu1_di_clk_root)
1860                 sel = 8;
1861         else if (parent == &ipu2_di_clk_root)
1862                 sel = 9;
1863         else if (parent == &ipu2_di_clk_root)
1864                 sel = 10;
1865         else if (parent == &ahb_clk)
1866                 sel = 11;
1867         else if (parent == &ipg_clk)
1868                 sel = 12;
1869         else if (parent == &ipg_perclk)
1870                 sel = 13;
1871         else if (parent == &ckil_clk)
1872                 sel = 14;
1873         else if (parent == &pll4_audio_main_clk)
1874                 sel = 15;
1875         else
1876                 return -EINVAL;
1877
1878         reg = __raw_readl(MXC_CCM_CCOSR);
1879         reg &= ~MXC_CCM_CCOSR_CKOL_SEL_MASK;
1880         reg |= sel << MXC_CCM_CCOSR_CKOL_SEL_OFFSET;
1881         __raw_writel(reg, MXC_CCM_CCOSR);
1882         return 0;
1883 }
1884
1885 static unsigned long _clk_cko1_round_rate(struct clk *clk,
1886                                                 unsigned long rate)
1887 {
1888         u32 div;
1889         u32 parent_rate = clk_get_rate(clk->parent);
1890
1891         div = parent_rate / rate;
1892
1893         /* Make sure rate is not greater than the maximum value for the clock.
1894          * Also prevent a div of 0.
1895          */
1896         if (div == 0)
1897                 div++;
1898
1899         if (div > 8)
1900                 div = 8;
1901
1902         return parent_rate / div;
1903 }
1904
1905 static int _clk_cko1_set_rate(struct clk *clk, unsigned long rate)
1906 {
1907         u32 reg, div;
1908         u32 parent_rate = clk_get_rate(clk->parent);
1909
1910         div = parent_rate / rate;
1911         if (div == 0)
1912                 div++;
1913         if (((parent_rate / div) != rate) || (div > 8))
1914                 return -EINVAL;
1915
1916         reg = __raw_readl(MXC_CCM_CCOSR);
1917         reg &= ~MXC_CCM_CCOSR_CKOL_DIV_MASK;
1918         reg |= div << MXC_CCM_CCOSR_CKOL_DIV_OFFSET;
1919         __raw_writel(reg, MXC_CCM_CCOSR);
1920
1921         return 0;
1922 }
1923
1924 static unsigned long _clk_cko1_get_rate(struct clk *clk)
1925 {
1926         u32 reg, div;
1927
1928         reg = __raw_readl(MXC_CCM_CCOSR);
1929         div = ((reg & MXC_CCM_CCOSR_CKOL_DIV_MASK) >>
1930                         MXC_CCM_CCOSR_CKOL_DIV_OFFSET) + 1;
1931
1932         return clk_get_rate(clk->parent) / div;
1933 }
1934
1935 static int cko1_clk_enable(struct clk *clk)
1936 {
1937         u32 reg;
1938         reg = __raw_readl(clk->enable_reg);
1939         reg |= clk->enable_shift;
1940         __raw_writel(reg, clk->enable_reg);
1941
1942         return 0;
1943 }
1944
1945 static struct clk cko1_clk0 = {
1946         __INIT_CLK_DEBUG(cko1_clk0)
1947         .parent = &ipg_clk,
1948         .enable_reg = MXC_CCM_CCOSR,
1949         .enable_shift = MXC_CCM_CCOSR_CKOL_EN,
1950         .enable = cko1_clk_enable,
1951         .disable = _clk_disable,
1952         .set_parent = _clk_cko1_clk0_set_parent,
1953         .round_rate = _clk_cko1_round_rate,
1954         .set_rate = _clk_cko1_set_rate,
1955         .get_rate = _clk_cko1_get_rate,
1956 };
1957
1958 static int _clk_ipu2_set_parent(struct clk *clk, struct clk *parent)
1959 {
1960         int mux;
1961         u32 reg = __raw_readl(MXC_CCM_CSCDR3)
1962                 & ~MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_MASK;
1963
1964         mux = _get_mux6(parent, &mmdc_ch0_axi_clk[0],
1965                 &pll2_pfd_400M, &pll3_120M, &pll3_pfd_540M, NULL, NULL);
1966
1967         reg |= (mux << MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_OFFSET);
1968
1969         __raw_writel(reg, MXC_CCM_CSCDR3);
1970
1971         return 0;
1972 }
1973
1974 static unsigned long _clk_ipu2_get_rate(struct clk *clk)
1975 {
1976         u32 reg, div;
1977
1978         reg = __raw_readl(MXC_CCM_CSCDR3);
1979         div = ((reg & MXC_CCM_CSCDR3_IPU2_HSP_PODF_MASK) >>
1980                         MXC_CCM_CSCDR3_IPU2_HSP_PODF_OFFSET) + 1;
1981
1982         return clk_get_rate(clk->parent) / div;
1983 }
1984
1985 static int _clk_ipu2_set_rate(struct clk *clk, unsigned long rate)
1986 {
1987         u32 reg, div;
1988         u32 parent_rate = clk_get_rate(clk->parent);
1989
1990         div = parent_rate / rate;
1991         if (div == 0)
1992                 div++;
1993         if (((parent_rate / div) != rate) || (div > 8))
1994                 return -EINVAL;
1995
1996         reg = __raw_readl(MXC_CCM_CSCDR3);
1997         reg &= ~MXC_CCM_CSCDR3_IPU2_HSP_PODF_MASK;
1998         reg |= (div - 1) << MXC_CCM_CSCDR3_IPU2_HSP_PODF_OFFSET;
1999         __raw_writel(reg, MXC_CCM_CSCDR3);
2000
2001         return 0;
2002 }
2003
2004 static struct clk ipu2_clk = {
2005         __INIT_CLK_DEBUG(ipu2_clk)
2006         .parent = &mmdc_ch0_axi_clk[0],
2007         .secondary = &mmdc_ch0_axi_clk[0],
2008         .enable_reg = MXC_CCM_CCGR3,
2009         .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET,
2010         .enable = _clk_enable,
2011         .disable = _clk_disable,
2012         .set_parent = _clk_ipu2_set_parent,
2013         .round_rate = _clk_ipu_round_rate,
2014         .set_rate = _clk_ipu2_set_rate,
2015         .get_rate = _clk_ipu2_get_rate,
2016         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
2017 };
2018
2019 static struct clk usdhc_dep_clk = {
2020         .parent = &mmdc_ch0_axi_clk[0],
2021         .secondary = &mx6per1_clk,
2022         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
2023         };
2024
2025 static unsigned long _clk_usdhc_round_rate(struct clk *clk,
2026                                                 unsigned long rate)
2027 {
2028         u32 div;
2029         u32 parent_rate = clk_get_rate(clk->parent);
2030
2031         div = parent_rate / rate;
2032
2033         /* Make sure rate is not greater than the maximum value for the clock.
2034          * Also prevent a div of 0.
2035          */
2036         if (div == 0)
2037                 div++;
2038
2039         if (div > 8)
2040                 div = 8;
2041
2042         return parent_rate / div;
2043 }
2044
2045 static int _clk_usdhc1_set_parent(struct clk *clk, struct clk *parent)
2046 {
2047         u32 reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_USDHC1_CLK_SEL;
2048
2049         if (parent == &pll2_pfd_352M)
2050                 reg |= (MXC_CCM_CSCMR1_USDHC1_CLK_SEL);
2051
2052         __raw_writel(reg, MXC_CCM_CSCMR1);
2053
2054         return 0;
2055 }
2056
2057 static unsigned long _clk_usdhc1_get_rate(struct clk *clk)
2058 {
2059         u32 reg, div;
2060
2061         reg = __raw_readl(MXC_CCM_CSCDR1);
2062         div = ((reg & MXC_CCM_CSCDR1_USDHC1_PODF_MASK) >>
2063                         MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET) + 1;
2064
2065         return clk_get_rate(clk->parent) / div;
2066 }
2067
2068 static int _clk_usdhc1_set_rate(struct clk *clk, unsigned long rate)
2069 {
2070         u32 reg, div;
2071         u32 parent_rate = clk_get_rate(clk->parent);
2072
2073         div = parent_rate / rate;
2074         if (div == 0)
2075                 div++;
2076         if (((parent_rate / div) != rate) || (div > 8))
2077                 return -EINVAL;
2078
2079         reg = __raw_readl(MXC_CCM_CSCDR1);
2080         reg &= ~MXC_CCM_CSCDR1_USDHC1_PODF_MASK;
2081         reg |= (div - 1) << MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET;
2082         __raw_writel(reg, MXC_CCM_CSCDR1);
2083
2084         return 0;
2085 }
2086
2087 static struct clk usdhc1_clk = {
2088         __INIT_CLK_DEBUG(usdhc1_clk)
2089         .id = 0,
2090         .parent = &pll2_pfd_400M,
2091         .secondary = &usdhc_dep_clk,
2092         .enable_reg = MXC_CCM_CCGR6,
2093         .enable_shift = MXC_CCM_CCGRx_CG1_OFFSET,
2094         .enable = _clk_enable,
2095         .disable = _clk_disable,
2096         .set_parent = _clk_usdhc1_set_parent,
2097         .round_rate = _clk_usdhc_round_rate,
2098         .set_rate = _clk_usdhc1_set_rate,
2099         .get_rate = _clk_usdhc1_get_rate,
2100         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
2101 };
2102
2103 static int _clk_usdhc2_set_parent(struct clk *clk, struct clk *parent)
2104 {
2105         u32 reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_USDHC2_CLK_SEL;
2106
2107         if (parent == &pll2_pfd_352M)
2108                 reg |= (MXC_CCM_CSCMR1_USDHC2_CLK_SEL);
2109
2110         __raw_writel(reg, MXC_CCM_CSCMR1);
2111
2112         return 0;
2113 }
2114
2115 static unsigned long _clk_usdhc2_get_rate(struct clk *clk)
2116 {
2117         u32 reg, div;
2118
2119         reg = __raw_readl(MXC_CCM_CSCDR1);
2120         div = ((reg & MXC_CCM_CSCDR1_USDHC2_PODF_MASK) >>
2121                         MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET) + 1;
2122
2123         return clk_get_rate(clk->parent) / div;
2124 }
2125
2126 static int _clk_usdhc2_set_rate(struct clk *clk, unsigned long rate)
2127 {
2128         u32 reg, div;
2129         u32 parent_rate = clk_get_rate(clk->parent);
2130
2131         div = parent_rate / rate;
2132         if (div == 0)
2133                 div++;
2134         if (((parent_rate / div) != rate) || (div > 8))
2135                 return -EINVAL;
2136
2137         reg = __raw_readl(MXC_CCM_CSCDR1);
2138         reg &= ~MXC_CCM_CSCDR1_USDHC2_PODF_MASK;
2139         reg |= (div - 1) << MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET;
2140         __raw_writel(reg, MXC_CCM_CSCDR1);
2141
2142         return 0;
2143 }
2144
2145 static struct clk usdhc2_clk = {
2146         __INIT_CLK_DEBUG(usdhc2_clk)
2147         .id = 1,
2148         .parent = &pll2_pfd_400M,
2149         .secondary = &usdhc_dep_clk,
2150         .enable_reg = MXC_CCM_CCGR6,
2151         .enable_shift = MXC_CCM_CCGRx_CG2_OFFSET,
2152         .enable = _clk_enable,
2153         .disable = _clk_disable,
2154         .set_parent = _clk_usdhc2_set_parent,
2155         .round_rate = _clk_usdhc_round_rate,
2156         .set_rate = _clk_usdhc2_set_rate,
2157         .get_rate = _clk_usdhc2_get_rate,
2158         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
2159 };
2160
2161 static int _clk_usdhc3_set_parent(struct clk *clk, struct clk *parent)
2162 {
2163         u32 reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_USDHC3_CLK_SEL;
2164
2165         if (parent == &pll2_pfd_352M)
2166                 reg |= (MXC_CCM_CSCMR1_USDHC3_CLK_SEL);
2167
2168         __raw_writel(reg, MXC_CCM_CSCMR1);
2169
2170         return 0;
2171 }
2172
2173 static unsigned long _clk_usdhc3_get_rate(struct clk *clk)
2174 {
2175         u32 reg, div;
2176
2177         reg = __raw_readl(MXC_CCM_CSCDR1);
2178         div = ((reg & MXC_CCM_CSCDR1_USDHC3_PODF_MASK) >>
2179                         MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET) + 1;
2180
2181         return clk_get_rate(clk->parent) / div;
2182 }
2183
2184 static int _clk_usdhc3_set_rate(struct clk *clk, unsigned long rate)
2185 {
2186         u32 reg, div;
2187         u32 parent_rate = clk_get_rate(clk->parent);
2188
2189         div = parent_rate / rate;
2190         if (div == 0)
2191                 div++;
2192         if (((parent_rate / div) != rate) || (div > 8))
2193                 return -EINVAL;
2194
2195         reg = __raw_readl(MXC_CCM_CSCDR1);
2196         reg &= ~MXC_CCM_CSCDR1_USDHC3_PODF_MASK;
2197         reg |= (div - 1) << MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET;
2198         __raw_writel(reg, MXC_CCM_CSCDR1);
2199
2200         return 0;
2201 }
2202
2203
2204 static struct clk usdhc3_clk = {
2205         __INIT_CLK_DEBUG(usdhc3_clk)
2206         .id = 2,
2207         .parent = &pll2_pfd_400M,
2208         .secondary = &usdhc_dep_clk,
2209         .enable_reg = MXC_CCM_CCGR6,
2210         .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET,
2211         .enable = _clk_enable,
2212         .disable = _clk_disable,
2213         .set_parent = _clk_usdhc3_set_parent,
2214         .round_rate = _clk_usdhc_round_rate,
2215         .set_rate = _clk_usdhc3_set_rate,
2216         .get_rate = _clk_usdhc3_get_rate,
2217         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
2218 };
2219
2220 static int _clk_usdhc4_set_parent(struct clk *clk, struct clk *parent)
2221 {
2222         u32 reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_USDHC4_CLK_SEL;
2223
2224         if (parent == &pll2_pfd_352M)
2225                 reg |= (MXC_CCM_CSCMR1_USDHC4_CLK_SEL);
2226
2227         __raw_writel(reg, MXC_CCM_CSCMR1);
2228
2229         return 0;
2230 }
2231
2232 static unsigned long _clk_usdhc4_get_rate(struct clk *clk)
2233 {
2234         u32 reg, div;
2235
2236         reg = __raw_readl(MXC_CCM_CSCDR1);
2237         div = ((reg & MXC_CCM_CSCDR1_USDHC4_PODF_MASK) >>
2238                         MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET) + 1;
2239
2240         return clk_get_rate(clk->parent) / div;
2241 }
2242
2243 static int _clk_usdhc4_set_rate(struct clk *clk, unsigned long rate)
2244 {
2245         u32 reg, div;
2246         u32 parent_rate = clk_get_rate(clk->parent);
2247
2248         div = parent_rate / rate;
2249         if (div == 0)
2250                 div++;
2251         if (((parent_rate / div) != rate) || (div > 8))
2252                 return -EINVAL;
2253
2254         reg = __raw_readl(MXC_CCM_CSCDR1);
2255         reg &= ~MXC_CCM_CSCDR1_USDHC4_PODF_MASK;
2256         reg |= (div - 1) << MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET;
2257         __raw_writel(reg, MXC_CCM_CSCDR1);
2258
2259         return 0;
2260 }
2261
2262
2263 static struct clk usdhc4_clk = {
2264         __INIT_CLK_DEBUG(usdhc4_clk)
2265         .id = 3,
2266         .parent = &pll2_pfd_400M,
2267         .secondary = &usdhc_dep_clk,
2268         .enable_reg = MXC_CCM_CCGR6,
2269         .enable_shift = MXC_CCM_CCGRx_CG4_OFFSET,
2270         .enable = _clk_enable,
2271         .disable = _clk_disable,
2272         .set_parent = _clk_usdhc4_set_parent,
2273         .round_rate = _clk_usdhc_round_rate,
2274         .set_rate = _clk_usdhc4_set_rate,
2275         .get_rate = _clk_usdhc4_get_rate,
2276         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
2277 };
2278
2279 static unsigned long _clk_ssi_round_rate(struct clk *clk,
2280                                                 unsigned long rate)
2281 {
2282         u32 pre, post;
2283         u32 parent_rate = clk_get_rate(clk->parent);
2284         u32 div = parent_rate / rate;
2285
2286         if (parent_rate % rate)
2287                 div++;
2288
2289         __calc_pre_post_dividers(1 << 6, div, &pre, &post);
2290
2291         return parent_rate / (pre * post);
2292 }
2293
2294 static unsigned long _clk_ssi1_get_rate(struct clk *clk)
2295 {
2296         u32 reg, prediv, podf;
2297
2298         reg = __raw_readl(MXC_CCM_CS1CDR);
2299
2300         prediv = ((reg & MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK)
2301                 >> MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET) + 1;
2302         podf = ((reg & MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK)
2303                 >> MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET) + 1;
2304
2305         return clk_get_rate(clk->parent) / (prediv * podf);
2306 }
2307
2308 static int _clk_ssi1_set_rate(struct clk *clk, unsigned long rate)
2309 {
2310         u32 reg, div, pre, post;
2311         u32 parent_rate = clk_get_rate(clk->parent);
2312
2313         div = parent_rate / rate;
2314         if (div == 0)
2315                 div++;
2316         if (((parent_rate / div) != rate) || div > 512)
2317                 return -EINVAL;
2318
2319         __calc_pre_post_dividers(1 << 6, div, &pre, &post);
2320
2321         reg = __raw_readl(MXC_CCM_CS1CDR);
2322         reg &= ~(MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK |
2323                  MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK);
2324         reg |= (post - 1) << MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET;
2325         reg |= (pre - 1) << MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET;
2326
2327         __raw_writel(reg, MXC_CCM_CS1CDR);
2328
2329         return 0;
2330 }
2331
2332
2333 static int _clk_ssi1_set_parent(struct clk *clk, struct clk *parent)
2334 {
2335         u32 reg, mux;
2336
2337         reg = __raw_readl(MXC_CCM_CSCMR1)
2338                 & ~MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK;
2339
2340         mux = _get_mux6(parent, &pll3_pfd_508M, &pll3_pfd_454M,
2341                         &pll4_audio_main_clk, NULL, NULL, NULL);
2342         reg |= (mux << MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET);
2343
2344         __raw_writel(reg, MXC_CCM_CSCMR1);
2345
2346         return 0;
2347 }
2348
2349 static struct clk ssi1_clk = {
2350         __INIT_CLK_DEBUG(ssi1_clk)
2351         .parent = &pll3_pfd_508M,
2352         .enable_reg = MXC_CCM_CCGR5,
2353         .enable_shift = MXC_CCM_CCGRx_CG9_OFFSET,
2354         .enable = _clk_enable,
2355         .disable = _clk_disable,
2356         .set_parent = _clk_ssi1_set_parent,
2357         .set_rate = _clk_ssi1_set_rate,
2358         .round_rate = _clk_ssi_round_rate,
2359         .get_rate = _clk_ssi1_get_rate,
2360 #ifdef CONFIG_SND_MXC_SOC_IRAM
2361          .secondary = &ocram_clk,
2362 #else
2363          .secondary = &mmdc_ch0_axi_clk[0],
2364 #endif
2365 };
2366
2367 static unsigned long _clk_ssi2_get_rate(struct clk *clk)
2368 {
2369         u32 reg, prediv, podf;
2370
2371         reg = __raw_readl(MXC_CCM_CS2CDR);
2372
2373         prediv = ((reg & MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK)
2374                 >> MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET) + 1;
2375         podf = ((reg & MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK)
2376                 >> MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET) + 1;
2377
2378         return clk_get_rate(clk->parent) / (prediv * podf);
2379 }
2380
2381 static int _clk_ssi2_set_rate(struct clk *clk, unsigned long rate)
2382 {
2383         u32 reg, div, pre, post;
2384         u32 parent_rate = clk_get_rate(clk->parent);
2385
2386         div = parent_rate / rate;
2387         if (div == 0)
2388                 div++;
2389         if (((parent_rate / div) != rate) || div > 512)
2390                 return -EINVAL;
2391
2392         __calc_pre_post_dividers(1 << 6, div, &pre, &post);
2393
2394         reg = __raw_readl(MXC_CCM_CS2CDR);
2395         reg &= ~(MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK |
2396                  MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK);
2397         reg |= (post - 1) << MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET;
2398         reg |= (pre - 1) << MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET;
2399
2400         __raw_writel(reg, MXC_CCM_CS2CDR);
2401
2402         return 0;
2403 }
2404
2405
2406 static int _clk_ssi2_set_parent(struct clk *clk, struct clk *parent)
2407 {
2408         u32 reg, mux;
2409
2410         reg = __raw_readl(MXC_CCM_CSCMR1)
2411                 & ~MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK;
2412
2413         mux = _get_mux6(parent, &pll3_pfd_508M, &pll3_pfd_454M,
2414                         &pll4_audio_main_clk, NULL, NULL, NULL);
2415         reg |= (mux << MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET);
2416
2417         __raw_writel(reg, MXC_CCM_CSCMR1);
2418
2419         return 0;
2420 }
2421
2422 static struct clk ssi2_clk = {
2423         __INIT_CLK_DEBUG(ssi2_clk)
2424         .parent = &pll3_pfd_508M,
2425         .enable_reg = MXC_CCM_CCGR5,
2426         .enable_shift = MXC_CCM_CCGRx_CG10_OFFSET,
2427         .enable = _clk_enable,
2428         .disable = _clk_disable,
2429         .set_parent = _clk_ssi2_set_parent,
2430         .set_rate = _clk_ssi2_set_rate,
2431         .round_rate = _clk_ssi_round_rate,
2432         .get_rate = _clk_ssi2_get_rate,
2433 #ifdef CONFIG_SND_MXC_SOC_IRAM
2434          .secondary = &ocram_clk,
2435 #else
2436          .secondary = &mmdc_ch0_axi_clk[0],
2437 #endif
2438 };
2439
2440 static unsigned long _clk_ssi3_get_rate(struct clk *clk)
2441 {
2442         u32 reg, prediv, podf;
2443
2444         reg = __raw_readl(MXC_CCM_CS1CDR);
2445
2446         prediv = ((reg & MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK)
2447                 >> MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET) + 1;
2448         podf = ((reg & MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK)
2449                 >> MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET) + 1;
2450
2451         return clk_get_rate(clk->parent) / (prediv * podf);
2452 }
2453
2454 static int _clk_ssi3_set_rate(struct clk *clk, unsigned long rate)
2455 {
2456         u32 reg, div, pre, post;
2457         u32 parent_rate = clk_get_rate(clk->parent);
2458
2459         div = parent_rate / rate;
2460         if (div == 0)
2461                 div++;
2462         if (((parent_rate / div) != rate) || div > 512)
2463                 return -EINVAL;
2464
2465         __calc_pre_post_dividers(1 << 6, div, &pre, &post);
2466
2467         reg = __raw_readl(MXC_CCM_CS1CDR);
2468         reg &= ~(MXC_CCM_CS1CDR_SSI3_CLK_PODF_MASK|
2469                  MXC_CCM_CS1CDR_SSI3_CLK_PRED_MASK);
2470         reg |= (post - 1) << MXC_CCM_CS1CDR_SSI3_CLK_PODF_OFFSET;
2471         reg |= (pre - 1) << MXC_CCM_CS1CDR_SSI3_CLK_PRED_OFFSET;
2472
2473         __raw_writel(reg, MXC_CCM_CS1CDR);
2474
2475         return 0;
2476 }
2477
2478
2479 static int _clk_ssi3_set_parent(struct clk *clk, struct clk *parent)
2480 {
2481         u32 reg, mux;
2482
2483         reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_SSI3_CLK_SEL_MASK;
2484
2485         mux = _get_mux6(parent, &pll3_pfd_508M, &pll3_pfd_454M,
2486                                 &pll4_audio_main_clk, NULL, NULL, NULL);
2487         reg |= (mux << MXC_CCM_CSCMR1_SSI3_CLK_SEL_OFFSET);
2488
2489         __raw_writel(reg, MXC_CCM_CSCMR1);
2490
2491         return 0;
2492 }
2493
2494 static struct clk ssi3_clk = {
2495         __INIT_CLK_DEBUG(ssi3_clk)
2496         .parent = &pll3_pfd_508M,
2497         .enable_reg = MXC_CCM_CCGR5,
2498         .enable_shift = MXC_CCM_CCGRx_CG11_OFFSET,
2499         .enable = _clk_enable,
2500         .disable = _clk_disable,
2501         .set_parent = _clk_ssi3_set_parent,
2502         .set_rate = _clk_ssi3_set_rate,
2503         .round_rate = _clk_ssi_round_rate,
2504         .get_rate = _clk_ssi3_get_rate,
2505 #ifdef CONFIG_SND_MXC_SOC_IRAM
2506          .secondary = &ocram_clk,
2507 #else
2508          .secondary = &mmdc_ch0_axi_clk[0],
2509 #endif
2510 };
2511
2512 static unsigned long _clk_ldb_di_round_rate(struct clk *clk,
2513                                                 unsigned long rate)
2514 {
2515         u32 parent_rate = clk_get_rate(clk->parent);
2516
2517         if (rate * 7 <= parent_rate + parent_rate/20)
2518                 return parent_rate / 7;
2519         else
2520                 return 2 * parent_rate / 7;
2521 }
2522
2523 static unsigned long _clk_ldb_di0_get_rate(struct clk *clk)
2524 {
2525         u32 div;
2526
2527         div = __raw_readl(MXC_CCM_CSCMR2) &
2528                 MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
2529
2530         if (div)
2531                 return clk_get_rate(clk->parent) / 7;
2532
2533         return (2 * clk_get_rate(clk->parent)) / 7;
2534 }
2535
2536 static int _clk_ldb_di0_set_rate(struct clk *clk, unsigned long rate)
2537 {
2538         u32 reg, div = 0;
2539         u32 parent_rate = clk_get_rate(clk->parent);
2540
2541         if (rate * 7 <= parent_rate + parent_rate/20) {
2542                 div = 7;
2543                 rate = parent_rate / 7;
2544         } else
2545                 rate = 2 * parent_rate / 7;
2546
2547         reg = __raw_readl(MXC_CCM_CSCMR2);
2548         if (div == 7)
2549                 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
2550         else
2551                 reg &= ~MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
2552
2553         __raw_writel(reg, MXC_CCM_CSCMR2);
2554
2555         return 0;
2556 }
2557
2558 static int _clk_ldb_di0_set_parent(struct clk *clk, struct clk *parent)
2559 {
2560         u32 reg, mux;
2561
2562         reg = __raw_readl(MXC_CCM_CS2CDR)
2563                 & ~MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK;
2564
2565         mux = _get_mux6(parent, &pll5_video_main_clk,
2566                 &pll2_pfd_352M, &pll2_pfd_400M, &pll3_pfd_540M,
2567                 &pll3_usb_otg_main_clk, NULL);
2568         reg |= (mux << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET);
2569
2570         __raw_writel(reg, MXC_CCM_CS2CDR);
2571
2572         return 0;
2573 }
2574
2575 static struct clk ldb_di0_clk = {
2576          __INIT_CLK_DEBUG(ldb_di0_clk)
2577         .id = 0,
2578         .parent = &pll3_pfd_540M,
2579         .enable_reg = MXC_CCM_CCGR3,
2580         .enable_shift = MXC_CCM_CCGRx_CG6_OFFSET,
2581         .enable = _clk_enable,
2582         .disable = _clk_disable,
2583         .set_parent = _clk_ldb_di0_set_parent,
2584         .set_rate = _clk_ldb_di0_set_rate,
2585         .round_rate = _clk_ldb_di_round_rate,
2586         .get_rate = _clk_ldb_di0_get_rate,
2587         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
2588 };
2589
2590 static unsigned long _clk_ldb_di1_get_rate(struct clk *clk)
2591 {
2592         u32 div;
2593
2594         div = __raw_readl(MXC_CCM_CSCMR2) &
2595                 MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
2596
2597         if (div)
2598                 return clk_get_rate(clk->parent) / 7;
2599
2600         return (2 * clk_get_rate(clk->parent)) / 7;
2601 }
2602
2603 static int _clk_ldb_di1_set_rate(struct clk *clk, unsigned long rate)
2604 {
2605         u32 reg, div = 0;
2606         u32 parent_rate = clk_get_rate(clk->parent);
2607
2608         if (rate * 7 <= parent_rate + parent_rate/20) {
2609                 div = 7;
2610                 rate = parent_rate / 7;
2611         } else
2612                 rate = 2 * parent_rate / 7;
2613
2614         reg = __raw_readl(MXC_CCM_CSCMR2);
2615         if (div == 7)
2616                 reg |= MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
2617         else
2618                 reg &= ~MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
2619
2620         __raw_writel(reg, MXC_CCM_CSCMR2);
2621
2622         return 0;
2623 }
2624
2625 static int _clk_ldb_di1_set_parent(struct clk *clk, struct clk *parent)
2626 {
2627         u32 reg, mux;
2628
2629         reg = __raw_readl(MXC_CCM_CS2CDR)
2630                 & ~MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK;
2631
2632         mux = _get_mux6(parent, &pll5_video_main_clk,
2633                 &pll2_pfd_352M, &pll2_pfd_400M, &pll3_pfd_540M,
2634                 &pll3_usb_otg_main_clk, NULL);
2635         reg |= (mux << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
2636
2637         __raw_writel(reg, MXC_CCM_CS2CDR);
2638
2639         return 0;
2640 }
2641
2642 static struct clk ldb_di1_clk = {
2643          __INIT_CLK_DEBUG(ldb_di1_clk)
2644         .id = 0,
2645         .parent = &pll3_pfd_540M,
2646         .enable_reg = MXC_CCM_CCGR3,
2647         .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
2648         .enable = _clk_enable,
2649         .disable = _clk_disable,
2650         .set_parent = _clk_ldb_di1_set_parent,
2651         .set_rate = _clk_ldb_di1_set_rate,
2652         .round_rate = _clk_ldb_di_round_rate,
2653         .get_rate = _clk_ldb_di1_get_rate,
2654         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
2655 };
2656
2657
2658 static unsigned long _clk_ipu_di_round_rate(struct clk *clk,
2659                                                 unsigned long rate)
2660 {
2661         u32 div;
2662         u32 parent_rate = clk_get_rate(clk->parent);
2663
2664         if ((clk->parent == &ldb_di0_clk) ||
2665                 (clk->parent == &ldb_di1_clk))
2666                 return parent_rate;
2667
2668         div = parent_rate / rate;
2669
2670         /* Make sure rate is not greater than the maximum value for the clock.
2671          * Also prevent a div of 0.
2672          */
2673         if (div == 0)
2674                 div++;
2675
2676         if (div > 8)
2677                 div = 8;
2678
2679         return parent_rate / div;
2680 }
2681
2682 static unsigned long _clk_ipu1_di0_get_rate(struct clk *clk)
2683 {
2684         u32 reg, div;
2685
2686         if ((clk->parent == &ldb_di0_clk) ||
2687                 (clk->parent == &ldb_di1_clk))
2688                 return clk_get_rate(clk->parent);
2689
2690         reg = __raw_readl(MXC_CCM_CHSCCDR);
2691
2692         div = ((reg & MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK) >>
2693                          MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET) + 1;
2694
2695         return clk_get_rate(clk->parent) / div;
2696 }
2697
2698 static int _clk_ipu1_di0_set_rate(struct clk *clk, unsigned long rate)
2699 {
2700         u32 reg, div;
2701         u32 parent_rate = clk_get_rate(clk->parent);
2702
2703         if ((clk->parent == &ldb_di0_clk) ||
2704                 (clk->parent == &ldb_di1_clk)) {
2705                 if (parent_rate == rate)
2706                         return 0;
2707                 else
2708                         return -EINVAL;
2709         }
2710
2711         div = parent_rate / rate;
2712         if (div == 0)
2713                 div++;
2714         if (((parent_rate / div) != rate) || (div > 8))
2715                 return -EINVAL;
2716
2717         reg = __raw_readl(MXC_CCM_CHSCCDR);
2718         reg &= ~MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK;
2719         reg |= (div - 1) << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET;
2720         __raw_writel(reg, MXC_CCM_CHSCCDR);
2721
2722         return 0;
2723 }
2724
2725
2726 static int _clk_ipu1_di0_set_parent(struct clk *clk, struct clk *parent)
2727 {
2728         u32 reg, mux;
2729
2730         if (parent == &ldb_di0_clk)
2731                 mux = 0x3;
2732         else if (parent == &ldb_di1_clk)
2733                 mux = 0x4;
2734         else {
2735                 reg = __raw_readl(MXC_CCM_CHSCCDR)
2736                         & ~MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK;
2737
2738                 mux = _get_mux6(parent, &mmdc_ch0_axi_clk[0],
2739                                 &pll3_usb_otg_main_clk, &pll5_video_main_clk,
2740                                 &pll2_pfd_352M, &pll2_pfd_400M, &pll3_pfd_540M);
2741                 reg |= (mux << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
2742
2743                 __raw_writel(reg, MXC_CCM_CHSCCDR);
2744
2745                 /* Derive clock from divided pre-muxed ipu1_di0 clock.*/
2746                 mux = 0;
2747         }
2748
2749         reg = __raw_readl(MXC_CCM_CHSCCDR)
2750                 & ~MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK;
2751         __raw_writel(reg | (mux << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET),
2752                 MXC_CCM_CHSCCDR);
2753
2754         return 0;
2755 }
2756
2757 static unsigned long _clk_ipu1_di1_get_rate(struct clk *clk)
2758 {
2759         u32 reg, div;
2760
2761         if ((clk->parent == &ldb_di0_clk) ||
2762                 (clk->parent == &ldb_di1_clk))
2763                 return clk_get_rate(clk->parent);
2764
2765         reg = __raw_readl(MXC_CCM_CHSCCDR);
2766
2767         div = ((reg & MXC_CCM_CHSCCDR_IPU1_DI1_PODF_MASK)
2768                         >> MXC_CCM_CHSCCDR_IPU1_DI1_PODF_OFFSET) + 1;
2769
2770         return clk_get_rate(clk->parent) / div;
2771 }
2772
2773 static int _clk_ipu1_di1_set_rate(struct clk *clk, unsigned long rate)
2774 {
2775         u32 reg, div;
2776         u32 parent_rate = clk_get_rate(clk->parent);
2777
2778         if ((clk->parent == &ldb_di0_clk) ||
2779                 (clk->parent == &ldb_di1_clk)) {
2780                 if (parent_rate == rate)
2781                         return 0;
2782                 else
2783                         return -EINVAL;
2784         }
2785
2786         div = parent_rate / rate;
2787         if (div == 0)
2788                 div++;
2789         if (((parent_rate / div) != rate) || (div > 8))
2790                 return -EINVAL;
2791
2792         reg = __raw_readl(MXC_CCM_CHSCCDR);
2793         reg &= ~MXC_CCM_CHSCCDR_IPU1_DI1_PODF_MASK;
2794         reg |= (div - 1) << MXC_CCM_CHSCCDR_IPU1_DI1_PODF_OFFSET;
2795         __raw_writel(reg, MXC_CCM_CHSCCDR);
2796
2797         return 0;
2798 }
2799
2800
2801 static int _clk_ipu1_di1_set_parent(struct clk *clk, struct clk *parent)
2802 {
2803         u32 reg, mux;
2804
2805         if (parent == &ldb_di0_clk)
2806                 mux = 0x3;
2807         else if (parent == &ldb_di1_clk)
2808                 mux = 0x4;
2809         else {
2810                 reg = __raw_readl(MXC_CCM_CHSCCDR)
2811                         & ~MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_MASK;
2812
2813                 mux = _get_mux6(parent, &mmdc_ch0_axi_clk[0],
2814                                 &pll3_usb_otg_main_clk, &pll5_video_main_clk,
2815                                 &pll2_pfd_352M, &pll2_pfd_400M, &pll3_pfd_540M);
2816                 reg |= (mux << MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_OFFSET);
2817
2818                 __raw_writel(reg, MXC_CCM_CHSCCDR);
2819
2820                 /* Derive clock from divided pre-muxed ipu1_di0 clock.*/
2821                 mux = 0;
2822         }
2823         reg = __raw_readl(MXC_CCM_CHSCCDR)
2824                 & ~MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_MASK;
2825         __raw_writel(reg | (mux << MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET),
2826                 MXC_CCM_CHSCCDR);
2827
2828         return 0;
2829 }
2830
2831 static struct clk ipu1_di_clk[] = {
2832         {
2833          __INIT_CLK_DEBUG(ipu1_di_clk_0)
2834         .id = 0,
2835         .parent = &pll5_video_main_clk,
2836         .enable_reg = MXC_CCM_CCGR3,
2837         .enable_shift = MXC_CCM_CCGRx_CG1_OFFSET,
2838         .enable = _clk_enable,
2839         .disable = _clk_disable,
2840         .set_parent = _clk_ipu1_di0_set_parent,
2841         .set_rate = _clk_ipu1_di0_set_rate,
2842         .round_rate = _clk_ipu_di_round_rate,
2843         .get_rate = _clk_ipu1_di0_get_rate,
2844         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
2845         },
2846         {
2847          __INIT_CLK_DEBUG(ipu1_di_clk_1)
2848         .id = 1,
2849         .parent = &pll5_video_main_clk,
2850         .enable_reg = MXC_CCM_CCGR3,
2851         .enable_shift = MXC_CCM_CCGRx_CG2_OFFSET,
2852         .enable = _clk_enable,
2853         .disable = _clk_disable,
2854         .set_parent = _clk_ipu1_di1_set_parent,
2855         .set_rate = _clk_ipu1_di1_set_rate,
2856         .round_rate = _clk_ipu_di_round_rate,
2857         .get_rate = _clk_ipu1_di1_get_rate,
2858         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
2859         },
2860 };
2861
2862 static unsigned long _clk_ipu2_di0_get_rate(struct clk *clk)
2863 {
2864         u32 reg, div;
2865
2866         if ((clk->parent == &ldb_di0_clk) ||
2867                 (clk->parent == &ldb_di1_clk))
2868                 return clk_get_rate(clk->parent);
2869
2870         reg = __raw_readl(MXC_CCM_CSCDR2);
2871
2872         div = ((reg & MXC_CCM_CSCDR2_IPU2_DI0_PODF_MASK) >>
2873                         MXC_CCM_CSCDR2_IPU2_DI0_PODF_OFFSET) + 1;
2874
2875         return clk_get_rate(clk->parent) / div;
2876 }
2877
2878 static int _clk_ipu2_di0_set_rate(struct clk *clk, unsigned long rate)
2879 {
2880         u32 reg, div;
2881         u32 parent_rate = clk_get_rate(clk->parent);
2882
2883         if ((clk->parent == &ldb_di0_clk) ||
2884                 (clk->parent == &ldb_di1_clk)) {
2885                 if (parent_rate == rate)
2886                         return 0;
2887                 else
2888                         return -EINVAL;
2889         }
2890
2891         div = parent_rate / rate;
2892         if (div == 0)
2893                 div++;
2894         if (((parent_rate / div) != rate) || (div > 8))
2895                 return -EINVAL;
2896
2897         reg = __raw_readl(MXC_CCM_CSCDR2);
2898         reg &= ~MXC_CCM_CSCDR2_IPU2_DI0_PODF_MASK;
2899         reg |= (div - 1) << MXC_CCM_CSCDR2_IPU2_DI0_PODF_OFFSET;
2900         __raw_writel(reg, MXC_CCM_CSCDR2);
2901
2902         return 0;
2903 }
2904
2905 static int _clk_ipu2_di0_set_parent(struct clk *clk, struct clk *parent)
2906 {
2907         u32 reg, mux;
2908
2909         if (parent == &ldb_di0_clk)
2910                 mux = 0x3;
2911         else if (parent == &ldb_di1_clk)
2912                 mux = 0x4;
2913         else {
2914                 reg = __raw_readl(MXC_CCM_CSCDR2)
2915                         & ~MXC_CCM_CSCDR2_IPU2_DI0_PRE_CLK_SEL_MASK;
2916
2917                 mux = _get_mux6(parent, &mmdc_ch0_axi_clk[0],
2918                                 &pll3_usb_otg_main_clk, &pll5_video_main_clk,
2919                                 &pll2_pfd_352M, &pll2_pfd_400M, &pll3_pfd_540M);
2920                 reg |= (mux << MXC_CCM_CSCDR2_IPU2_DI0_PRE_CLK_SEL_OFFSET);
2921
2922                 __raw_writel(reg, MXC_CCM_CSCDR2);
2923
2924                 /* Derive clock from divided pre-muxed ipu2_di0 clock.*/
2925                 mux = 0;
2926         }
2927         reg = __raw_readl(MXC_CCM_CSCDR2)
2928                 & ~MXC_CCM_CSCDR2_IPU2_DI0_CLK_SEL_MASK;
2929         __raw_writel(reg | (mux << MXC_CCM_CSCDR2_IPU2_DI0_CLK_SEL_OFFSET),
2930                 MXC_CCM_CSCDR2);
2931
2932         return 0;
2933 }
2934
2935 static unsigned long _clk_ipu2_di1_get_rate(struct clk *clk)
2936 {
2937         u32 reg, div;
2938
2939         if ((clk->parent == &ldb_di0_clk) ||
2940                 (clk->parent == &ldb_di1_clk))
2941                 return clk_get_rate(clk->parent);
2942
2943         reg = __raw_readl(MXC_CCM_CSCDR2);
2944
2945         div = ((reg & MXC_CCM_CSCDR2_IPU2_DI1_PODF_MASK)
2946                 >> MXC_CCM_CSCDR2_IPU2_DI1_PODF_OFFSET) + 1;
2947
2948         return clk_get_rate(clk->parent) / div;
2949 }
2950
2951 static int _clk_ipu2_di1_set_rate(struct clk *clk, unsigned long rate)
2952 {
2953         u32 reg, div;
2954         u32 parent_rate = clk_get_rate(clk->parent);
2955
2956         if ((clk->parent == &ldb_di0_clk) ||
2957                 (clk->parent == &ldb_di1_clk)) {
2958                 if (parent_rate == rate)
2959                         return 0;
2960                 else
2961                         return -EINVAL;
2962         }
2963
2964         div = parent_rate / rate;
2965         if (div == 0)
2966                 div++;
2967         if (((parent_rate / div) != rate) || (div > 8))
2968                 return -EINVAL;
2969
2970         reg = __raw_readl(MXC_CCM_CSCDR2);
2971         reg &= ~MXC_CCM_CSCDR2_IPU2_DI1_PODF_MASK;
2972         reg |= (div - 1) << MXC_CCM_CSCDR2_IPU2_DI1_PODF_OFFSET;
2973         __raw_writel(reg, MXC_CCM_CSCDR2);
2974
2975         return 0;
2976 }
2977
2978 static int _clk_ipu2_di1_set_parent(struct clk *clk, struct clk *parent)
2979 {
2980         u32 reg, mux;
2981
2982         if (parent == &ldb_di0_clk)
2983                 mux = 0x3;
2984         else if (parent == &ldb_di1_clk)
2985                 mux = 0x4;
2986         else {
2987                 reg = __raw_readl(MXC_CCM_CSCDR2)
2988                         & ~MXC_CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_MASK;
2989
2990                 mux = _get_mux6(parent, &mmdc_ch0_axi_clk[0],
2991                                 &pll3_usb_otg_main_clk, &pll5_video_main_clk,
2992                                 &pll2_pfd_352M, &pll2_pfd_400M, &pll3_pfd_540M);
2993                 reg |= (mux << MXC_CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_OFFSET);
2994
2995                 __raw_writel(reg, MXC_CCM_CSCDR2);
2996
2997                 /* Derive clock from divided pre-muxed ipu1_di0 clock.*/
2998                 mux = 0;
2999         }
3000         reg = __raw_readl(MXC_CCM_CSCDR2)
3001                 & ~MXC_CCM_CSCDR2_IPU2_DI1_CLK_SEL_MASK;
3002         __raw_writel(reg | (mux << MXC_CCM_CSCDR2_IPU2_DI1_CLK_SEL_OFFSET),
3003                 MXC_CCM_CSCDR2);
3004
3005         return 0;
3006 }
3007
3008 static struct clk ipu2_di_clk[] = {
3009         {
3010          __INIT_CLK_DEBUG(ipu2_di_clk_0)
3011         .id = 0,
3012         .parent = &pll5_video_main_clk,
3013         .enable_reg = MXC_CCM_CCGR3,
3014         .enable_shift = MXC_CCM_CCGRx_CG4_OFFSET,
3015         .enable = _clk_enable,
3016         .disable = _clk_disable,
3017         .set_parent = _clk_ipu2_di0_set_parent,
3018         .set_rate = _clk_ipu2_di0_set_rate,
3019         .round_rate = _clk_ipu_di_round_rate,
3020         .get_rate = _clk_ipu2_di0_get_rate,
3021         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
3022         },
3023         {
3024          __INIT_CLK_DEBUG(ipu2_di_clk_1)
3025         .id = 1,
3026         .parent = &pll5_video_main_clk,
3027         .enable_reg = MXC_CCM_CCGR3,
3028         .enable_shift = MXC_CCM_CCGRx_CG5_OFFSET,
3029         .enable = _clk_enable,
3030         .disable = _clk_disable,
3031         .set_parent = _clk_ipu2_di1_set_parent,
3032         .set_rate = _clk_ipu2_di1_set_rate,
3033         .round_rate = _clk_ipu_di_round_rate,
3034         .get_rate = _clk_ipu2_di1_get_rate,
3035         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
3036         },
3037 };
3038
3039 static unsigned long _clk_can_root_round_rate(struct clk *clk,
3040                                                 unsigned long rate)
3041 {
3042         u32 div;
3043         u32 parent_rate = clk_get_rate(clk->parent);
3044
3045         div = parent_rate / rate;
3046
3047         /* Make sure rate is not greater than the maximum value for the clock.
3048          * Also prevent a div of 0.
3049          */
3050         if (div == 0)
3051                 div++;
3052
3053         if (div > 64)
3054                 div = 64;
3055
3056         return parent_rate / div;
3057 }
3058
3059 static int _clk_can_root_set_rate(struct clk *clk, unsigned long rate)
3060 {
3061         u32 reg, div;
3062         u32 parent_rate = clk_get_rate(clk->parent);
3063
3064         div = parent_rate / rate;
3065         if (div == 0)
3066                 div++;
3067         if (((parent_rate / div) != rate) || (div > 64))
3068                 return -EINVAL;
3069
3070         reg = __raw_readl(MXC_CCM_CSCMR2) & MXC_CCM_CSCMR2_CAN_CLK_PODF_MASK;
3071         reg |= ((div - 1) << MXC_CCM_CSCMR2_CAN_CLK_PODF_OFFSET);
3072
3073         __raw_writel(reg, MXC_CCM_CSCMR2);
3074
3075         return 0;
3076 }
3077
3078 static unsigned long _clk_can_root_get_rate(struct clk *clk)
3079 {
3080         u32 reg, div;
3081         unsigned long val;
3082
3083         reg = __raw_readl(MXC_CCM_CSCMR2) & MXC_CCM_CSCMR2_CAN_CLK_PODF_MASK;
3084         div = (reg >> MXC_CCM_CSCMR2_CAN_CLK_PODF_OFFSET) + 1;
3085         val = clk_get_rate(clk->parent) / div;
3086
3087         return val;
3088 }
3089
3090 static struct clk can_clk_root = {
3091          __INIT_CLK_DEBUG(can_clk_root)
3092         .parent = &pll3_60M,
3093         .set_rate = _clk_can_root_set_rate,
3094         .get_rate = _clk_can_root_get_rate,
3095         .round_rate = _clk_can_root_round_rate,
3096 };
3097
3098 static struct clk can2_clk[] = {
3099         {
3100          __INIT_CLK_DEBUG(can2_module_clk)
3101         .id = 0,
3102         .parent = &can_clk_root,
3103         .enable_reg = MXC_CCM_CCGR0,
3104         .enable_shift = MXC_CCM_CCGRx_CG9_OFFSET,
3105         .enable = _clk_enable,
3106         .disable = _clk_disable,
3107         .secondary = &can2_clk[1],
3108         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
3109         },
3110         {
3111          __INIT_CLK_DEBUG(can2_serial_clk)
3112         .id = 1,
3113         .parent = &can_clk_root,
3114         .enable_reg = MXC_CCM_CCGR0,
3115         .enable_shift = MXC_CCM_CCGRx_CG10_OFFSET,
3116         .enable = _clk_enable,
3117         .disable = _clk_disable,
3118         },
3119 };
3120
3121
3122 static struct clk can1_clk[] = {
3123         {
3124          __INIT_CLK_DEBUG(can1_module_clk)
3125         .id = 0,
3126         .parent = &can_clk_root,
3127         .enable_reg = MXC_CCM_CCGR0,
3128         .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
3129         .enable = _clk_enable,
3130         .disable = _clk_disable,
3131         .secondary = &can1_clk[1],
3132         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
3133         },
3134         {
3135          __INIT_CLK_DEBUG(can1_serial_clk)
3136         .id = 1,
3137         .parent = &can_clk_root,
3138         .enable_reg = MXC_CCM_CCGR0,
3139         .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET,
3140         .enable = _clk_enable,
3141         .disable = _clk_disable,
3142         },
3143 };
3144
3145 static unsigned long _clk_spdif_round_rate(struct clk *clk,
3146                                                 unsigned long rate)
3147 {
3148         u32 pre, post;
3149         u32 parent_rate = clk_get_rate(clk->parent);
3150         u32 div = parent_rate / rate;
3151
3152         if (parent_rate % rate)
3153                 div++;
3154
3155         __calc_pre_post_dividers(1 << 3, div, &pre, &post);
3156
3157         return parent_rate / (pre * post);
3158 }
3159
3160 static int _clk_spdif0_set_parent(struct clk *clk, struct clk *parent)
3161 {
3162         u32 reg, mux;
3163
3164         reg = __raw_readl(MXC_CCM_CDCDR)
3165                 & ~MXC_CCM_CDCDR_SPDIF0_CLK_SEL_MASK;
3166
3167         mux = _get_mux6(parent, &pll4_audio_main_clk,
3168                 &pll3_pfd_508M, &pll3_pfd_454M,
3169                 &pll3_sw_clk, NULL, NULL);
3170         reg |= mux << MXC_CCM_CDCDR_SPDIF0_CLK_SEL_OFFSET;
3171
3172         __raw_writel(reg, MXC_CCM_CDCDR);
3173
3174         return 0;
3175 }
3176
3177 static unsigned long _clk_spdif0_get_rate(struct clk *clk)
3178 {
3179         u32 reg, pred, podf;
3180
3181         reg = __raw_readl(MXC_CCM_CDCDR);
3182
3183         pred = ((reg & MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK)
3184                 >> MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET) + 1;
3185         podf = ((reg & MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK)
3186                 >> MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET) + 1;
3187
3188         return clk_get_rate(clk->parent) / (pred * podf);
3189 }
3190
3191 static int _clk_spdif0_set_rate(struct clk *clk, unsigned long rate)
3192 {
3193         u32 reg, div, pre, post;
3194         u32 parent_rate = clk_get_rate(clk->parent);
3195
3196         div = parent_rate / rate;
3197         if (div == 0)
3198                 div++;
3199         if (((parent_rate / div) != rate) || div > 64)
3200                 return -EINVAL;
3201
3202         __calc_pre_post_dividers(1 << 3, div, &pre, &post);
3203
3204         reg = __raw_readl(MXC_CCM_CDCDR);
3205         reg &= ~(MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK|
3206                  MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK);
3207         reg |= (post - 1) << MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET;
3208         reg |= (pre - 1) << MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET;
3209
3210         __raw_writel(reg, MXC_CCM_CDCDR);
3211
3212         return 0;
3213 }
3214
3215 static struct clk spdif0_clk[] = {
3216         {
3217         __INIT_CLK_DEBUG(spdif0_clk_0)
3218         .id = 0,
3219         .parent = &pll3_sw_clk,
3220          .enable = _clk_enable,
3221          .enable_reg = MXC_CCM_CCGR5,
3222          .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
3223          .disable = _clk_disable,
3224          .secondary = &spdif0_clk[1],
3225          .set_rate = _clk_spdif0_set_rate,
3226          .get_rate = _clk_spdif0_get_rate,
3227          .set_parent = _clk_spdif0_set_parent,
3228          .round_rate = _clk_spdif_round_rate,
3229         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
3230         },
3231         {
3232         __INIT_CLK_DEBUG(spdif0_clk_1)
3233          .id = 1,
3234          .parent = &ipg_clk,
3235          .secondary = &spba_clk,
3236          },
3237 };
3238
3239 static unsigned long _clk_esai_round_rate(struct clk *clk,
3240                                                 unsigned long rate)
3241 {
3242         u32 pre, post;
3243         u32 parent_rate = clk_get_rate(clk->parent);
3244         u32 div = parent_rate / rate;
3245
3246         if (parent_rate % rate)
3247                 div++;
3248
3249         __calc_pre_post_dividers(1 << 3, div, &pre, &post);
3250
3251         return parent_rate / (pre * post);
3252 }
3253
3254 static int _clk_esai_set_parent(struct clk *clk, struct clk *parent)
3255 {
3256         u32 reg, mux;
3257
3258         reg = __raw_readl(MXC_CCM_CSCMR2) & ~MXC_CCM_CSCMR2_ESAI_CLK_SEL_MASK;
3259
3260         mux = _get_mux6(parent, &pll4_audio_main_clk, &pll3_pfd_508M,
3261                         &pll3_pfd_454M, &pll3_sw_clk, NULL, NULL);
3262         reg |= mux << MXC_CCM_CSCMR2_ESAI_CLK_SEL_OFFSET;
3263
3264         __raw_writel(reg, MXC_CCM_CSCMR2);
3265
3266         return 0;
3267 }
3268
3269 static unsigned long _clk_esai_get_rate(struct clk *clk)
3270 {
3271         u32 reg, pred, podf;
3272
3273         reg = __raw_readl(MXC_CCM_CS1CDR);
3274
3275         pred = ((reg & MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK)
3276                 >> MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET) + 1;
3277         podf = ((reg & MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK)
3278                 >> MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET) + 1;
3279
3280         return clk_get_rate(clk->parent) / (pred * podf);
3281 }
3282
3283 static int _clk_esai_set_rate(struct clk *clk, unsigned long rate)
3284 {
3285         u32 reg, div, pre, post;
3286         u32 parent_rate = clk_get_rate(clk->parent);
3287
3288         div = parent_rate / rate;
3289         if (div == 0)
3290                 div++;
3291         if (((parent_rate / div) != rate) || div > 64)
3292                 return -EINVAL;
3293
3294         __calc_pre_post_dividers(1 << 3, div, &pre, &post);
3295
3296         reg = __raw_readl(MXC_CCM_CS1CDR);
3297         reg &= ~(MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK|
3298                  MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK);
3299         reg |= (post - 1) << MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET;
3300         reg |= (pre - 1) << MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET;
3301
3302         __raw_writel(reg, MXC_CCM_CS1CDR);
3303
3304         return 0;
3305 }
3306
3307 static struct clk esai_clk = {
3308         __INIT_CLK_DEBUG(esai_clk)
3309          .id = 0,
3310          .parent = &pll3_sw_clk,
3311          .secondary = &spba_clk,
3312          .enable_reg = MXC_CCM_CCGR1,
3313          .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET,
3314          .enable = _clk_enable,
3315          .disable = _clk_disable,
3316          .set_rate = _clk_esai_set_rate,
3317          .get_rate = _clk_esai_get_rate,
3318          .set_parent = _clk_esai_set_parent,
3319          .round_rate = _clk_esai_round_rate,
3320 };
3321
3322 static int _clk_enet_enable(struct clk *clk)
3323 {
3324         unsigned int reg;
3325
3326         /* Enable ENET ref clock */
3327         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
3328         reg &= ~ANADIG_PLL_BYPASS;
3329         reg &= ~ANADIG_PLL_ENABLE;
3330         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
3331
3332         _clk_enable(clk);
3333         return 0;
3334 }
3335
3336 static void _clk_enet_disable(struct clk *clk)
3337 {
3338         unsigned int reg;
3339
3340         _clk_disable(clk);
3341
3342         /* Enable ENET ref clock */
3343         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
3344         reg |= ANADIG_PLL_BYPASS;
3345         reg |= ANADIG_PLL_ENABLE;
3346         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
3347 }
3348
3349 static int _clk_enet_set_rate(struct clk *clk, unsigned long rate)
3350 {
3351         unsigned int reg, div = 1;
3352
3353         switch (rate) {
3354         case 25000000:
3355                 div = 0;
3356                 break;
3357         case 50000000:
3358                 div = 1;
3359                 break;
3360         case 100000000:
3361                 div = 2;
3362                 break;
3363         case 125000000:
3364                 div = 3;
3365                 break;
3366         default:
3367                 return -EINVAL;
3368         }
3369         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
3370         reg &= ~ANADIG_PLL_ENET_DIV_SELECT_MASK;
3371         reg |= (div << ANADIG_PLL_ENET_DIV_SELECT_OFFSET);
3372         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
3373
3374         return 0;
3375 }
3376
3377 static unsigned long _clk_enet_get_rate(struct clk *clk)
3378 {
3379         unsigned int div;
3380
3381         div = (__raw_readl(PLL8_ENET_BASE_ADDR))
3382                 & ANADIG_PLL_ENET_DIV_SELECT_MASK;
3383
3384         switch (div) {
3385         case 0:
3386                 div = 20;
3387                 break;
3388         case 1:
3389                 div = 10;
3390                 break;
3391         case 3:
3392                 div = 5;
3393                 break;
3394         case 4:
3395                 div = 4;
3396                 break;
3397         }
3398
3399         return 500000000 / div;
3400 }
3401
3402 static struct clk enet_clk[] = {
3403         {
3404         __INIT_CLK_DEBUG(enet_clk)
3405          .id = 0,
3406          .parent = &pll8_enet_main_clk,
3407          .enable_reg = MXC_CCM_CCGR1,
3408          .enable_shift = MXC_CCM_CCGRx_CG5_OFFSET,
3409          .enable = _clk_enet_enable,
3410          .disable = _clk_enet_disable,
3411          .set_rate = _clk_enet_set_rate,
3412          .get_rate = _clk_enet_get_rate,
3413         .secondary = &enet_clk[1],
3414         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
3415         },
3416         {
3417         .parent = &mmdc_ch0_axi_clk[0],
3418         .secondary = &mx6per1_clk,
3419         },
3420 };
3421
3422 static struct clk ecspi_clk[] = {
3423         {
3424         __INIT_CLK_DEBUG(ecspi0_clk)
3425         .id = 0,
3426         .parent = &pll3_60M,
3427         .secondary = &spba_clk,
3428         .enable_reg = MXC_CCM_CCGR1,
3429         .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET,
3430         .enable = _clk_enable,
3431         .disable = _clk_disable,
3432         },
3433         {
3434         __INIT_CLK_DEBUG(ecspi1_clk)
3435         .id = 1,
3436         .parent = &pll3_60M,
3437         .secondary = &spba_clk,
3438         .enable_reg = MXC_CCM_CCGR1,
3439         .enable_shift = MXC_CCM_CCGRx_CG1_OFFSET,
3440         .enable = _clk_enable,
3441         .disable = _clk_disable,
3442         },
3443         {
3444         __INIT_CLK_DEBUG(ecspi2_clk)
3445         .id = 2,
3446         .parent = &pll3_60M,
3447         .secondary = &spba_clk,
3448         .enable_reg = MXC_CCM_CCGR1,
3449         .enable_shift = MXC_CCM_CCGRx_CG2_OFFSET,
3450         .enable = _clk_enable,
3451         .disable = _clk_disable,
3452         },
3453         {
3454         __INIT_CLK_DEBUG(ecspi3_clk)
3455         .id = 3,
3456         .parent = &pll3_60M,
3457         .secondary = &spba_clk,
3458         .enable_reg = MXC_CCM_CCGR1,
3459         .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET,
3460         .enable = _clk_enable,
3461         .disable = _clk_disable,
3462         },
3463         {
3464         __INIT_CLK_DEBUG(ecspi4_clk)
3465         .id = 4,
3466         .parent = &pll3_60M,
3467         .secondary = &spba_clk,
3468         .enable_reg = MXC_CCM_CCGR1,
3469         .enable_shift = MXC_CCM_CCGRx_CG4_OFFSET,
3470         .enable = _clk_enable,
3471         .disable = _clk_disable,
3472         },
3473 };
3474
3475 static unsigned long _clk_emi_slow_round_rate(struct clk *clk,
3476                                                 unsigned long rate)
3477 {
3478         u32 div;
3479         u32 parent_rate = clk_get_rate(clk->parent);
3480
3481         div = parent_rate / rate;
3482
3483         /* Make sure rate is not greater than the maximum value for the clock.
3484          * Also prevent a div of 0.
3485          */
3486         if (div == 0)
3487                 div++;
3488
3489         if (div > 8)
3490                 div = 8;
3491
3492         return parent_rate / div;
3493 }
3494
3495 static int _clk_emi_slow_set_parent(struct clk *clk, struct clk *parent)
3496 {
3497         int mux;
3498         u32 reg = __raw_readl(MXC_CCM_CSCMR1)
3499                 & ~MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK;
3500
3501         mux = _get_mux6(parent, &axi_clk, &pll3_usb_otg_main_clk,
3502                                 &pll2_pfd_400M, &pll2_pfd_352M, NULL, NULL);
3503         reg |= (mux << MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET);
3504         __raw_writel(reg, MXC_CCM_CSCMR1);
3505
3506         return 0;
3507 }
3508
3509 static unsigned long _clk_emi_slow_get_rate(struct clk *clk)
3510 {
3511         u32 reg, div;
3512
3513         reg = __raw_readl(MXC_CCM_CSCMR1);
3514         div = ((reg & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK) >>
3515                         MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET) + 1;
3516
3517         return clk_get_rate(clk->parent) / div;
3518 }
3519
3520 static int _clk_emi_slow_set_rate(struct clk *clk, unsigned long rate)
3521 {
3522         u32 reg, div;
3523         u32 parent_rate = clk_get_rate(clk->parent);
3524
3525         div = parent_rate / rate;
3526         if (div == 0)
3527                 div++;
3528         if (((parent_rate / div) != rate) || (div > 8))
3529                 return -EINVAL;
3530
3531         reg = __raw_readl(MXC_CCM_CSCMR1);
3532         reg &= ~MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK;
3533         reg |= (div - 1) << MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET;
3534         __raw_writel(reg, MXC_CCM_CSCMR1);
3535
3536         return 0;
3537 }
3538
3539 static struct clk emi_slow_clk = {
3540         __INIT_CLK_DEBUG(emi_slow_clk)
3541          .id = 0,
3542          .parent = &axi_clk,
3543          .enable_reg = MXC_CCM_CCGR6,
3544          .enable_shift = MXC_CCM_CCGRx_CG5_OFFSET,
3545          .enable = _clk_enable,
3546          .disable = _clk_disable,
3547          .set_rate = _clk_emi_slow_set_rate,
3548          .get_rate = _clk_emi_slow_get_rate,
3549          .round_rate = _clk_emi_slow_round_rate,
3550          .set_parent = _clk_emi_slow_set_parent,
3551 };
3552
3553 static unsigned long _clk_emi_round_rate(struct clk *clk,
3554                                                 unsigned long rate)
3555 {
3556         u32 div;
3557         u32 parent_rate = clk_get_rate(clk->parent);
3558
3559         div = parent_rate / rate;
3560
3561         /* Make sure rate is not greater than the maximum value for the clock.
3562          * Also prevent a div of 0.
3563          */
3564         if (div == 0)
3565                 div++;
3566
3567         if (div > 8)
3568                 div = 8;
3569
3570         return parent_rate / div;
3571 }
3572
3573 static int _clk_emi_set_parent(struct clk *clk, struct clk *parent)
3574 {
3575         int mux;
3576         u32 reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_ACLK_EMI_MASK;
3577
3578         mux = _get_mux6(parent, &axi_clk, &pll3_usb_otg_main_clk,
3579                         &pll2_pfd_400M, &pll2_pfd_352M, NULL, NULL);
3580         reg |= (mux << MXC_CCM_CSCMR1_ACLK_EMI_OFFSET);
3581         __raw_writel(reg, MXC_CCM_CSCMR1);
3582
3583         return 0;
3584 }
3585
3586 static unsigned long _clk_emi_get_rate(struct clk *clk)
3587 {
3588         u32 reg, div;
3589
3590         reg = __raw_readl(MXC_CCM_CSCMR1);
3591         div = ((reg & MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK) >>
3592                         MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET) + 1;
3593
3594         return clk_get_rate(clk->parent) / div;
3595 }
3596
3597 static int _clk_emi_set_rate(struct clk *clk, unsigned long rate)
3598 {
3599         u32 reg, div;
3600         u32 parent_rate = clk_get_rate(clk->parent);
3601
3602         div = parent_rate / rate;
3603         if (div == 0)
3604                 div++;
3605         if (((parent_rate / div) != rate) || (div > 8))
3606                 return -EINVAL;
3607
3608         reg = __raw_readl(MXC_CCM_CSCMR1);
3609         reg &= ~MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK;
3610         reg |= (div - 1) << MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET;
3611         __raw_writel(reg, MXC_CCM_CSCMR1);
3612
3613         return 0;
3614 }
3615
3616 static struct clk emi_clk = {
3617         __INIT_CLK_DEBUG(emi_clk)
3618          .id = 0,
3619          .parent = &axi_clk,
3620          .set_rate = _clk_emi_set_rate,
3621          .get_rate = _clk_emi_get_rate,
3622          .round_rate = _clk_emi_round_rate,
3623          .set_parent = _clk_emi_set_parent,
3624 };
3625
3626 static unsigned long _clk_enfc_round_rate(struct clk *clk,
3627                                                 unsigned long rate)
3628 {
3629         u32 pre, post;
3630         u32 parent_rate = clk_get_rate(clk->parent);
3631         u32 div = parent_rate / rate;
3632
3633         if (parent_rate % rate)
3634                 div++;
3635
3636         __calc_pre_post_dividers(1 << 6, div, &pre, &post);
3637
3638         return parent_rate / (pre * post);
3639 }
3640
3641 static int _clk_enfc_set_parent(struct clk *clk, struct clk *parent)
3642 {
3643         u32 reg, mux;
3644
3645         reg = __raw_readl(MXC_CCM_CS2CDR)
3646                 & ~MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK;
3647
3648         mux = _get_mux6(parent, &pll2_pfd_352M,
3649                 &pll2_528_bus_main_clk, &pll3_usb_otg_main_clk,
3650                 &pll2_pfd_400M, NULL, NULL);
3651         reg |= mux << MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET;
3652
3653         __raw_writel(reg, MXC_CCM_CS2CDR);
3654
3655         return 0;
3656 }
3657
3658 static unsigned long _clk_enfc_get_rate(struct clk *clk)
3659 {
3660         u32 reg, pred, podf;
3661
3662         reg = __raw_readl(MXC_CCM_CS2CDR);
3663
3664         pred = ((reg & MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK)
3665                 >> MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET) + 1;
3666         podf = ((reg & MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK)
3667                 >> MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET) + 1;
3668
3669         return clk_get_rate(clk->parent) / (pred * podf);
3670 }
3671
3672 static int _clk_enfc_set_rate(struct clk *clk, unsigned long rate)
3673 {
3674         u32 reg, div, pre, post;
3675         u32 parent_rate = clk_get_rate(clk->parent);
3676
3677         div = parent_rate / rate;
3678         if (div == 0)
3679                 div++;
3680         if (((parent_rate / div) != rate) || div > 512)
3681                 return -EINVAL;
3682
3683         __calc_pre_post_dividers(1 << 6, div, &pre, &post);
3684
3685         reg = __raw_readl(MXC_CCM_CS2CDR);
3686         reg &= ~(MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK|
3687                  MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK);
3688         reg |= (post - 1) << MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET;
3689         reg |= (pre - 1) << MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET;
3690
3691         __raw_writel(reg, MXC_CCM_CS2CDR);
3692
3693         return 0;
3694 }
3695
3696 static struct clk enfc_clk = {
3697         __INIT_CLK_DEBUG(enfc_clk)
3698          .id = 0,
3699          .parent = &pll2_pfd_352M,
3700          .enable_reg = MXC_CCM_CCGR2,
3701          .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
3702          .enable = _clk_enable,
3703          .disable = _clk_disable,
3704          .set_rate = _clk_enfc_set_rate,
3705          .get_rate = _clk_enfc_get_rate,
3706          .round_rate = _clk_enfc_round_rate,
3707          .set_parent = _clk_enfc_set_parent,
3708 };
3709
3710 static unsigned long _clk_uart_round_rate(struct clk *clk,
3711                                                 unsigned long rate)
3712 {
3713         u32 div;
3714         u32 parent_rate = clk_get_rate(clk->parent);
3715
3716         div = parent_rate / rate;
3717
3718         /* Make sure rate is not greater than the maximum value for the clock.
3719          * Also prevent a div of 0.
3720          */
3721         if (div == 0)
3722                 div++;
3723
3724         if (div > 64)
3725                 div = 64;
3726
3727         return parent_rate / div;
3728 }
3729
3730 static int _clk_uart_set_rate(struct clk *clk, unsigned long rate)
3731 {
3732         u32 reg, div;
3733         u32 parent_rate = clk_get_rate(clk->parent);
3734
3735         div = parent_rate / rate;
3736         if (div == 0)
3737                 div++;
3738         if (((parent_rate / div) != rate) || (div > 64))
3739                 return -EINVAL;
3740
3741         reg = __raw_readl(MXC_CCM_CSCDR1) & MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
3742         reg |= ((div - 1) << MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET);
3743
3744         __raw_writel(reg, MXC_CCM_CSCDR1);
3745
3746         return 0;
3747 }
3748
3749 static unsigned long _clk_uart_get_rate(struct clk *clk)
3750 {
3751         u32 reg, div;
3752         unsigned long val;
3753
3754         reg = __raw_readl(MXC_CCM_CSCDR1) & MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
3755         div = (reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET) + 1;
3756         val = clk_get_rate(clk->parent) / div;
3757
3758         return val;
3759 }
3760
3761 static struct clk uart_clk[] = {
3762         {
3763         __INIT_CLK_DEBUG(uart_clk)
3764          .id = 0,
3765          .parent = &pll3_80M,
3766          .enable_reg = MXC_CCM_CCGR5,
3767          .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET,
3768          .enable = _clk_enable,
3769          .disable = _clk_disable,
3770          .secondary = &uart_clk[1],
3771          .set_rate = _clk_uart_set_rate,
3772          .get_rate = _clk_uart_get_rate,
3773          .round_rate = _clk_uart_round_rate,
3774         },
3775         {
3776         __INIT_CLK_DEBUG(uart_serial_clk)
3777          .id = 1,
3778          .enable_reg = MXC_CCM_CCGR5,
3779          .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
3780          .enable = _clk_enable,
3781          .disable = _clk_disable,
3782         },
3783 };
3784
3785 static unsigned long _clk_hsi_tx_round_rate(struct clk *clk,
3786                                                 unsigned long rate)
3787 {
3788         u32 div;
3789         u32 parent_rate = clk_get_rate(clk->parent);
3790
3791         div = parent_rate / rate;
3792
3793         /* Make sure rate is not greater than the maximum value for the clock.
3794          * Also prevent a div of 0.
3795          */
3796         if (div == 0)
3797                 div++;
3798
3799         if (div > 8)
3800                 div = 8;
3801
3802         return parent_rate / div;
3803 }
3804
3805 static int _clk_hsi_tx_set_parent(struct clk *clk, struct clk *parent)
3806 {
3807         u32 reg = __raw_readl(MXC_CCM_CDCDR) & ~MXC_CCM_CDCDR_HSI_TX_CLK_SEL;
3808
3809         if (parent == &pll2_pfd_400M)
3810                 reg |= (MXC_CCM_CDCDR_HSI_TX_CLK_SEL);
3811
3812         __raw_writel(reg, MXC_CCM_CDCDR);
3813
3814         return 0;
3815 }
3816
3817 static unsigned long _clk_hsi_tx_get_rate(struct clk *clk)
3818 {
3819         u32 reg, div;
3820
3821         reg = __raw_readl(MXC_CCM_CDCDR);
3822         div = ((reg & MXC_CCM_CDCDR_HSI_TX_PODF_MASK) >>
3823                         MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET) + 1;
3824
3825         return clk_get_rate(clk->parent) / div;
3826 }
3827
3828 static int _clk_hsi_tx_set_rate(struct clk *clk, unsigned long rate)
3829 {
3830         u32 reg, div;
3831         u32 parent_rate = clk_get_rate(clk->parent);
3832
3833         div = parent_rate / rate;
3834         if (div == 0)
3835                 div++;
3836         if (((parent_rate / div) != rate) || (div > 8))
3837                 return -EINVAL;
3838
3839         reg = __raw_readl(MXC_CCM_CDCDR);
3840         reg &= ~MXC_CCM_CDCDR_HSI_TX_PODF_MASK;
3841         reg |= (div - 1) << MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET;
3842         __raw_writel(reg, MXC_CCM_CDCDR);
3843
3844         return 0;
3845 }
3846
3847 static struct clk hsi_tx_clk[] = {
3848         {
3849          __INIT_CLK_DEBUG(hsi_tx_clk)
3850         .id = 0,
3851          .parent = &pll2_pfd_400M,
3852         .enable_reg = MXC_CCM_CCGR3,
3853         .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET,
3854         .enable = _clk_enable,
3855         .disable = _clk_disable,
3856         .set_parent = _clk_hsi_tx_set_parent,
3857         .round_rate = _clk_hsi_tx_round_rate,
3858         .set_rate = _clk_hsi_tx_set_rate,
3859         .get_rate = _clk_hsi_tx_get_rate,
3860          .secondary = &hsi_tx_clk[1],
3861         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
3862         },
3863         {
3864         .parent = &mx6per1_clk,
3865         .secondary = &mx6per2_clk,
3866          },
3867 };
3868
3869 static struct clk mipi_pllref_clk = {
3870          __INIT_CLK_DEBUG(mipi_pllref_clk)
3871         .id = 0,
3872         .parent = &pll3_pfd_540M,
3873         .enable_reg = MXC_CCM_CCGR3,
3874         .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET,
3875         .enable = _clk_enable,
3876         .disable = _clk_disable,
3877 };
3878
3879 static struct clk hdmi_clk[] = {
3880         {
3881          __INIT_CLK_DEBUG(hdmi_isfr_clk)
3882         .id = 0,
3883         .parent = &pll3_pfd_540M,
3884         .enable_reg = MXC_CCM_CCGR2,
3885         .enable_shift = MXC_CCM_CCGRx_CG2_OFFSET,
3886         .enable = _clk_enable,
3887         .disable = _clk_disable,
3888         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
3889         },
3890         {
3891          __INIT_CLK_DEBUG(hdmi_iahb_clk)
3892         .id = 1,
3893          .parent = &ahb_clk,
3894         .enable_reg = MXC_CCM_CCGR2,
3895         .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET,
3896         .enable = _clk_enable,
3897         .disable = _clk_disable,
3898         },
3899 };
3900
3901 static struct clk caam_clk[] = {
3902         {
3903          __INIT_CLK_DEBUG(caam_mem_clk)
3904         .id = 0,
3905         .enable_reg = MXC_CCM_CCGR0,
3906         .enable_shift = MXC_CCM_CCGRx_CG4_OFFSET,
3907         .enable = _clk_enable,
3908         .disable = _clk_disable,
3909         .secondary = &caam_clk[1],
3910         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
3911         },
3912         {
3913          __INIT_CLK_DEBUG(caam_aclk_clk)
3914         .id = 1,
3915         .enable_reg = MXC_CCM_CCGR0,
3916         .enable_shift = MXC_CCM_CCGRx_CG5_OFFSET,
3917         .enable = _clk_enable,
3918         .disable = _clk_disable,
3919         .secondary = &caam_clk[2],
3920         },
3921         {
3922          __INIT_CLK_DEBUG(caam_ipg_clk)
3923         .id = 2,
3924         .enable_reg = MXC_CCM_CCGR0,
3925         .enable_shift = MXC_CCM_CCGRx_CG4_OFFSET,
3926         .enable = _clk_enable,
3927         .disable = _clk_disable,
3928         .parent = &mmdc_ch0_axi_clk[0],
3929         .secondary = &mx6per1_clk,
3930         },
3931 };
3932
3933 static int _clk_asrc_serial_set_parent(struct clk *clk, struct clk *parent)
3934 {
3935         u32 reg, mux;
3936
3937         reg = __raw_readl(MXC_CCM_CDCDR) & ~MXC_CCM_CDCDR_SPDIF1_CLK_SEL_MASK;
3938
3939         mux = _get_mux6(parent, &pll4_audio_main_clk, &pll3_pfd_508M,
3940                         &pll3_pfd_454M, &pll3_sw_clk, NULL, NULL);
3941         reg |= mux << MXC_CCM_CDCDR_SPDIF1_CLK_SEL_OFFSET;
3942
3943         __raw_writel(reg, MXC_CCM_CDCDR);
3944
3945         return 0;
3946 }
3947
3948 static unsigned long _clk_asrc_serial_get_rate(struct clk *clk)
3949 {
3950         u32 reg, pred, podf;
3951
3952         reg = __raw_readl(MXC_CCM_CDCDR);
3953
3954         pred = ((reg & MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK)
3955                 >> MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET) + 1;
3956         podf = ((reg & MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK)
3957                 >> MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET) + 1;
3958
3959         return clk_get_rate(clk->parent) / (pred * podf);
3960 }
3961
3962 static int _clk_asrc_serial_set_rate(struct clk *clk, unsigned long rate)
3963 {
3964         u32 reg, div, pre, post;
3965         u32 parent_rate = clk_get_rate(clk->parent);
3966
3967         div = parent_rate / rate;
3968         if (div == 0)
3969                 div++;
3970         if (((parent_rate / div) != rate) || div > 64)
3971                 return -EINVAL;
3972
3973         __calc_pre_post_dividers(1 << 3, div, &pre, &post);
3974
3975         reg = __raw_readl(MXC_CCM_CDCDR);
3976         reg &= ~(MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK|
3977                  MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK);
3978         reg |= (post - 1) << MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET;
3979         reg |= (pre - 1) << MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET;
3980
3981         __raw_writel(reg, MXC_CCM_CDCDR);
3982
3983         return 0;
3984 }
3985
3986 static unsigned long _clk_asrc_serial_round_rate(struct clk *clk,
3987                                                 unsigned long rate)
3988 {
3989         u32 pre, post;
3990         u32 parent_rate = clk_get_rate(clk->parent);
3991         u32 div = parent_rate / rate;
3992
3993         if (parent_rate % rate)
3994                 div++;
3995
3996         __calc_pre_post_dividers(1 << 3, div, &pre, &post);
3997
3998         return parent_rate / (pre * post);
3999 }
4000
4001 static struct clk asrc_clk[] = {
4002         {
4003         __INIT_CLK_DEBUG(asrc_clk)
4004         .id = 0,
4005         .parent = &pll4_audio_main_clk,
4006         .enable_reg = MXC_CCM_CCGR0,
4007         .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET,
4008         .enable = _clk_enable,
4009         .disable = _clk_disable,
4010         .secondary = &spba_clk,
4011         },
4012         {
4013         /*In the MX6 spec, asrc_serial_clk is listed as SPDIF1 clk
4014          * This clock can never be gated and does  not have any
4015          * CCGR bits associated with it.
4016          */
4017         __INIT_CLK_DEBUG(asrc_serial_clk)
4018         .id = 1,
4019         .parent = &pll3_sw_clk,
4020          .set_rate = _clk_asrc_serial_set_rate,
4021          .get_rate = _clk_asrc_serial_get_rate,
4022          .set_parent = _clk_asrc_serial_set_parent,
4023          .round_rate = _clk_asrc_serial_round_rate,
4024         },
4025 };
4026
4027 static struct clk apbh_dma_clk = {
4028         __INIT_CLK_DEBUG(apbh_dma_clk)
4029         .parent = &usdhc3_clk,
4030         .secondary = &mx6per1_clk,
4031         .enable = _clk_enable,
4032         .disable = _clk_disable_inwait,
4033         .enable_reg = MXC_CCM_CCGR0,
4034         .enable_shift = MXC_CCM_CCGRx_CG2_OFFSET,
4035 };
4036
4037 static struct clk aips_tz2_clk = {
4038         __INIT_CLK_DEBUG(aips_tz2_clk)
4039         .parent = &ahb_clk,
4040         .enable_reg = MXC_CCM_CCGR0,
4041         .enable_shift = MXC_CCM_CCGRx_CG1_OFFSET,
4042         .enable = _clk_enable,
4043         .disable = _clk_disable_inwait,
4044 };
4045
4046 static struct clk aips_tz1_clk = {
4047         __INIT_CLK_DEBUG(aips_tz1_clk)
4048         .parent = &ahb_clk,
4049         .enable_reg = MXC_CCM_CCGR0,
4050         .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET,
4051         .enable = _clk_enable,
4052         .disable = _clk_disable_inwait,
4053 };
4054
4055
4056 static struct clk openvg_axi_clk = {
4057         __INIT_CLK_DEBUG(openvg_axi_clk)
4058         .parent = &gpu2d_axi_clk,
4059         .enable = _clk_enable,
4060         .enable_reg = MXC_CCM_CCGR3,
4061         .enable_shift = MXC_CCM_CCGRx_CG15_OFFSET,
4062         .disable = _clk_disable,
4063         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
4064 };
4065
4066 static unsigned long _clk_gpu3d_core_round_rate(struct clk *clk,
4067                                                 unsigned long rate)
4068 {
4069         u32 div;
4070         u32 parent_rate = clk_get_rate(clk->parent);
4071
4072         div = parent_rate / rate;
4073
4074         /* Make sure rate is not greater than the maximum value for the clock.
4075          * Also prevent a div of 0.
4076          */
4077         if (div == 0)
4078                 div++;
4079
4080         if (div > 8)
4081                 div = 8;
4082
4083         return parent_rate / div;
4084 }
4085
4086 static int _clk_gpu3d_core_set_parent(struct clk *clk, struct clk *parent)
4087 {
4088         int mux;
4089         u32 reg = __raw_readl(MXC_CCM_CBCMR)
4090                 & ~MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK;
4091
4092         mux = _get_mux6(parent, &mmdc_ch0_axi_clk[0],
4093                 &pll3_usb_otg_main_clk,
4094                 &pll2_pfd_594M, &pll2_pfd_400M, NULL, NULL);
4095         reg |= (mux << MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET);
4096         __raw_writel(reg, MXC_CCM_CBCMR);
4097
4098         return 0;
4099 }
4100
4101 static unsigned long _clk_gpu3d_core_get_rate(struct clk *clk)
4102 {
4103         u32 reg, div;
4104
4105         reg = __raw_readl(MXC_CCM_CBCMR);
4106         div = ((reg & MXC_CCM_CBCMR_GPU3D_CORE_PODF_MASK) >>
4107                         MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET) + 1;
4108
4109         return clk_get_rate(clk->parent) / div;
4110 }
4111
4112 static int _clk_gpu3d_core_set_rate(struct clk *clk, unsigned long rate)
4113 {
4114         u32 reg, div;
4115         u32 parent_rate = clk_get_rate(clk->parent);
4116
4117         div = parent_rate / rate;
4118         if (div == 0)
4119                 div++;
4120         if (div > 8)
4121                 div = 8;
4122
4123         reg = __raw_readl(MXC_CCM_CBCMR);
4124         reg &= ~MXC_CCM_CBCMR_GPU3D_CORE_PODF_MASK;
4125         reg |= (div - 1) << MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET;
4126         __raw_writel(reg, MXC_CCM_CBCMR);
4127
4128         return 0;
4129 }
4130
4131 static struct clk gpu3d_core_clk[] = {
4132         {
4133         __INIT_CLK_DEBUG(gpu3d_core_clk)
4134         .parent = &pll2_pfd_594M,
4135         .enable = _clk_enable,
4136         .enable_reg = MXC_CCM_CCGR1,
4137         .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
4138         .disable = _clk_disable,
4139         .set_parent = _clk_gpu3d_core_set_parent,
4140         .set_rate = _clk_gpu3d_core_set_rate,
4141         .get_rate = _clk_gpu3d_core_get_rate,
4142         .round_rate = _clk_gpu3d_core_round_rate,
4143         .secondary = &gpu3d_core_clk[1],
4144         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
4145         },
4146         {
4147         .parent = &gpu3d_axi_clk,
4148         .secondary = &mx6fast1_clk,
4149         },
4150 };
4151
4152 static unsigned long _clk_gpu2d_core_round_rate(struct clk *clk,
4153                                                 unsigned long rate)
4154 {
4155         u32 div;
4156         u32 parent_rate = clk_get_rate(clk->parent);
4157
4158         div = parent_rate / rate;
4159
4160         /* Make sure rate is not greater than the maximum value for the clock.
4161          * Also prevent a div of 0.
4162          */
4163         if (div == 0)
4164                 div++;
4165
4166         if (div > 8)
4167                 div = 8;
4168
4169         return parent_rate / div;
4170 }
4171
4172 static int _clk_gpu2d_core_set_parent(struct clk *clk, struct clk *parent)
4173 {
4174         int mux;
4175         u32 reg = __raw_readl(MXC_CCM_CBCMR) &
4176                                 ~MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK;
4177
4178         mux = _get_mux6(parent, &axi_clk, &pll3_usb_otg_main_clk,
4179                 &pll2_pfd_352M, &pll2_pfd_400M, NULL, NULL);
4180         reg |= (mux << MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET);
4181         __raw_writel(reg, MXC_CCM_CBCMR);
4182
4183         return 0;
4184 }
4185
4186 static unsigned long _clk_gpu2d_core_get_rate(struct clk *clk)
4187 {
4188         u32 reg, div;
4189
4190         reg = __raw_readl(MXC_CCM_CBCMR);
4191         div = ((reg & MXC_CCM_CBCMR_GPU2D_CORE_PODF_MASK) >>
4192                         MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET) + 1;
4193
4194         return clk_get_rate(clk->parent) / div;
4195 }
4196
4197 static int _clk_gpu2d_core_set_rate(struct clk *clk, unsigned long rate)
4198 {
4199         u32 reg, div;
4200         u32 parent_rate = clk_get_rate(clk->parent);
4201
4202         div = parent_rate / rate;
4203         if (div == 0)
4204                 div++;
4205         if (((parent_rate / div) != rate) || (div > 8))
4206                 return -EINVAL;
4207
4208         reg = __raw_readl(MXC_CCM_CBCMR);
4209         reg &= ~MXC_CCM_CBCMR_GPU2D_CORE_PODF_MASK;
4210         reg |= (div - 1) << MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET;
4211         __raw_writel(reg, MXC_CCM_CBCMR);
4212
4213         return 0;
4214 }
4215 static struct clk gpu2d_core_clk[] = {
4216         {
4217         __INIT_CLK_DEBUG(gpu2d_core_clk)
4218         .parent = &pll2_pfd_352M,
4219         .enable = _clk_enable,
4220         .enable_reg = MXC_CCM_CCGR1,
4221         .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET,
4222         .disable = _clk_disable,
4223         .set_parent = _clk_gpu2d_core_set_parent,
4224         .set_rate = _clk_gpu2d_core_set_rate,
4225         .get_rate = _clk_gpu2d_core_get_rate,
4226         .round_rate = _clk_gpu2d_core_round_rate,
4227         .secondary = &gpu2d_core_clk[1],
4228         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
4229         },
4230         {
4231         .parent = &gpu2d_axi_clk,
4232         .secondary = &mx6fast1_clk,
4233         },
4234 };
4235
4236 static unsigned long _clk_gpu3d_shader_round_rate(struct clk *clk,
4237                                                 unsigned long rate)
4238 {
4239         u32 div;
4240         u32 parent_rate = clk_get_rate(clk->parent);
4241
4242         div = parent_rate / rate;
4243
4244         /* Make sure rate is not greater than the maximum value for the clock.
4245          * Also prevent a div of 0.
4246          */
4247         if (div == 0)
4248                 div++;
4249
4250         if (div > 8)
4251                 div = 8;
4252
4253         return parent_rate / div;
4254 }
4255
4256 static int _clk_gpu3d_shader_set_parent(struct clk *clk, struct clk *parent)
4257 {
4258         int mux;
4259         u32 reg = __raw_readl(MXC_CCM_CBCMR)
4260                 & ~MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_MASK;
4261
4262         mux = _get_mux6(parent, &mmdc_ch0_axi_clk[0],
4263                 &pll3_usb_otg_main_clk,
4264                 &pll2_pfd_594M, &pll3_pfd_720M, NULL, NULL);
4265         reg |= (mux << MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET);
4266         __raw_writel(reg, MXC_CCM_CBCMR);
4267
4268         return 0;
4269 }
4270
4271 static unsigned long _clk_gpu3d_shader_get_rate(struct clk *clk)
4272 {
4273         u32 reg, div;
4274
4275         reg = __raw_readl(MXC_CCM_CBCMR);
4276         div = ((reg & MXC_CCM_CBCMR_GPU3D_SHADER_PODF_MASK) >>
4277                         MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET) + 1;
4278
4279         return clk_get_rate(clk->parent) / div;
4280 }
4281
4282 static int _clk_gpu3d_shader_set_rate(struct clk *clk, unsigned long rate)
4283 {
4284         u32 reg, div;
4285         u32 parent_rate = clk_get_rate(clk->parent);
4286
4287         div = parent_rate / rate;
4288         if (div == 0)
4289                 div++;
4290         if (div > 8)
4291                 div = 8;
4292
4293         reg = __raw_readl(MXC_CCM_CBCMR);
4294         reg &= ~MXC_CCM_CBCMR_GPU3D_SHADER_PODF_MASK;
4295         reg |= (div - 1) << MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET;
4296         __raw_writel(reg, MXC_CCM_CBCMR);
4297
4298         return 0;
4299 }
4300
4301
4302 static struct clk gpu3d_shader_clk = {
4303         __INIT_CLK_DEBUG(gpu3d_shader_clk)
4304         .parent = &pll3_pfd_720M,
4305         .secondary = &mmdc_ch0_axi_clk[0],
4306         .enable = _clk_enable,
4307         .enable_reg = MXC_CCM_CCGR1,
4308         .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
4309         .disable = _clk_disable,
4310         .set_parent = _clk_gpu3d_shader_set_parent,
4311         .set_rate = _clk_gpu3d_shader_set_rate,
4312         .get_rate = _clk_gpu3d_shader_get_rate,
4313         .round_rate = _clk_gpu3d_shader_round_rate,
4314         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
4315 };
4316
4317 /* set the parent by the ipcg table */
4318 static struct clk gpmi_nfc_clk[] = {
4319         {       /* gpmi_io_clk */
4320         __INIT_CLK_DEBUG(gpmi_io_clk)
4321         .parent = &enfc_clk,
4322         .secondary = &gpmi_nfc_clk[1],
4323         .enable = _clk_enable,
4324         .enable_reg = MXC_CCM_CCGR4,
4325         .enable_shift = MXC_CCM_CCGRx_CG14_OFFSET,
4326         .disable = _clk_disable,
4327         },
4328         {       /* gpmi_apb_clk */
4329         __INIT_CLK_DEBUG(gpmi_apb_clk)
4330         .parent = &usdhc3_clk,
4331         .secondary = &gpmi_nfc_clk[2],
4332         .enable = _clk_enable,
4333         .enable_reg = MXC_CCM_CCGR4,
4334         .enable_shift = MXC_CCM_CCGRx_CG15_OFFSET,
4335         .disable = _clk_disable,
4336         },
4337         {       /* bch_clk */
4338         __INIT_CLK_DEBUG(gpmi_bch_clk)
4339         .parent = &usdhc4_clk,
4340         .secondary = &gpmi_nfc_clk[3],
4341         .enable = _clk_enable,
4342         .enable_reg = MXC_CCM_CCGR4,
4343         .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
4344         .disable = _clk_disable,
4345         },
4346         {       /* bch_apb_clk */
4347         __INIT_CLK_DEBUG(gpmi_bch_apb_clk)
4348         .parent = &usdhc3_clk,
4349         .secondary = &gpmi_nfc_clk[4],
4350         .enable = _clk_enable,
4351         .enable_reg = MXC_CCM_CCGR4,
4352         .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET,
4353         .disable = _clk_disable,
4354         },
4355         {       /* bch relative clk */
4356         __INIT_CLK_DEBUG(pl301_mx6qperl_bch)
4357         .parent = &mx6per1_clk,
4358         .secondary = &mmdc_ch0_axi_clk[0],
4359         },
4360 };
4361
4362 static struct clk pwm_clk[] = {
4363         {
4364         __INIT_CLK_DEBUG(pwm_clk_0)
4365          .parent = &ipg_perclk,
4366          .id = 0,
4367          .enable_reg = MXC_CCM_CCGR4,
4368          .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET,
4369          .enable = _clk_enable,
4370          .disable = _clk_disable,
4371          },
4372         {
4373         __INIT_CLK_DEBUG(pwm_clk_1)
4374          .parent = &ipg_perclk,
4375          .id = 1,
4376          .enable_reg = MXC_CCM_CCGR4,
4377          .enable_shift = MXC_CCM_CCGRx_CG9_OFFSET,
4378          .enable = _clk_enable,
4379          .disable = _clk_disable,
4380          },
4381         {
4382         __INIT_CLK_DEBUG(pwm_clk_2)
4383          .parent = &ipg_perclk,
4384          .id = 2,
4385          .enable_reg = MXC_CCM_CCGR4,
4386          .enable_shift = MXC_CCM_CCGRx_CG10_OFFSET,
4387          .enable = _clk_enable,
4388          .disable = _clk_disable,
4389          },
4390         {
4391         __INIT_CLK_DEBUG(pwm_clk_3)
4392          .parent = &ipg_perclk,
4393          .id = 3,
4394          .enable_reg = MXC_CCM_CCGR4,
4395          .enable_shift = MXC_CCM_CCGRx_CG11_OFFSET,
4396          .enable = _clk_enable,
4397          .disable = _clk_disable,
4398          },
4399 };
4400
4401 static int _clk_pcie_enable(struct clk *clk)
4402 {
4403         unsigned int reg;
4404
4405         /* Enable SATA ref clock */
4406         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
4407         reg |= ANADIG_PLL_ENET_EN_PCIE;
4408         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
4409
4410         _clk_enable(clk);
4411
4412         return 0;
4413 }
4414
4415 static void _clk_pcie_disable(struct clk *clk)
4416 {
4417         unsigned int reg;
4418
4419         _clk_disable(clk);
4420
4421         /* Disable SATA ref clock */
4422         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
4423         reg &= ~ANADIG_PLL_ENET_EN_PCIE;
4424         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
4425 }
4426
4427 static struct clk pcie_clk[] = {
4428         {
4429         __INIT_CLK_DEBUG(pcie_clk)
4430         .parent = &pcie_axi_clk,
4431         .enable = _clk_pcie_enable,
4432         .disable = _clk_pcie_disable,
4433         .enable_reg = MXC_CCM_CCGR4,
4434         .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET,
4435         .secondary = &pcie_clk[1],
4436         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
4437         },
4438         {
4439         .parent = &mmdc_ch0_axi_clk[0],
4440         .secondary = &mx6fast1_clk,
4441         },
4442 };
4443
4444 static int _clk_sata_enable(struct clk *clk)
4445 {
4446         unsigned int reg;
4447
4448         /* Clear Power Down and Enable PLLs */
4449         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
4450         reg &= ~ANADIG_PLL_ENET_POWER_DOWN;
4451         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
4452
4453         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
4454         reg |= ANADIG_PLL_ENET_EN;
4455         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
4456
4457         /* Waiting for the PLL is locked */
4458         if (!WAIT(ANADIG_PLL_ENET_LOCK & __raw_readl(PLL8_ENET_BASE_ADDR),
4459                                 SPIN_DELAY))
4460                 panic("pll8 lock failed\n");
4461
4462         /* Disable the bypass */
4463         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
4464         reg &= ~ANADIG_PLL_ENET_BYPASS;
4465         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
4466
4467         /* Enable SATA ref clock */
4468         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
4469         reg |= ANADIG_PLL_ENET_EN_SATA;
4470         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
4471
4472         _clk_enable(clk);
4473
4474         return 0;
4475 }
4476
4477 static void _clk_sata_disable(struct clk *clk)
4478 {
4479         unsigned int reg;
4480
4481         _clk_disable(clk);
4482
4483         /* Disable SATA ref clock */
4484         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
4485         reg &= ~ANADIG_PLL_ENET_EN_SATA;
4486         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
4487 }
4488
4489 static struct clk sata_clk[] = {
4490         {
4491         __INIT_CLK_DEBUG(sata_clk)
4492         .parent = &ipg_clk,
4493         .enable = _clk_sata_enable,
4494         .enable_reg = MXC_CCM_CCGR5,
4495         .enable_shift = MXC_CCM_CCGRx_CG2_OFFSET,
4496         .disable = _clk_sata_disable,
4497         .secondary = &sata_clk[1],
4498         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
4499         },
4500         {
4501         .parent = &mmdc_ch0_axi_clk[0],
4502         .secondary = &mx6per1_clk,
4503         }
4504 };
4505
4506 static struct clk usboh3_clk[] = {
4507         {
4508         __INIT_CLK_DEBUG(usboh3_clk)
4509         .parent = &ahb_clk,
4510         .enable = _clk_enable,
4511         .enable_reg = MXC_CCM_CCGR6,
4512         .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET,
4513         .disable = _clk_disable,
4514         .secondary = &usboh3_clk[1],
4515         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
4516         },
4517         {
4518         .parent = &mmdc_ch0_axi_clk[0],
4519         .secondary = &mx6per1_clk,
4520         },
4521 };
4522
4523 static int _clk_enable1(struct clk *clk)
4524 {
4525         u32 reg;
4526         reg = __raw_readl(clk->enable_reg);
4527         reg |= 1 << clk->enable_shift;
4528         __raw_writel(reg, clk->enable_reg);
4529
4530         return 0;
4531 }
4532
4533 static void _clk_disable1(struct clk *clk)
4534 {
4535         u32 reg;
4536         reg = __raw_readl(clk->enable_reg);
4537         reg &= ~(1 << clk->enable_shift);
4538         __raw_writel(reg, clk->enable_reg);
4539 }
4540
4541 static int _clk_clko_set_parent(struct clk *clk, struct clk *parent)
4542 {
4543         u32 sel, reg;
4544
4545         if (parent == &pll3_usb_otg_main_clk)
4546                 sel = 0;
4547         else if (parent == &pll2_528_bus_main_clk)
4548                 sel = 1;
4549         else if (parent == &pll1_sys_main_clk)
4550                 sel = 2;
4551         else if (parent == &pll5_video_main_clk)
4552                 sel = 3;
4553         else if (parent == &axi_clk)
4554                 sel = 5;
4555         else if (parent == &enfc_clk)
4556                 sel = 6;
4557         else if (parent == &ipu1_di_clk[0])
4558                 sel = 7;
4559         else if (parent == &ipu1_di_clk[1])
4560                 sel = 8;
4561         else if (parent == &ipu2_di_clk[0])
4562                 sel = 9;
4563         else if (parent == &ipu2_di_clk[1])
4564                 sel = 10;
4565         else if (parent == &ahb_clk)
4566                 sel = 11;
4567         else if (parent == &ipg_clk)
4568                 sel = 12;
4569         else if (parent == &ipg_perclk)
4570                 sel = 13;
4571         else if (parent == &ckil_clk)
4572                 sel = 14;
4573         else if (parent == &pll4_audio_main_clk)
4574                 sel = 15;
4575         else
4576                 return -EINVAL;
4577
4578         reg = __raw_readl(MXC_CCM_CCOSR);
4579         reg &= ~MXC_CCM_CCOSR_CKOL_SEL_MASK;
4580         reg |= sel << MXC_CCM_CCOSR_CKOL_SEL_OFFSET;
4581         __raw_writel(reg, MXC_CCM_CCOSR);
4582         return 0;
4583 }
4584
4585 static unsigned long _clk_clko_get_rate(struct clk *clk)
4586 {
4587         u32 reg = __raw_readl(MXC_CCM_CCOSR);
4588         u32 div = ((reg & MXC_CCM_CCOSR_CKOL_DIV_MASK) >>
4589                         MXC_CCM_CCOSR_CKOL_DIV_OFFSET) + 1;
4590         return clk_get_rate(clk->parent) / div;
4591 }
4592
4593 static int _clk_clko_set_rate(struct clk *clk, unsigned long rate)
4594 {
4595         u32 reg;
4596         u32 parent_rate = clk_get_rate(clk->parent);
4597         u32 div = parent_rate / rate;
4598
4599         if (div == 0)
4600                 div++;
4601         if (((parent_rate / div) != rate) || (div > 8))
4602                 return -EINVAL;
4603
4604         reg = __raw_readl(MXC_CCM_CCOSR);
4605         reg &= ~MXC_CCM_CCOSR_CKOL_DIV_MASK;
4606         reg |= (div - 1) << MXC_CCM_CCOSR_CKOL_DIV_OFFSET;
4607         __raw_writel(reg, MXC_CCM_CCOSR);
4608         return 0;
4609 }
4610
4611 static unsigned long _clk_clko_round_rate(struct clk *clk,
4612                                                 unsigned long rate)
4613 {
4614         u32 parent_rate = clk_get_rate(clk->parent);
4615         u32 div = parent_rate / rate;
4616
4617         /* Make sure rate is not greater than the maximum value for the clock.
4618          * Also prevent a div of 0.
4619          */
4620         if (div == 0)
4621                 div++;
4622         if (div > 8)
4623                 div = 8;
4624         return parent_rate / div;
4625 }
4626
4627 static struct clk clko_clk = {
4628         __INIT_CLK_DEBUG(clko_clk)
4629         .parent = &pll2_528_bus_main_clk,
4630         .enable = _clk_enable1,
4631         .enable_reg = MXC_CCM_CCOSR,
4632         .enable_shift = MXC_CCM_CCOSR_CKOL_EN_OFFSET,
4633         .disable = _clk_disable1,
4634         .set_parent = _clk_clko_set_parent,
4635         .set_rate = _clk_clko_set_rate,
4636         .get_rate = _clk_clko_get_rate,
4637         .round_rate = _clk_clko_round_rate,
4638 };
4639
4640 static struct clk perfmon0_clk = {
4641         __INIT_CLK_DEBUG(perfmon0_clk)
4642         .parent = &mmdc_ch0_axi_clk[0],
4643         .enable = _clk_enable1,
4644         .enable_reg = MXC_CCM_CCGR4,
4645         .enable_shift = MXC_CCM_CCGRx_CG1_OFFSET,
4646         .disable = _clk_disable1,
4647 };
4648
4649 static struct clk perfmon1_clk = {
4650         __INIT_CLK_DEBUG(perfmon1_clk)
4651         .parent = &ipu1_clk,
4652         .enable = _clk_enable1,
4653         .enable_reg = MXC_CCM_CCGR4,
4654         .enable_shift = MXC_CCM_CCGRx_CG2_OFFSET,
4655         .disable = _clk_disable1,
4656 };
4657
4658 static struct clk perfmon2_clk = {
4659         __INIT_CLK_DEBUG(perfmon2_clk)
4660         .parent = &mmdc_ch0_axi_clk[0],
4661         .enable = _clk_enable1,
4662         .enable_reg = MXC_CCM_CCGR4,
4663         .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET,
4664         .disable = _clk_disable1,
4665 };
4666
4667 static struct clk dummy_clk = {
4668         .id = 0,
4669 };
4670
4671 #define _REGISTER_CLOCK(d, n, c) \
4672         { \
4673                 .dev_id = d, \
4674                 .con_id = n, \
4675                 .clk = &c, \
4676         }
4677
4678
4679 static struct clk_lookup lookups[] = {
4680         _REGISTER_CLOCK(NULL, "osc", osc_clk),
4681         _REGISTER_CLOCK(NULL, "ckih", ckih_clk),
4682         _REGISTER_CLOCK(NULL, "ckih2", ckih2_clk),
4683         _REGISTER_CLOCK(NULL, "ckil", ckil_clk),
4684         _REGISTER_CLOCK(NULL, "pll1_main_clk", pll1_sys_main_clk),
4685         _REGISTER_CLOCK(NULL, "pll1_sw_clk", pll1_sw_clk),
4686         _REGISTER_CLOCK(NULL, "pll2", pll2_528_bus_main_clk),
4687         _REGISTER_CLOCK(NULL, "pll2_pfd_400M", pll2_pfd_400M),
4688         _REGISTER_CLOCK(NULL, "pll2_pfd_352M", pll2_pfd_352M),
4689         _REGISTER_CLOCK(NULL, "pll2_pfd_594M", pll2_pfd_594M),
4690         _REGISTER_CLOCK(NULL, "pll2_200M", pll2_200M),
4691         _REGISTER_CLOCK(NULL, "pll3_main_clk", pll3_usb_otg_main_clk),
4692         _REGISTER_CLOCK(NULL, "pll3_pfd_508M", pll3_pfd_508M),
4693         _REGISTER_CLOCK(NULL, "pll3_pfd_454M", pll3_pfd_454M),
4694         _REGISTER_CLOCK(NULL, "pll3_pfd_720M", pll3_pfd_720M),
4695         _REGISTER_CLOCK(NULL, "pll3_pfd_540M", pll3_pfd_540M),
4696         _REGISTER_CLOCK(NULL, "pll3_sw_clk", pll3_sw_clk),
4697         _REGISTER_CLOCK(NULL, "pll3_120M", pll3_120M),
4698         _REGISTER_CLOCK(NULL, "pll3_120M", pll3_80M),
4699         _REGISTER_CLOCK(NULL, "pll3_120M", pll3_60M),
4700         _REGISTER_CLOCK(NULL, "pll4", pll4_audio_main_clk),
4701         _REGISTER_CLOCK(NULL, "pll5", pll5_video_main_clk),
4702         _REGISTER_CLOCK(NULL, "pll4", pll6_MLB_main_clk),
4703         _REGISTER_CLOCK(NULL, "pll3", pll7_usb_host_main_clk),
4704         _REGISTER_CLOCK(NULL, "pll4", pll8_enet_main_clk),
4705         _REGISTER_CLOCK(NULL, "cpu_clk", cpu_clk),
4706         _REGISTER_CLOCK(NULL, "periph_clk", periph_clk),
4707         _REGISTER_CLOCK(NULL, "axi_clk", axi_clk),
4708         _REGISTER_CLOCK(NULL, "mmdc_ch0_axi", mmdc_ch0_axi_clk[0]),
4709         _REGISTER_CLOCK(NULL, "mmdc_ch1_axi", mmdc_ch1_axi_clk[0]),
4710         _REGISTER_CLOCK(NULL, "ahb", ahb_clk),
4711         _REGISTER_CLOCK(NULL, "ipg_clk", ipg_clk),
4712         _REGISTER_CLOCK(NULL, "ipg_perclk", ipg_perclk),
4713         _REGISTER_CLOCK(NULL, "spba", spba_clk),
4714         _REGISTER_CLOCK("imx-sdma", NULL, sdma_clk[0]),
4715         _REGISTER_CLOCK(NULL, "gpu2d_axi_clk", gpu2d_axi_clk),
4716         _REGISTER_CLOCK(NULL, "gpu3d_axi_clk", gpu3d_axi_clk),
4717         _REGISTER_CLOCK(NULL, "pcie_axi_clk", pcie_axi_clk),
4718         _REGISTER_CLOCK(NULL, "vdo_axi_clk", vdo_axi_clk),
4719         _REGISTER_CLOCK(NULL, "iim_clk", iim_clk),
4720         _REGISTER_CLOCK(NULL, "i2c_clk", i2c_clk[0]),
4721         _REGISTER_CLOCK("imx-i2c.1", NULL, i2c_clk[1]),
4722         _REGISTER_CLOCK("imx-i2c.2", NULL, i2c_clk[2]),
4723         _REGISTER_CLOCK(NULL, "vpu_clk", vpu_clk[0]),
4724         _REGISTER_CLOCK(NULL, "ipu1_clk", ipu1_clk),
4725         _REGISTER_CLOCK(NULL, "ipu2_clk", ipu2_clk),
4726         _REGISTER_CLOCK(NULL, "cko1_clk0", cko1_clk0),
4727         _REGISTER_CLOCK("sdhci-esdhc-imx.0", NULL, usdhc1_clk),
4728         _REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL, usdhc2_clk),
4729         _REGISTER_CLOCK("sdhci-esdhc-imx.2", NULL, usdhc3_clk),
4730         _REGISTER_CLOCK("sdhci-esdhc-imx.3", NULL, usdhc4_clk),
4731         _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk),
4732         _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk),
4733         _REGISTER_CLOCK("imx-ssi.2", NULL, ssi3_clk),
4734         _REGISTER_CLOCK(NULL, "ipu1_di0_clk", ipu1_di_clk[0]),
4735         _REGISTER_CLOCK(NULL, "ipu1_di1_clk", ipu1_di_clk[1]),
4736         _REGISTER_CLOCK(NULL, "ipu2_di0_clk", ipu2_di_clk[0]),
4737         _REGISTER_CLOCK(NULL, "ipu2_di1_clk", ipu2_di_clk[1]),
4738         _REGISTER_CLOCK(NULL, "can_root_clk", can_clk_root),
4739         _REGISTER_CLOCK("imx6q-flexcan.0", NULL, can1_clk[0]),
4740         _REGISTER_CLOCK("imx6q-flexcan.1", NULL, can2_clk[0]),
4741         _REGISTER_CLOCK(NULL, "ldb_di0_clk", ldb_di0_clk),
4742         _REGISTER_CLOCK(NULL, "ldb_di1_clk", ldb_di1_clk),
4743         _REGISTER_CLOCK("mxc_spdif.0", NULL, spdif0_clk[0]),
4744         _REGISTER_CLOCK(NULL, "esai_clk", esai_clk),
4745         _REGISTER_CLOCK("imx6q-ecspi.0", NULL, ecspi_clk[0]),
4746         _REGISTER_CLOCK("imx6q-ecspi.1", NULL, ecspi_clk[1]),
4747         _REGISTER_CLOCK("imx6q-ecspi.2", NULL, ecspi_clk[2]),
4748         _REGISTER_CLOCK("imx6q-ecspi.3", NULL, ecspi_clk[3]),
4749         _REGISTER_CLOCK("imx6q-ecspi.4", NULL, ecspi_clk[4]),
4750         _REGISTER_CLOCK(NULL, "emi_slow_clk", emi_slow_clk),
4751         _REGISTER_CLOCK(NULL, "emi_clk", emi_clk),
4752         _REGISTER_CLOCK(NULL, "enfc_clk", enfc_clk),
4753         _REGISTER_CLOCK("imx-uart.0", NULL, uart_clk[0]),
4754         _REGISTER_CLOCK("imx-uart.1", NULL, uart_clk[0]),
4755         _REGISTER_CLOCK("imx-uart.2", NULL, uart_clk[0]),
4756         _REGISTER_CLOCK("imx-uart.3", NULL, uart_clk[0]),
4757         _REGISTER_CLOCK(NULL, "hsi_tx", hsi_tx_clk[0]),
4758         _REGISTER_CLOCK(NULL, "caam_clk", caam_clk[0]),
4759         _REGISTER_CLOCK(NULL, "asrc_clk", asrc_clk[0]),
4760         _REGISTER_CLOCK(NULL, "asrc_serial_clk", asrc_clk[1]),
4761         _REGISTER_CLOCK("mxs-dma-apbh", NULL, apbh_dma_clk),
4762         _REGISTER_CLOCK(NULL, "openvg_axi_clk", openvg_axi_clk),
4763         _REGISTER_CLOCK(NULL, "gpu3d_clk", gpu3d_core_clk[0]),
4764         _REGISTER_CLOCK(NULL, "gpu2d_clk", gpu2d_core_clk[0]),
4765         _REGISTER_CLOCK(NULL, "gpu3d_shader_clk", gpu3d_shader_clk),
4766         _REGISTER_CLOCK(NULL, "gpt", gpt_clk[0]),
4767         _REGISTER_CLOCK("imx6q-gpmi-nfc.0", NULL, gpmi_nfc_clk[0]),
4768         _REGISTER_CLOCK(NULL, "gpmi-apb", gpmi_nfc_clk[1]),
4769         _REGISTER_CLOCK(NULL, "bch", gpmi_nfc_clk[2]),
4770         _REGISTER_CLOCK(NULL, "bch-apb", gpmi_nfc_clk[3]),
4771         _REGISTER_CLOCK(NULL, "pl301_mx6qperl-bch", gpmi_nfc_clk[4]),
4772         _REGISTER_CLOCK("mxc_pwm.0", NULL, pwm_clk[0]),
4773         _REGISTER_CLOCK("mxc_pwm.1", NULL, pwm_clk[1]),
4774         _REGISTER_CLOCK("mxc_pwm.2", NULL, pwm_clk[2]),
4775         _REGISTER_CLOCK("mxc_pwm.3", NULL, pwm_clk[3]),
4776         _REGISTER_CLOCK(NULL, "pcie_clk", pcie_clk[0]),
4777         _REGISTER_CLOCK("fec.0", NULL, enet_clk[0]),
4778         _REGISTER_CLOCK(NULL, "imx_sata_clk", sata_clk[0]),
4779         _REGISTER_CLOCK(NULL, "usboh3_clk", usboh3_clk[0]),
4780         _REGISTER_CLOCK(NULL, "usb_phy1_clk", usb_phy1_clk),
4781         _REGISTER_CLOCK(NULL, "usb_phy3_clk", usb_phy3_clk),
4782         _REGISTER_CLOCK(NULL, "usb_phy4_clk", usb_phy4_clk),
4783         _REGISTER_CLOCK("imx2-wdt.0", NULL, dummy_clk),
4784         _REGISTER_CLOCK("imx2-wdt.1", NULL, dummy_clk),
4785         _REGISTER_CLOCK(NULL, "hdmi_isfr_clk", hdmi_clk[0]),
4786         _REGISTER_CLOCK(NULL, "hdmi_iahb_clk", hdmi_clk[1]),
4787         _REGISTER_CLOCK(NULL, "mipi_pllref_clk", mipi_pllref_clk),
4788         _REGISTER_CLOCK(NULL, NULL, vdoa_clk),
4789         _REGISTER_CLOCK(NULL, NULL, aips_tz2_clk),
4790         _REGISTER_CLOCK(NULL, NULL, aips_tz1_clk),
4791         _REGISTER_CLOCK(NULL, "clko_clk", clko_clk),
4792         _REGISTER_CLOCK("mxs-perfmon.0", "perfmon", perfmon0_clk),
4793         _REGISTER_CLOCK("mxs-perfmon.1", "perfmon", perfmon1_clk),
4794         _REGISTER_CLOCK("mxs-perfmon.2", "perfmon", perfmon2_clk),
4795 };
4796
4797
4798 static void clk_tree_init(void)
4799
4800 {
4801         unsigned int reg;
4802
4803         reg = __raw_readl(MMDC_MDMISC_OFFSET);
4804         if ((reg & MMDC_MDMISC_DDR_TYPE_MASK) ==
4805                 (0x1 << MMDC_MDMISC_DDR_TYPE_OFFSET)) {
4806                 clk_set_parent(&periph_clk, &pll2_pfd_400M);
4807                 printk(KERN_INFO "Set periph_clk's parent to pll2_pfd_400M!\n");
4808         }
4809 }
4810
4811
4812 int __init mx6_clocks_init(unsigned long ckil, unsigned long osc,
4813         unsigned long ckih1, unsigned long ckih2)
4814 {
4815         __iomem void *base;
4816         int i;
4817
4818         external_low_reference = ckil;
4819         external_high_reference = ckih1;
4820         ckih2_reference = ckih2;
4821         oscillator_reference = osc;
4822
4823         apll_base = ioremap(ANATOP_BASE_ADDR, SZ_4K);
4824
4825         for (i = 0; i < ARRAY_SIZE(lookups); i++) {
4826                 clkdev_add(&lookups[i]);
4827                 clk_debug_register(lookups[i].clk);
4828         }
4829
4830         /* Disable un-necessary PFDs & PLLs */
4831
4832         /* keep correct count. */
4833         clk_enable(&cpu_clk);
4834         clk_enable(&periph_clk);
4835
4836         clk_tree_init();
4837
4838         if (pll2_pfd_400M.usecount == 0)
4839                 pll2_pfd_400M.disable(&pll2_pfd_400M);
4840         pll2_pfd_352M.disable(&pll2_pfd_352M);
4841         pll2_pfd_594M.disable(&pll2_pfd_594M);
4842
4843 #if !defined(CONFIG_FEC_1588)
4844         pll3_pfd_454M.disable(&pll3_pfd_454M);
4845         pll3_pfd_508M.disable(&pll3_pfd_508M);
4846         pll3_pfd_540M.disable(&pll3_pfd_540M);
4847         pll3_pfd_720M.disable(&pll3_pfd_720M);
4848
4849         pll3_usb_otg_main_clk.disable(&pll3_usb_otg_main_clk);
4850 #endif
4851         pll4_audio_main_clk.disable(&pll4_audio_main_clk);
4852         pll5_video_main_clk.disable(&pll5_video_main_clk);
4853         pll6_MLB_main_clk.disable(&pll6_MLB_main_clk);
4854         pll7_usb_host_main_clk.disable(&pll7_usb_host_main_clk);
4855         pll8_enet_main_clk.disable(&pll8_enet_main_clk);
4856
4857         sata_clk[0].disable(&sata_clk[0]);
4858         pcie_clk[0].disable(&pcie_clk[0]);
4859
4860         /* Initialize Audio and Video PLLs to valid frequency (650MHz). */
4861         clk_set_rate(&pll4_audio_main_clk, 650000000);
4862         clk_set_rate(&pll5_video_main_clk, 650000000);
4863
4864         clk_set_parent(&ipu1_di_clk[0], &pll5_video_main_clk);
4865         clk_set_parent(&ipu1_di_clk[1], &pll5_video_main_clk);
4866         clk_set_parent(&ipu2_di_clk[0], &pll5_video_main_clk);
4867         clk_set_parent(&ipu2_di_clk[1], &pll5_video_main_clk);
4868
4869         clk_set_parent(&cko1_clk0, &ipg_clk);
4870         clk_set_rate(&cko1_clk0, 22000000);
4871         clk_enable(&cko1_clk0);
4872
4873         clk_set_parent(&emi_clk, &pll2_pfd_400M);
4874         clk_set_rate(&emi_clk, 200000000);
4875
4876         clk_set_parent(&gpu3d_shader_clk, &pll2_pfd_594M);
4877         clk_set_rate(&gpu3d_shader_clk, 594000000);
4878         clk_set_parent(&gpu3d_core_clk[0], &mmdc_ch0_axi_clk[0]);
4879         clk_set_rate(&gpu3d_core_clk[0], 528000000);
4880
4881         /*
4882          * FIXME: asrc needs to use asrc_serial(spdif1) clock to do sample
4883          * rate convertion and this clock frequency can not be too high, set
4884          * it to the minimum value 7.5Mhz to make asrc work properly.
4885          */
4886         clk_set_parent(&asrc_clk[1], &pll3_sw_clk);
4887         clk_set_rate(&asrc_clk[1], 7500000);
4888
4889         /* set the NAND to 11MHz. Too fast will cause dma timeout. */
4890         clk_set_rate(&enfc_clk, enfc_clk.round_rate(&enfc_clk, 11000000));
4891
4892         mx6_cpu_op_init();
4893         cpu_op_tbl = get_cpu_op(&cpu_op_nr);
4894
4895         /* Gate off all possible clocks */
4896         if (mxc_jtag_enabled) {
4897                 __raw_writel(3 << MXC_CCM_CCGRx_CG11_OFFSET |
4898                              3 << MXC_CCM_CCGRx_CG2_OFFSET |
4899                              3 << MXC_CCM_CCGRx_CG1_OFFSET |
4900                              3 << MXC_CCM_CCGRx_CG0_OFFSET, MXC_CCM_CCGR0);
4901         } else {
4902                 __raw_writel(1 << MXC_CCM_CCGRx_CG11_OFFSET |
4903                              3 << MXC_CCM_CCGRx_CG2_OFFSET |
4904                              3 << MXC_CCM_CCGRx_CG1_OFFSET |
4905                              3 << MXC_CCM_CCGRx_CG0_OFFSET, MXC_CCM_CCGR0);
4906         }
4907         __raw_writel(3 << MXC_CCM_CCGRx_CG10_OFFSET, MXC_CCM_CCGR1);
4908         __raw_writel(1 << MXC_CCM_CCGRx_CG12_OFFSET |
4909                      1 << MXC_CCM_CCGRx_CG11_OFFSET |
4910                      3 << MXC_CCM_CCGRx_CG10_OFFSET |
4911                      3 << MXC_CCM_CCGRx_CG9_OFFSET |
4912                      3 << MXC_CCM_CCGRx_CG8_OFFSET, MXC_CCM_CCGR2);
4913         __raw_writel(1 << MXC_CCM_CCGRx_CG14_OFFSET |
4914                      3 << MXC_CCM_CCGRx_CG13_OFFSET |
4915                      3 << MXC_CCM_CCGRx_CG12_OFFSET |
4916                      3 << MXC_CCM_CCGRx_CG11_OFFSET |
4917                      3 << MXC_CCM_CCGRx_CG10_OFFSET, MXC_CCM_CCGR3);
4918         __raw_writel(3 << MXC_CCM_CCGRx_CG7_OFFSET |
4919                         1 << MXC_CCM_CCGRx_CG6_OFFSET |
4920                         1 << MXC_CCM_CCGRx_CG4_OFFSET, MXC_CCM_CCGR4);
4921         __raw_writel(1 << MXC_CCM_CCGRx_CG0_OFFSET, MXC_CCM_CCGR5);
4922
4923         __raw_writel(0, MXC_CCM_CCGR6);
4924
4925         /* Lower the ipg_perclk frequency to 8.25MHz. */
4926         clk_set_rate(&ipg_perclk, 8250000);
4927
4928         /* S/PDIF */
4929         clk_set_parent(&spdif0_clk[0], &pll3_pfd_454M);
4930
4931         base = ioremap(GPT_BASE_ADDR, SZ_4K);
4932         mxc_timer_init(&gpt_clk[0], base, MXC_INT_GPT);
4933
4934         /* Set the core to max frequency requested. */
4935         mx6_set_cpu_voltage(cpu_op_tbl[0].cpu_voltage);
4936         clk_set_rate(&cpu_clk, cpu_op_tbl[0].pll_rate);
4937
4938         lp_high_freq = 0;
4939         lp_med_freq = 0;
4940
4941         return 0;
4942
4943 }