arch/arm/mach-mx6/clock.c

   1
   2 /*
   3  * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
   4  */
   5
   6 /*
   7  * The code contained herein is licensed under the GNU General Public
   8  * License. You may obtain a copy of the GNU General Public License
   9  * Version 2 or later at the following locations:
  10  *
  11  * http://www.opensource.org/licenses/gpl-license.html
  12  * http://www.gnu.org/copyleft/gpl.html
  13  */
  14
  15 #include <linux/kernel.h>
  16 #include <linux/init.h>
  17 #include <linux/types.h>
  18 #include <linux/time.h>
  19 #include <linux/hrtimer.h>
  20 #include <linux/mm.h>
  21 #include <linux/errno.h>
  22 #include <linux/delay.h>
  23 #include <linux/clk.h>
  24 #include <linux/io.h>
  25 #include <linux/clkdev.h>
  26 #include <asm/div64.h>
  27 #include <mach/hardware.h>
  28 #include <mach/common.h>
  29 #include <mach/clock.h>
  30 #include <mach/mxc_dvfs.h>
  31 #include "crm_regs.h"
  32
  33 #ifdef CONFIG_CLK_DEBUG
  34 #define __INIT_CLK_DEBUG(n)     .name = #n,
  35 #else
  36 #define __INIT_CLK_DEBUG(n)
  37 #endif
  38
  39 void __iomem *apll_base;
  40 static struct clk pll1_sys_main_clk;
  41 static struct clk pll2_528_bus_main_clk;
  42 static struct clk pll3_usb_otg_main_clk;
  43 static struct clk pll4_audio_main_clk;
  44 static struct clk pll5_video_main_clk;
  45 static struct clk pll6_MLB_main_clk;
  46 static struct clk pll7_usb_host_main_clk;
  47 static struct clk pll8_enet_main_clk;
  48 static struct clk apbh_dma_clk;
  49
  50 #define SPIN_DELAY      1000000 /* in nanoseconds */
  51
  52 #define WAIT(exp, timeout) \
  53 ({ \
  54         struct timespec nstimeofday; \
  55         struct timespec curtime; \
  56         int result = 1; \
  57         getnstimeofday(&nstimeofday); \
  58         while (!(exp)) { \
  59                 getnstimeofday(&curtime); \
  60                 if ((curtime.tv_nsec - nstimeofday.tv_nsec) > (timeout)) { \
  61                         result = 0; \
  62                         break; \
  63                 } \
  64         } \
  65         result; \
  66 })
  67
  68 /* External clock values passed-in by the board code */
  69 static unsigned long external_high_reference, external_low_reference;
  70 static unsigned long oscillator_reference, ckih2_reference;
  71
  72 static void __calc_pre_post_dividers(u32 div, u32 *pre, u32 *post)
  73 {
  74         u32 min_pre, temp_pre, old_err, err;
  75
  76         if (div >= 512) {
  77                 *pre = 8;
  78                 *post = 64;
  79         } else if (div >= 8) {
  80                 min_pre = (div - 1) / 64 + 1;
  81                 old_err = 8;
  82                 for (temp_pre = 8; temp_pre >= min_pre; temp_pre--) {
  83                         err = div % temp_pre;
  84                         if (err == 0) {
  85                                 *pre = temp_pre;
  86                                 break;
  87                         }
  88                         err = temp_pre - err;
  89                         if (err < old_err) {
  90                                 old_err = err;
  91                                 *pre = temp_pre;
  92                         }
  93                 }
  94                 *post = (div + *pre - 1) / *pre;
  95         } else if (div < 8) {
  96                 *pre = div;
  97                 *post = 1;
  98         }
  99 }
 100
 101 static int _clk_enable(struct clk *clk)
 102 {
 103         u32 reg;
 104         reg = __raw_readl(clk->enable_reg);
 105         reg |= MXC_CCM_CCGRx_CG_MASK << clk->enable_shift;
 106         __raw_writel(reg, clk->enable_reg);
 107
 108         return 0;
 109 }
 110
 111 static void _clk_disable(struct clk *clk)
 112 {
 113         u32 reg;
 114         reg = __raw_readl(clk->enable_reg);
 115         reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift);
 116         /* TODO: un-comment the disable code */
 117         /* __raw_writel(reg, clk->enable_reg); */
 118
 119 }
 120
 121 static void _clk_disable_inwait(struct clk *clk)
 122 {
 123         u32 reg;
 124         reg = __raw_readl(clk->enable_reg);
 125         reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift);
 126         reg |= 1 << clk->enable_shift;
 127         /* TODO: un-comment the disable code */
 128         /* __raw_writel(reg, clk->enable_reg); */
 129 }
 130
 131 /*
 132  * For the 4-to-1 muxed input clock
 133  */
 134 static inline u32 _get_mux(struct clk *parent, struct clk *m0,
 135                            struct clk *m1, struct clk *m2, struct clk *m3)
 136 {
 137         if (parent == m0)
 138                 return 0;
 139         else if (parent == m1)
 140                 return 1;
 141         else if (parent == m2)
 142                 return 2;
 143         else if (parent == m3)
 144                 return 3;
 145         else
 146                 BUG();
 147
 148         return 0;
 149 }
 150
 151 static inline void __iomem *_get_pll_base(struct clk *pll)
 152 {
 153         if (pll == &pll1_sys_main_clk)
 154                 return PLL1_SYS_BASE_ADDR;
 155         else if (pll == &pll2_528_bus_main_clk)
 156                 return PLL2_528_BASE_ADDR;
 157         else if (pll == &pll3_usb_otg_main_clk)
 158                 return PLL3_480_USB1_BASE_ADDR;
 159         else if (pll == &pll4_audio_main_clk)
 160                 return PLL4_AUDIO_BASE_ADDR;
 161         else if (pll == &pll5_video_main_clk)
 162                 return PLL5_VIDEO_BASE_ADDR;
 163         else if (pll == &pll6_MLB_main_clk)
 164                 return PLL6_MLB_BASE_ADDR;
 165         else if (pll == &pll7_usb_host_main_clk)
 166                 return PLL7_480_USB2_BASE_ADDR;
 167         else if (pll == &pll8_enet_main_clk)
 168                 return PLL8_ENET_BASE_ADDR;
 169         else
 170                 BUG();
 171         return NULL;
 172 }
 173
 174
 175 /*
 176  * For the 6-to-1 muxed input clock
 177  */
 178 static inline u32 _get_mux6(struct clk *parent, struct clk *m0, struct clk *m1,
 179                             struct clk *m2, struct clk *m3, struct clk *m4,
 180                             struct clk *m5)
 181 {
 182         if (parent == m0)
 183                 return 0;
 184         else if (parent == m1)
 185                 return 1;
 186         else if (parent == m2)
 187                 return 2;
 188         else if (parent == m3)
 189                 return 3;
 190         else if (parent == m4)
 191                 return 4;
 192         else if (parent == m5)
 193                 return 5;
 194         else
 195                 BUG();
 196
 197         return 0;
 198 }
 199 static unsigned long get_high_reference_clock_rate(struct clk *clk)
 200 {
 201         return external_high_reference;
 202 }
 203
 204 static unsigned long get_low_reference_clock_rate(struct clk *clk)
 205 {
 206         return external_low_reference;
 207 }
 208
 209 static unsigned long get_oscillator_reference_clock_rate(struct clk *clk)
 210 {
 211         return oscillator_reference;
 212 }
 213
 214 static unsigned long get_ckih2_reference_clock_rate(struct clk *clk)
 215 {
 216         return ckih2_reference;
 217 }
 218
 219 /* External high frequency clock */
 220 static struct clk ckih_clk = {
 221         __INIT_CLK_DEBUG(ckih_clk)
 222         .get_rate = get_high_reference_clock_rate,
 223 };
 224
 225 static struct clk ckih2_clk = {
 226         __INIT_CLK_DEBUG(ckih2_clk)
 227         .get_rate = get_ckih2_reference_clock_rate,
 228 };
 229
 230 static struct clk osc_clk = {
 231         __INIT_CLK_DEBUG(osc_clk)
 232         .get_rate = get_oscillator_reference_clock_rate,
 233 };
 234
 235 /* External low frequency (32kHz) clock */
 236 static struct clk ckil_clk = {
 237         __INIT_CLK_DEBUG(ckil_clk)
 238         .get_rate = get_low_reference_clock_rate,
 239 };
 240
 241 static unsigned long pfd_round_rate(struct clk *clk, unsigned long rate)
 242 {
 243         u32 frac;
 244         u64 tmp;
 245
 246         tmp = (u64)clk_get_rate(clk->parent) * 18;
 247         do_div(tmp, rate);
 248         frac = tmp;
 249         frac = frac < 18 ? 18 : frac;
 250         frac = frac > 35 ? 35 : frac;
 251         do_div(tmp, frac);
 252         return tmp;
 253 }
 254
 255 static unsigned long pfd_get_rate(struct clk *clk)
 256 {
 257         u32 frac;
 258         u64 tmp;
 259         tmp = (u64)clk_get_rate(clk->parent) * 18;
 260
 261         if (apbh_dma_clk.usecount == 0)
 262                 apbh_dma_clk.enable(&apbh_dma_clk);
 263
 264         frac = (__raw_readl(clk->enable_reg) >> clk->enable_shift) &
 265                         ANADIG_PFD_FRAC_MASK;
 266
 267         do_div(tmp, frac);
 268
 269         return tmp;
 270 }
 271
 272 static int pfd_set_rate(struct clk *clk, unsigned long rate)
 273 {
 274         u32 frac;
 275         u64 tmp;
 276         tmp = (u64)clk_get_rate(clk->parent) * 18;
 277
 278         if (apbh_dma_clk.usecount == 0)
 279                 apbh_dma_clk.enable(&apbh_dma_clk);
 280
 281         /* Round up the divider so that we don't set a rate
 282           * higher than what is requested. */
 283         tmp += rate/2;
 284         do_div(tmp, rate);
 285         frac = tmp;
 286         frac = frac < 12 ? 12 : frac;
 287         frac = frac > 35 ? 35 : frac;
 288         /* clear clk frac bits */
 289         __raw_writel(ANADIG_PFD_FRAC_MASK << clk->enable_shift,
 290                         (int)clk->enable_reg + 8);
 291         /* set clk frac bits */
 292         __raw_writel(frac << clk->enable_shift,
 293                         (int)clk->enable_reg + 4);
 294
 295         tmp = (u64)clk_get_rate(clk->parent) * 18;
 296         do_div(tmp, frac);
 297
 298         if (apbh_dma_clk.usecount == 0)
 299                 apbh_dma_clk.disable(&apbh_dma_clk);
 300         return 0;
 301 }
 302
 303 static int _clk_pfd_enable(struct clk *clk)
 304 {
 305         if (apbh_dma_clk.usecount == 0)
 306                 apbh_dma_clk.enable(&apbh_dma_clk);
 307
 308         /* clear clk gate bit */
 309         __raw_writel((1 << (clk->enable_shift + 7)),
 310                         (int)clk->enable_reg + 8);
 311
 312         if (apbh_dma_clk.usecount == 0)
 313                 apbh_dma_clk.disable(&apbh_dma_clk);
 314
 315         return 0;
 316 }
 317
 318 static void _clk_pfd_disable(struct clk *clk)
 319 {
 320         if (apbh_dma_clk.usecount == 0)
 321                 apbh_dma_clk.enable(&apbh_dma_clk);
 322
 323         /* set clk gate bit */
 324         __raw_writel((1 << (clk->enable_shift + 7)),
 325                         (int)clk->enable_reg + 4);
 326
 327         if (apbh_dma_clk.usecount == 0)
 328                 apbh_dma_clk.disable(&apbh_dma_clk);
 329 }
 330
 331 static void _clk_usb_phy_enable(struct clk *clk)
 332 {
 333         u32 usb_phy_reg;
 334         usb_phy_reg = __raw_readl(clk->enable_reg);
 335         __raw_writel(usb_phy_reg | clk->enable_shift, clk->enable_reg);
 336 }
 337
 338 static void _clk_usb_phy_disable(struct clk *clk)
 339 {
 340         u32 usb_phy_reg;
 341         usb_phy_reg = __raw_readl(clk->enable_reg);
 342         __raw_writel(usb_phy_reg & (~clk->enable_shift), clk->enable_reg);
 343 }
 344
 345 static int _clk_pll_enable(struct clk *clk)
 346 {
 347         unsigned int reg;
 348         void __iomem *pllbase;
 349
 350         pllbase = _get_pll_base(clk);
 351
 352         reg = __raw_readl(pllbase);
 353         reg &= ~ANADIG_PLL_BYPASS;
 354         reg &= ~ANADIG_PLL_POWER_DOWN;
 355
 356         /* The 480MHz PLLs have the opposite definition for power bit. */
 357         if (clk == &pll3_usb_otg_main_clk || clk == &pll7_usb_host_main_clk)
 358                 reg |= ANADIG_PLL_POWER_DOWN;
 359
 360         __raw_writel(reg, pllbase);
 361
 362         /* Wait for PLL to lock */
 363         if (!WAIT(__raw_readl(pllbase) & ANADIG_PLL_LOCK,
 364                                 SPIN_DELAY))
 365                 panic("pll enable failed\n");
 366
 367         /* Enable the PLL output now*/
 368         reg = __raw_readl(pllbase);
 369         reg |= ANADIG_PLL_ENABLE;
 370         __raw_writel(reg, pllbase);
 371
 372         return 0;
 373 }
 374
 375 static void _clk_pll_disable(struct clk *clk)
 376 {
 377         unsigned int reg;
 378         void __iomem *pllbase;
 379
 380         pllbase = _get_pll_base(clk);
 381
 382         reg = __raw_readl(pllbase);
 383         reg &= ~ANADIG_PLL_ENABLE;
 384         reg |= ANADIG_PLL_BYPASS;
 385         reg |= ANADIG_PLL_POWER_DOWN;
 386         if (clk == &pll3_usb_otg_main_clk || clk == &pll7_usb_host_main_clk)
 387                 reg &= ~ANADIG_PLL_POWER_DOWN;
 388         __raw_writel(reg, pllbase);
 389 }
 390
 391 static unsigned long  _clk_pll1_main_get_rate(struct clk *clk)
 392 {
 393         unsigned int div;
 394         unsigned long val;
 395
 396         div = __raw_readl(PLL1_SYS_BASE_ADDR) & ANADIG_PLL_SYS_DIV_SELECT_MASK;
 397         val = (clk_get_rate(clk->parent) * div) / 2;
 398         return val;
 399 }
 400
 401 static int _clk_pll1_main_set_rate(struct clk *clk, unsigned long rate)
 402 {
 403         unsigned int reg,  div;
 404
 405         if (rate/1000 < 650000 || rate/1000 > 1300000000)
 406                 return -EINVAL;
 407
 408         div = (rate * 2) / clk_get_rate(clk->parent) ;
 409
 410         reg = __raw_readl(PLL1_SYS_BASE_ADDR) & ~ANADIG_PLL_SYS_DIV_SELECT_MASK;
 411         reg |= div;
 412         __raw_writel(reg, PLL1_SYS_BASE_ADDR);
 413
 414         return 0;
 415 }
 416
 417 static struct clk pll1_sys_main_clk = {
 418         __INIT_CLK_DEBUG(pll1_sys_main_clk)
 419         .parent = &osc_clk,
 420         .get_rate = _clk_pll1_main_get_rate,
 421         .set_rate = _clk_pll1_main_set_rate,
 422         .enable = _clk_pll_enable,
 423         .disable = _clk_pll_disable,
 424 };
 425
 426 static int _clk_pll1_sw_set_parent(struct clk *clk, struct clk *parent)
 427 {
 428         u32 reg;
 429
 430         reg = __raw_readl(MXC_CCM_CCSR);
 431
 432         if (parent == &pll1_sys_main_clk) {
 433                 reg &= ~MXC_CCM_CCSR_PLL1_SW_CLK_SEL;
 434                 __raw_writel(reg, MXC_CCM_CCSR);
 435                 /* Set the step_clk parent to be lp_apm, to save power. */
 436                 reg = __raw_readl(MXC_CCM_CCSR);
 437                 reg = (reg & ~MXC_CCM_CCSR_STEP_SEL);
 438         } else {
 439                 /* Set STEP_CLK to be the parent*/
 440                 if (parent == &osc_clk) {
 441                         /* Set STEP_CLK to be sourced from LPAPM. */
 442                         reg = __raw_readl(MXC_CCM_CCSR);
 443                         reg = (reg & ~MXC_CCM_CCSR_STEP_SEL);
 444                         __raw_writel(reg, MXC_CCM_CCSR);
 445                 } else {
 446                         /* Set STEP_CLK to be sourced from PLL2-PDF (400MHz). */
 447                         reg = __raw_readl(MXC_CCM_CCSR);
 448                         reg |= MXC_CCM_CCSR_STEP_SEL;
 449                         __raw_writel(reg, MXC_CCM_CCSR);
 450
 451                 }
 452                 reg = __raw_readl(MXC_CCM_CCSR);
 453                 reg |= MXC_CCM_CCSR_PLL1_SW_CLK_SEL;
 454                 reg = __raw_readl(MXC_CCM_CCSR);
 455         }
 456         __raw_writel(reg, MXC_CCM_CCSR);
 457
 458         return 0;
 459 }
 460
 461 static unsigned long _clk_pll1_sw_get_rate(struct clk *clk)
 462 {
 463         return clk_get_rate(clk->parent);
 464 }
 465
 466 static struct clk pll1_sw_clk = {
 467         __INIT_CLK_DEBUG(pll1_sw_clk)
 468         .parent = &pll1_sys_main_clk,
 469         .set_parent = _clk_pll1_sw_set_parent,
 470         .get_rate = _clk_pll1_sw_get_rate,
 471 };
 472
 473 static unsigned long _clk_pll2_main_get_rate(struct clk *clk)
 474 {
 475         unsigned int div;
 476         unsigned long val;
 477
 478         div = __raw_readl(PLL2_528_BASE_ADDR) & ANADIG_PLL_528_DIV_SELECT;
 479
 480         if (div == 1)
 481                 val = clk_get_rate(clk->parent) * 22;
 482
 483         else
 484                 val = clk_get_rate(clk->parent) * 20;
 485
 486         return val;
 487 }
 488
 489 static int _clk_pll2_main_set_rate(struct clk *clk, unsigned long rate)
 490 {
 491         unsigned int reg,  div;
 492
 493         if (rate == 528000000)
 494                 div = 1;
 495         else if (rate == 480000000)
 496                 div = 0;
 497         else
 498                 return -EINVAL;
 499
 500         reg = __raw_readl(PLL2_528_BASE_ADDR);
 501         reg &= ~ANADIG_PLL_528_DIV_SELECT;
 502         reg |= div;
 503         __raw_writel(reg, PLL2_528_BASE_ADDR);
 504
 505         return 0;
 506 }
 507
 508 static struct clk pll2_528_bus_main_clk = {
 509         __INIT_CLK_DEBUG(pll2_528_bus_main_clk)
 510         .parent = &osc_clk,
 511         .get_rate = _clk_pll2_main_get_rate,
 512         .set_rate = _clk_pll2_main_set_rate,
 513         .enable = _clk_pll_enable,
 514         .disable = _clk_pll_disable,
 515 };
 516
 517 static struct clk pll2_pfd_400M = {
 518         __INIT_CLK_DEBUG(pll2_pfd_400M)
 519         .parent = &pll2_528_bus_main_clk,
 520         .enable_reg = (void *)PFD_528_BASE_ADDR,
 521         .enable_shift = ANADIG_PFD2_FRAC_OFFSET,
 522         .enable = _clk_pfd_enable,
 523         .disable = _clk_pfd_disable,
 524         .get_rate = pfd_get_rate,
 525         .set_rate = pfd_set_rate,
 526         .get_rate = pfd_get_rate,
 527         .round_rate = pfd_round_rate,
 528 };
 529
 530 static struct clk pll2_pfd_352M = {
 531         __INIT_CLK_DEBUG(pll2_pfd_352M)
 532         .parent = &pll2_528_bus_main_clk,
 533         .enable_reg = (void *)PFD_528_BASE_ADDR,
 534         .enable_shift = ANADIG_PFD0_FRAC_OFFSET,
 535         .enable = _clk_pfd_enable,
 536         .disable = _clk_pfd_disable,
 537         .set_rate = pfd_set_rate,
 538         .get_rate = pfd_get_rate,
 539         .round_rate = pfd_round_rate,
 540 };
 541
 542 static struct clk pll2_pfd_594M = {
 543         __INIT_CLK_DEBUG(pll2_pfd_594M)
 544         .parent = &pll2_528_bus_main_clk,
 545         .enable_reg = (void *)PFD_528_BASE_ADDR,
 546         .enable_shift = ANADIG_PFD1_FRAC_OFFSET,
 547         .enable = _clk_pfd_enable,
 548         .disable = _clk_pfd_disable,
 549         .set_rate = pfd_set_rate,
 550         .get_rate = pfd_get_rate,
 551         .round_rate = pfd_round_rate,
 552 };
 553
 554 static unsigned long _clk_pll2_200M_get_rate(struct clk *clk)
 555 {
 556         return clk_get_rate(clk->parent) / 2;
 557 }
 558
 559 static struct clk pll2_200M = {
 560         __INIT_CLK_DEBUG(pll2_200M)
 561         .parent = &pll2_pfd_400M,
 562         .get_rate = _clk_pll2_200M_get_rate,
 563 };
 564
 565 static unsigned long _clk_pll3_usb_otg_get_rate(struct clk *clk)
 566 {
 567         unsigned int div;
 568         unsigned long val;
 569
 570         div = __raw_readl(PLL3_480_USB1_BASE_ADDR)
 571                 & ANADIG_PLL_480_DIV_SELECT_MASK;
 572
 573         if (div == 1)
 574                 val = clk_get_rate(clk->parent) * 22;
 575         else
 576                 val = clk_get_rate(clk->parent) * 20;
 577         return val;
 578 }
 579
 580 static int _clk_pll3_usb_otg_set_rate(struct clk *clk, unsigned long rate)
 581 {
 582         unsigned int reg,  div;
 583
 584         if (rate == 528000000)
 585                 div = 1;
 586         else if (rate == 480000000)
 587                 div = 0;
 588         else
 589                 return -EINVAL;
 590
 591         reg = __raw_readl(PLL3_480_USB1_BASE_ADDR);
 592         reg &= ~ANADIG_PLL_480_DIV_SELECT_MASK;
 593         reg |= div;
 594         __raw_writel(reg, PLL3_480_USB1_BASE_ADDR);
 595
 596         return 0;
 597 }
 598
 599
 600 /* same as pll3_main_clk. These two clocks should always be the same */
 601 static struct clk pll3_usb_otg_main_clk = {
 602         __INIT_CLK_DEBUG(pll3_usb_otg_main_clk)
 603         .parent = &osc_clk,
 604         .enable = _clk_pll_enable,
 605         .disable = _clk_pll_disable,
 606         .set_rate = _clk_pll3_usb_otg_set_rate,
 607         .get_rate = _clk_pll3_usb_otg_get_rate,
 608 };
 609
 610 static struct clk usb_phy1_clk = {
 611         __INIT_CLK_DEBUG(usb_phy1_clk)
 612         .parent = &pll3_usb_otg_main_clk,
 613         .enable = _clk_usb_phy_enable,
 614         .disable = _clk_usb_phy_disable,
 615         .enable_reg = (void *)PLL3_480_USB1_BASE_ADDR,
 616         .enable_shift = ANADIG_PLL_480_EN_USB_CLKS,
 617         .set_rate = _clk_pll3_usb_otg_set_rate,
 618         .get_rate = _clk_pll3_usb_otg_get_rate,
 619
 620 };
 621
 622 static struct clk pll3_pfd_508M = {
 623         __INIT_CLK_DEBUG(pll3_pfd_508M)
 624         .parent = &pll3_usb_otg_main_clk,
 625         .enable_reg = (void *)PFD_480_BASE_ADDR,
 626         .enable_shift = ANADIG_PFD2_FRAC_OFFSET,
 627         .enable = _clk_pfd_enable,
 628         .disable = _clk_pfd_disable,
 629         .set_rate = pfd_set_rate,
 630         .round_rate = pfd_round_rate,
 631 };
 632
 633 static struct clk pll3_pfd_454M = {
 634         __INIT_CLK_DEBUG(pll3_pfd_454M)
 635         .parent = &pll3_usb_otg_main_clk,
 636         .enable_reg = (void *)PFD_480_BASE_ADDR,
 637         .enable_shift = ANADIG_PFD3_FRAC_OFFSET,
 638         .enable = _clk_pfd_enable,
 639         .disable = _clk_pfd_disable,
 640         .set_rate = pfd_set_rate,
 641         .get_rate = pfd_get_rate,
 642         .round_rate = pfd_round_rate,
 643 };
 644
 645 static struct clk pll3_pfd_720M = {
 646         __INIT_CLK_DEBUG(pll3_pfd_720M)
 647         .parent = &pll3_usb_otg_main_clk,
 648         .enable_reg = (void *)PFD_480_BASE_ADDR,
 649         .enable_shift = ANADIG_PFD0_FRAC_OFFSET,
 650         .enable = _clk_pfd_enable,
 651         .disable = _clk_pfd_disable,
 652         .set_rate = pfd_set_rate,
 653         .get_rate = pfd_get_rate,
 654         .round_rate = pfd_round_rate,
 655 };
 656
 657 static struct clk pll3_pfd_540M = {
 658         __INIT_CLK_DEBUG(pll3_pfd_540M)
 659         .parent = &pll3_usb_otg_main_clk,
 660         .enable_reg = (void *)PFD_480_BASE_ADDR,
 661         .enable_shift = ANADIG_PFD1_FRAC_OFFSET,
 662         .enable = _clk_pfd_enable,
 663         .disable = _clk_pfd_disable,
 664         .set_rate = pfd_set_rate,
 665         .get_rate = pfd_get_rate,
 666         .round_rate = pfd_round_rate,
 667         .get_rate = pfd_get_rate,
 668 };
 669
 670 static unsigned long _clk_pll3_sw_get_rate(struct clk *clk)
 671 {
 672         return clk_get_rate(clk->parent);
 673 }
 674
 675 /* same as pll3_main_clk. These two clocks should always be the same */
 676 static struct clk pll3_sw_clk = {
 677         __INIT_CLK_DEBUG(pll3_sw_clk)
 678         .parent = &pll3_usb_otg_main_clk,
 679         .get_rate = _clk_pll3_sw_get_rate,
 680 };
 681
 682 static unsigned long _clk_pll3_120M_get_rate(struct clk *clk)
 683 {
 684         return clk_get_rate(clk->parent) / 4;
 685 }
 686
 687 static struct clk pll3_120M = {
 688         __INIT_CLK_DEBUG(pll3_120M)
 689         .parent = &pll3_sw_clk,
 690         .get_rate = _clk_pll3_120M_get_rate,
 691 };
 692
 693 static unsigned long _clk_pll3_80M_get_rate(struct clk *clk)
 694 {
 695         return clk_get_rate(clk->parent) / 6;
 696 }
 697
 698 static struct clk pll3_80M = {
 699         __INIT_CLK_DEBUG(pll3_80M)
 700         .parent = &pll3_sw_clk,
 701         .get_rate = _clk_pll3_80M_get_rate,
 702 };
 703
 704 static unsigned long _clk_pll3_60M_get_rate(struct clk *clk)
 705 {
 706         return clk_get_rate(clk->parent) / 8;
 707 }
 708
 709 static struct clk pll3_60M = {
 710         __INIT_CLK_DEBUG(pll3_60M)
 711         .parent = &pll3_sw_clk,
 712         .get_rate = _clk_pll3_60M_get_rate,
 713 };
 714
 715 static struct clk pll4_audio_main_clk = {
 716         __INIT_CLK_DEBUG(pll4_audio_main_clk)
 717         .parent = &osc_clk,
 718         .enable = _clk_pll_enable,
 719         .disable = _clk_pll_disable,
 720 };
 721
 722 static struct clk pll5_video_main_clk = {
 723         __INIT_CLK_DEBUG(pll5_video_main_clk)
 724         .parent = &osc_clk,
 725         .enable = _clk_pll_enable,
 726         .disable = _clk_pll_disable,
 727 };
 728
 729 static struct clk pll6_MLB_main_clk = {
 730         __INIT_CLK_DEBUG(pll6_MLB_main_clk)
 731         .parent = &osc_clk,
 732         .enable = _clk_pll_enable,
 733         .disable = _clk_pll_disable,
 734 };
 735
 736 static unsigned long _clk_pll7_usb_otg_get_rate(struct clk *clk)
 737 {
 738         unsigned int div;
 739         unsigned long val;
 740
 741         div = __raw_readl(PLL7_480_USB2_BASE_ADDR)
 742                 & ANADIG_PLL_480_DIV_SELECT_MASK;
 743
 744         if (div == 1)
 745                 val = clk_get_rate(clk->parent) * 22;
 746         else
 747                 val = clk_get_rate(clk->parent) * 20;
 748         return val;
 749 }
 750
 751 static int _clk_pll7_usb_otg_set_rate(struct clk *clk, unsigned long rate)
 752 {
 753         unsigned int reg,  div;
 754
 755         if (rate == 528000000)
 756                 div = 1;
 757         else if (rate == 480000000)
 758                 div = 0;
 759         else
 760                 return -EINVAL;
 761
 762         reg = __raw_readl(PLL7_480_USB2_BASE_ADDR);
 763         reg &= ~ANADIG_PLL_480_DIV_SELECT_MASK;
 764         reg |= div;
 765         __raw_writel(reg, PLL7_480_USB2_BASE_ADDR);
 766
 767         return 0;
 768 }
 769
 770 static struct clk pll7_usb_host_main_clk = {
 771         __INIT_CLK_DEBUG(pll7_usb_host_main_clk)
 772         .parent = &osc_clk,
 773         .enable = _clk_pll_enable,
 774         .disable = _clk_pll_disable,
 775         .set_rate = _clk_pll7_usb_otg_set_rate,
 776         .get_rate = _clk_pll7_usb_otg_get_rate,
 777
 778 };
 779
 780 static struct clk usb_phy2_clk = {
 781         __INIT_CLK_DEBUG(usb_phy2_clk)
 782         .parent = &pll7_usb_host_main_clk,
 783         .enable = _clk_usb_phy_enable,
 784         .disable = _clk_usb_phy_disable,
 785         .enable_reg = (void *)PLL7_480_USB2_BASE_ADDR,
 786         .enable_shift = ANADIG_PLL_480_EN_USB_CLKS,
 787         .set_rate = _clk_pll7_usb_otg_set_rate,
 788         .get_rate = _clk_pll7_usb_otg_get_rate,
 789
 790 };
 791
 792 static struct clk pll8_enet_main_clk = {
 793         __INIT_CLK_DEBUG(pll8_enet_main_clk)
 794         .parent = &osc_clk,
 795         .enable = _clk_pll_enable,
 796         .disable = _clk_pll_disable,
 797 };
 798
 799 static unsigned long _clk_arm_get_rate(struct clk *clk)
 800 {
 801         u32 cacrr, div;
 802
 803         cacrr = __raw_readl(MXC_CCM_CACRR);
 804         div = (cacrr & MXC_CCM_CACRR_ARM_PODF_MASK) + 1;
 805         return clk_get_rate(clk->parent) / div;
 806 }
 807
 808 static int _clk_arm_set_rate(struct clk *clk, unsigned long rate)
 809 {
 810         u32 div;
 811
 812         div = (clk_get_rate(clk->parent) / rate);
 813         if (div > 8)
 814                 return -1;
 815
 816         __raw_writel(div - 1, MXC_CCM_CACRR);
 817
 818         return 0;
 819 }
 820
 821 static struct clk cpu_clk = {
 822         __INIT_CLK_DEBUG(cpu_clk)
 823         .parent = &pll1_sw_clk,
 824         .set_rate = _clk_arm_set_rate,
 825         .get_rate = _clk_arm_get_rate,
 826 };
 827
 828 static int _clk_periph_set_parent(struct clk *clk, struct clk *parent)
 829 {
 830         u32 reg;
 831         int mux;
 832
 833         mux = _get_mux6(parent, &pll2_528_bus_main_clk, &pll2_pfd_400M,
 834                 &pll2_pfd_352M, &pll2_200M, &pll3_sw_clk, &osc_clk);
 835
 836         if (mux <= 3) {
 837                 /* Set the pre_periph_clk multiplexer */
 838                 reg = __raw_readl(MXC_CCM_CBCMR);
 839                 reg &= ~MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK;
 840                 reg |= mux << MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET;
 841                 __raw_writel(reg, MXC_CCM_CBCMR);
 842
 843         /* Set the periph_clk_sel multiplexer. */
 844                 reg = __raw_readl(MXC_CCM_CBCDR);
 845                 reg &= ~MXC_CCM_CBCDR_PERIPH_CLK_SEL;
 846                 __raw_writel(reg, MXC_CCM_CBCDR);
 847         } else {
 848                 /* Set the periph_clk2_podf divider to divide by 1. */
 849                 reg = __raw_readl(MXC_CCM_CBCDR);
 850                 reg &= ~MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK;
 851                 __raw_writel(reg, MXC_CCM_CBCDR);
 852
 853                 /* Set the periph_clk2_sel mux. */
 854                 reg = __raw_readl(MXC_CCM_CBCMR);
 855                 reg &= ~MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK;
 856                 reg |= ((mux - 4) << MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET);
 857                 __raw_writel(reg, MXC_CCM_CBCMR);
 858         }
 859
 860         if (!WAIT(!(__raw_readl(MXC_CCM_CDHIPR)
 861              & MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY), SPIN_DELAY))
 862                 panic("pll _clk_axi_a_set_rate failed\n");
 863
 864         return 0;
 865 }
 866
 867 static unsigned long _clk_periph_get_rate(struct clk *clk)
 868 {
 869         u32 div = 1;
 870         u32 reg;
 871         unsigned long val;
 872
 873         if ((clk->parent == &pll3_sw_clk) || (clk->parent == &osc_clk)) {
 874                 reg = __raw_readl(MXC_CCM_CBCDR)
 875                         & MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK;
 876                 div = (reg >> MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET) + 1;
 877         }
 878         val = clk_get_rate(clk->parent) / div;
 879         return val;
 880 }
 881
 882 static struct clk periph_clk = {
 883         __INIT_CLK_DEBUG(periph_clk)
 884         .parent = &pll2_528_bus_main_clk,
 885         .set_parent = _clk_periph_set_parent,
 886         .get_rate = _clk_periph_get_rate,
 887 };
 888
 889 static unsigned long _clk_axi_get_rate(struct clk *clk)
 890 {
 891         u32 div, reg;
 892         unsigned long val;
 893
 894         reg = __raw_readl(MXC_CCM_CBCDR) & MXC_CCM_CBCDR_AXI_PODF_MASK;
 895         div = (reg >> MXC_CCM_CBCDR_AXI_PODF_OFFSET);
 896
 897         val = clk_get_rate(clk->parent) / (div + 1);
 898         return val;
 899 }
 900
 901 static int _clk_axi_set_rate(struct clk *clk, unsigned long rate)
 902 {
 903         u32 reg, div;
 904         u32 parent_rate = clk_get_rate(clk->parent);
 905
 906         div = parent_rate / rate;
 907
 908         if (div == 0)
 909                 div++;
 910         if (((parent_rate / div) != rate) || (div > 8))
 911                 return -EINVAL;
 912
 913         reg = __raw_readl(MXC_CCM_CBCDR);
 914         reg &= ~MXC_CCM_CBCDR_AXI_PODF_MASK;
 915         reg |= (div - 1) << MXC_CCM_CBCDR_AXI_PODF_OFFSET;
 916         __raw_writel(reg, MXC_CCM_CBCDR);
 917
 918         if (!WAIT(!(__raw_readl(MXC_CCM_CDHIPR)
 919              & MXC_CCM_CDHIPR_AXI_PODF_BUSY), SPIN_DELAY))
 920                 panic("pll _clk_axi_a_set_rate failed\n");
 921
 922         return 0;
 923 }
 924
 925 static unsigned long _clk_axi_round_rate(struct clk *clk,
 926                                                 unsigned long rate)
 927 {
 928         u32 div;
 929         u32 parent_rate = clk_get_rate(clk->parent);
 930
 931         div = parent_rate / rate;
 932
 933         /* Make sure rate is not greater than the maximum
 934          * value for the clock.
 935          * Also prevent a div of 0.
 936          */
 937
 938         if (div > 8)
 939                 div = 8;
 940         else if (div == 0)
 941                 div++;
 942
 943         return parent_rate / div;
 944 }
 945
 946 static int _clk_axi_set_parent(struct clk *clk, struct clk *parent)
 947 {
 948         u32 reg;
 949         int mux;
 950
 951         mux = _get_mux6(parent, &periph_clk, &pll2_pfd_400M,
 952                                 &pll3_pfd_540M, NULL, NULL, NULL);
 953
 954         if (mux == 0) {
 955                 /* Set the AXI_SEL mux */
 956                 reg = __raw_readl(MXC_CCM_CBCDR) & ~MXC_CCM_CBCDR_AXI_SEL;
 957                 __raw_writel(reg, MXC_CCM_CBCDR);
 958         } else {
 959                 /* Set the AXI_ALT_SEL mux. */
 960                 reg = __raw_readl(MXC_CCM_CBCDR)
 961                         & ~MXC_CCM_CBCDR_AXI_ALT_SEL_MASK;
 962                 reg = ((mux - 1) << MXC_CCM_CBCDR_AXI_ALT_SEL_OFFSET);\
 963                 __raw_writel(reg, MXC_CCM_CBCDR);
 964
 965                 /* Set the AXI_SEL mux */
 966                 reg = __raw_readl(MXC_CCM_CBCDR) & ~MXC_CCM_CBCDR_AXI_SEL;
 967                 reg |= MXC_CCM_CBCDR_AXI_SEL;
 968                 __raw_writel(reg, MXC_CCM_CBCDR);
 969         }
 970         return 0;
 971 }
 972
 973 static struct clk axi_clk = {
 974         __INIT_CLK_DEBUG(axi_clk)
 975         .parent = &periph_clk,
 976         .set_parent = _clk_axi_set_parent,
 977         .set_rate = _clk_axi_set_rate,
 978         .get_rate = _clk_axi_get_rate,
 979         .round_rate = _clk_axi_round_rate,
 980 };
 981
 982 static unsigned long _clk_ahb_get_rate(struct clk *clk)
 983 {
 984         u32 reg, div;
 985
 986         reg = __raw_readl(MXC_CCM_CBCDR);
 987         div = ((reg & MXC_CCM_CBCDR_AHB_PODF_MASK) >>
 988                MXC_CCM_CBCDR_AHB_PODF_OFFSET) + 1;
 989
 990         return clk_get_rate(clk->parent) / div;
 991 }
 992
 993 static int _clk_ahb_set_rate(struct clk *clk, unsigned long rate)
 994 {
 995         u32 reg, div;
 996         u32 parent_rate = clk_get_rate(clk->parent);
 997
 998         div = parent_rate / rate;
 999         if (div == 0)
1000                 div++;
1001         if (((parent_rate / div) != rate) || (div > 8))
1002                 return -EINVAL;
1003
1004         reg = __raw_readl(MXC_CCM_CBCDR);
1005         reg &= ~MXC_CCM_CBCDR_AHB_PODF_MASK;
1006         reg |= (div - 1) << MXC_CCM_CBCDR_AHB_PODF_OFFSET;
1007         __raw_writel(reg, MXC_CCM_CBCDR);
1008
1009         if (!WAIT(!(__raw_readl(MXC_CCM_CDHIPR) & MXC_CCM_CDHIPR_AHB_PODF_BUSY),
1010                                 SPIN_DELAY))
1011                         panic("_clk_ahb_set_rate failed\n");
1012
1013         return 0;
1014 }
1015
1016 static unsigned long _clk_ahb_round_rate(struct clk *clk,
1017                                                 unsigned long rate)
1018 {
1019         u32 div;
1020         u32 parent_rate = clk_get_rate(clk->parent);
1021
1022         div = parent_rate / rate;
1023
1024         /* Make sure rate is not greater than the maximum value for the clock.
1025          * Also prevent a div of 0.
1026          */
1027         if (div == 0)
1028                 div++;
1029
1030         if (div > 8)
1031                 div = 8;
1032
1033         return parent_rate / div;
1034 }
1035
1036 static struct clk ahb_clk = {
1037         __INIT_CLK_DEBUG(ahb_clk)
1038         .parent = &periph_clk,
1039         .get_rate = _clk_ahb_get_rate,
1040         .set_rate = _clk_ahb_set_rate,
1041         .round_rate = _clk_ahb_round_rate,
1042 };
1043
1044 static unsigned long _clk_ipg_get_rate(struct clk *clk)
1045 {
1046         u32 reg, div;
1047
1048         reg = __raw_readl(MXC_CCM_CBCDR);
1049         div = ((reg & MXC_CCM_CBCDR_IPG_PODF_MASK) >>
1050                 MXC_CCM_CBCDR_IPG_PODF_OFFSET) + 1;
1051
1052         return clk_get_rate(clk->parent) / div;
1053 }
1054
1055
1056 static struct clk ipg_clk = {
1057         __INIT_CLK_DEBUG(ipg_clk)
1058         .parent = &ahb_clk,
1059         .get_rate = _clk_ipg_get_rate,
1060 };
1061
1062 static unsigned long _clk_mmdc_ch0_axi_get_rate(struct clk *clk)
1063 {
1064         u32 reg, div;
1065
1066         reg = __raw_readl(MXC_CCM_CBCDR);
1067         div = ((reg & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
1068                         MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET) + 1;
1069
1070         return clk_get_rate(clk->parent) / div;
1071 }
1072
1073 static int _clk_mmdc_ch0_axi_set_rate(struct clk *clk, unsigned long rate)
1074 {
1075         u32 reg, div;
1076         u32 parent_rate = clk_get_rate(clk->parent);
1077
1078         div = parent_rate / rate;
1079         if (div == 0)
1080                 div++;
1081         if (((parent_rate / div) != rate) || (div > 8))
1082                 return -EINVAL;
1083
1084         reg = __raw_readl(MXC_CCM_CBCDR);
1085         reg &= ~MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK;
1086         reg |= (div - 1) << MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
1087         __raw_writel(reg, MXC_CCM_CBCDR);
1088
1089         if (!WAIT(!(__raw_readl(MXC_CCM_CDHIPR)
1090                 & MXC_CCM_CDHIPR_MMDC_CH0_PODF_BUSY),
1091                                 SPIN_DELAY))
1092                         panic("_clk_mmdc_ch0_axi_set_rate failed\n");
1093
1094         return 0;
1095 }
1096
1097 static unsigned long _clk_mmdc_ch0_axi_round_rate(struct clk *clk,
1098                                                 unsigned long rate)
1099 {
1100         u32 div;
1101         u32 parent_rate = clk_get_rate(clk->parent);
1102
1103         div = parent_rate / rate;
1104
1105         /* Make sure rate is not greater than the maximum value for the clock.
1106          * Also prevent a div of 0.
1107          */
1108         if (div == 0)
1109                 div++;
1110
1111         if (div > 8)
1112                 div = 8;
1113
1114         return parent_rate / div;
1115 }
1116
1117 static struct clk mmdc_ch0_axi_clk[] = {
1118         {
1119         __INIT_CLK_DEBUG(mmdc_ch0_axi_clk)
1120         .id = 0,
1121         .parent = &periph_clk,
1122         .enable = _clk_enable,
1123         .disable = _clk_disable,
1124         .enable_reg = MXC_CCM_CCGR3,
1125         .enable_shift = MXC_CCM_CCGRx_CG10_OFFSET,
1126         .secondary = &mmdc_ch0_axi_clk[1],
1127         .get_rate = _clk_mmdc_ch0_axi_get_rate,
1128         .set_rate = _clk_mmdc_ch0_axi_set_rate,
1129         .round_rate = _clk_mmdc_ch0_axi_round_rate,
1130         },
1131         {
1132         __INIT_CLK_DEBUG(mmdc_ch0_ipg_clk)
1133         .id = 0,
1134         .parent = &ipg_clk,
1135         .enable = _clk_enable,
1136         .disable = _clk_disable,
1137         .enable_reg = MXC_CCM_CCGR3,
1138         .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET,
1139         },
1140 };
1141
1142 static unsigned long _clk_mmdc_ch1_axi_get_rate(struct clk *clk)
1143 {
1144         u32 reg, div;
1145
1146         reg = __raw_readl(MXC_CCM_CBCDR);
1147         div = ((reg & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) >>
1148                         MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET) + 1;
1149
1150         return clk_get_rate(clk->parent) / div;
1151 }
1152
1153 static int _clk_mmdc_ch1_axi_set_rate(struct clk *clk, unsigned long rate)
1154 {
1155         u32 reg, div;
1156         u32 parent_rate = clk_get_rate(clk->parent);
1157
1158         div = parent_rate / rate;
1159         if (div == 0)
1160                 div++;
1161         if (((parent_rate / div) != rate) || (div > 8))
1162                 return -EINVAL;
1163
1164         reg = __raw_readl(MXC_CCM_CBCDR);
1165         reg &= ~MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK;
1166         reg |= (div - 1) << MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
1167         __raw_writel(reg, MXC_CCM_CBCDR);
1168
1169         if (!WAIT(!(__raw_readl(MXC_CCM_CDHIPR)
1170                 & MXC_CCM_CDHIPR_MMDC_CH1_PODF_BUSY), SPIN_DELAY))
1171                         panic("_clk_mmdc_ch1_axi_set_rate failed\n");
1172
1173         return 0;
1174 }
1175
1176 static unsigned long _clk_mmdc_ch1_axi_round_rate(struct clk *clk,
1177                                                 unsigned long rate)
1178 {
1179         u32 div;
1180         u32 parent_rate = clk_get_rate(clk->parent);
1181
1182         div = parent_rate / rate;
1183
1184         /* Make sure rate is not greater than the maximum value for the clock.
1185          * Also prevent a div of 0.
1186          */
1187         if (div == 0)
1188                 div++;
1189
1190         if (div > 8)
1191                 div = 8;
1192
1193         return parent_rate / div;
1194 }
1195
1196 static struct clk mmdc_ch1_axi_clk[] = {
1197         {
1198         __INIT_CLK_DEBUG(mmdc_ch1_axi_clk)
1199         .id = 0,
1200         .parent = &pll2_pfd_400M,
1201         .enable = _clk_enable,
1202         .disable = _clk_disable,
1203         .enable_reg = MXC_CCM_CCGR3,
1204         .enable_shift = MXC_CCM_CCGRx_CG11_OFFSET,
1205         .secondary = &mmdc_ch1_axi_clk[1],
1206         .get_rate = _clk_mmdc_ch1_axi_get_rate,
1207         .set_rate = _clk_mmdc_ch1_axi_set_rate,
1208         .round_rate = _clk_mmdc_ch1_axi_round_rate,
1209         },
1210         {
1211         .id = 1,
1212         __INIT_CLK_DEBUG(mmdc_ch1_ipg_clk)
1213         .parent = &ipg_clk,
1214         .enable = _clk_enable,
1215         .disable = _clk_disable,
1216         .enable_reg = MXC_CCM_CCGR3,
1217         .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
1218         },
1219 };
1220
1221 static struct clk ipg_perclk = {
1222         __INIT_CLK_DEBUG(ipg_perclk)
1223         .parent = &ipg_clk,
1224 };
1225
1226 static struct clk spba_clk = {
1227         __INIT_CLK_DEBUG(spba_clk)
1228         .parent = &ipg_clk,
1229         .enable_reg = MXC_CCM_CCGR5,
1230         .enable_shift = MXC_CCM_CCGRx_CG6_OFFSET,
1231         .enable = _clk_enable,
1232         .disable = _clk_disable,
1233 };
1234
1235 static struct clk sdma_clk = {
1236          __INIT_CLK_DEBUG(sdma_clk)
1237          .parent = &ahb_clk,
1238          .enable_reg = MXC_CCM_CCGR5,
1239          .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET,
1240          .enable = _clk_enable,
1241          .disable = _clk_disable,
1242 };
1243
1244 static int _clk_gpu2d_axi_set_parent(struct clk *clk, struct clk *parent)
1245 {
1246         u32 reg = __raw_readl(MXC_CCM_CBCMR) & MXC_CCM_CBCMR_GPU2D_AXI_CLK_SEL;
1247
1248         if (parent == &ahb_clk)
1249                 reg |= MXC_CCM_CBCMR_GPU2D_AXI_CLK_SEL;
1250
1251         __raw_writel(reg, MXC_CCM_CBCMR);
1252
1253         return 0;
1254 }
1255
1256 static struct clk gpu2d_axi_clk = {
1257         __INIT_CLK_DEBUG(gpu2d_axi_clk)
1258         .parent = &axi_clk,
1259         .set_parent = _clk_gpu2d_axi_set_parent,
1260         .get_rate = _clk_axi_get_rate,
1261 };
1262
1263 static int _clk_gpu3d_axi_set_parent(struct clk *clk, struct clk *parent)
1264 {
1265         u32 reg = __raw_readl(MXC_CCM_CBCMR) & MXC_CCM_CBCMR_GPU3D_AXI_CLK_SEL;
1266
1267         if (parent == &ahb_clk)
1268                 reg |= MXC_CCM_CBCMR_GPU3D_AXI_CLK_SEL;
1269
1270         __raw_writel(reg, MXC_CCM_CBCMR);
1271
1272         return 0;
1273 }
1274
1275 static struct clk gpu3d_axi_clk = {
1276         __INIT_CLK_DEBUG(gpu3d_axi_clk)
1277         .parent = &axi_clk,
1278         .set_parent = _clk_gpu3d_axi_set_parent,
1279         .get_rate = _clk_axi_get_rate,
1280 };
1281
1282 static int _clk_pcie_axi_set_parent(struct clk *clk, struct clk *parent)
1283 {
1284         u32 reg = __raw_readl(MXC_CCM_CBCMR) & MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL;
1285
1286         if (parent == &ahb_clk)
1287                 reg |= MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL;
1288
1289         __raw_writel(reg, MXC_CCM_CBCMR);
1290
1291         return 0;
1292 }
1293
1294 static struct clk pcie_axi_clk = {
1295         __INIT_CLK_DEBUG(pcie_axi_clk)
1296         .parent = &axi_clk,
1297         .set_parent = _clk_pcie_axi_set_parent,
1298         .get_rate = _clk_axi_get_rate,
1299 };
1300
1301 static int _clk_vdo_axi_set_parent(struct clk *clk, struct clk *parent)
1302 {
1303         u32 reg = __raw_readl(MXC_CCM_CBCMR) & MXC_CCM_CBCMR_VDOAXI_CLK_SEL;
1304
1305         if (parent == &ahb_clk)
1306                 reg |= MXC_CCM_CBCMR_VDOAXI_CLK_SEL;
1307
1308         __raw_writel(reg, MXC_CCM_CBCMR);
1309
1310         return 0;
1311 }
1312
1313 static struct clk vdo_axi_clk = {
1314         __INIT_CLK_DEBUG(vdo_axi_clk)
1315         .parent = &axi_clk,
1316         .enable_reg = MXC_CCM_CCGR6,
1317         .enable_shift = MXC_CCM_CCGRx_CG6_OFFSET,
1318         .enable = _clk_enable,
1319         .disable = _clk_disable,
1320         .set_parent = _clk_vdo_axi_set_parent,
1321         .get_rate = _clk_axi_get_rate,
1322 };
1323
1324 static struct clk vdoa_clk = {
1325         __INIT_CLK_DEBUG(vdoa_clk)
1326         .id = 0,
1327         .parent = &axi_clk,
1328         .enable_reg = MXC_CCM_CCGR2,
1329         .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
1330         .enable = _clk_enable,
1331         .disable = _clk_disable,
1332 };
1333
1334 static struct clk gpt_clk[] = {
1335         {
1336         __INIT_CLK_DEBUG(gpt_clk)
1337          .parent = &ipg_perclk,
1338          .id = 0,
1339          .enable_reg = MXC_CCM_CCGR1,
1340          .enable_shift = MXC_CCM_CCGRx_CG10_OFFSET,
1341          .enable = _clk_enable,
1342          .disable = _clk_disable,
1343          .secondary = &gpt_clk[1],
1344          },
1345         {
1346         __INIT_CLK_DEBUG(gpt_serial_clk)
1347          .id = 0,
1348          .enable_reg = MXC_CCM_CCGR1,
1349          .enable_shift = MXC_CCM_CCGRx_CG11_OFFSET,
1350          .enable = _clk_enable,
1351          .disable = _clk_disable,
1352          },
1353 };
1354
1355 static struct clk iim_clk = {
1356         __INIT_CLK_DEBUG(iim_clk)
1357         .parent = &ipg_clk,
1358         .enable = _clk_enable,
1359         .enable_reg = MXC_CCM_CCGR2,
1360         .enable_shift = MXC_CCM_CCGRx_CG6_OFFSET,
1361         .disable = _clk_disable,
1362 };
1363
1364 static struct clk i2c_clk[] = {
1365         {
1366         __INIT_CLK_DEBUG(i2c_clk_0)
1367          .id = 0,
1368          .parent = &ipg_perclk,
1369          .enable_reg = MXC_CCM_CCGR2,
1370          .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET,
1371          .enable = _clk_enable,
1372          .disable = _clk_disable,
1373          },
1374         {
1375         __INIT_CLK_DEBUG(i2c_clk_1)
1376          .id = 1,
1377          .parent = &ipg_perclk,
1378          .enable_reg = MXC_CCM_CCGR2,
1379          .enable_shift = MXC_CCM_CCGRx_CG4_OFFSET,
1380          .enable = _clk_enable,
1381          .disable = _clk_disable,
1382          },
1383         {
1384         __INIT_CLK_DEBUG(i2c_clk_2)
1385          .id = 2,
1386          .parent = &ipg_perclk,
1387          .enable_reg = MXC_CCM_CCGR2,
1388          .enable_shift = MXC_CCM_CCGRx_CG5_OFFSET,
1389          .enable = _clk_enable,
1390          .disable = _clk_disable,
1391          },
1392 };
1393
1394 static int _clk_vpu_axi_set_parent(struct clk *clk, struct clk *parent)
1395 {
1396         int mux;
1397         u32 reg = __raw_readl(MXC_CCM_CBCMR)
1398                 & MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK;
1399
1400         mux = _get_mux6(parent, &axi_clk, &pll2_pfd_400M,
1401                 &pll2_pfd_352M, NULL, NULL, NULL);
1402
1403         reg |= (mux << MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET);
1404
1405         __raw_writel(reg, MXC_CCM_CBCMR);
1406
1407         return 0;
1408 }
1409
1410 static unsigned long _clk_vpu_axi_get_rate(struct clk *clk)
1411 {
1412         u32 reg, div;
1413
1414         reg = __raw_readl(MXC_CCM_CSCDR1);
1415         div = ((reg & MXC_CCM_CSCDR1_VPU_AXI_PODF_MASK) >>
1416                         MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET) + 1;
1417
1418         return clk_get_rate(clk->parent) / div;
1419 }
1420
1421 static int _clk_vpu_axi_set_rate(struct clk *clk, unsigned long rate)
1422 {
1423         u32 reg, div;
1424         u32 parent_rate = clk_get_rate(clk->parent);
1425
1426         div = parent_rate / rate;
1427         if (div == 0)
1428                 div++;
1429         if (((parent_rate / div) != rate) || (div > 8))
1430                 return -EINVAL;
1431
1432         reg = __raw_readl(MXC_CCM_CSCDR1);
1433         reg &= ~MXC_CCM_CSCDR1_VPU_AXI_PODF_MASK;
1434         reg |= (div - 1) << MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET;
1435         __raw_writel(reg, MXC_CCM_CSCDR1);
1436
1437         return 0;
1438 }
1439
1440 static unsigned long _clk_vpu_axi_round_rate(struct clk *clk,
1441                                                 unsigned long rate)
1442 {
1443         u32 div;
1444         u32 parent_rate = clk_get_rate(clk->parent);
1445
1446         div = parent_rate / rate;
1447
1448         /* Make sure rate is not greater than the maximum value for the clock.
1449          * Also prevent a div of 0.
1450          */
1451         if (div == 0)
1452                 div++;
1453
1454         if (div > 8)
1455                 div = 8;
1456
1457         return parent_rate / div;
1458 }
1459
1460 static struct clk vpu_clk = {
1461         __INIT_CLK_DEBUG(vpu_clk)
1462         .parent = &axi_clk,
1463         .enable_reg = MXC_CCM_CCGR6,
1464         .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
1465         .enable = _clk_enable,
1466         .disable = _clk_disable,
1467         .set_parent = _clk_vpu_axi_set_parent,
1468         .round_rate = _clk_vpu_axi_round_rate,
1469         .set_rate = _clk_vpu_axi_set_rate,
1470         .get_rate = _clk_vpu_axi_get_rate,
1471 };
1472
1473 static int _clk_ipu1_set_parent(struct clk *clk, struct clk *parent)
1474 {
1475         int mux;
1476         u32 reg = __raw_readl(MXC_CCM_CSCDR3)
1477                 & MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_MASK;
1478
1479         mux = _get_mux6(parent, &mmdc_ch0_axi_clk[0],
1480                 &pll2_pfd_400M, &pll3_120M, &pll3_pfd_540M, NULL, NULL);
1481
1482         reg |= (mux << MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_OFFSET);
1483
1484         __raw_writel(reg, MXC_CCM_CSCDR3);
1485
1486         return 0;
1487 }
1488
1489 static unsigned long _clk_ipu1_get_rate(struct clk *clk)
1490 {
1491         u32 reg, div;
1492
1493         reg = __raw_readl(MXC_CCM_CSCDR3);
1494         div = ((reg & MXC_CCM_CSCDR3_IPU1_HSP_PODF_MASK) >>
1495                         MXC_CCM_CSCDR3_IPU1_HSP_PODF_OFFSET) + 1;
1496
1497         return clk_get_rate(clk->parent) / div;
1498 }
1499
1500 static int _clk_ipu1_set_rate(struct clk *clk, unsigned long rate)
1501 {
1502         u32 reg, div;
1503         u32 parent_rate = clk_get_rate(clk->parent);
1504
1505         div = parent_rate / rate;
1506         if (div == 0)
1507                 div++;
1508         if (((parent_rate / div) != rate) || (div > 8))
1509                 return -EINVAL;
1510
1511         reg = __raw_readl(MXC_CCM_CSCDR3);
1512         reg &= ~MXC_CCM_CSCDR3_IPU1_HSP_PODF_MASK;
1513         reg |= (div - 1) << MXC_CCM_CSCDR3_IPU1_HSP_PODF_OFFSET;
1514         __raw_writel(reg, MXC_CCM_CSCDR3);
1515
1516         return 0;
1517 }
1518
1519 static unsigned long _clk_ipu_round_rate(struct clk *clk,
1520                                                 unsigned long rate)
1521 {
1522         u32 div;
1523         u32 parent_rate = clk_get_rate(clk->parent);
1524
1525         div = parent_rate / rate;
1526
1527         /* Make sure rate is not greater than the maximum value for the clock.
1528          * Also prevent a div of 0.
1529          */
1530         if (div == 0)
1531                 div++;
1532
1533         if (div > 8)
1534                 div = 8;
1535
1536         return parent_rate / div;
1537 }
1538
1539 static struct clk ipu1_clk = {
1540         __INIT_CLK_DEBUG(ipu1_clk)
1541         .parent = &mmdc_ch0_axi_clk[0],
1542         .enable_reg = MXC_CCM_CCGR3,
1543         .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET,
1544         .enable = _clk_enable,
1545         .disable = _clk_disable,
1546         .set_parent = _clk_ipu1_set_parent,
1547         .round_rate = _clk_ipu_round_rate,
1548         .set_rate = _clk_ipu1_set_rate,
1549         .get_rate = _clk_ipu1_get_rate,
1550 };
1551
1552 static int _clk_ipu2_set_parent(struct clk *clk, struct clk *parent)
1553 {
1554         int mux;
1555         u32 reg = __raw_readl(MXC_CCM_CSCDR3)
1556                 & MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_MASK;
1557
1558         mux = _get_mux6(parent, &mmdc_ch0_axi_clk[0],
1559                 &pll2_pfd_400M, &pll3_120M, &pll3_pfd_540M, NULL, NULL);
1560
1561         reg |= (mux << MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_OFFSET);
1562
1563         __raw_writel(reg, MXC_CCM_CSCDR3);
1564
1565         return 0;
1566 }
1567
1568 static unsigned long _clk_ipu2_get_rate(struct clk *clk)
1569 {
1570         u32 reg, div;
1571
1572         reg = __raw_readl(MXC_CCM_CSCDR3);
1573         div = ((reg & MXC_CCM_CSCDR3_IPU2_HSP_PODF_MASK) >>
1574                         MXC_CCM_CSCDR3_IPU2_HSP_PODF_OFFSET) + 1;
1575
1576         return clk_get_rate(clk->parent) / div;
1577 }
1578
1579 static int _clk_ipu2_set_rate(struct clk *clk, unsigned long rate)
1580 {
1581         u32 reg, div;
1582         u32 parent_rate = clk_get_rate(clk->parent);
1583
1584         div = parent_rate / rate;
1585         if (div == 0)
1586                 div++;
1587         if (((parent_rate / div) != rate) || (div > 8))
1588                 return -EINVAL;
1589
1590         reg = __raw_readl(MXC_CCM_CSCDR3);
1591         reg &= ~MXC_CCM_CSCDR3_IPU2_HSP_PODF_MASK;
1592         reg |= (div - 1) << MXC_CCM_CSCDR3_IPU2_HSP_PODF_OFFSET;
1593         __raw_writel(reg, MXC_CCM_CSCDR3);
1594
1595         return 0;
1596 }
1597
1598 static struct clk ipu2_clk = {
1599         __INIT_CLK_DEBUG(ipu2_clk)
1600         .parent = &mmdc_ch0_axi_clk[0],
1601         .enable_reg = MXC_CCM_CCGR3,
1602         .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET,
1603         .enable = _clk_enable,
1604         .disable = _clk_disable,
1605         .set_parent = _clk_ipu2_set_parent,
1606         .round_rate = _clk_ipu_round_rate,
1607         .set_rate = _clk_ipu2_set_rate,
1608         .get_rate = _clk_ipu2_get_rate,
1609 };
1610
1611 static unsigned long _clk_usdhc_round_rate(struct clk *clk,
1612                                                 unsigned long rate)
1613 {
1614         u32 div;
1615         u32 parent_rate = clk_get_rate(clk->parent);
1616
1617         div = parent_rate / rate;
1618
1619         /* Make sure rate is not greater than the maximum value for the clock.
1620          * Also prevent a div of 0.
1621          */
1622         if (div == 0)
1623                 div++;
1624
1625         if (div > 8)
1626                 div = 8;
1627
1628         return parent_rate / div;
1629 }
1630
1631 static int _clk_usdhc1_set_parent(struct clk *clk, struct clk *parent)
1632 {
1633         u32 reg = __raw_readl(MXC_CCM_CSCMR1) & MXC_CCM_CSCMR1_USDHC1_CLK_SEL;
1634
1635         if (parent == &pll2_pfd_352M)
1636                 reg |= (MXC_CCM_CSCMR1_USDHC1_CLK_SEL);
1637
1638         __raw_writel(reg, MXC_CCM_CSCMR1);
1639
1640         return 0;
1641 }
1642
1643 static unsigned long _clk_usdhc1_get_rate(struct clk *clk)
1644 {
1645         u32 reg, div;
1646
1647         reg = __raw_readl(MXC_CCM_CSCDR1);
1648         div = ((reg & MXC_CCM_CSCDR1_USDHC1_PODF_MASK) >>
1649                         MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET) + 1;
1650
1651         return clk_get_rate(clk->parent) / div;
1652 }
1653
1654 static int _clk_usdhc1_set_rate(struct clk *clk, unsigned long rate)
1655 {
1656         u32 reg, div;
1657         u32 parent_rate = clk_get_rate(clk->parent);
1658
1659         div = parent_rate / rate;
1660         if (div == 0)
1661                 div++;
1662         if (((parent_rate / div) != rate) || (div > 8))
1663                 return -EINVAL;
1664
1665         reg = __raw_readl(MXC_CCM_CSCDR1);
1666         reg &= ~MXC_CCM_CSCDR1_USDHC1_PODF_MASK;
1667         reg |= (div - 1) << MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET;
1668         __raw_writel(reg, MXC_CCM_CSCDR1);
1669
1670         return 0;
1671 }
1672
1673 static struct clk usdhc1_clk = {
1674         __INIT_CLK_DEBUG(usdhc1_clk)
1675         .id = 0,
1676         .parent = &pll2_pfd_400M,
1677         .enable_reg = MXC_CCM_CCGR6,
1678         .enable_shift = MXC_CCM_CCGRx_CG1_OFFSET,
1679         .enable = _clk_enable,
1680         .disable = _clk_disable,
1681         .set_parent = _clk_usdhc1_set_parent,
1682         .round_rate = _clk_usdhc_round_rate,
1683         .set_rate = _clk_usdhc1_set_rate,
1684         .get_rate = _clk_usdhc1_get_rate,
1685 };
1686
1687 static int _clk_usdhc2_set_parent(struct clk *clk, struct clk *parent)
1688 {
1689         u32 reg = __raw_readl(MXC_CCM_CSCMR1) & MXC_CCM_CSCMR1_USDHC2_CLK_SEL;
1690
1691         if (parent == &pll2_pfd_352M)
1692                 reg |= (MXC_CCM_CSCMR1_USDHC2_CLK_SEL);
1693
1694         __raw_writel(reg, MXC_CCM_CSCMR1);
1695
1696         return 0;
1697 }
1698
1699 static unsigned long _clk_usdhc2_get_rate(struct clk *clk)
1700 {
1701         u32 reg, div;
1702
1703         reg = __raw_readl(MXC_CCM_CSCDR1);
1704         div = ((reg & MXC_CCM_CSCDR1_USDHC2_PODF_MASK) >>
1705                         MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET) + 1;
1706
1707         return clk_get_rate(clk->parent) / div;
1708 }
1709
1710 static int _clk_usdhc2_set_rate(struct clk *clk, unsigned long rate)
1711 {
1712         u32 reg, div;
1713         u32 parent_rate = clk_get_rate(clk->parent);
1714
1715         div = parent_rate / rate;
1716         if (div == 0)
1717                 div++;
1718         if (((parent_rate / div) != rate) || (div > 8))
1719                 return -EINVAL;
1720
1721         reg = __raw_readl(MXC_CCM_CSCDR1);
1722         reg &= ~MXC_CCM_CSCDR1_USDHC2_PODF_MASK;
1723         reg |= (div - 1) << MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET;
1724         __raw_writel(reg, MXC_CCM_CSCDR1);
1725
1726         return 0;
1727 }
1728
1729 static struct clk usdhc2_clk = {
1730         __INIT_CLK_DEBUG(usdhc2_clk)
1731         .id = 1,
1732         .parent = &pll2_pfd_400M,
1733         .enable_reg = MXC_CCM_CCGR6,
1734         .enable_shift = MXC_CCM_CCGRx_CG2_OFFSET,
1735         .enable = _clk_enable,
1736         .disable = _clk_disable,
1737         .set_parent = _clk_usdhc2_set_parent,
1738         .round_rate = _clk_usdhc_round_rate,
1739         .set_rate = _clk_usdhc2_set_rate,
1740         .get_rate = _clk_usdhc2_get_rate,
1741 };
1742
1743 static int _clk_usdhc3_set_parent(struct clk *clk, struct clk *parent)
1744 {
1745         u32 reg = __raw_readl(MXC_CCM_CSCMR1) & MXC_CCM_CSCMR1_USDHC3_CLK_SEL;
1746
1747         if (parent == &pll2_pfd_352M)
1748                 reg |= (MXC_CCM_CSCMR1_USDHC3_CLK_SEL);
1749
1750         __raw_writel(reg, MXC_CCM_CSCMR1);
1751
1752         return 0;
1753 }
1754
1755 static unsigned long _clk_usdhc3_get_rate(struct clk *clk)
1756 {
1757         u32 reg, div;
1758
1759         reg = __raw_readl(MXC_CCM_CSCDR1);
1760         div = ((reg & MXC_CCM_CSCDR1_USDHC3_PODF_MASK) >>
1761                         MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET) + 1;
1762
1763         return clk_get_rate(clk->parent) / div;
1764 }
1765
1766 static int _clk_usdhc3_set_rate(struct clk *clk, unsigned long rate)
1767 {
1768         u32 reg, div;
1769         u32 parent_rate = clk_get_rate(clk->parent);
1770
1771         div = parent_rate / rate;
1772         if (div == 0)
1773                 div++;
1774         if (((parent_rate / div) != rate) || (div > 8))
1775                 return -EINVAL;
1776
1777         reg = __raw_readl(MXC_CCM_CSCDR1);
1778         reg &= ~MXC_CCM_CSCDR1_USDHC3_PODF_MASK;
1779         reg |= (div - 1) << MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET;
1780         __raw_writel(reg, MXC_CCM_CSCDR1);
1781
1782         return 0;
1783 }
1784
1785
1786 static struct clk usdhc3_clk = {
1787         __INIT_CLK_DEBUG(usdhc3_clk)
1788         .id = 2,
1789         .parent = &pll2_pfd_400M,
1790         .enable_reg = MXC_CCM_CCGR6,
1791         .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET,
1792         .enable = _clk_enable,
1793         .disable = _clk_disable,
1794         .set_parent = _clk_usdhc3_set_parent,
1795         .round_rate = _clk_usdhc_round_rate,
1796         .set_rate = _clk_usdhc3_set_rate,
1797         .get_rate = _clk_usdhc3_get_rate,
1798 };
1799
1800 static int _clk_usdhc4_set_parent(struct clk *clk, struct clk *parent)
1801 {
1802         u32 reg = __raw_readl(MXC_CCM_CSCMR1) & MXC_CCM_CSCMR1_USDHC4_CLK_SEL;
1803
1804         if (parent == &pll2_pfd_352M)
1805                 reg |= (MXC_CCM_CSCMR1_USDHC4_CLK_SEL);
1806
1807         __raw_writel(reg, MXC_CCM_CSCMR1);
1808
1809         return 0;
1810 }
1811
1812 static unsigned long _clk_usdhc4_get_rate(struct clk *clk)
1813 {
1814         u32 reg, div;
1815
1816         reg = __raw_readl(MXC_CCM_CSCDR1);
1817         div = ((reg & MXC_CCM_CSCDR1_USDHC4_PODF_MASK) >>
1818                         MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET) + 1;
1819
1820         return clk_get_rate(clk->parent) / div;
1821 }
1822
1823 static int _clk_usdhc4_set_rate(struct clk *clk, unsigned long rate)
1824 {
1825         u32 reg, div;
1826         u32 parent_rate = clk_get_rate(clk->parent);
1827
1828         div = parent_rate / rate;
1829         if (div == 0)
1830                 div++;
1831         if (((parent_rate / div) != rate) || (div > 8))
1832                 return -EINVAL;
1833
1834         reg = __raw_readl(MXC_CCM_CSCDR1);
1835         reg &= ~MXC_CCM_CSCDR1_USDHC4_PODF_MASK;
1836         reg |= (div - 1) << MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET;
1837         __raw_writel(reg, MXC_CCM_CSCDR1);
1838
1839         return 0;
1840 }
1841
1842
1843 static struct clk usdhc4_clk = {
1844         __INIT_CLK_DEBUG(usdhc4_clk)
1845         .id = 3,
1846         .parent = &pll2_pfd_400M,
1847         .enable_reg = MXC_CCM_CCGR6,
1848         .enable_shift = MXC_CCM_CCGRx_CG4_OFFSET,
1849         .enable = _clk_enable,
1850         .disable = _clk_disable,
1851         .set_parent = _clk_usdhc4_set_parent,
1852         .round_rate = _clk_usdhc_round_rate,
1853         .set_rate = _clk_usdhc4_set_rate,
1854         .get_rate = _clk_usdhc4_get_rate,
1855 };
1856
1857 static unsigned long _clk_ssi_round_rate(struct clk *clk,
1858                                                 unsigned long rate)
1859 {
1860         u32 pre, post;
1861         u32 parent_rate = clk_get_rate(clk->parent);
1862         u32 div = parent_rate / rate;
1863
1864         if (parent_rate % rate)
1865                 div++;
1866
1867         __calc_pre_post_dividers(div, &pre, &post);
1868
1869         return parent_rate / (pre * post);
1870 }
1871
1872 static unsigned long _clk_ssi1_get_rate(struct clk *clk)
1873 {
1874         u32 reg, prediv, podf;
1875
1876         reg = __raw_readl(MXC_CCM_CS1CDR);
1877
1878         prediv = ((reg & MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK)
1879                 >> MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET) + 1;
1880         podf = ((reg & MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK)
1881                 >> MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET) + 1;
1882
1883         return clk_get_rate(clk->parent) / (prediv * podf);
1884 }
1885
1886 static int _clk_ssi1_set_rate(struct clk *clk, unsigned long rate)
1887 {
1888         u32 reg, div, pre, post;
1889         u32 parent_rate = clk_get_rate(clk->parent);
1890
1891         div = parent_rate / rate;
1892         if (div == 0)
1893                 div++;
1894         if (((parent_rate / div) != rate) || div > 512)
1895                 return -EINVAL;
1896
1897         __calc_pre_post_dividers(div, &pre, &post);
1898
1899         reg = __raw_readl(MXC_CCM_CS1CDR);
1900         reg &= ~(MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK |
1901                  MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK);
1902         reg |= (post - 1) << MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET;
1903         reg |= (pre - 1) << MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET;
1904
1905         __raw_writel(reg, MXC_CCM_CS1CDR);
1906
1907         return 0;
1908 }
1909
1910
1911 static int _clk_ssi1_set_parent(struct clk *clk, struct clk *parent)
1912 {
1913         u32 reg, mux;
1914
1915         reg = __raw_readl(MXC_CCM_CSCMR1)
1916                 & MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK;
1917
1918         mux = _get_mux6(parent, &pll3_pfd_508M, &pll3_pfd_454M,
1919                         &pll4_audio_main_clk, NULL, NULL, NULL);
1920         reg |= (mux << MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET);
1921
1922         __raw_writel(reg, MXC_CCM_CSCMR1);
1923
1924         return 0;
1925 }
1926
1927 static struct clk ssi1_clk = {
1928         __INIT_CLK_DEBUG(ssi1_clk)
1929         .parent = &pll3_pfd_508M,
1930         .enable_reg = MXC_CCM_CCGR5,
1931         .enable_shift = MXC_CCM_CCGRx_CG9_OFFSET,
1932         .enable = _clk_enable,
1933         .disable = _clk_disable,
1934         .set_parent = _clk_ssi1_set_parent,
1935         .set_rate = _clk_ssi1_set_rate,
1936         .round_rate = _clk_ssi_round_rate,
1937         .get_rate = _clk_ssi1_get_rate,
1938 };
1939
1940 static unsigned long _clk_ssi2_get_rate(struct clk *clk)
1941 {
1942         u32 reg, prediv, podf;
1943
1944         reg = __raw_readl(MXC_CCM_CS2CDR);
1945
1946         prediv = ((reg & MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK)
1947                 >> MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET) + 1;
1948         podf = ((reg & MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK)
1949                 >> MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET) + 1;
1950
1951         return clk_get_rate(clk->parent) / (prediv * podf);
1952 }
1953
1954 static int _clk_ssi2_set_rate(struct clk *clk, unsigned long rate)
1955 {
1956         u32 reg, div, pre, post;
1957         u32 parent_rate = clk_get_rate(clk->parent);
1958
1959         div = parent_rate / rate;
1960         if (div == 0)
1961                 div++;
1962         if (((parent_rate / div) != rate) || div > 512)
1963                 return -EINVAL;
1964
1965         __calc_pre_post_dividers(div, &pre, &post);
1966
1967         reg = __raw_readl(MXC_CCM_CS2CDR);
1968         reg &= ~(MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK |
1969                  MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK);
1970         reg |= (post - 1) << MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET;
1971         reg |= (pre - 1) << MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET;
1972
1973         __raw_writel(reg, MXC_CCM_CS2CDR);
1974
1975         return 0;
1976 }
1977
1978
1979 static int _clk_ssi2_set_parent(struct clk *clk, struct clk *parent)
1980 {
1981         u32 reg, mux;
1982
1983         reg = __raw_readl(MXC_CCM_CSCMR1)
1984                 & MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK;
1985
1986         mux = _get_mux6(parent, &pll3_pfd_508M, &pll3_pfd_454M,
1987                         &pll4_audio_main_clk, NULL, NULL, NULL);
1988         reg |= (mux << MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET);
1989
1990         __raw_writel(reg, MXC_CCM_CSCMR1);
1991
1992         return 0;
1993 }
1994
1995 static struct clk ssi2_clk = {
1996         __INIT_CLK_DEBUG(ssi2_clk)
1997         .parent = &pll3_pfd_508M,
1998         .enable_reg = MXC_CCM_CCGR5,
1999         .enable_shift = MXC_CCM_CCGRx_CG10_OFFSET,
2000         .enable = _clk_enable,
2001         .disable = _clk_disable,
2002         .set_parent = _clk_ssi2_set_parent,
2003         .set_rate = _clk_ssi2_set_rate,
2004         .round_rate = _clk_ssi_round_rate,
2005         .get_rate = _clk_ssi2_get_rate,
2006 };
2007
2008 static unsigned long _clk_ssi3_get_rate(struct clk *clk)
2009 {
2010         u32 reg, prediv, podf;
2011
2012         reg = __raw_readl(MXC_CCM_CS1CDR);
2013
2014         prediv = ((reg & MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK)
2015                 >> MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET) + 1;
2016         podf = ((reg & MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK)
2017                 >> MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET) + 1;
2018
2019         return clk_get_rate(clk->parent) / (prediv * podf);
2020 }
2021
2022 static int _clk_ssi3_set_rate(struct clk *clk, unsigned long rate)
2023 {
2024         u32 reg, div, pre, post;
2025         u32 parent_rate = clk_get_rate(clk->parent);
2026
2027         div = parent_rate / rate;
2028         if (div == 0)
2029                 div++;
2030         if (((parent_rate / div) != rate) || div > 512)
2031                 return -EINVAL;
2032
2033         __calc_pre_post_dividers(div, &pre, &post);
2034
2035         reg = __raw_readl(MXC_CCM_CS1CDR);
2036         reg &= ~(MXC_CCM_CS1CDR_SSI3_CLK_PODF_MASK|
2037                  MXC_CCM_CS1CDR_SSI3_CLK_PRED_MASK);
2038         reg |= (post - 1) << MXC_CCM_CS1CDR_SSI3_CLK_PODF_OFFSET;
2039         reg |= (pre - 1) << MXC_CCM_CS1CDR_SSI3_CLK_PRED_OFFSET;
2040
2041         __raw_writel(reg, MXC_CCM_CS1CDR);
2042
2043         return 0;
2044 }
2045
2046
2047 static int _clk_ssi3_set_parent(struct clk *clk, struct clk *parent)
2048 {
2049         u32 reg, mux;
2050
2051         reg = __raw_readl(MXC_CCM_CSCMR1) & MXC_CCM_CSCMR1_SSI3_CLK_SEL_MASK;
2052
2053         mux = _get_mux6(parent, &pll3_pfd_508M, &pll3_pfd_454M,
2054                                 &pll4_audio_main_clk, NULL, NULL, NULL);
2055         reg |= (mux << MXC_CCM_CSCMR1_SSI3_CLK_SEL_OFFSET);
2056
2057         __raw_writel(reg, MXC_CCM_CSCMR1);
2058
2059         return 0;
2060 }
2061
2062 static struct clk ssi3_clk = {
2063         __INIT_CLK_DEBUG(ssi3_clk)
2064         .parent = &pll3_pfd_508M,
2065         .enable_reg = MXC_CCM_CCGR5,
2066         .enable_shift = MXC_CCM_CCGRx_CG11_OFFSET,
2067         .enable = _clk_enable,
2068         .disable = _clk_disable,
2069         .set_parent = _clk_ssi3_set_parent,
2070         .set_rate = _clk_ssi3_set_rate,
2071         .round_rate = _clk_ssi_round_rate,
2072         .get_rate = _clk_ssi3_get_rate,
2073 };
2074
2075 static unsigned long _clk_ldb_di_round_rate(struct clk *clk,
2076                                                 unsigned long rate)
2077 {
2078         u32 parent_rate = clk_get_rate(clk->parent);
2079
2080         if (rate * 7 <= parent_rate + parent_rate/20)
2081                 return parent_rate / 7;
2082         else
2083                 return 2 * parent_rate / 7;
2084 }
2085
2086 static unsigned long _clk_ldb_di0_get_rate(struct clk *clk)
2087 {
2088         u32 div;
2089
2090         div = __raw_readl(MXC_CCM_CSCMR2) &
2091                 MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
2092
2093         if (div)
2094                 return clk_get_rate(clk->parent) / 7;
2095
2096         return (2 * clk_get_rate(clk->parent)) / 7;
2097 }
2098
2099 static int _clk_ldb_di0_set_rate(struct clk *clk, unsigned long rate)
2100 {
2101         u32 reg, div = 0;
2102         u32 parent_rate = clk_get_rate(clk->parent);
2103
2104         if (rate * 7 <= parent_rate + parent_rate/20) {
2105                 div = 7;
2106                 rate = parent_rate / 7;
2107         } else
2108                 rate = 2 * parent_rate / 7;
2109
2110         reg = __raw_readl(MXC_CCM_CSCMR2);
2111         if (div == 7)
2112                 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
2113         else
2114                 reg &= ~MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
2115
2116         __raw_writel(reg, MXC_CCM_CSCMR2);
2117
2118         return 0;
2119 }
2120
2121 static int _clk_ldb_di0_set_parent(struct clk *clk, struct clk *parent)
2122 {
2123         u32 reg, mux;
2124
2125         reg = __raw_readl(MXC_CCM_CS2CDR)
2126                 & MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK;
2127
2128         mux = _get_mux6(parent, &pll5_video_main_clk,
2129                 &pll2_pfd_352M, &pll2_pfd_400M, &pll3_pfd_540M,
2130                 &pll3_usb_otg_main_clk, NULL);
2131         reg |= (mux << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET);
2132
2133         __raw_writel(reg, MXC_CCM_CS2CDR);
2134
2135         return 0;
2136 }
2137
2138 static struct clk ldb_di0_clk = {
2139          __INIT_CLK_DEBUG(ldb_di0_clk)
2140         .id = 0,
2141         .parent = &pll3_pfd_540M,
2142         .enable_reg = MXC_CCM_CCGR3,
2143         .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
2144         .enable = _clk_enable,
2145         .disable = _clk_disable,
2146         .set_parent = _clk_ldb_di0_set_parent,
2147         .set_rate = _clk_ldb_di0_set_rate,
2148         .round_rate = _clk_ldb_di_round_rate,
2149         .get_rate = _clk_ldb_di0_get_rate,
2150 };
2151
2152 static unsigned long _clk_ldb_di1_get_rate(struct clk *clk)
2153 {
2154         u32 div;
2155
2156         div = __raw_readl(MXC_CCM_CSCMR2) &
2157                 MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
2158
2159         if (div)
2160                 return clk_get_rate(clk->parent) / 7;
2161
2162         return (2 * clk_get_rate(clk->parent)) / 7;
2163 }
2164
2165 static int _clk_ldb_di1_set_rate(struct clk *clk, unsigned long rate)
2166 {
2167         u32 reg, div = 0;
2168         u32 parent_rate = clk_get_rate(clk->parent);
2169
2170         if (rate * 7 <= parent_rate + parent_rate/20) {
2171                 div = 7;
2172                 rate = parent_rate / 7;
2173         } else
2174                 rate = 2 * parent_rate / 7;
2175
2176         reg = __raw_readl(MXC_CCM_CSCMR2);
2177         if (div == 7)
2178                 reg |= MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
2179         else
2180                 reg &= ~MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
2181
2182         __raw_writel(reg, MXC_CCM_CSCMR2);
2183
2184         return 0;
2185 }
2186
2187 static int _clk_ldb_di1_set_parent(struct clk *clk, struct clk *parent)
2188 {
2189         u32 reg, mux;
2190
2191         reg = __raw_readl(MXC_CCM_CS2CDR)
2192                 & MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK;
2193
2194         mux = _get_mux6(parent, &pll5_video_main_clk,
2195                 &pll2_pfd_352M, &pll2_pfd_400M, &pll3_pfd_540M,
2196                 &pll3_usb_otg_main_clk, NULL);
2197         reg |= (mux << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
2198
2199         __raw_writel(reg, MXC_CCM_CS2CDR);
2200
2201         return 0;
2202 }
2203
2204 static struct clk ldb_di1_clk = {
2205          __INIT_CLK_DEBUG(ldb_di1_clk)
2206         .id = 0,
2207         .parent = &pll3_pfd_540M,
2208         .enable_reg = MXC_CCM_CCGR3,
2209         .enable_shift = MXC_CCM_CCGRx_CG14_OFFSET,
2210         .enable = _clk_enable,
2211         .disable = _clk_disable,
2212         .set_parent = _clk_ldb_di1_set_parent,
2213         .set_rate = _clk_ldb_di1_set_rate,
2214         .round_rate = _clk_ldb_di_round_rate,
2215         .get_rate = _clk_ldb_di1_get_rate,
2216 };
2217
2218
2219 static unsigned long _clk_ipu_di_round_rate(struct clk *clk,
2220                                                 unsigned long rate)
2221 {
2222         u32 div;
2223         u32 parent_rate = clk_get_rate(clk->parent);
2224
2225         if ((clk->parent == &ldb_di0_clk) ||
2226                 (clk->parent == &ldb_di1_clk))
2227                 return parent_rate;
2228
2229         div = parent_rate / rate;
2230
2231         /* Make sure rate is not greater than the maximum value for the clock.
2232          * Also prevent a div of 0.
2233          */
2234         if (div == 0)
2235                 div++;
2236
2237         if (div > 8)
2238                 div = 8;
2239
2240         return parent_rate / div;
2241 }
2242
2243 static unsigned long _clk_ipu1_di0_get_rate(struct clk *clk)
2244 {
2245         u32 reg, div;
2246
2247         if ((clk->parent == &ldb_di0_clk) ||
2248                 (clk->parent == &ldb_di1_clk))
2249                 return clk_get_rate(clk->parent);
2250
2251         reg = __raw_readl(MXC_CCM_CHSCCDR);
2252
2253         div = ((reg & MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK) >>
2254                          MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET) + 1;
2255
2256         return clk_get_rate(clk->parent) / div;
2257 }
2258
2259 static int _clk_ipu1_di0_set_rate(struct clk *clk, unsigned long rate)
2260 {
2261         u32 reg, div;
2262         u32 parent_rate = clk_get_rate(clk->parent);
2263
2264         if ((clk->parent == &ldb_di0_clk) ||
2265                 (clk->parent == &ldb_di1_clk)) {
2266                 if (parent_rate == rate)
2267                         return 0;
2268                 else
2269                         return -EINVAL;
2270         }
2271
2272         div = parent_rate / rate;
2273         if (div == 0)
2274                 div++;
2275         if (((parent_rate / div) != rate) || (div > 8))
2276                 return -EINVAL;
2277
2278         reg = __raw_readl(MXC_CCM_CHSCCDR);
2279         reg &= ~MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK;
2280         reg |= (div - 1) << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET;
2281         __raw_writel(reg, MXC_CCM_CHSCCDR);
2282
2283         return 0;
2284 }
2285
2286
2287 static int _clk_ipu1_di0_set_parent(struct clk *clk, struct clk *parent)
2288 {
2289         u32 reg, mux;
2290
2291         if (parent == &ldb_di0_clk)
2292                 mux = 0x3;
2293         else if (parent == &ldb_di1_clk)
2294                 mux = 0x4;
2295         else {
2296                 reg = __raw_readl(MXC_CCM_CHSCCDR)
2297                         & ~MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK;
2298
2299                 mux = _get_mux6(parent, &mmdc_ch0_axi_clk[0],
2300                                 &pll3_usb_otg_main_clk, &pll5_video_main_clk,
2301                                 &pll2_pfd_352M, &pll2_pfd_400M, &pll3_pfd_540M);
2302                 reg |= (mux << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
2303
2304                 __raw_writel(reg, MXC_CCM_CHSCCDR);
2305
2306                 /* Derive clock from divided pre-muxed ipu1_di0 clock.*/
2307                 mux = 0;
2308         }
2309
2310         reg = __raw_readl(MXC_CCM_CHSCCDR)
2311                 & ~MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK;
2312         __raw_writel(reg | (mux << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET),
2313                 MXC_CCM_CHSCCDR);
2314
2315         return 0;
2316 }
2317
2318 static unsigned long _clk_ipu1_di1_get_rate(struct clk *clk)
2319 {
2320         u32 reg, div;
2321
2322         if ((clk->parent == &ldb_di0_clk) ||
2323                 (clk->parent == &ldb_di1_clk))
2324                 return clk_get_rate(clk->parent);
2325
2326         reg = __raw_readl(MXC_CCM_CHSCCDR);
2327
2328         div = (reg & MXC_CCM_CHSCCDR_IPU1_DI1_PODF_MASK) + 1;
2329
2330         return clk_get_rate(clk->parent) / div;
2331 }
2332
2333 static int _clk_ipu1_di1_set_rate(struct clk *clk, unsigned long rate)
2334 {
2335         u32 reg, div;
2336         u32 parent_rate = clk_get_rate(clk->parent);
2337
2338         if ((clk->parent == &ldb_di0_clk) ||
2339                 (clk->parent == &ldb_di1_clk)) {
2340                 if (parent_rate == rate)
2341                         return 0;
2342                 else
2343                         return -EINVAL;
2344         }
2345
2346         div = parent_rate / rate;
2347         if (div == 0)
2348                 div++;
2349         if (((parent_rate / div) != rate) || (div > 8))
2350                 return -EINVAL;
2351
2352         reg = __raw_readl(MXC_CCM_CHSCCDR);
2353         reg &= ~MXC_CCM_CHSCCDR_IPU1_DI1_PODF_MASK;
2354         reg |= (div - 1) << MXC_CCM_CHSCCDR_IPU1_DI1_PODF_OFFSET;
2355         __raw_writel(reg, MXC_CCM_CHSCCDR);
2356
2357         return 0;
2358 }
2359
2360
2361 static int _clk_ipu1_di1_set_parent(struct clk *clk, struct clk *parent)
2362 {
2363         u32 reg, mux;
2364
2365         if (parent == &ldb_di0_clk)
2366                 mux = 0x3;
2367         else if (parent == &ldb_di1_clk)
2368                 mux = 0x4;
2369         else {
2370                 reg = __raw_readl(MXC_CCM_CHSCCDR)
2371                         & ~MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_MASK;
2372
2373                 mux = _get_mux6(parent, &mmdc_ch0_axi_clk[0],
2374                                 &pll3_usb_otg_main_clk, &pll5_video_main_clk,
2375                                 &pll2_pfd_352M, &pll2_pfd_400M, &pll3_pfd_540M);
2376                 reg |= (mux << MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_OFFSET);
2377
2378                 __raw_writel(reg, MXC_CCM_CHSCCDR);
2379
2380                 /* Derive clock from divided pre-muxed ipu1_di0 clock.*/
2381                 mux = 0;
2382         }
2383         reg = __raw_readl(MXC_CCM_CHSCCDR)
2384                 & ~MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_MASK;
2385         __raw_writel(reg | (mux << MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET),
2386                 MXC_CCM_CHSCCDR);
2387
2388         return 0;
2389 }
2390
2391 static struct clk ipu1_di_clk[] = {
2392         {
2393          __INIT_CLK_DEBUG(ipu1_di_clk_0)
2394         .id = 0,
2395         .parent = &pll3_pfd_540M,
2396         .enable_reg = MXC_CCM_CCGR3,
2397         .enable_shift = MXC_CCM_CCGRx_CG1_OFFSET,
2398         .enable = _clk_enable,
2399         .disable = _clk_disable,
2400         .set_parent = _clk_ipu1_di0_set_parent,
2401         .set_rate = _clk_ipu1_di0_set_rate,
2402         .round_rate = _clk_ipu_di_round_rate,
2403         .get_rate = _clk_ipu1_di0_get_rate,
2404         },
2405         {
2406          __INIT_CLK_DEBUG(ipu1_di_clk_1)
2407         .id = 1,
2408         .parent = &pll3_pfd_540M,
2409         .enable_reg = MXC_CCM_CCGR3,
2410         .enable_shift = MXC_CCM_CCGRx_CG2_OFFSET,
2411         .enable = _clk_enable,
2412         .disable = _clk_disable,
2413         .set_parent = _clk_ipu1_di1_set_parent,
2414         .set_rate = _clk_ipu1_di1_set_rate,
2415         .round_rate = _clk_ipu_di_round_rate,
2416         .get_rate = _clk_ipu1_di1_get_rate,
2417         },
2418 };
2419
2420 static unsigned long _clk_ipu2_di0_get_rate(struct clk *clk)
2421 {
2422         u32 reg, div;
2423
2424         if ((clk->parent == &ldb_di0_clk) ||
2425                 (clk->parent == &ldb_di1_clk))
2426                 return clk_get_rate(clk->parent);
2427
2428         reg = __raw_readl(MXC_CCM_CHSCCDR);
2429
2430         div = (reg & MXC_CCM_CHSCCDR_IPU2_DI0_PODF_MASK) + 1;
2431
2432         return clk_get_rate(clk->parent) / div;
2433 }
2434
2435 static int _clk_ipu2_di0_set_rate(struct clk *clk, unsigned long rate)
2436 {
2437         u32 reg, div;
2438         u32 parent_rate = clk_get_rate(clk->parent);
2439
2440         if ((clk->parent == &ldb_di0_clk) ||
2441                 (clk->parent == &ldb_di1_clk)) {
2442                 if (parent_rate == rate)
2443                         return 0;
2444                 else
2445                         return -EINVAL;
2446         }
2447
2448         div = parent_rate / rate;
2449         if (div == 0)
2450                 div++;
2451         if (((parent_rate / div) != rate) || (div > 8))
2452                 return -EINVAL;
2453
2454         reg = __raw_readl(MXC_CCM_CHSCCDR);
2455         reg &= ~MXC_CCM_CHSCCDR_IPU2_DI0_PODF_MASK;
2456         reg |= (div - 1) << MXC_CCM_CHSCCDR_IPU2_DI0_PODF_OFFSET;
2457         __raw_writel(reg, MXC_CCM_CHSCCDR);
2458
2459         return 0;
2460 }
2461
2462 static int _clk_ipu2_di0_set_parent(struct clk *clk, struct clk *parent)
2463 {
2464         u32 reg, mux;
2465
2466         if (parent == &ldb_di0_clk)
2467                 mux = 0x3;
2468         else if (parent == &ldb_di1_clk)
2469                 mux = 0x4;
2470         else {
2471                 reg = __raw_readl(MXC_CCM_CHSCCDR)
2472                         & ~MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_MASK;
2473
2474                 mux = _get_mux6(parent, &mmdc_ch0_axi_clk[0],
2475                                 &pll3_usb_otg_main_clk, &pll5_video_main_clk,
2476                                 &pll2_pfd_352M, &pll2_pfd_400M, &pll3_pfd_540M);
2477                 reg |= (mux << MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_OFFSET);
2478
2479                 __raw_writel(reg, MXC_CCM_CHSCCDR);
2480
2481                 /* Derive clock from divided pre-muxed ipu2_di0 clock.*/
2482                 mux = 0;
2483         }
2484         reg = __raw_readl(MXC_CCM_CHSCCDR)
2485                 & ~MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_MASK;
2486         __raw_writel(reg | (mux << MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_OFFSET),
2487                 MXC_CCM_CHSCCDR);
2488
2489         return 0;
2490 }
2491
2492 static unsigned long _clk_ipu2_di1_get_rate(struct clk *clk)
2493 {
2494         u32 reg, div;
2495
2496         if ((clk->parent == &ldb_di0_clk) ||
2497                 (clk->parent == &ldb_di1_clk))
2498                 return clk_get_rate(clk->parent);
2499
2500         reg = __raw_readl(MXC_CCM_CHSCCDR);
2501
2502         div = (reg & MXC_CCM_CHSCCDR_IPU2_DI1_PODF_MASK) + 1;
2503
2504         return clk_get_rate(clk->parent) / div;
2505 }
2506
2507 static int _clk_ipu2_di1_set_rate(struct clk *clk, unsigned long rate)
2508 {
2509         u32 reg, div;
2510         u32 parent_rate = clk_get_rate(clk->parent);
2511
2512         if ((clk->parent == &ldb_di0_clk) ||
2513                 (clk->parent == &ldb_di1_clk)) {
2514                 if (parent_rate == rate)
2515                         return 0;
2516                 else
2517                         return -EINVAL;
2518         }
2519
2520         div = parent_rate / rate;
2521         if (div == 0)
2522                 div++;
2523         if (((parent_rate / div) != rate) || (div > 8))
2524                 return -EINVAL;
2525
2526         reg = __raw_readl(MXC_CCM_CHSCCDR);
2527         reg &= ~MXC_CCM_CHSCCDR_IPU2_DI1_PODF_MASK;
2528         reg |= (div - 1) << MXC_CCM_CHSCCDR_IPU2_DI1_PODF_OFFSET;
2529         __raw_writel(reg, MXC_CCM_CHSCCDR);
2530
2531         return 0;
2532 }
2533
2534 static int _clk_ipu2_di1_set_parent(struct clk *clk, struct clk *parent)
2535 {
2536         u32 reg, mux;
2537
2538         if (parent == &ldb_di0_clk)
2539                 mux = 0x3;
2540         else if (parent == &ldb_di1_clk)
2541                 mux = 0x4;
2542         else {
2543                 reg = __raw_readl(MXC_CCM_CHSCCDR)
2544                         & ~MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_MASK;
2545
2546                 mux = _get_mux6(parent, &mmdc_ch0_axi_clk[0],
2547                                 &pll3_usb_otg_main_clk, &pll5_video_main_clk,
2548                                 &pll2_pfd_352M, &pll2_pfd_400M, &pll3_pfd_540M);
2549                 reg |= (mux << MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_OFFSET);
2550
2551                 __raw_writel(reg, MXC_CCM_CHSCCDR);
2552
2553                 /* Derive clock from divided pre-muxed ipu1_di0 clock.*/
2554                 mux = 0;
2555         }
2556         reg = __raw_readl(MXC_CCM_CHSCCDR)
2557                 & ~MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_MASK;
2558         __raw_writel(reg | (mux << MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_OFFSET),
2559                 MXC_CCM_CHSCCDR);
2560
2561         return 0;
2562 }
2563
2564 static struct clk ipu2_di_clk[] = {
2565         {
2566          __INIT_CLK_DEBUG(ipu2_di_clk_0)
2567         .id = 0,
2568         .parent = &pll3_pfd_540M,
2569         .enable_reg = MXC_CCM_CCGR3,
2570         .enable_shift = MXC_CCM_CCGRx_CG1_OFFSET,
2571         .enable = _clk_enable,
2572         .disable = _clk_disable,
2573         .set_parent = _clk_ipu2_di0_set_parent,
2574         .set_rate = _clk_ipu2_di0_set_rate,
2575         .round_rate = _clk_ipu_di_round_rate,
2576         .get_rate = _clk_ipu2_di0_get_rate,
2577         },
2578         {
2579          __INIT_CLK_DEBUG(ipu2_di_clk_1)
2580         .id = 1,
2581         .parent = &pll3_pfd_540M,
2582         .enable_reg = MXC_CCM_CCGR3,
2583         .enable_shift = MXC_CCM_CCGRx_CG2_OFFSET,
2584         .enable = _clk_enable,
2585         .disable = _clk_disable,
2586         .set_parent = _clk_ipu2_di1_set_parent,
2587         .set_rate = _clk_ipu2_di1_set_rate,
2588         .round_rate = _clk_ipu_di_round_rate,
2589         .get_rate = _clk_ipu2_di1_get_rate,
2590         },
2591 };
2592
2593 static struct clk can2_clk[] = {
2594         {
2595          __INIT_CLK_DEBUG(can2_module_clk)
2596         .id = 0,
2597         .parent = &pll3_sw_clk,
2598         .enable_reg = MXC_CCM_CCGR0,
2599         .enable_shift = MXC_CCM_CCGRx_CG9_OFFSET,
2600         .enable = _clk_enable,
2601         .disable = _clk_disable,
2602         .secondary = &can2_clk[1],
2603         },
2604         {
2605          __INIT_CLK_DEBUG(can2_serial_clk)
2606         .id = 1,
2607         .parent = &pll3_sw_clk,
2608         .enable_reg = MXC_CCM_CCGR0,
2609         .enable_shift = MXC_CCM_CCGRx_CG10_OFFSET,
2610         .enable = _clk_enable,
2611         .disable = _clk_disable,
2612         },
2613 };
2614
2615
2616 static struct clk can1_clk[] = {
2617         {
2618          __INIT_CLK_DEBUG(can1_module_clk)
2619         .id = 0,
2620         .parent = &pll3_sw_clk,
2621         .enable_reg = MXC_CCM_CCGR0,
2622         .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
2623         .enable = _clk_enable,
2624         .disable = _clk_disable,
2625         .secondary = &can1_clk[1],
2626         },
2627         {
2628          __INIT_CLK_DEBUG(can1_serial_clk)
2629         .id = 1,
2630         .parent = &pll3_sw_clk,
2631         .enable_reg = MXC_CCM_CCGR0,
2632         .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET,
2633         .enable = _clk_enable,
2634         .disable = _clk_disable,
2635         },
2636 };
2637
2638 static unsigned long _clk_spdif_round_rate(struct clk *clk,
2639                                                 unsigned long rate)
2640 {
2641         u32 pre, post;
2642         u32 parent_rate = clk_get_rate(clk->parent);
2643         u32 div = parent_rate / rate;
2644
2645         if (parent_rate % rate)
2646                 div++;
2647
2648         __calc_pre_post_dividers(div, &pre, &post);
2649
2650         return parent_rate / (pre * post);
2651 }
2652
2653 static int _clk_spdif0_set_parent(struct clk *clk, struct clk *parent)
2654 {
2655         u32 reg, mux;
2656
2657         reg = __raw_readl(MXC_CCM_CDCDR)
2658                 & MXC_CCM_CDCDR_SPDIF0_CLK_SEL_MASK;
2659
2660         mux = _get_mux6(parent, &pll4_audio_main_clk,
2661                 &pll3_pfd_508M, &pll3_pfd_454M,
2662                 &pll3_sw_clk, NULL, NULL);
2663         reg |= mux << MXC_CCM_CDCDR_SPDIF0_CLK_SEL_OFFSET;
2664
2665         __raw_writel(reg, MXC_CCM_CDCDR);
2666
2667         return 0;
2668 }
2669
2670 static unsigned long _clk_spdif0_get_rate(struct clk *clk)
2671 {
2672         u32 reg, pred, podf;
2673
2674         reg = __raw_readl(MXC_CCM_CDCDR);
2675
2676         pred = ((reg & MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK)
2677                 >> MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET) + 1;
2678         podf = ((reg & MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK)
2679                 >> MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET) + 1;
2680
2681         return clk_get_rate(clk->parent) / (pred * podf);
2682 }
2683
2684 static int _clk_spdif0_set_rate(struct clk *clk, unsigned long rate)
2685 {
2686         u32 reg, div, pre, post;
2687         u32 parent_rate = clk_get_rate(clk->parent);
2688
2689         div = parent_rate / rate;
2690         if (div == 0)
2691                 div++;
2692         if (((parent_rate / div) != rate) || div > 512)
2693                 return -EINVAL;
2694
2695         __calc_pre_post_dividers(div, &pre, &post);
2696
2697         reg = __raw_readl(MXC_CCM_CDCDR);
2698         reg &= ~(MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK|
2699                  MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK);
2700         reg |= (post - 1) << MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET;
2701         reg |= (pre - 1) << MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET;
2702
2703         __raw_writel(reg, MXC_CCM_CDCDR);
2704
2705         return 0;
2706 }
2707
2708 static struct clk spdif0_clk[] = {
2709         {
2710         __INIT_CLK_DEBUG(spdif0_clk_0)
2711         .id = 0,
2712         .parent = &pll3_sw_clk,
2713          .enable = _clk_enable,
2714          .enable_reg = MXC_CCM_CCGR5,
2715          .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
2716          .disable = _clk_disable,
2717          .secondary = &spdif0_clk[1],
2718          .set_rate = _clk_spdif0_set_rate,
2719          .get_rate = _clk_spdif0_get_rate,
2720          .set_parent = _clk_spdif0_set_parent,
2721          .round_rate = _clk_spdif_round_rate,
2722         },
2723         {
2724         __INIT_CLK_DEBUG(spdif0_clk_1)
2725          .id = 1,
2726          .parent = &ipg_clk,
2727          .secondary = &spba_clk,
2728          },
2729 };
2730
2731 static int _clk_spdif1_set_parent(struct clk *clk, struct clk *parent)
2732 {
2733         u32 reg, mux;
2734
2735         reg = __raw_readl(MXC_CCM_CDCDR) & MXC_CCM_CDCDR_SPDIF1_CLK_SEL_MASK;
2736
2737         mux = _get_mux6(parent, &pll4_audio_main_clk, &pll3_pfd_508M,
2738                         &pll3_pfd_454M, &pll3_sw_clk, NULL, NULL);
2739         reg |= mux << MXC_CCM_CDCDR_SPDIF1_CLK_SEL_OFFSET;
2740
2741         __raw_writel(reg, MXC_CCM_CDCDR);
2742
2743         return 0;
2744 }
2745
2746 static unsigned long _clk_spdif1_get_rate(struct clk *clk)
2747 {
2748         u32 reg, pred, podf;
2749
2750         reg = __raw_readl(MXC_CCM_CDCDR);
2751
2752         pred = ((reg & MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK)
2753                 >> MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET) + 1;
2754         podf = ((reg & MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK)
2755                 >> MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET) + 1;
2756
2757         return clk_get_rate(clk->parent) / (pred * podf);
2758 }
2759
2760 static int _clk_spdif1_set_rate(struct clk *clk, unsigned long rate)
2761 {
2762         u32 reg, div, pre, post;
2763         u32 parent_rate = clk_get_rate(clk->parent);
2764
2765         div = parent_rate / rate;
2766         if (div == 0)
2767                 div++;
2768         if (((parent_rate / div) != rate) || div > 512)
2769                 return -EINVAL;
2770
2771         __calc_pre_post_dividers(div, &pre, &post);
2772
2773         reg = __raw_readl(MXC_CCM_CDCDR);
2774         reg &= ~(MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK|
2775                  MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK);
2776         reg |= (post - 1) << MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET;
2777         reg |= (pre - 1) << MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET;
2778
2779         __raw_writel(reg, MXC_CCM_CDCDR);
2780
2781         return 0;
2782 }
2783
2784 static struct clk spdif1_clk[] = {
2785         {
2786         __INIT_CLK_DEBUG(spdif1_clk_0)
2787         .id = 0,
2788         .parent = &pll3_sw_clk,
2789          .enable = _clk_enable,
2790          .enable_reg = MXC_CCM_CCGR5,
2791          .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
2792          .disable = _clk_disable,
2793          .secondary = &spdif1_clk[1],
2794          .set_rate = _clk_spdif1_set_rate,
2795          .get_rate = _clk_spdif1_get_rate,
2796          .set_parent = _clk_spdif1_set_parent,
2797          .round_rate = _clk_spdif_round_rate,
2798         },
2799         {
2800         __INIT_CLK_DEBUG(spdif1_clk_1)
2801          .id = 0,
2802          .parent = &ipg_clk,
2803          .secondary = &spba_clk,
2804          },
2805 };
2806
2807 static unsigned long _clk_esai_round_rate(struct clk *clk,
2808                                                 unsigned long rate)
2809 {
2810         u32 pre, post;
2811         u32 parent_rate = clk_get_rate(clk->parent);
2812         u32 div = parent_rate / rate;
2813
2814         if (parent_rate % rate)
2815                 div++;
2816
2817         __calc_pre_post_dividers(div, &pre, &post);
2818
2819         return parent_rate / (pre * post);
2820 }
2821
2822 static int _clk_esai_set_parent(struct clk *clk, struct clk *parent)
2823 {
2824         u32 reg, mux;
2825
2826         reg = __raw_readl(MXC_CCM_CSCMR2) & MXC_CCM_CSCMR2_ESAI_CLK_SEL_MASK;
2827
2828         mux = _get_mux6(parent, &pll4_audio_main_clk, &pll3_pfd_508M,
2829                         &pll3_pfd_454M, &pll3_sw_clk, NULL, NULL);
2830         reg |= mux << MXC_CCM_CSCMR2_ESAI_CLK_SEL_OFFSET;
2831
2832         __raw_writel(reg, MXC_CCM_CSCMR2);
2833
2834         return 0;
2835 }
2836
2837 static unsigned long _clk_esai_get_rate(struct clk *clk)
2838 {
2839         u32 reg, pred, podf;
2840
2841         reg = __raw_readl(MXC_CCM_CS1CDR);
2842
2843         pred = ((reg & MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK)
2844                 >> MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET) + 1;
2845         podf = ((reg & MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK)
2846                 >> MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET) + 1;
2847
2848         return clk_get_rate(clk->parent) / (pred * podf);
2849 }
2850
2851 static int _clk_esai_set_rate(struct clk *clk, unsigned long rate)
2852 {
2853         u32 reg, div, pre, post;
2854         u32 parent_rate = clk_get_rate(clk->parent);
2855
2856         div = parent_rate / rate;
2857         if (div == 0)
2858                 div++;
2859         if (((parent_rate / div) != rate) || div > 512)
2860                 return -EINVAL;
2861
2862         __calc_pre_post_dividers(div, &pre, &post);
2863
2864         reg = __raw_readl(MXC_CCM_CS1CDR);
2865         reg &= ~(MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK|
2866                  MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK);
2867         reg |= (post - 1) << MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET;
2868         reg |= (pre - 1) << MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET;
2869
2870         __raw_writel(reg, MXC_CCM_CS1CDR);
2871
2872         return 0;
2873 }
2874
2875 static struct clk esai_clk = {
2876         __INIT_CLK_DEBUG(esai_clk)
2877          .id = 0,
2878          .parent = &pll3_sw_clk,
2879          .enable_reg = MXC_CCM_CCGR1,
2880          .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET,
2881          .enable = _clk_enable,
2882          .disable = _clk_disable,
2883          .set_rate = _clk_esai_set_rate,
2884          .get_rate = _clk_esai_get_rate,
2885          .set_parent = _clk_esai_set_parent,
2886          .round_rate = _clk_esai_round_rate,
2887 };
2888
2889 static int _clk_enet_enable(struct clk *clk)
2890 {
2891         unsigned int reg;
2892
2893         /* Enable ENET ref clock */
2894         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
2895         reg &= ~ANADIG_PLL_BYPASS;
2896         reg &= ~ANADIG_PLL_ENABLE;
2897         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
2898
2899         _clk_enable(clk);
2900         return 0;
2901 }
2902
2903 static void _clk_enet_disable(struct clk *clk)
2904 {
2905         unsigned int reg;
2906
2907         _clk_disable(clk);
2908
2909         /* Enable ENET ref clock */
2910         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
2911         reg |= ANADIG_PLL_BYPASS;
2912         reg |= ANADIG_PLL_ENABLE;
2913         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
2914 }
2915
2916 static int _clk_enet_set_rate(struct clk *clk, unsigned long rate)
2917 {
2918         unsigned int reg, div = 1;
2919
2920         switch (rate) {
2921         case 25000000:
2922                 div = 0;
2923                 break;
2924         case 50000000:
2925                 div = 1;
2926                 break;
2927         case 100000000:
2928                 div = 2;
2929                 break;
2930         case 125000000:
2931                 div = 3;
2932                 break;
2933         default:
2934                 return -EINVAL;
2935         }
2936         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
2937         reg &= ~ANADIG_PLL_ENET_DIV_SELECT_MASK;
2938         reg |= (div << ANADIG_PLL_ENET_DIV_SELECT_OFFSET);
2939         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
2940
2941         return 0;
2942 }
2943
2944 static unsigned long _clk_enet_get_rate(struct clk *clk)
2945 {
2946         unsigned int div;
2947
2948         div = (__raw_readl(PLL8_ENET_BASE_ADDR))
2949                 & ANADIG_PLL_ENET_DIV_SELECT_MASK;
2950
2951         return 500000000 / (div + 1);
2952 }
2953
2954 static struct clk enet_clk = {
2955         __INIT_CLK_DEBUG(enet_clk)
2956          .id = 0,
2957          .parent = &pll8_enet_main_clk,
2958          .enable_reg = MXC_CCM_CCGR1,
2959          .enable_shift = MXC_CCM_CCGRx_CG10_OFFSET,
2960          .enable = _clk_enet_enable,
2961          .disable = _clk_enet_disable,
2962          .set_rate = _clk_enet_set_rate,
2963          .get_rate = _clk_enet_get_rate,
2964 };
2965
2966 static struct clk ecspi_clk[] = {
2967         {
2968         __INIT_CLK_DEBUG(ecspi0_clk)
2969         .id = 0,
2970         .parent = &pll3_60M,
2971         .enable_reg = MXC_CCM_CCGR1,
2972         .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET,
2973         .enable = _clk_enable,
2974         .disable = _clk_disable,
2975         },
2976         {
2977         __INIT_CLK_DEBUG(ecspi1_clk)
2978         .id = 1,
2979         .parent = &pll3_60M,
2980         .enable_reg = MXC_CCM_CCGR1,
2981         .enable_shift = MXC_CCM_CCGRx_CG1_OFFSET,
2982         .enable = _clk_enable,
2983         .disable = _clk_disable,
2984         },
2985         {
2986         __INIT_CLK_DEBUG(ecspi2_clk)
2987         .id = 2,
2988         .parent = &pll3_60M,
2989         .enable_reg = MXC_CCM_CCGR1,
2990         .enable_shift = MXC_CCM_CCGRx_CG2_OFFSET,
2991         .enable = _clk_enable,
2992         .disable = _clk_disable,
2993         },
2994         {
2995         __INIT_CLK_DEBUG(ecspi3_clk)
2996         .id = 3,
2997         .parent = &pll3_60M,
2998         .enable_reg = MXC_CCM_CCGR1,
2999         .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET,
3000         .enable = _clk_enable,
3001         .disable = _clk_disable,
3002         },
3003         {
3004         __INIT_CLK_DEBUG(ecspi4_clk)
3005         .id = 4,
3006         .parent = &pll3_60M,
3007         .enable_reg = MXC_CCM_CCGR1,
3008         .enable_shift = MXC_CCM_CCGRx_CG4_OFFSET,
3009         .enable = _clk_enable,
3010         .disable = _clk_disable,
3011         },
3012 };
3013
3014 static unsigned long _clk_emi_slow_round_rate(struct clk *clk,
3015                                                 unsigned long rate)
3016 {
3017         u32 div;
3018         u32 parent_rate = clk_get_rate(clk->parent);
3019
3020         div = parent_rate / rate;
3021
3022         /* Make sure rate is not greater than the maximum value for the clock.
3023          * Also prevent a div of 0.
3024          */
3025         if (div == 0)
3026                 div++;
3027
3028         if (div > 8)
3029                 div = 8;
3030
3031         return parent_rate / div;
3032 }
3033
3034 static int _clk_emi_slow_set_parent(struct clk *clk, struct clk *parent)
3035 {
3036         int mux;
3037         u32 reg = __raw_readl(MXC_CCM_CSCMR1)
3038                 & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK;
3039
3040         mux = _get_mux6(parent, &axi_clk, &pll3_usb_otg_main_clk,
3041                                 &pll2_pfd_400M, &pll2_pfd_352M, NULL, NULL);
3042         reg |= (mux << MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET);
3043         __raw_writel(reg, MXC_CCM_CSCMR1);
3044
3045         return 0;
3046 }
3047
3048 static unsigned long _clk_emi_slow_get_rate(struct clk *clk)
3049 {
3050         u32 reg, div;
3051
3052         reg = __raw_readl(MXC_CCM_CSCMR1);
3053         div = ((reg & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK) >>
3054                         MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET) + 1;
3055
3056         return clk_get_rate(clk->parent) / div;
3057 }
3058
3059 static int _clk_emi_slow_set_rate(struct clk *clk, unsigned long rate)
3060 {
3061         u32 reg, div;
3062         u32 parent_rate = clk_get_rate(clk->parent);
3063
3064         div = parent_rate / rate;
3065         if (div == 0)
3066                 div++;
3067         if (((parent_rate / div) != rate) || (div > 8))
3068                 return -EINVAL;
3069
3070         reg = __raw_readl(MXC_CCM_CSCMR1);
3071         reg &= ~MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK;
3072         reg |= (div - 1) << MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET;
3073         __raw_writel(reg, MXC_CCM_CSCMR1);
3074
3075         return 0;
3076 }
3077
3078 static struct clk emi_slow_clk = {
3079         __INIT_CLK_DEBUG(emi_slow_clk)
3080          .id = 0,
3081          .parent = &axi_clk,
3082          .enable_reg = MXC_CCM_CCGR6,
3083          .enable_shift = MXC_CCM_CCGRx_CG5_OFFSET,
3084          .enable = _clk_enable,
3085          .disable = _clk_disable,
3086          .set_rate = _clk_emi_slow_set_rate,
3087          .get_rate = _clk_emi_slow_get_rate,
3088          .round_rate = _clk_emi_slow_round_rate,
3089          .set_parent = _clk_emi_slow_set_parent,
3090 };
3091
3092 static unsigned long _clk_emi_round_rate(struct clk *clk,
3093                                                 unsigned long rate)
3094 {
3095         u32 div;
3096         u32 parent_rate = clk_get_rate(clk->parent);
3097
3098         div = parent_rate / rate;
3099
3100         /* Make sure rate is not greater than the maximum value for the clock.
3101          * Also prevent a div of 0.
3102          */
3103         if (div == 0)
3104                 div++;
3105
3106         if (div > 8)
3107                 div = 8;
3108
3109         return parent_rate / div;
3110 }
3111
3112 static int _clk_emi_set_parent(struct clk *clk, struct clk *parent)
3113 {
3114         int mux;
3115         u32 reg = __raw_readl(MXC_CCM_CSCMR1) & MXC_CCM_CSCMR1_ACLK_EMI_MASK;
3116
3117         mux = _get_mux6(parent, &axi_clk, &pll3_usb_otg_main_clk,
3118                         &pll2_pfd_400M, &pll2_pfd_352M, NULL, NULL);
3119         reg |= (mux << MXC_CCM_CSCMR1_ACLK_EMI_OFFSET);
3120         __raw_writel(reg, MXC_CCM_CSCMR1);
3121
3122         return 0;
3123 }
3124
3125 static unsigned long _clk_emi_get_rate(struct clk *clk)
3126 {
3127         u32 reg, div;
3128
3129         reg = __raw_readl(MXC_CCM_CSCMR1);
3130         div = ((reg & MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK) >>
3131                         MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET) + 1;
3132
3133         return clk_get_rate(clk->parent) / div;
3134 }
3135
3136 static int _clk_emi_set_rate(struct clk *clk, unsigned long rate)
3137 {
3138         u32 reg, div;
3139         u32 parent_rate = clk_get_rate(clk->parent);
3140
3141         div = parent_rate / rate;
3142         if (div == 0)
3143                 div++;
3144         if (((parent_rate / div) != rate) || (div > 8))
3145                 return -EINVAL;
3146
3147         reg = __raw_readl(MXC_CCM_CSCMR1);
3148         reg &= ~MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK;
3149         reg |= (div - 1) << MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET;
3150         __raw_writel(reg, MXC_CCM_CSCMR1);
3151
3152         return 0;
3153 }
3154
3155 static struct clk emi_clk = {
3156         __INIT_CLK_DEBUG(emi_clk)
3157          .id = 0,
3158          .parent = &axi_clk,
3159          .set_rate = _clk_emi_set_rate,
3160          .get_rate = _clk_emi_get_rate,
3161          .round_rate = _clk_emi_round_rate,
3162          .set_parent = _clk_emi_set_parent,
3163 };
3164
3165 static unsigned long _clk_enfc_round_rate(struct clk *clk,
3166                                                 unsigned long rate)
3167 {
3168         u32 pre, post;
3169         u32 parent_rate = clk_get_rate(clk->parent);
3170         u32 div = parent_rate / rate;
3171
3172         if (parent_rate % rate)
3173                 div++;
3174
3175         __calc_pre_post_dividers(div, &pre, &post);
3176
3177         return parent_rate / (pre * post);
3178 }
3179
3180 static int _clk_enfc_set_parent(struct clk *clk, struct clk *parent)
3181 {
3182         u32 reg, mux;
3183
3184         reg = __raw_readl(MXC_CCM_CS2CDR)
3185                 & MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK;
3186
3187         mux = _get_mux6(parent, &pll2_pfd_352M,
3188                 &pll2_528_bus_main_clk, &pll3_usb_otg_main_clk,
3189                 &pll2_pfd_400M, NULL, NULL);
3190         reg |= mux << MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET;
3191
3192         __raw_writel(reg, MXC_CCM_CS2CDR);
3193
3194         return 0;
3195 }
3196
3197 static unsigned long _clk_enfc_get_rate(struct clk *clk)
3198 {
3199         u32 reg, pred, podf;
3200
3201         reg = __raw_readl(MXC_CCM_CS2CDR);
3202
3203         pred = ((reg & MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK)
3204                 >> MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET) + 1;
3205         podf = ((reg & MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK)
3206                 >> MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET) + 1;
3207
3208         return clk_get_rate(clk->parent) / (pred * podf);
3209 }
3210
3211 static int _clk_enfc_set_rate(struct clk *clk, unsigned long rate)
3212 {
3213         u32 reg, div, pre, post;
3214         u32 parent_rate = clk_get_rate(clk->parent);
3215
3216         div = parent_rate / rate;
3217         if (div == 0)
3218                 div++;
3219         if (((parent_rate / div) != rate) || div > 512)
3220                 return -EINVAL;
3221
3222         __calc_pre_post_dividers(div, &pre, &post);
3223
3224         reg = __raw_readl(MXC_CCM_CS2CDR);
3225         reg &= ~(MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK|
3226                  MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK);
3227         reg |= (post - 1) << MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET;
3228         reg |= (pre - 1) << MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET;
3229
3230         __raw_writel(reg, MXC_CCM_CS2CDR);
3231
3232         return 0;
3233 }
3234
3235 static struct clk enfc_clk = {
3236         __INIT_CLK_DEBUG(enfc_clk)
3237          .id = 0,
3238          .parent = &pll2_pfd_352M,
3239          .enable_reg = MXC_CCM_CCGR2,
3240          .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
3241          .enable = _clk_enable,
3242          .disable = _clk_disable,
3243          .set_rate = _clk_enfc_set_rate,
3244          .get_rate = _clk_enfc_get_rate,
3245          .round_rate = _clk_enfc_round_rate,
3246          .set_parent = _clk_enfc_set_parent,
3247 };
3248
3249 static unsigned long _clk_uart_round_rate(struct clk *clk,
3250                                                 unsigned long rate)
3251 {
3252         u32 div;
3253         u32 parent_rate = clk_get_rate(clk->parent);
3254
3255         div = parent_rate / rate;
3256
3257         /* Make sure rate is not greater than the maximum value for the clock.
3258          * Also prevent a div of 0.
3259          */
3260         if (div == 0)
3261                 div++;
3262
3263         if (div > 64)
3264                 div = 64;
3265
3266         return parent_rate / div;
3267 }
3268
3269 static int _clk_uart_set_rate(struct clk *clk, unsigned long rate)
3270 {
3271         u32 reg, div;
3272         u32 parent_rate = clk_get_rate(clk->parent);
3273
3274         div = parent_rate / rate;
3275         if (div == 0)
3276                 div++;
3277         if (((parent_rate / div) != rate) || (div > 64))
3278                 return -EINVAL;
3279
3280         reg = __raw_readl(MXC_CCM_CSCDR1) & MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
3281         reg |= ((div - 1) << MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET);
3282
3283         __raw_writel(reg, MXC_CCM_CSCDR1);
3284
3285         return 0;
3286 }
3287
3288 static unsigned long _clk_uart_get_rate(struct clk *clk)
3289 {
3290         u32 reg, div;
3291         unsigned long val;
3292
3293         reg = __raw_readl(MXC_CCM_CSCDR1) & MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
3294         div = (reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET) + 1;
3295         val = clk_get_rate(clk->parent) / div;
3296
3297         return val;
3298 }
3299
3300 static struct clk uart_clk[] = {
3301         {
3302         __INIT_CLK_DEBUG(uart_clk)
3303          .id = 0,
3304          .parent = &pll3_80M,
3305          .enable_reg = MXC_CCM_CCGR5,
3306          .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET,
3307          .enable = _clk_enable,
3308          .disable = _clk_disable,
3309          .secondary = &uart_clk[1],
3310          .set_rate = _clk_uart_set_rate,
3311          .get_rate = _clk_uart_get_rate,
3312          .round_rate = _clk_uart_round_rate,
3313         },
3314         {
3315         __INIT_CLK_DEBUG(uart_serial_clk)
3316          .id = 1,
3317          .enable_reg = MXC_CCM_CCGR5,
3318          .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
3319          .enable = _clk_enable,
3320          .disable = _clk_disable,
3321         },
3322 };
3323
3324 static unsigned long _clk_hsi_tx_round_rate(struct clk *clk,
3325                                                 unsigned long rate)
3326 {
3327         u32 div;
3328         u32 parent_rate = clk_get_rate(clk->parent);
3329
3330         div = parent_rate / rate;
3331
3332         /* Make sure rate is not greater than the maximum value for the clock.
3333          * Also prevent a div of 0.
3334          */
3335         if (div == 0)
3336                 div++;
3337
3338         if (div > 8)
3339                 div = 8;
3340
3341         return parent_rate / div;
3342 }
3343
3344 static int _clk_hsi_tx_set_parent(struct clk *clk, struct clk *parent)
3345 {
3346         u32 reg = __raw_readl(MXC_CCM_CDCDR) & MXC_CCM_CDCDR_HSI_TX_CLK_SEL;
3347
3348         if (parent == &pll2_pfd_400M)
3349                 reg |= (MXC_CCM_CDCDR_HSI_TX_CLK_SEL);
3350
3351         __raw_writel(reg, MXC_CCM_CDCDR);
3352
3353         return 0;
3354 }
3355
3356 static unsigned long _clk_hsi_tx_get_rate(struct clk *clk)
3357 {
3358         u32 reg, div;
3359
3360         reg = __raw_readl(MXC_CCM_CDCDR);
3361         div = ((reg & MXC_CCM_CDCDR_HSI_TX_PODF_MASK) >>
3362                         MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET) + 1;
3363
3364         return clk_get_rate(clk->parent) / div;
3365 }
3366
3367 static int _clk_hsi_tx_set_rate(struct clk *clk, unsigned long rate)
3368 {
3369         u32 reg, div;
3370         u32 parent_rate = clk_get_rate(clk->parent);
3371
3372         div = parent_rate / rate;
3373         if (div == 0)
3374                 div++;
3375         if (((parent_rate / div) != rate) || (div > 8))
3376                 return -EINVAL;
3377
3378         reg = __raw_readl(MXC_CCM_CDCDR);
3379         reg &= ~MXC_CCM_CDCDR_HSI_TX_PODF_MASK;
3380         reg |= (div - 1) << MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET;
3381         __raw_writel(reg, MXC_CCM_CDCDR);
3382
3383         return 0;
3384 }
3385
3386 static struct clk hsi_tx_clk = {
3387          __INIT_CLK_DEBUG(hsi_tx_clk)
3388         .id = 0,
3389          .parent = &pll2_pfd_400M,
3390         .enable_reg = MXC_CCM_CCGR3,
3391         .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET,
3392         .enable = _clk_enable,
3393         .disable = _clk_disable,
3394         .set_parent = _clk_hsi_tx_set_parent,
3395         .round_rate = _clk_hsi_tx_round_rate,
3396         .set_rate = _clk_hsi_tx_set_rate,
3397         .get_rate = _clk_hsi_tx_get_rate,
3398 };
3399
3400 static struct clk video_27M_clk = {
3401          __INIT_CLK_DEBUG(video_27M_clk)
3402         .id = 0,
3403          .parent = &pll2_pfd_400M,
3404         .enable_reg = MXC_CCM_CCGR2,
3405         .enable_shift = MXC_CCM_CCGRx_CG2_OFFSET,
3406         .enable = _clk_enable,
3407         .disable = _clk_disable,
3408 };
3409
3410 static struct clk caam_clk[] = {
3411         {
3412          __INIT_CLK_DEBUG(caam_mem_clk)
3413         .id = 0,
3414         .enable_reg = MXC_CCM_CCGR0,
3415         .enable_shift = MXC_CCM_CCGRx_CG4_OFFSET,
3416         .enable = _clk_enable,
3417         .disable = _clk_disable,
3418         .secondary = &caam_clk[1],
3419         },
3420         {
3421          __INIT_CLK_DEBUG(caam_aclk_clk)
3422         .id = 1,
3423         .enable_reg = MXC_CCM_CCGR0,
3424         .enable_shift = MXC_CCM_CCGRx_CG5_OFFSET,
3425         .enable = _clk_enable,
3426         .disable = _clk_disable,
3427         },
3428         {
3429          __INIT_CLK_DEBUG(caam_ipg_clk)
3430         .id = 2,
3431         .enable_reg = MXC_CCM_CCGR0,
3432         .enable_shift = MXC_CCM_CCGRx_CG4_OFFSET,
3433         .enable = _clk_enable,
3434         .disable = _clk_disable,
3435         },
3436 };
3437
3438 static struct clk asrc_clk = {
3439         __INIT_CLK_DEBUG(asrc_clk)
3440         .id = 0,
3441         .parent = &pll4_audio_main_clk,
3442         .enable_reg = MXC_CCM_CCGR0,
3443         .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET,
3444         .enable = _clk_enable,
3445         .disable = _clk_disable,
3446 };
3447
3448 static struct clk apbh_dma_clk = {
3449         __INIT_CLK_DEBUG(apbh_dma_clk)
3450         .parent = &ahb_clk,
3451         .enable = _clk_enable,
3452         .disable = _clk_disable_inwait,
3453         .enable_reg = MXC_CCM_CCGR0,
3454         .enable_shift = MXC_CCM_CCGRx_CG2_OFFSET,
3455 };
3456
3457 static struct clk aips_tz2_clk = {
3458         __INIT_CLK_DEBUG(aips_tz2_clk)
3459         .parent = &ahb_clk,
3460         .enable_reg = MXC_CCM_CCGR0,
3461         .enable_shift = MXC_CCM_CCGRx_CG1_OFFSET,
3462         .enable = _clk_enable,
3463         .disable = _clk_disable_inwait,
3464 };
3465
3466 static struct clk aips_tz1_clk = {
3467         __INIT_CLK_DEBUG(aips_tz1_clk)
3468         .parent = &ahb_clk,
3469         .enable_reg = MXC_CCM_CCGR0,
3470         .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET,
3471         .enable = _clk_enable,
3472         .disable = _clk_disable_inwait,
3473 };
3474
3475
3476 static struct clk openvg_axi_clk = {
3477         __INIT_CLK_DEBUG(openvg_axi_clk)
3478         .enable = _clk_enable,
3479         .enable_reg = MXC_CCM_CCGR3,
3480         .enable_shift = MXC_CCM_CCGRx_CG15_OFFSET,
3481         .disable = _clk_disable,
3482 };
3483
3484 static unsigned long _clk_gpu3d_core_round_rate(struct clk *clk,
3485                                                 unsigned long rate)
3486 {
3487         u32 div;
3488         u32 parent_rate = clk_get_rate(clk->parent);
3489
3490         div = parent_rate / rate;
3491
3492         /* Make sure rate is not greater than the maximum value for the clock.
3493          * Also prevent a div of 0.
3494          */
3495         if (div == 0)
3496                 div++;
3497
3498         if (div > 8)
3499                 div = 8;
3500
3501         return parent_rate / div;
3502 }
3503
3504 static int _clk_gpu3d_core_set_parent(struct clk *clk, struct clk *parent)
3505 {
3506         int mux;
3507         u32 reg = __raw_readl(MXC_CCM_CBCMR)
3508                 & MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK;
3509
3510         mux = _get_mux6(parent, &mmdc_ch0_axi_clk[0],
3511                 &pll3_usb_otg_main_clk,
3512                 &pll2_pfd_594M, &pll2_pfd_400M, NULL, NULL);
3513         reg |= (mux << MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET);
3514         __raw_writel(reg, MXC_CCM_CBCMR);
3515
3516         return 0;
3517 }
3518
3519 static unsigned long _clk_gpu3d_core_get_rate(struct clk *clk)
3520 {
3521         u32 reg, div;
3522
3523         reg = __raw_readl(MXC_CCM_CBCMR);
3524         div = ((reg & MXC_CCM_CBCMR_GPU3D_CORE_PODF_MASK) >>
3525                         MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET) + 1;
3526
3527         return clk_get_rate(clk->parent) / div;
3528 }
3529
3530 static int _clk_gpu3d_core_set_rate(struct clk *clk, unsigned long rate)
3531 {
3532         u32 reg, div;
3533         u32 parent_rate = clk_get_rate(clk->parent);
3534
3535         div = parent_rate / rate;
3536         if (div == 0)
3537                 div++;
3538         if (((parent_rate / div) != rate) || (div > 8))
3539                 return -EINVAL;
3540
3541         reg = __raw_readl(MXC_CCM_CBCMR);
3542         reg &= ~MXC_CCM_CBCMR_GPU3D_CORE_PODF_MASK;
3543         reg |= (div - 1) << MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET;
3544         __raw_writel(reg, MXC_CCM_CBCMR);
3545
3546         return 0;
3547 }
3548
3549 static struct clk gpu3d_core_clk = {
3550         __INIT_CLK_DEBUG(gpu3d_core_clk)
3551         .parent = &pll2_pfd_594M,
3552         .enable = _clk_enable,
3553         .enable_reg = MXC_CCM_CCGR1,
3554         .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
3555         .disable = _clk_disable,
3556         .set_parent = _clk_gpu3d_core_set_parent,
3557         .set_rate = _clk_gpu3d_core_set_rate,
3558         .get_rate = _clk_gpu3d_core_get_rate,
3559         .round_rate = _clk_gpu3d_core_round_rate,
3560 };
3561
3562 static unsigned long _clk_gpu2d_core_round_rate(struct clk *clk,
3563                                                 unsigned long rate)
3564 {
3565         u32 div;
3566         u32 parent_rate = clk_get_rate(clk->parent);
3567
3568         div = parent_rate / rate;
3569
3570         /* Make sure rate is not greater than the maximum value for the clock.
3571          * Also prevent a div of 0.
3572          */
3573         if (div == 0)
3574                 div++;
3575
3576         if (div > 8)
3577                 div = 8;
3578
3579         return parent_rate / div;
3580 }
3581
3582 static int _clk_gpu2d_core_set_parent(struct clk *clk, struct clk *parent)
3583 {
3584         int mux;
3585         u32 reg = __raw_readl(MXC_CCM_CBCMR) & MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK;
3586
3587         mux = _get_mux6(parent, &axi_clk, &pll3_usb_otg_main_clk,
3588                 &pll2_pfd_352M, &pll2_pfd_400M, NULL, NULL);
3589         reg |= (mux << MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET);
3590         __raw_writel(reg, MXC_CCM_CBCMR);
3591
3592         return 0;
3593 }
3594
3595 static unsigned long _clk_gpu2d_core_get_rate(struct clk *clk)
3596 {
3597         u32 reg, div;
3598
3599         reg = __raw_readl(MXC_CCM_CBCMR);
3600         div = ((reg & MXC_CCM_CBCMR_GPU2D_CORE_PODF_MASK) >>
3601                         MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET) + 1;
3602
3603         return clk_get_rate(clk->parent) / div;
3604 }
3605
3606 static int _clk_gpu2d_core_set_rate(struct clk *clk, unsigned long rate)
3607 {
3608         u32 reg, div;
3609         u32 parent_rate = clk_get_rate(clk->parent);
3610
3611         div = parent_rate / rate;
3612         if (div == 0)
3613                 div++;
3614         if (((parent_rate / div) != rate) || (div > 8))
3615                 return -EINVAL;
3616
3617         reg = __raw_readl(MXC_CCM_CBCMR);
3618         reg &= ~MXC_CCM_CBCMR_GPU3D_CORE_PODF_MASK;
3619         reg |= (div - 1) << MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET;
3620         __raw_writel(reg, MXC_CCM_CBCMR);
3621
3622         return 0;
3623 }
3624 static struct clk gpu2d_core_clk = {
3625         __INIT_CLK_DEBUG(gpu2d_core_clk)
3626         .parent = &pll2_pfd_352M,
3627         .enable = _clk_enable,
3628         .enable_reg = MXC_CCM_CCGR1,
3629         .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET,
3630         .disable = _clk_disable,
3631         .set_parent = _clk_gpu2d_core_set_parent,
3632         .set_rate = _clk_gpu2d_core_set_rate,
3633         .get_rate = _clk_gpu2d_core_get_rate,
3634         .round_rate = _clk_gpu2d_core_round_rate,
3635 };
3636
3637 static unsigned long _clk_gpu3d_shader_round_rate(struct clk *clk,
3638                                                 unsigned long rate)
3639 {
3640         u32 div;
3641         u32 parent_rate = clk_get_rate(clk->parent);
3642
3643         div = parent_rate / rate;
3644
3645         /* Make sure rate is not greater than the maximum value for the clock.
3646          * Also prevent a div of 0.
3647          */
3648         if (div == 0)
3649                 div++;
3650
3651         if (div > 8)
3652                 div = 8;
3653
3654         return parent_rate / div;
3655 }
3656
3657 static int _clk_gpu3d_shader_set_parent(struct clk *clk, struct clk *parent)
3658 {
3659         int mux;
3660         u32 reg = __raw_readl(MXC_CCM_CBCMR)
3661                 & MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_MASK;
3662
3663         mux = _get_mux6(parent, &mmdc_ch0_axi_clk[0],
3664                 &pll3_usb_otg_main_clk,
3665                 &pll2_pfd_594M, &pll3_pfd_720M, NULL, NULL);
3666         reg |= (mux << MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET);
3667         __raw_writel(reg, MXC_CCM_CBCMR);
3668
3669         return 0;
3670 }
3671
3672 static unsigned long _clk_gpu3d_shader_get_rate(struct clk *clk)
3673 {
3674         u32 reg, div;
3675
3676         reg = __raw_readl(MXC_CCM_CBCMR);
3677         div = ((reg & MXC_CCM_CBCMR_GPU3D_SHADER_PODF_MASK) >>
3678                         MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET) + 1;
3679
3680         return clk_get_rate(clk->parent) / div;
3681 }
3682
3683 static int _clk_gpu3d_shader_set_rate(struct clk *clk, unsigned long rate)
3684 {
3685         u32 reg, div;
3686         u32 parent_rate = clk_get_rate(clk->parent);
3687
3688         div = parent_rate / rate;
3689         if (div == 0)
3690                 div++;
3691         if (((parent_rate / div) != rate) || (div > 8))
3692                 return -EINVAL;
3693
3694         reg = __raw_readl(MXC_CCM_CBCMR);
3695         reg &= ~MXC_CCM_CBCMR_GPU3D_SHADER_PODF_MASK;
3696         reg |= (div - 1) << MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET;
3697         __raw_writel(reg, MXC_CCM_CBCMR);
3698
3699         return 0;
3700 }
3701
3702
3703 static struct clk gpu3d_shader_clk = {
3704         __INIT_CLK_DEBUG(gpu3d_shader_clk)
3705         .parent = &pll3_pfd_720M,
3706         .enable = _clk_enable,
3707         .enable_reg = MXC_CCM_CCGR1,
3708         .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
3709         .disable = _clk_disable,
3710         .set_parent = _clk_gpu3d_shader_set_parent,
3711         .set_rate = _clk_gpu3d_shader_set_rate,
3712         .get_rate = _clk_gpu3d_shader_get_rate,
3713         .round_rate = _clk_gpu3d_shader_round_rate,
3714 };
3715
3716 static struct clk gpmi_nfc_clk[] = {
3717         {       /* gpmi_io_clk */
3718         __INIT_CLK_DEBUG(gpmi_io_clk)
3719         .parent = &osc_clk,
3720         .secondary = &gpmi_nfc_clk[1],
3721         .enable = _clk_enable,
3722         .enable_reg = MXC_CCM_CCGR4,
3723         .enable_shift = MXC_CCM_CCGRx_CG14_OFFSET,
3724         .disable = _clk_disable,
3725         },
3726         {       /* gpmi_apb_clk */
3727         __INIT_CLK_DEBUG(gpmi_apb_clk)
3728         .parent = &apbh_dma_clk,
3729         .secondary = &gpmi_nfc_clk[2],
3730         .enable = _clk_enable,
3731         .enable_reg = MXC_CCM_CCGR4,
3732         .enable_shift = MXC_CCM_CCGRx_CG15_OFFSET,
3733         .disable = _clk_disable,
3734         },
3735         {       /* bch_clk */
3736         __INIT_CLK_DEBUG(gpmi_bch_clk)
3737         .parent = &osc_clk,
3738         .secondary = &gpmi_nfc_clk[3],
3739         .enable = _clk_enable,
3740         .enable_reg = MXC_CCM_CCGR4,
3741         .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
3742         .disable = _clk_disable,
3743         },
3744         {       /* bch_apb_clk */
3745         __INIT_CLK_DEBUG(gpmi_bch_apb_clk)
3746         .parent = &apbh_dma_clk,
3747         .enable = _clk_enable,
3748         .enable_reg = MXC_CCM_CCGR4,
3749         .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET,
3750         .disable = _clk_disable,
3751         },
3752 };
3753
3754 static struct clk pwm_clk[] = {
3755         {
3756         __INIT_CLK_DEBUG(pwm_clk_0)
3757          .parent = &ipg_perclk,
3758          .id = 0,
3759          .enable_reg = MXC_CCM_CCGR4,
3760          .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET,
3761          .enable = _clk_enable,
3762          .disable = _clk_disable,
3763          },
3764         {
3765         __INIT_CLK_DEBUG(pwm_clk_1)
3766          .parent = &ipg_perclk,
3767          .id = 1,
3768          .enable_reg = MXC_CCM_CCGR4,
3769          .enable_shift = MXC_CCM_CCGRx_CG9_OFFSET,
3770          .enable = _clk_enable,
3771          .disable = _clk_disable,
3772          },
3773         {
3774         __INIT_CLK_DEBUG(pwm_clk_2)
3775          .parent = &ipg_perclk,
3776          .id = 2,
3777          .enable_reg = MXC_CCM_CCGR4,
3778          .enable_shift = MXC_CCM_CCGRx_CG10_OFFSET,
3779          .enable = _clk_enable,
3780          .disable = _clk_disable,
3781          },
3782         {
3783         __INIT_CLK_DEBUG(pwm_clk_3)
3784          .parent = &ipg_perclk,
3785          .id = 3,
3786          .enable_reg = MXC_CCM_CCGR4,
3787          .enable_shift = MXC_CCM_CCGRx_CG11_OFFSET,
3788          .enable = _clk_enable,
3789          .disable = _clk_disable,
3790          },
3791 };
3792
3793 static int _clk_pcie_enable(struct clk *clk)
3794 {
3795         unsigned int reg;
3796
3797         /* Enable SATA ref clock */
3798         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
3799         reg |= ANADIG_PLL_ENET_EN_PCIE;
3800         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
3801
3802         _clk_enable(clk);
3803
3804         return 0;
3805 }
3806
3807 static void _clk_pcie_disable(struct clk *clk)
3808 {
3809         unsigned int reg;
3810
3811         _clk_disable(clk);
3812
3813         /* Disable SATA ref clock */
3814         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
3815         reg &= ~ANADIG_PLL_ENET_EN_PCIE;
3816         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
3817 }
3818
3819 static struct clk pcie_clk = {
3820         __INIT_CLK_DEBUG(pcie_clk)
3821         .parent = &pcie_axi_clk,
3822         .enable = _clk_pcie_enable,
3823         .disable = _clk_pcie_disable,
3824         .enable_reg = MXC_CCM_CCGR4,
3825         .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET,
3826 };
3827
3828 static int _clk_sata_enable(struct clk *clk)
3829 {
3830         unsigned int reg;
3831
3832         /* Enable SATA ref clock */
3833         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
3834         reg |= ANADIG_PLL_ENET_EN_SATA;
3835         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
3836
3837         _clk_enable(clk);
3838
3839         return 0;
3840 }
3841
3842 static void _clk_sata_disable(struct clk *clk)
3843 {
3844         unsigned int reg;
3845
3846         _clk_disable(clk);
3847
3848         /* Disable SATA ref clock */
3849         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
3850         reg &= ~ANADIG_PLL_ENET_EN_SATA;
3851         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
3852 }
3853
3854 static struct clk sata_clk = {
3855         __INIT_CLK_DEBUG(sata_clk)
3856         .parent = &ipg_clk,
3857         .enable = _clk_sata_enable,
3858         .enable_reg = MXC_CCM_CCGR5,
3859         .enable_shift = MXC_CCM_CCGRx_CG2_OFFSET,
3860         .disable = _clk_sata_disable,
3861 };
3862
3863 static struct clk usboh3_clk = {
3864         __INIT_CLK_DEBUG(usboh3_clk)
3865         .parent = &ipg_clk,
3866         .enable = _clk_enable,
3867         .enable_reg = MXC_CCM_CCGR6,
3868         .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET,
3869         .disable = _clk_disable,
3870 };
3871
3872 #define _REGISTER_CLOCK(d, n, c) \
3873         { \
3874                 .dev_id = d, \
3875                 .con_id = n, \
3876                 .clk = &c, \
3877         }
3878
3879
3880 static struct clk_lookup lookups[] = {
3881         _REGISTER_CLOCK(NULL, "osc", osc_clk),
3882         _REGISTER_CLOCK(NULL, "ckih", ckih_clk),
3883         _REGISTER_CLOCK(NULL, "ckih2", ckih2_clk),
3884         _REGISTER_CLOCK(NULL, "ckil", ckil_clk),
3885         _REGISTER_CLOCK(NULL, "pll1_main_clk", pll1_sys_main_clk),
3886         _REGISTER_CLOCK(NULL, "pll1_sw_clk", pll1_sw_clk),
3887         _REGISTER_CLOCK(NULL, "pll2", pll2_528_bus_main_clk),
3888         _REGISTER_CLOCK(NULL, "pll2_pfd_400M", pll2_pfd_400M),
3889         _REGISTER_CLOCK(NULL, "pll2_pfd_352M", pll2_pfd_352M),
3890         _REGISTER_CLOCK(NULL, "pll2_pfd_594M", pll2_pfd_594M),
3891         _REGISTER_CLOCK(NULL, "pll2_200M", pll2_200M),
3892         _REGISTER_CLOCK(NULL, "pll3_main_clk", pll3_usb_otg_main_clk),
3893         _REGISTER_CLOCK(NULL, "pll3_pfd_508M", pll3_pfd_508M),
3894         _REGISTER_CLOCK(NULL, "pll3_pfd_454M", pll3_pfd_454M),
3895         _REGISTER_CLOCK(NULL, "pll3_pfd_720M", pll3_pfd_720M),
3896         _REGISTER_CLOCK(NULL, "pll3_pfd_540M", pll3_pfd_540M),
3897         _REGISTER_CLOCK(NULL, "pll3_sw_clk", pll3_sw_clk),
3898         _REGISTER_CLOCK(NULL, "pll3_120M", pll3_120M),
3899         _REGISTER_CLOCK(NULL, "pll3_120M", pll3_80M),
3900         _REGISTER_CLOCK(NULL, "pll3_120M", pll3_60M),
3901         _REGISTER_CLOCK(NULL, "pll4", pll4_audio_main_clk),
3902         _REGISTER_CLOCK(NULL, "pll5", pll5_video_main_clk),
3903         _REGISTER_CLOCK(NULL, "pll4", pll6_MLB_main_clk),
3904         _REGISTER_CLOCK(NULL, "pll3", pll7_usb_host_main_clk),
3905         _REGISTER_CLOCK(NULL, "pll4", pll8_enet_main_clk),
3906         _REGISTER_CLOCK(NULL, "cpu_clk", cpu_clk),
3907         _REGISTER_CLOCK(NULL, "periph_clk", periph_clk),
3908         _REGISTER_CLOCK(NULL, "axi_clk", axi_clk),
3909         _REGISTER_CLOCK(NULL, "mmdc_ch0_axi", mmdc_ch0_axi_clk[0]),
3910         _REGISTER_CLOCK(NULL, "mmdc_ch1_axi", mmdc_ch1_axi_clk[0]),
3911         _REGISTER_CLOCK(NULL, "ahb", ahb_clk),
3912         _REGISTER_CLOCK(NULL, "ipg_clk", ipg_clk),
3913         _REGISTER_CLOCK(NULL, "ipg_perclk", ipg_perclk),
3914         _REGISTER_CLOCK(NULL, "spba", spba_clk),
3915         _REGISTER_CLOCK("imx-sdma", NULL, sdma_clk),
3916         _REGISTER_CLOCK(NULL, "gpu2d_axi_clk", gpu2d_axi_clk),
3917         _REGISTER_CLOCK(NULL, "gpu3d_axi_clk", gpu3d_axi_clk),
3918         _REGISTER_CLOCK(NULL, "pcie_axi_clk", pcie_axi_clk),
3919         _REGISTER_CLOCK(NULL, "vdo_axi_clk", vdo_axi_clk),
3920         _REGISTER_CLOCK(NULL, "iim_clk", iim_clk),
3921         _REGISTER_CLOCK(NULL, "i2c_clk", i2c_clk[0]),
3922         _REGISTER_CLOCK("imx-i2c.1", NULL, i2c_clk[1]),
3923         _REGISTER_CLOCK("imx-i2c.2", NULL, i2c_clk[2]),
3924         _REGISTER_CLOCK(NULL, "vpu_clk", vpu_clk),
3925         _REGISTER_CLOCK(NULL, "ipu1_clk", ipu1_clk),
3926         _REGISTER_CLOCK(NULL, "ipu2_clk", ipu2_clk),
3927         _REGISTER_CLOCK("sdhci-esdhc-imx.0", NULL, usdhc1_clk),
3928         _REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL, usdhc2_clk),
3929         _REGISTER_CLOCK("sdhci-esdhc-imx.2", NULL, usdhc3_clk),
3930         _REGISTER_CLOCK("sdhci-esdhc-imx.3", NULL, usdhc4_clk),
3931         _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk),
3932         _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk),
3933         _REGISTER_CLOCK("imx-ssi.2", NULL, ssi3_clk),
3934         _REGISTER_CLOCK(NULL, "ipu1_di0_clk", ipu1_di_clk[0]),
3935         _REGISTER_CLOCK(NULL, "ipu1_di1_clk", ipu1_di_clk[1]),
3936         _REGISTER_CLOCK(NULL, "ipu2_di0_clk", ipu2_di_clk[0]),
3937         _REGISTER_CLOCK(NULL, "ipu2_di1_clk", ipu2_di_clk[1]),
3938         _REGISTER_CLOCK("FlexCAN.0", "can_clk", can1_clk[0]),
3939         _REGISTER_CLOCK("FlexCAN.1", "can_clk", can2_clk[0]),
3940         _REGISTER_CLOCK(NULL, "ldb_di0_clk", ldb_di0_clk),
3941         _REGISTER_CLOCK(NULL, "ldb_di1_clk", ldb_di1_clk),
3942         _REGISTER_CLOCK("mxc_alsa_spdif.0", NULL, spdif0_clk[0]),
3943         _REGISTER_CLOCK("mxc_alsa_spdif.1", NULL, spdif1_clk[0]),
3944         _REGISTER_CLOCK(NULL, "esai_clk", esai_clk),
3945         _REGISTER_CLOCK("mxc_spi.0", NULL, ecspi_clk[0]),
3946         _REGISTER_CLOCK("mxc_spi.1", NULL, ecspi_clk[1]),
3947         _REGISTER_CLOCK("mxc_spi.2", NULL, ecspi_clk[2]),
3948         _REGISTER_CLOCK("mxc_spi.3", NULL, ecspi_clk[3]),
3949         _REGISTER_CLOCK("mxc_spi.4", NULL, ecspi_clk[4]),
3950         _REGISTER_CLOCK(NULL, "emi_slow_clk", emi_slow_clk),
3951         _REGISTER_CLOCK(NULL, "emi_clk", emi_clk),
3952         _REGISTER_CLOCK(NULL, "enfc_clk", enfc_clk),
3953         _REGISTER_CLOCK("imx-uart.0", NULL, uart_clk[0]),
3954         _REGISTER_CLOCK(NULL, "hsi_tx", hsi_tx_clk),
3955         _REGISTER_CLOCK(NULL, "caam_clk", caam_clk[0]),
3956         _REGISTER_CLOCK(NULL, "asrc_clk", asrc_clk),
3957         _REGISTER_CLOCK(NULL, "apbh_dma_clk", apbh_dma_clk),
3958         _REGISTER_CLOCK(NULL, "openvg_axi_clk", openvg_axi_clk),
3959         _REGISTER_CLOCK(NULL, "gpu3d_clk", gpu3d_core_clk),
3960         _REGISTER_CLOCK(NULL, "gpu2d_clk", gpu2d_core_clk),
3961         _REGISTER_CLOCK(NULL, "gpu3d_shader_clk", gpu3d_shader_clk),
3962         _REGISTER_CLOCK(NULL, "gpt", gpt_clk[0]),
3963         _REGISTER_CLOCK(NULL, "gpmi-nfc", gpmi_nfc_clk[0]),
3964         _REGISTER_CLOCK(NULL, "gpmi-apb", gpmi_nfc_clk[1]),
3965         _REGISTER_CLOCK(NULL, "bch", gpmi_nfc_clk[2]),
3966         _REGISTER_CLOCK(NULL, "bch-apb", gpmi_nfc_clk[3]),
3967         _REGISTER_CLOCK("mxc_pwm.0", NULL, pwm_clk[0]),
3968         _REGISTER_CLOCK("mxc_pwm.1", NULL, pwm_clk[1]),
3969         _REGISTER_CLOCK("mxc_pwm.2", NULL, pwm_clk[2]),
3970         _REGISTER_CLOCK("mxc_pwm.3", NULL, pwm_clk[3]),
3971         _REGISTER_CLOCK(NULL, "pcie_clk", pcie_clk),
3972         _REGISTER_CLOCK(NULL, "enet_clk", enet_clk),
3973         _REGISTER_CLOCK(NULL, "imx_sata_clk", sata_clk),
3974         _REGISTER_CLOCK(NULL, "usboh3_clk", usboh3_clk),
3975         _REGISTER_CLOCK(NULL, "usb_phy1_clk", usb_phy1_clk),
3976         _REGISTER_CLOCK(NULL, "usb_phy2_clk", usb_phy2_clk),
3977         _REGISTER_CLOCK(NULL, "video_27M_clk", video_27M_clk),
3978 };
3979
3980
3981 static void clk_tree_init(void)
3982
3983 {
3984
3985 }
3986
3987
3988 int __init mx6_clocks_init(unsigned long ckil, unsigned long osc,
3989         unsigned long ckih1, unsigned long ckih2)
3990 {
3991         __iomem void *base;
3992         u32 reg;
3993
3994         int i;
3995
3996         external_low_reference = ckil;
3997         external_high_reference = ckih1;
3998         ckih2_reference = ckih2;
3999         oscillator_reference = osc;
4000
4001         apll_base = ioremap(ANATOP_BASE_ADDR, SZ_4K);
4002
4003         clk_tree_init();
4004
4005         for (i = 0; i < ARRAY_SIZE(lookups); i++) {
4006                 clkdev_add(&lookups[i]);
4007                 clk_debug_register(lookups[i].clk);
4008         }
4009
4010         /* Make sure all clocks are ON initially */
4011         __raw_writel(0xFFFFFFFF, MXC_CCM_CCGR0);
4012         __raw_writel(0xFFFFFFFF, MXC_CCM_CCGR1);
4013         __raw_writel(0xFFFFFFFF, MXC_CCM_CCGR2);
4014         __raw_writel(0xFFFFFFFF, MXC_CCM_CCGR3);
4015         __raw_writel(0xFFFFFFFF, MXC_CCM_CCGR4);
4016         __raw_writel(0xFFFFFFFF, MXC_CCM_CCGR5);
4017         __raw_writel(0xFFFFFFFF, MXC_CCM_CCGR6);
4018
4019         base = ioremap(GPT_BASE_ADDR, SZ_4K);
4020         mxc_timer_init(&gpt_clk[0], base, MXC_INT_GPT);
4021
4022         return 0;
4023
4024 }