arch/arm/mach-mx6/clock.c

   1
   2 /*
   3  * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
   4  */
   5
   6 /*
   7  * The code contained herein is licensed under the GNU General Public
   8  * License. You may obtain a copy of the GNU General Public License
   9  * Version 2 or later at the following locations:
  10  *
  11  * http://www.opensource.org/licenses/gpl-license.html
  12  * http://www.gnu.org/copyleft/gpl.html
  13  */
  14
  15 #include <linux/kernel.h>
  16 #include <linux/init.h>
  17 #include <linux/types.h>
  18 #include <linux/time.h>
  19 #include <linux/hrtimer.h>
  20 #include <linux/mm.h>
  21 #include <linux/errno.h>
  22 #include <linux/delay.h>
  23 #include <linux/clk.h>
  24 #include <linux/io.h>
  25 #include <linux/clkdev.h>
  26 #include <asm/div64.h>
  27 #include <mach/hardware.h>
  28 #include <mach/common.h>
  29 #include <mach/clock.h>
  30 #include <mach/mxc_dvfs.h>
  31 #include "crm_regs.h"
  32 #include "cpu_op-mx6.h"
  33
  34 #ifdef CONFIG_CLK_DEBUG
  35 #define __INIT_CLK_DEBUG(n)     .name = #n,
  36 #else
  37 #define __INIT_CLK_DEBUG(n)
  38 #endif
  39
  40 extern int mxc_jtag_enabled;
  41 extern struct cpu_op *(*get_cpu_op)(int *op);
  42 extern int lp_high_freq;
  43 extern int lp_med_freq;
  44
  45 void __iomem *apll_base;
  46 static struct clk pll1_sys_main_clk;
  47 static struct clk pll2_528_bus_main_clk;
  48 static struct clk pll2_pfd_400M;
  49 static struct clk pll3_usb_otg_main_clk;
  50 static struct clk pll4_audio_main_clk;
  51 static struct clk pll5_video_main_clk;
  52 static struct clk pll6_MLB_main_clk;
  53 static struct clk pll7_usb_host_main_clk;
  54 static struct clk pll8_enet_main_clk;
  55 static struct clk apbh_dma_clk;
  56 static struct clk openvg_axi_clk;
  57 static struct clk enfc_clk;
  58 static struct clk ipu1_di_clk_root;
  59 static struct clk ipu2_di_clk_root;
  60 static struct clk usdhc3_clk;
  61
  62 static struct cpu_op *cpu_op_tbl;
  63 static int cpu_op_nr;
  64
  65 #define SPIN_DELAY      1000000 /* in nanoseconds */
  66
  67 #define AUDIO_VIDEO_MIN_CLK_FREQ        650000000
  68 #define AUDIO_VIDEO_MAX_CLK_FREQ        1300000000
  69
  70 #define WAIT(exp, timeout) \
  71 ({ \
  72         struct timespec nstimeofday; \
  73         struct timespec curtime; \
  74         int result = 1; \
  75         getnstimeofday(&nstimeofday); \
  76         while (!(exp)) { \
  77                 getnstimeofday(&curtime); \
  78                 if ((curtime.tv_nsec - nstimeofday.tv_nsec) > (timeout)) { \
  79                         result = 0; \
  80                         break; \
  81                 } \
  82         } \
  83         result; \
  84 })
  85
  86 /* External clock values passed-in by the board code */
  87 static unsigned long external_high_reference, external_low_reference;
  88 static unsigned long oscillator_reference, ckih2_reference;
  89
  90 static void __calc_pre_post_dividers(u32 max_podf, u32 div, u32 *pre, u32 *post)
  91 {
  92         u32 min_pre, temp_pre, old_err, err;
  93
  94         /* Some of the podfs are 3 bits while others are 6 bits.
  95           * Handle both cases here.
  96           */
  97         if (div >= 512 && (max_podf == 64)) {
  98                 /* For pre = 3bits and podf = 6 bits, max divider is 512. */
  99                 *pre = 8;
 100                 *post = 64;
 101         } else if (div >= 64 && (max_podf == 8)) {
 102                 /* For pre = 3bits and podf = 3 bits, max divider is 64. */
 103                 *pre = 8;
 104                 *post = 8;
 105         } else if (div >= 8) {
 106                 /* Find the minimum pre-divider for a max podf */
 107                 if (max_podf == 64)
 108                         min_pre = (div - 1) / (1 << 6) + 1;
 109                 else
 110                         min_pre = (div - 1) / (1 << 3) + 1;
 111                 old_err = 8;
 112                 /* Now loop through to find the max pre-divider. */
 113                 for (temp_pre = 8; temp_pre >= min_pre; temp_pre--) {
 114                         err = div % temp_pre;
 115                         if (err == 0) {
 116                                 *pre = temp_pre;
 117                                 break;
 118                         }
 119                         err = temp_pre - err;
 120                         if (err < old_err) {
 121                                 old_err = err;
 122                                 *pre = temp_pre;
 123                         }
 124                 }
 125                 *post = (div + *pre - 1) / *pre;
 126         } else if (div < 8) {
 127                 *pre = div;
 128                 *post = 1;
 129         }
 130 }
 131
 132 static int _clk_enable(struct clk *clk)
 133 {
 134         u32 reg;
 135         reg = __raw_readl(clk->enable_reg);
 136         reg |= MXC_CCM_CCGRx_CG_MASK << clk->enable_shift;
 137         __raw_writel(reg, clk->enable_reg);
 138
 139         if (clk->flags & AHB_HIGH_SET_POINT)
 140                 lp_high_freq++;
 141         else if (clk->flags & AHB_MED_SET_POINT)
 142                 lp_med_freq++;
 143
 144         return 0;
 145 }
 146
 147 static void _clk_disable(struct clk *clk)
 148 {
 149         u32 reg;
 150         reg = __raw_readl(clk->enable_reg);
 151         reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift);
 152         __raw_writel(reg, clk->enable_reg);
 153
 154         if (clk->flags & AHB_HIGH_SET_POINT)
 155                 lp_high_freq--;
 156         else if (clk->flags & AHB_MED_SET_POINT)
 157                 lp_med_freq--;
 158 }
 159
 160 static void _clk_disable_inwait(struct clk *clk)
 161 {
 162         u32 reg;
 163         reg = __raw_readl(clk->enable_reg);
 164         reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift);
 165         reg |= 1 << clk->enable_shift;
 166         __raw_writel(reg, clk->enable_reg);
 167 }
 168
 169 /*
 170  * For the 4-to-1 muxed input clock
 171  */
 172 static inline u32 _get_mux(struct clk *parent, struct clk *m0,
 173                            struct clk *m1, struct clk *m2, struct clk *m3)
 174 {
 175         if (parent == m0)
 176                 return 0;
 177         else if (parent == m1)
 178                 return 1;
 179         else if (parent == m2)
 180                 return 2;
 181         else if (parent == m3)
 182                 return 3;
 183         else
 184                 BUG();
 185
 186         return 0;
 187 }
 188
 189 static inline void __iomem *_get_pll_base(struct clk *pll)
 190 {
 191         if (pll == &pll1_sys_main_clk)
 192                 return PLL1_SYS_BASE_ADDR;
 193         else if (pll == &pll2_528_bus_main_clk)
 194                 return PLL2_528_BASE_ADDR;
 195         else if (pll == &pll3_usb_otg_main_clk)
 196                 return PLL3_480_USB1_BASE_ADDR;
 197         else if (pll == &pll4_audio_main_clk)
 198                 return PLL4_AUDIO_BASE_ADDR;
 199         else if (pll == &pll5_video_main_clk)
 200                 return PLL5_VIDEO_BASE_ADDR;
 201         else if (pll == &pll6_MLB_main_clk)
 202                 return PLL6_MLB_BASE_ADDR;
 203         else if (pll == &pll7_usb_host_main_clk)
 204                 return PLL7_480_USB2_BASE_ADDR;
 205         else if (pll == &pll8_enet_main_clk)
 206                 return PLL8_ENET_BASE_ADDR;
 207         else
 208                 BUG();
 209         return NULL;
 210 }
 211
 212
 213 /*
 214  * For the 6-to-1 muxed input clock
 215  */
 216 static inline u32 _get_mux6(struct clk *parent, struct clk *m0, struct clk *m1,
 217                             struct clk *m2, struct clk *m3, struct clk *m4,
 218                             struct clk *m5)
 219 {
 220         if (parent == m0)
 221                 return 0;
 222         else if (parent == m1)
 223                 return 1;
 224         else if (parent == m2)
 225                 return 2;
 226         else if (parent == m3)
 227                 return 3;
 228         else if (parent == m4)
 229                 return 4;
 230         else if (parent == m5)
 231                 return 5;
 232         else
 233                 BUG();
 234
 235         return 0;
 236 }
 237 static unsigned long get_high_reference_clock_rate(struct clk *clk)
 238 {
 239         return external_high_reference;
 240 }
 241
 242 static unsigned long get_low_reference_clock_rate(struct clk *clk)
 243 {
 244         return external_low_reference;
 245 }
 246
 247 static unsigned long get_oscillator_reference_clock_rate(struct clk *clk)
 248 {
 249         return oscillator_reference;
 250 }
 251
 252 static unsigned long get_ckih2_reference_clock_rate(struct clk *clk)
 253 {
 254         return ckih2_reference;
 255 }
 256
 257 /* External high frequency clock */
 258 static struct clk ckih_clk = {
 259         __INIT_CLK_DEBUG(ckih_clk)
 260         .get_rate = get_high_reference_clock_rate,
 261 };
 262
 263 static struct clk ckih2_clk = {
 264         __INIT_CLK_DEBUG(ckih2_clk)
 265         .get_rate = get_ckih2_reference_clock_rate,
 266 };
 267
 268 static struct clk osc_clk = {
 269         __INIT_CLK_DEBUG(osc_clk)
 270         .get_rate = get_oscillator_reference_clock_rate,
 271 };
 272
 273 /* External low frequency (32kHz) clock */
 274 static struct clk ckil_clk = {
 275         __INIT_CLK_DEBUG(ckil_clk)
 276         .get_rate = get_low_reference_clock_rate,
 277 };
 278
 279 static unsigned long pfd_round_rate(struct clk *clk, unsigned long rate)
 280 {
 281         u32 frac;
 282         u64 tmp;
 283
 284         tmp = (u64)clk_get_rate(clk->parent) * 18;
 285         tmp += rate/2;
 286         do_div(tmp, rate);
 287         frac = tmp;
 288         frac = frac < 12 ? 12 : frac;
 289         frac = frac > 35 ? 35 : frac;
 290         tmp = (u64)clk_get_rate(clk->parent) * 18;
 291         do_div(tmp, frac);
 292         return tmp;
 293 }
 294
 295 static unsigned long pfd_get_rate(struct clk *clk)
 296 {
 297         u32 frac;
 298         u64 tmp;
 299         tmp = (u64)clk_get_rate(clk->parent) * 18;
 300
 301         if (apbh_dma_clk.usecount == 0)
 302                 apbh_dma_clk.enable(&apbh_dma_clk);
 303
 304         frac = (__raw_readl(clk->enable_reg) >> clk->enable_shift) &
 305                         ANADIG_PFD_FRAC_MASK;
 306
 307         do_div(tmp, frac);
 308
 309         return tmp;
 310 }
 311
 312 static int pfd_set_rate(struct clk *clk, unsigned long rate)
 313 {
 314         u32 frac;
 315         u64 tmp;
 316         tmp = (u64)clk_get_rate(clk->parent) * 18;
 317
 318         if (apbh_dma_clk.usecount == 0)
 319                 apbh_dma_clk.enable(&apbh_dma_clk);
 320
 321         /* Round up the divider so that we don't set a rate
 322           * higher than what is requested. */
 323         tmp += rate/2;
 324         do_div(tmp, rate);
 325         frac = tmp;
 326         frac = frac < 12 ? 12 : frac;
 327         frac = frac > 35 ? 35 : frac;
 328         /* clear clk frac bits */
 329         __raw_writel(ANADIG_PFD_FRAC_MASK << clk->enable_shift,
 330                         (int)clk->enable_reg + 8);
 331         /* set clk frac bits */
 332         __raw_writel(frac << clk->enable_shift,
 333                         (int)clk->enable_reg + 4);
 334
 335         tmp = (u64)clk_get_rate(clk->parent) * 18;
 336         do_div(tmp, frac);
 337
 338         if (apbh_dma_clk.usecount == 0)
 339                 apbh_dma_clk.disable(&apbh_dma_clk);
 340         return 0;
 341 }
 342
 343 static int _clk_pfd_enable(struct clk *clk)
 344 {
 345         if (apbh_dma_clk.usecount == 0)
 346                 apbh_dma_clk.enable(&apbh_dma_clk);
 347
 348         /* clear clk gate bit */
 349         __raw_writel((1 << (clk->enable_shift + 7)),
 350                         (int)clk->enable_reg + 8);
 351
 352         if (apbh_dma_clk.usecount == 0)
 353                 apbh_dma_clk.disable(&apbh_dma_clk);
 354
 355         return 0;
 356 }
 357
 358 static void _clk_pfd_disable(struct clk *clk)
 359 {
 360         if (apbh_dma_clk.usecount == 0)
 361                 apbh_dma_clk.enable(&apbh_dma_clk);
 362
 363         /* set clk gate bit */
 364         __raw_writel((1 << (clk->enable_shift + 7)),
 365                         (int)clk->enable_reg + 4);
 366
 367         if (apbh_dma_clk.usecount == 0)
 368                 apbh_dma_clk.disable(&apbh_dma_clk);
 369 }
 370
 371 static int _clk_pll_enable(struct clk *clk)
 372 {
 373         unsigned int reg;
 374         void __iomem *pllbase;
 375
 376         pllbase = _get_pll_base(clk);
 377
 378         reg = __raw_readl(pllbase);
 379         reg &= ~ANADIG_PLL_BYPASS;
 380         reg &= ~ANADIG_PLL_POWER_DOWN;
 381
 382         /* The 480MHz PLLs have the opposite definition for power bit. */
 383         if (clk == &pll3_usb_otg_main_clk || clk == &pll7_usb_host_main_clk)
 384                 reg |= ANADIG_PLL_POWER_DOWN;
 385
 386         __raw_writel(reg, pllbase);
 387
 388         /* Wait for PLL to lock */
 389         if (!WAIT(__raw_readl(pllbase) & ANADIG_PLL_LOCK,
 390                                 SPIN_DELAY))
 391                 panic("pll enable failed\n");
 392
 393         /* Enable the PLL output now*/
 394         reg = __raw_readl(pllbase);
 395         reg |= ANADIG_PLL_ENABLE;
 396         __raw_writel(reg, pllbase);
 397
 398         return 0;
 399 }
 400
 401 static void _clk_pll_disable(struct clk *clk)
 402 {
 403         unsigned int reg;
 404         void __iomem *pllbase;
 405
 406         pllbase = _get_pll_base(clk);
 407
 408         reg = __raw_readl(pllbase);
 409         reg |= ANADIG_PLL_BYPASS;
 410         reg |= ANADIG_PLL_POWER_DOWN;
 411
 412         /* The 480MHz PLLs, pll3 & pll7, have the opposite
 413          * definition for power bit.
 414          */
 415         if (clk == &pll3_usb_otg_main_clk || clk == &pll7_usb_host_main_clk)
 416                 reg &= ~ANADIG_PLL_POWER_DOWN;
 417         __raw_writel(reg, pllbase);
 418 }
 419
 420 static unsigned long  _clk_pll1_main_get_rate(struct clk *clk)
 421 {
 422         unsigned int div;
 423         unsigned long val;
 424
 425         div = __raw_readl(PLL1_SYS_BASE_ADDR) & ANADIG_PLL_SYS_DIV_SELECT_MASK;
 426         val = (clk_get_rate(clk->parent) * div) / 2;
 427         return val;
 428 }
 429
 430 static int _clk_pll1_main_set_rate(struct clk *clk, unsigned long rate)
 431 {
 432         unsigned int reg,  div;
 433
 434         if (rate < AUDIO_VIDEO_MIN_CLK_FREQ || rate > AUDIO_VIDEO_MAX_CLK_FREQ)
 435                 return -EINVAL;
 436
 437         div = (rate * 2) / clk_get_rate(clk->parent) ;
 438
 439         reg = __raw_readl(PLL1_SYS_BASE_ADDR) & ~ANADIG_PLL_SYS_DIV_SELECT_MASK;
 440         reg |= div;
 441         __raw_writel(reg, PLL1_SYS_BASE_ADDR);
 442
 443         return 0;
 444 }
 445
 446 static struct clk pll1_sys_main_clk = {
 447         __INIT_CLK_DEBUG(pll1_sys_main_clk)
 448         .parent = &osc_clk,
 449         .get_rate = _clk_pll1_main_get_rate,
 450         .set_rate = _clk_pll1_main_set_rate,
 451         .enable = _clk_pll_enable,
 452         .disable = _clk_pll_disable,
 453 };
 454
 455 static int _clk_pll1_sw_set_parent(struct clk *clk, struct clk *parent)
 456 {
 457         u32 reg;
 458
 459         reg = __raw_readl(MXC_CCM_CCSR);
 460
 461         if (parent == &pll1_sys_main_clk) {
 462                 reg &= ~MXC_CCM_CCSR_PLL1_SW_CLK_SEL;
 463                 __raw_writel(reg, MXC_CCM_CCSR);
 464                 /* Set the step_clk parent to be lp_apm, to save power. */
 465                 reg = __raw_readl(MXC_CCM_CCSR);
 466                 reg = (reg & ~MXC_CCM_CCSR_STEP_SEL);
 467         } else {
 468                 /* Set STEP_CLK to be the parent*/
 469                 if (parent == &osc_clk) {
 470                         /* Set STEP_CLK to be sourced from LPAPM. */
 471                         reg = __raw_readl(MXC_CCM_CCSR);
 472                         reg = (reg & ~MXC_CCM_CCSR_STEP_SEL);
 473                         __raw_writel(reg, MXC_CCM_CCSR);
 474                 } else {
 475                         /* Set STEP_CLK to be sourced from PLL2-PDF (400MHz). */
 476                         reg = __raw_readl(MXC_CCM_CCSR);
 477                         reg |= MXC_CCM_CCSR_STEP_SEL;
 478                         __raw_writel(reg, MXC_CCM_CCSR);
 479
 480                 }
 481                 reg = __raw_readl(MXC_CCM_CCSR);
 482                 reg |= MXC_CCM_CCSR_PLL1_SW_CLK_SEL;
 483         }
 484         __raw_writel(reg, MXC_CCM_CCSR);
 485         return 0;
 486 }
 487
 488 static unsigned long _clk_pll1_sw_get_rate(struct clk *clk)
 489 {
 490         return clk_get_rate(clk->parent);
 491 }
 492
 493 static struct clk pll1_sw_clk = {
 494         __INIT_CLK_DEBUG(pll1_sw_clk)
 495         .parent = &pll1_sys_main_clk,
 496         .set_parent = _clk_pll1_sw_set_parent,
 497         .get_rate = _clk_pll1_sw_get_rate,
 498 };
 499
 500 static unsigned long _clk_pll2_main_get_rate(struct clk *clk)
 501 {
 502         unsigned int div;
 503         unsigned long val;
 504
 505         div = __raw_readl(PLL2_528_BASE_ADDR) & ANADIG_PLL_528_DIV_SELECT;
 506
 507         if (div == 1)
 508                 val = clk_get_rate(clk->parent) * 22;
 509
 510         else
 511                 val = clk_get_rate(clk->parent) * 20;
 512
 513         return val;
 514 }
 515
 516 static int _clk_pll2_main_set_rate(struct clk *clk, unsigned long rate)
 517 {
 518         unsigned int reg,  div;
 519
 520         if (rate == 528000000)
 521                 div = 1;
 522         else if (rate == 480000000)
 523                 div = 0;
 524         else
 525                 return -EINVAL;
 526
 527         reg = __raw_readl(PLL2_528_BASE_ADDR);
 528         reg &= ~ANADIG_PLL_528_DIV_SELECT;
 529         reg |= div;
 530         __raw_writel(reg, PLL2_528_BASE_ADDR);
 531
 532         return 0;
 533 }
 534
 535 static struct clk pll2_528_bus_main_clk = {
 536         __INIT_CLK_DEBUG(pll2_528_bus_main_clk)
 537         .parent = &osc_clk,
 538         .get_rate = _clk_pll2_main_get_rate,
 539         .set_rate = _clk_pll2_main_set_rate,
 540         .enable = _clk_pll_enable,
 541         .disable = _clk_pll_disable,
 542 };
 543
 544 static struct clk pll2_pfd_400M = {
 545         __INIT_CLK_DEBUG(pll2_pfd_400M)
 546         .parent = &pll2_528_bus_main_clk,
 547         .enable_reg = (void *)PFD_528_BASE_ADDR,
 548         .enable_shift = ANADIG_PFD2_FRAC_OFFSET,
 549         .enable = _clk_pfd_enable,
 550         .disable = _clk_pfd_disable,
 551         .get_rate = pfd_get_rate,
 552         .set_rate = pfd_set_rate,
 553         .get_rate = pfd_get_rate,
 554         .round_rate = pfd_round_rate,
 555 };
 556
 557 static struct clk pll2_pfd_352M = {
 558         __INIT_CLK_DEBUG(pll2_pfd_352M)
 559         .parent = &pll2_528_bus_main_clk,
 560         .enable_reg = (void *)PFD_528_BASE_ADDR,
 561         .enable_shift = ANADIG_PFD0_FRAC_OFFSET,
 562         .enable = _clk_pfd_enable,
 563         .disable = _clk_pfd_disable,
 564         .set_rate = pfd_set_rate,
 565         .get_rate = pfd_get_rate,
 566         .round_rate = pfd_round_rate,
 567 };
 568
 569 static struct clk pll2_pfd_594M = {
 570         __INIT_CLK_DEBUG(pll2_pfd_594M)
 571         .parent = &pll2_528_bus_main_clk,
 572         .enable_reg = (void *)PFD_528_BASE_ADDR,
 573         .enable_shift = ANADIG_PFD1_FRAC_OFFSET,
 574         .enable = _clk_pfd_enable,
 575         .disable = _clk_pfd_disable,
 576         .set_rate = pfd_set_rate,
 577         .get_rate = pfd_get_rate,
 578         .round_rate = pfd_round_rate,
 579 };
 580
 581 static unsigned long _clk_pll2_200M_get_rate(struct clk *clk)
 582 {
 583         return clk_get_rate(clk->parent) / 2;
 584 }
 585
 586 static struct clk pll2_200M = {
 587         __INIT_CLK_DEBUG(pll2_200M)
 588         .parent = &pll2_pfd_400M,
 589         .get_rate = _clk_pll2_200M_get_rate,
 590 };
 591
 592 static unsigned long _clk_pll3_usb_otg_get_rate(struct clk *clk)
 593 {
 594         unsigned int div;
 595         unsigned long val;
 596
 597         div = __raw_readl(PLL3_480_USB1_BASE_ADDR)
 598                 & ANADIG_PLL_480_DIV_SELECT_MASK;
 599
 600         if (div == 1)
 601                 val = clk_get_rate(clk->parent) * 22;
 602         else
 603                 val = clk_get_rate(clk->parent) * 20;
 604         return val;
 605 }
 606
 607 static int _clk_pll3_usb_otg_set_rate(struct clk *clk, unsigned long rate)
 608 {
 609         unsigned int reg,  div;
 610
 611         if (rate == 528000000)
 612                 div = 1;
 613         else if (rate == 480000000)
 614                 div = 0;
 615         else
 616                 return -EINVAL;
 617
 618         reg = __raw_readl(PLL3_480_USB1_BASE_ADDR);
 619         reg &= ~ANADIG_PLL_480_DIV_SELECT_MASK;
 620         reg |= div;
 621         __raw_writel(reg, PLL3_480_USB1_BASE_ADDR);
 622
 623         return 0;
 624 }
 625
 626
 627 /* same as pll3_main_clk. These two clocks should always be the same */
 628 static struct clk pll3_usb_otg_main_clk = {
 629         __INIT_CLK_DEBUG(pll3_usb_otg_main_clk)
 630         .parent = &osc_clk,
 631         .enable = _clk_pll_enable,
 632         .disable = _clk_pll_disable,
 633         .set_rate = _clk_pll3_usb_otg_set_rate,
 634         .get_rate = _clk_pll3_usb_otg_get_rate,
 635 };
 636
 637 static struct clk usb_phy1_clk = {
 638         __INIT_CLK_DEBUG(usb_phy1_clk)
 639         .parent = &pll3_usb_otg_main_clk,
 640         .set_rate = _clk_pll3_usb_otg_set_rate,
 641         .get_rate = _clk_pll3_usb_otg_get_rate,
 642 };
 643
 644 static struct clk pll3_pfd_508M = {
 645         __INIT_CLK_DEBUG(pll3_pfd_508M)
 646         .parent = &pll3_usb_otg_main_clk,
 647         .enable_reg = (void *)PFD_480_BASE_ADDR,
 648         .enable_shift = ANADIG_PFD2_FRAC_OFFSET,
 649         .enable = _clk_pfd_enable,
 650         .disable = _clk_pfd_disable,
 651         .set_rate = pfd_set_rate,
 652         .get_rate = pfd_get_rate,
 653         .round_rate = pfd_round_rate,
 654 };
 655
 656 static struct clk pll3_pfd_454M = {
 657         __INIT_CLK_DEBUG(pll3_pfd_454M)
 658         .parent = &pll3_usb_otg_main_clk,
 659         .enable_reg = (void *)PFD_480_BASE_ADDR,
 660         .enable_shift = ANADIG_PFD3_FRAC_OFFSET,
 661         .enable = _clk_pfd_enable,
 662         .disable = _clk_pfd_disable,
 663         .set_rate = pfd_set_rate,
 664         .get_rate = pfd_get_rate,
 665         .round_rate = pfd_round_rate,
 666 };
 667
 668 static struct clk pll3_pfd_720M = {
 669         __INIT_CLK_DEBUG(pll3_pfd_720M)
 670         .parent = &pll3_usb_otg_main_clk,
 671         .enable_reg = (void *)PFD_480_BASE_ADDR,
 672         .enable_shift = ANADIG_PFD0_FRAC_OFFSET,
 673         .enable = _clk_pfd_enable,
 674         .disable = _clk_pfd_disable,
 675         .set_rate = pfd_set_rate,
 676         .get_rate = pfd_get_rate,
 677         .round_rate = pfd_round_rate,
 678 };
 679
 680 static struct clk pll3_pfd_540M = {
 681         __INIT_CLK_DEBUG(pll3_pfd_540M)
 682         .parent = &pll3_usb_otg_main_clk,
 683         .enable_reg = (void *)PFD_480_BASE_ADDR,
 684         .enable_shift = ANADIG_PFD1_FRAC_OFFSET,
 685         .enable = _clk_pfd_enable,
 686         .disable = _clk_pfd_disable,
 687         .set_rate = pfd_set_rate,
 688         .get_rate = pfd_get_rate,
 689         .round_rate = pfd_round_rate,
 690         .get_rate = pfd_get_rate,
 691 };
 692
 693 static unsigned long _clk_pll3_sw_get_rate(struct clk *clk)
 694 {
 695         return clk_get_rate(clk->parent);
 696 }
 697
 698 /* same as pll3_main_clk. These two clocks should always be the same */
 699 static struct clk pll3_sw_clk = {
 700         __INIT_CLK_DEBUG(pll3_sw_clk)
 701         .parent = &pll3_usb_otg_main_clk,
 702         .get_rate = _clk_pll3_sw_get_rate,
 703 };
 704
 705 static unsigned long _clk_pll3_120M_get_rate(struct clk *clk)
 706 {
 707         return clk_get_rate(clk->parent) / 4;
 708 }
 709
 710 static struct clk pll3_120M = {
 711         __INIT_CLK_DEBUG(pll3_120M)
 712         .parent = &pll3_sw_clk,
 713         .get_rate = _clk_pll3_120M_get_rate,
 714 };
 715
 716 static unsigned long _clk_pll3_80M_get_rate(struct clk *clk)
 717 {
 718         return clk_get_rate(clk->parent) / 6;
 719 }
 720
 721 static struct clk pll3_80M = {
 722         __INIT_CLK_DEBUG(pll3_80M)
 723         .parent = &pll3_sw_clk,
 724         .get_rate = _clk_pll3_80M_get_rate,
 725 };
 726
 727 static unsigned long _clk_pll3_60M_get_rate(struct clk *clk)
 728 {
 729         return clk_get_rate(clk->parent) / 8;
 730 }
 731
 732 static struct clk pll3_60M = {
 733         __INIT_CLK_DEBUG(pll3_60M)
 734         .parent = &pll3_sw_clk,
 735         .get_rate = _clk_pll3_60M_get_rate,
 736 };
 737
 738 static unsigned long  _clk_audio_video_get_rate(struct clk *clk)
 739 {
 740         unsigned int div, mfn, mfd;
 741         unsigned long rate;
 742         unsigned int parent_rate = clk_get_rate(clk->parent);
 743         void __iomem *pllbase;
 744
 745         if (clk == &pll4_audio_main_clk)
 746                 pllbase = PLL4_AUDIO_BASE_ADDR;
 747         else
 748                 pllbase = PLL5_VIDEO_BASE_ADDR;
 749
 750         div = __raw_readl(pllbase) & ANADIG_PLL_SYS_DIV_SELECT_MASK;
 751         mfn = __raw_readl(pllbase + PLL_NUM_DIV_OFFSET);
 752         mfd = __raw_readl(pllbase + PLL_DENOM_DIV_OFFSET);
 753
 754         rate = (parent_rate * div) + ((parent_rate / mfd) * mfn);
 755
 756         return rate;
 757 }
 758
 759 static int _clk_audio_video_set_rate(struct clk *clk, unsigned long rate)
 760 {
 761         unsigned int reg,  div;
 762         unsigned int mfn, mfd = 1000000;
 763         s64 temp64;
 764         unsigned int parent_rate = clk_get_rate(clk->parent);
 765         void __iomem *pllbase;
 766
 767         if ((rate < AUDIO_VIDEO_MIN_CLK_FREQ) ||
 768                 (rate > AUDIO_VIDEO_MAX_CLK_FREQ))
 769                 return -EINVAL;
 770
 771         if (clk == &pll4_audio_main_clk)
 772                 pllbase = PLL4_AUDIO_BASE_ADDR;
 773         else
 774                 pllbase = PLL5_VIDEO_BASE_ADDR;
 775
 776         div = rate / parent_rate ;
 777         temp64 = (u64) (rate - (div * parent_rate));
 778         temp64 *= mfd;
 779         do_div(temp64, parent_rate);
 780         mfn = temp64;
 781
 782         reg = __raw_readl(pllbase) & ~ANADIG_PLL_SYS_DIV_SELECT_MASK;
 783         reg |= div;
 784         __raw_writel(reg, pllbase);
 785         __raw_writel(mfn, pllbase + PLL_NUM_DIV_OFFSET);
 786         __raw_writel(mfd, pllbase + PLL_DENOM_DIV_OFFSET);
 787
 788         return 0;
 789 }
 790
 791 static unsigned long _clk_audio_video_round_rate(struct clk *clk,
 792                                                 unsigned long rate)
 793 {
 794         if (rate < AUDIO_VIDEO_MIN_CLK_FREQ)
 795                 return AUDIO_VIDEO_MIN_CLK_FREQ;
 796
 797         if (rate > AUDIO_VIDEO_MAX_CLK_FREQ)
 798                 return AUDIO_VIDEO_MAX_CLK_FREQ;
 799
 800         return rate;
 801 }
 802
 803
 804 static struct clk pll4_audio_main_clk = {
 805         __INIT_CLK_DEBUG(pll4_audio_main_clk)
 806         .parent = &osc_clk,
 807         .enable = _clk_pll_enable,
 808         .disable = _clk_pll_disable,
 809         .set_rate = _clk_audio_video_set_rate,
 810         .get_rate = _clk_audio_video_get_rate,
 811         .round_rate = _clk_audio_video_round_rate,
 812 };
 813
 814
 815 static struct clk pll5_video_main_clk = {
 816         __INIT_CLK_DEBUG(pll5_video_main_clk)
 817         .parent = &osc_clk,
 818         .enable = _clk_pll_enable,
 819         .disable = _clk_pll_disable,
 820         .set_rate = _clk_audio_video_set_rate,
 821         .get_rate = _clk_audio_video_get_rate,
 822         .round_rate = _clk_audio_video_round_rate,
 823 };
 824
 825 static struct clk pll6_MLB_main_clk = {
 826         __INIT_CLK_DEBUG(pll6_MLB_main_clk)
 827         .parent = &osc_clk,
 828         .enable = _clk_pll_enable,
 829         .disable = _clk_pll_disable,
 830 };
 831
 832 static unsigned long _clk_pll7_usb_otg_get_rate(struct clk *clk)
 833 {
 834         unsigned int div;
 835         unsigned long val;
 836
 837         div = __raw_readl(PLL7_480_USB2_BASE_ADDR)
 838                 & ANADIG_PLL_480_DIV_SELECT_MASK;
 839
 840         if (div == 1)
 841                 val = clk_get_rate(clk->parent) * 22;
 842         else
 843                 val = clk_get_rate(clk->parent) * 20;
 844         return val;
 845 }
 846
 847 static int _clk_pll7_usb_otg_set_rate(struct clk *clk, unsigned long rate)
 848 {
 849         unsigned int reg,  div;
 850
 851         if (rate == 528000000)
 852                 div = 1;
 853         else if (rate == 480000000)
 854                 div = 0;
 855         else
 856                 return -EINVAL;
 857
 858         reg = __raw_readl(PLL7_480_USB2_BASE_ADDR);
 859         reg &= ~ANADIG_PLL_480_DIV_SELECT_MASK;
 860         reg |= div;
 861         __raw_writel(reg, PLL7_480_USB2_BASE_ADDR);
 862
 863         return 0;
 864 }
 865
 866 static struct clk pll7_usb_host_main_clk = {
 867         __INIT_CLK_DEBUG(pll7_usb_host_main_clk)
 868         .parent = &osc_clk,
 869         .enable = _clk_pll_enable,
 870         .disable = _clk_pll_disable,
 871         .set_rate = _clk_pll7_usb_otg_set_rate,
 872         .get_rate = _clk_pll7_usb_otg_get_rate,
 873
 874 };
 875
 876 static struct clk pll8_enet_main_clk = {
 877         __INIT_CLK_DEBUG(pll8_enet_main_clk)
 878         .parent = &osc_clk,
 879         .enable = _clk_pll_enable,
 880         .disable = _clk_pll_disable,
 881 };
 882
 883 static unsigned long _clk_arm_get_rate(struct clk *clk)
 884 {
 885         u32 cacrr, div;
 886
 887         cacrr = __raw_readl(MXC_CCM_CACRR);
 888         div = (cacrr & MXC_CCM_CACRR_ARM_PODF_MASK) + 1;
 889         return clk_get_rate(clk->parent) / div;
 890 }
 891
 892 static int _clk_arm_set_rate(struct clk *clk, unsigned long rate)
 893 {
 894         int i;
 895         u32 div;
 896         u32 parent_rate;
 897         struct clk *old_parent = pll1_sw_clk.parent;
 898
 899         for (i = 0; i < cpu_op_nr; i++) {
 900                 if (rate == cpu_op_tbl[i].cpu_rate)
 901                         break;
 902         }
 903         if (i >= cpu_op_nr)
 904                 return -EINVAL;
 905
 906         if (rate <= clk_get_rate(&pll2_pfd_400M)) {
 907                 /*
 908                   * Move pll1_sw_clk to PLL2_PFD_400M
 909                   * so that we can disable PLL1.
 910                   */
 911                 if (pll2_pfd_400M.usecount == 0)
 912                         pll2_pfd_400M.enable(&pll2_pfd_400M);
 913                 pll1_sw_clk.set_parent(&pll1_sw_clk, &pll2_pfd_400M);
 914                 pll1_sw_clk.parent = &pll2_pfd_400M;
 915         } else {
 916                 /* Rate is above 400MHz.  We may need to relock PLL1. */
 917                 pll1_sw_clk.set_parent(&pll1_sw_clk, &osc_clk);
 918                 if (pll1_sys_main_clk.usecount == 0)
 919                         pll1_sys_main_clk.enable(&pll1_sys_main_clk);
 920                 pll1_sys_main_clk.set_rate(&pll1_sys_main_clk, cpu_op_tbl[i].pll_rate);
 921                 pll1_sw_clk.set_parent(&pll1_sw_clk, &pll1_sys_main_clk);
 922                 pll1_sw_clk.parent = &pll1_sys_main_clk;
 923         }
 924
 925         parent_rate = clk_get_rate(clk->parent);
 926         div = parent_rate / rate;
 927
 928         if (div == 0)
 929                 div = 1;
 930
 931         if ((parent_rate / div) > rate)
 932                 div++;
 933
 934         if (div > 8)
 935                 return -1;
 936
 937         __raw_writel(div - 1, MXC_CCM_CACRR);
 938
 939         /* Increment current parent's usecount. */
 940         pll1_sw_clk.parent->usecount++;
 941
 942         /* Decrement the current parent's usecount */
 943         old_parent->usecount--;
 944
 945         if (old_parent->usecount == 0)
 946                 old_parent->disable(old_parent);
 947
 948         return 0;
 949 }
 950
 951 static struct clk cpu_clk = {
 952         __INIT_CLK_DEBUG(cpu_clk)
 953         .parent = &pll1_sw_clk,
 954         .set_rate = _clk_arm_set_rate,
 955         .get_rate = _clk_arm_get_rate,
 956 };
 957
 958 static int _clk_periph_set_parent(struct clk *clk, struct clk *parent)
 959 {
 960         u32 reg;
 961         int mux;
 962
 963         mux = _get_mux6(parent, &pll2_528_bus_main_clk, &pll2_pfd_400M,
 964                 &pll2_pfd_352M, &pll2_200M, &pll3_sw_clk, &osc_clk);
 965
 966         if (mux <= 3) {
 967                 /* Set the pre_periph_clk multiplexer */
 968                 reg = __raw_readl(MXC_CCM_CBCMR);
 969                 reg &= ~MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK;
 970                 reg |= mux << MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET;
 971                 __raw_writel(reg, MXC_CCM_CBCMR);
 972
 973                 /* Set the periph_clk_sel multiplexer. */
 974                 reg = __raw_readl(MXC_CCM_CBCDR);
 975                 reg &= ~MXC_CCM_CBCDR_PERIPH_CLK_SEL;
 976                 __raw_writel(reg, MXC_CCM_CBCDR);
 977         } else {
 978                 reg = __raw_readl(MXC_CCM_CBCDR);
 979                 /* Set the periph_clk2_podf divider to divide by 1. */
 980                 reg &= ~MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK;
 981                 __raw_writel(reg, MXC_CCM_CBCDR);
 982
 983                 /* Set the periph_clk2_sel mux. */
 984                 reg = __raw_readl(MXC_CCM_CBCMR);
 985                 reg &= ~MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK;
 986                 reg |= ((mux - 4) << MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET);
 987                 __raw_writel(reg, MXC_CCM_CBCMR);
 988
 989                 while (__raw_readl(MXC_CCM_CDHIPR))
 990                         ;
 991
 992                 reg = __raw_readl(MXC_CCM_CBCDR);
 993                 /* Set periph_clk_sel to select periph_clk2. */
 994                 reg |= MXC_CCM_CBCDR_PERIPH_CLK_SEL;
 995                 __raw_writel(reg, MXC_CCM_CBCDR);
 996         }
 997
 998         if (!WAIT(!(__raw_readl(MXC_CCM_CDHIPR)
 999              & MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY), SPIN_DELAY))
1000                 panic("_clk_periph_set_parent failed\n");
1001
1002         return 0;
1003 }
1004
1005 static unsigned long _clk_periph_get_rate(struct clk *clk)
1006 {
1007         u32 div = 1;
1008         u32 reg;
1009         unsigned long val;
1010
1011         if ((clk->parent == &pll3_sw_clk) || (clk->parent == &osc_clk)) {
1012                 reg = __raw_readl(MXC_CCM_CBCDR)
1013                         & MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK;
1014                 div = (reg >> MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET) + 1;
1015         }
1016         val = clk_get_rate(clk->parent) / div;
1017         return val;
1018 }
1019
1020 static struct clk periph_clk = {
1021         __INIT_CLK_DEBUG(periph_clk)
1022         .parent = &pll2_528_bus_main_clk,
1023         .set_parent = _clk_periph_set_parent,
1024         .get_rate = _clk_periph_get_rate,
1025 };
1026
1027 static unsigned long _clk_axi_get_rate(struct clk *clk)
1028 {
1029         u32 div, reg;
1030         unsigned long val;
1031
1032         reg = __raw_readl(MXC_CCM_CBCDR) & MXC_CCM_CBCDR_AXI_PODF_MASK;
1033         div = (reg >> MXC_CCM_CBCDR_AXI_PODF_OFFSET);
1034
1035         val = clk_get_rate(clk->parent) / (div + 1);
1036         return val;
1037 }
1038
1039 static int _clk_axi_set_rate(struct clk *clk, unsigned long rate)
1040 {
1041         u32 reg, div;
1042         u32 parent_rate = clk_get_rate(clk->parent);
1043
1044         div = parent_rate / rate;
1045
1046         if (div == 0)
1047                 div++;
1048         if (((parent_rate / div) != rate) || (div > 8))
1049                 return -EINVAL;
1050
1051         reg = __raw_readl(MXC_CCM_CBCDR);
1052         reg &= ~MXC_CCM_CBCDR_AXI_PODF_MASK;
1053         reg |= (div - 1) << MXC_CCM_CBCDR_AXI_PODF_OFFSET;
1054         __raw_writel(reg, MXC_CCM_CBCDR);
1055
1056         if (!WAIT(!(__raw_readl(MXC_CCM_CDHIPR)
1057              & MXC_CCM_CDHIPR_AXI_PODF_BUSY), SPIN_DELAY))
1058                 panic("pll _clk_axi_a_set_rate failed\n");
1059
1060         return 0;
1061 }
1062
1063 static unsigned long _clk_axi_round_rate(struct clk *clk,
1064                                                 unsigned long rate)
1065 {
1066         u32 div;
1067         u32 parent_rate = clk_get_rate(clk->parent);
1068
1069         div = parent_rate / rate;
1070
1071         /* Make sure rate is not greater than the maximum
1072          * value for the clock.
1073          * Also prevent a div of 0.
1074          */
1075
1076         if (div > 8)
1077                 div = 8;
1078         else if (div == 0)
1079                 div++;
1080
1081         return parent_rate / div;
1082 }
1083
1084 static int _clk_axi_set_parent(struct clk *clk, struct clk *parent)
1085 {
1086         u32 reg;
1087         int mux;
1088
1089         mux = _get_mux6(parent, &periph_clk, &pll2_pfd_400M,
1090                                 &pll3_pfd_540M, NULL, NULL, NULL);
1091
1092         if (mux == 0) {
1093                 /* Set the AXI_SEL mux */
1094                 reg = __raw_readl(MXC_CCM_CBCDR) & ~MXC_CCM_CBCDR_AXI_SEL;
1095                 __raw_writel(reg, MXC_CCM_CBCDR);
1096         } else {
1097                 /* Set the AXI_ALT_SEL mux. */
1098                 reg = __raw_readl(MXC_CCM_CBCDR)
1099                         & ~MXC_CCM_CBCDR_AXI_ALT_SEL_MASK;
1100                 reg = ((mux - 1) << MXC_CCM_CBCDR_AXI_ALT_SEL_OFFSET);
1101                 __raw_writel(reg, MXC_CCM_CBCDR);
1102
1103                 /* Set the AXI_SEL mux */
1104                 reg = __raw_readl(MXC_CCM_CBCDR) & ~MXC_CCM_CBCDR_AXI_SEL;
1105                 reg |= MXC_CCM_CBCDR_AXI_SEL;
1106                 __raw_writel(reg, MXC_CCM_CBCDR);
1107         }
1108         return 0;
1109 }
1110
1111 static struct clk axi_clk = {
1112         __INIT_CLK_DEBUG(axi_clk)
1113         .parent = &periph_clk,
1114         .set_parent = _clk_axi_set_parent,
1115         .set_rate = _clk_axi_set_rate,
1116         .get_rate = _clk_axi_get_rate,
1117         .round_rate = _clk_axi_round_rate,
1118 };
1119
1120 static unsigned long _clk_ahb_get_rate(struct clk *clk)
1121 {
1122         u32 reg, div;
1123
1124         reg = __raw_readl(MXC_CCM_CBCDR);
1125         div = ((reg & MXC_CCM_CBCDR_AHB_PODF_MASK) >>
1126                MXC_CCM_CBCDR_AHB_PODF_OFFSET) + 1;
1127
1128         return clk_get_rate(clk->parent) / div;
1129 }
1130
1131 static int _clk_ahb_set_rate(struct clk *clk, unsigned long rate)
1132 {
1133         u32 reg, div;
1134         u32 parent_rate = clk_get_rate(clk->parent);
1135
1136         div = parent_rate / rate;
1137         if (div == 0)
1138                 div++;
1139         if (((parent_rate / div) != rate) || (div > 8))
1140                 return -EINVAL;
1141
1142         reg = __raw_readl(MXC_CCM_CBCDR);
1143         reg &= ~MXC_CCM_CBCDR_AHB_PODF_MASK;
1144         reg |= (div - 1) << MXC_CCM_CBCDR_AHB_PODF_OFFSET;
1145         __raw_writel(reg, MXC_CCM_CBCDR);
1146
1147         if (!WAIT(!(__raw_readl(MXC_CCM_CDHIPR) & MXC_CCM_CDHIPR_AHB_PODF_BUSY),
1148                                 SPIN_DELAY))
1149                         panic("_clk_ahb_set_rate failed\n");
1150
1151         return 0;
1152 }
1153
1154 static unsigned long _clk_ahb_round_rate(struct clk *clk,
1155                                                 unsigned long rate)
1156 {
1157         u32 div;
1158         u32 parent_rate = clk_get_rate(clk->parent);
1159
1160         div = parent_rate / rate;
1161
1162         /* Make sure rate is not greater than the maximum value for the clock.
1163          * Also prevent a div of 0.
1164          */
1165         if (div == 0)
1166                 div++;
1167
1168         if (div > 8)
1169                 div = 8;
1170
1171         return parent_rate / div;
1172 }
1173
1174 static struct clk ahb_clk = {
1175         __INIT_CLK_DEBUG(ahb_clk)
1176         .parent = &periph_clk,
1177         .get_rate = _clk_ahb_get_rate,
1178         .set_rate = _clk_ahb_set_rate,
1179         .round_rate = _clk_ahb_round_rate,
1180 };
1181
1182 static unsigned long _clk_ipg_get_rate(struct clk *clk)
1183 {
1184         u32 reg, div;
1185
1186         reg = __raw_readl(MXC_CCM_CBCDR);
1187         div = ((reg & MXC_CCM_CBCDR_IPG_PODF_MASK) >>
1188                 MXC_CCM_CBCDR_IPG_PODF_OFFSET) + 1;
1189
1190         return clk_get_rate(clk->parent) / div;
1191 }
1192
1193
1194 static struct clk ipg_clk = {
1195         __INIT_CLK_DEBUG(ipg_clk)
1196         .parent = &ahb_clk,
1197         .get_rate = _clk_ipg_get_rate,
1198 };
1199
1200 static struct clk tzasc1_clk = {
1201         __INIT_CLK_DEBUG(tzasc1_clk)
1202         .id = 0,
1203         .parent = &ipg_clk,
1204         .enable_reg = MXC_CCM_CCGR2,
1205         .enable_shift = MXC_CCM_CCGRx_CG11_OFFSET,
1206         .enable = _clk_enable,
1207         .disable = _clk_disable_inwait,
1208 };
1209
1210 static struct clk tzasc2_clk = {
1211         __INIT_CLK_DEBUG(tzasc2_clk)
1212         .id = 0,
1213         .parent = &ipg_clk,
1214         .enable_reg = MXC_CCM_CCGR2,
1215         .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET,
1216         .enable = _clk_enable,
1217         .disable = _clk_disable_inwait,
1218 };
1219
1220 static struct clk mx6fast1_clk = {
1221         __INIT_CLK_DEBUG(mx6fast1_clk)
1222         .id = 0,
1223         .parent = &ahb_clk,
1224         .enable_reg = MXC_CCM_CCGR4,
1225         .enable_shift = MXC_CCM_CCGRx_CG4_OFFSET,
1226         .enable = _clk_enable,
1227         .disable = _clk_disable_inwait,
1228 };
1229
1230 static struct clk mx6per1_clk = {
1231         __INIT_CLK_DEBUG(mx6per1_clk)
1232         .id = 0,
1233         .parent = &ahb_clk,
1234         .secondary = &mx6fast1_clk,
1235         .enable_reg = MXC_CCM_CCGR4,
1236         .enable_shift = MXC_CCM_CCGRx_CG6_OFFSET,
1237         .enable = _clk_enable,
1238         .disable = _clk_disable_inwait,
1239 };
1240
1241 static struct clk mx6per2_clk = {
1242         __INIT_CLK_DEBUG(mx6per2_clk)
1243         .id = 0,
1244         .parent = &ahb_clk,
1245         .enable_reg = MXC_CCM_CCGR4,
1246         .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
1247         .enable = _clk_enable,
1248         .disable = _clk_disable_inwait,
1249 };
1250
1251 static unsigned long _clk_mmdc_ch0_axi_get_rate(struct clk *clk)
1252 {
1253         u32 reg, div;
1254
1255         reg = __raw_readl(MXC_CCM_CBCDR);
1256         div = ((reg & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
1257                         MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET) + 1;
1258
1259         return clk_get_rate(clk->parent) / div;
1260 }
1261
1262 static int _clk_mmdc_ch0_axi_set_rate(struct clk *clk, unsigned long rate)
1263 {
1264         u32 reg, div;
1265         u32 parent_rate = clk_get_rate(clk->parent);
1266
1267         div = parent_rate / rate;
1268         if (div == 0)
1269                 div++;
1270         if (((parent_rate / div) != rate) || (div > 8))
1271                 return -EINVAL;
1272
1273         reg = __raw_readl(MXC_CCM_CBCDR);
1274         reg &= ~MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK;
1275         reg |= (div - 1) << MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
1276         __raw_writel(reg, MXC_CCM_CBCDR);
1277
1278         if (!WAIT(!(__raw_readl(MXC_CCM_CDHIPR)
1279                 & MXC_CCM_CDHIPR_MMDC_CH0_PODF_BUSY),
1280                                 SPIN_DELAY))
1281                         panic("_clk_mmdc_ch0_axi_set_rate failed\n");
1282
1283         return 0;
1284 }
1285
1286 static unsigned long _clk_mmdc_ch0_axi_round_rate(struct clk *clk,
1287                                                 unsigned long rate)
1288 {
1289         u32 div;
1290         u32 parent_rate = clk_get_rate(clk->parent);
1291
1292         div = parent_rate / rate;
1293
1294         /* Make sure rate is not greater than the maximum value for the clock.
1295          * Also prevent a div of 0.
1296          */
1297         if (div == 0)
1298                 div++;
1299
1300         if (div > 8)
1301                 div = 8;
1302
1303         return parent_rate / div;
1304 }
1305
1306 static struct clk mmdc_ch0_axi_clk[] = {
1307         {
1308         __INIT_CLK_DEBUG(mmdc_ch0_axi_clk)
1309         .id = 0,
1310         .parent = &periph_clk,
1311         .enable = _clk_enable,
1312         .disable = _clk_disable_inwait,
1313         .enable_reg = MXC_CCM_CCGR3,
1314         .enable_shift = MXC_CCM_CCGRx_CG10_OFFSET,
1315         .secondary = &mmdc_ch0_axi_clk[1],
1316         .get_rate = _clk_mmdc_ch0_axi_get_rate,
1317         .set_rate = _clk_mmdc_ch0_axi_set_rate,
1318         .round_rate = _clk_mmdc_ch0_axi_round_rate,
1319         },
1320         {
1321         __INIT_CLK_DEBUG(mmdc_ch0_ipg_clk)
1322         .id = 0,
1323         .parent = &ipg_clk,
1324         .enable = _clk_enable,
1325         .disable = _clk_disable_inwait,
1326         .enable_reg = MXC_CCM_CCGR3,
1327         .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET,
1328         .secondary = &tzasc1_clk,
1329         },
1330 };
1331
1332 static unsigned long _clk_mmdc_ch1_axi_get_rate(struct clk *clk)
1333 {
1334         u32 reg, div;
1335
1336         reg = __raw_readl(MXC_CCM_CBCDR);
1337         div = ((reg & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) >>
1338                         MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET) + 1;
1339
1340         return clk_get_rate(clk->parent) / div;
1341 }
1342
1343 static int _clk_mmdc_ch1_axi_set_rate(struct clk *clk, unsigned long rate)
1344 {
1345         u32 reg, div;
1346         u32 parent_rate = clk_get_rate(clk->parent);
1347
1348         div = parent_rate / rate;
1349         if (div == 0)
1350                 div++;
1351         if (((parent_rate / div) != rate) || (div > 8))
1352                 return -EINVAL;
1353
1354         reg = __raw_readl(MXC_CCM_CBCDR);
1355         reg &= ~MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK;
1356         reg |= (div - 1) << MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
1357         __raw_writel(reg, MXC_CCM_CBCDR);
1358
1359         if (!WAIT(!(__raw_readl(MXC_CCM_CDHIPR)
1360                 & MXC_CCM_CDHIPR_MMDC_CH1_PODF_BUSY), SPIN_DELAY))
1361                         panic("_clk_mmdc_ch1_axi_set_rate failed\n");
1362
1363         return 0;
1364 }
1365
1366 static unsigned long _clk_mmdc_ch1_axi_round_rate(struct clk *clk,
1367                                                 unsigned long rate)
1368 {
1369         u32 div;
1370         u32 parent_rate = clk_get_rate(clk->parent);
1371
1372         div = parent_rate / rate;
1373
1374         /* Make sure rate is not greater than the maximum value for the clock.
1375          * Also prevent a div of 0.
1376          */
1377         if (div == 0)
1378                 div++;
1379
1380         if (div > 8)
1381                 div = 8;
1382
1383         return parent_rate / div;
1384 }
1385
1386 static struct clk mmdc_ch1_axi_clk[] = {
1387         {
1388         __INIT_CLK_DEBUG(mmdc_ch1_axi_clk)
1389         .id = 0,
1390         .parent = &pll2_pfd_400M,
1391         .enable = _clk_enable,
1392         .disable = _clk_disable,
1393         .enable_reg = MXC_CCM_CCGR3,
1394         .enable_shift = MXC_CCM_CCGRx_CG11_OFFSET,
1395         .secondary = &mmdc_ch1_axi_clk[1],
1396         .get_rate = _clk_mmdc_ch1_axi_get_rate,
1397         .set_rate = _clk_mmdc_ch1_axi_set_rate,
1398         .round_rate = _clk_mmdc_ch1_axi_round_rate,
1399         },
1400         {
1401         .id = 1,
1402         __INIT_CLK_DEBUG(mmdc_ch1_ipg_clk)
1403         .parent = &ipg_clk,
1404         .enable = _clk_enable,
1405         .disable = _clk_disable,
1406         .enable_reg = MXC_CCM_CCGR3,
1407         .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
1408         .secondary = &tzasc2_clk,
1409         },
1410 };
1411
1412 static struct clk ocram_clk = {
1413         __INIT_CLK_DEBUG(ocram_clk)
1414         .id = 0,
1415         .parent = &ahb_clk,
1416         .enable_reg = MXC_CCM_CCGR3,
1417         .enable_shift = MXC_CCM_CCGRx_CG14_OFFSET,
1418         .enable = _clk_enable,
1419         .disable = _clk_disable_inwait,
1420 };
1421
1422 static unsigned long _clk_ipg_perclk_get_rate(struct clk *clk)
1423 {
1424         u32 reg, div;
1425
1426         reg = __raw_readl(MXC_CCM_CSCMR1);
1427         div = ((reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK) >>
1428                         MXC_CCM_CSCMR1_PERCLK_PODF_OFFSET) + 1;
1429
1430         return clk_get_rate(clk->parent) / div;
1431 }
1432
1433 static int _clk_ipg_perclk_set_rate(struct clk *clk, unsigned long rate)
1434 {
1435         u32 reg, div;
1436         u32 parent_rate = clk_get_rate(clk->parent);
1437
1438         div = parent_rate / rate;
1439         if (div == 0)
1440                 div++;
1441         if (((parent_rate / div) != rate) || (div > 64))
1442                 return -EINVAL;
1443
1444         reg = __raw_readl(MXC_CCM_CSCMR1);
1445         reg &= ~MXC_CCM_CSCMR1_PERCLK_PODF_MASK;
1446         reg |= (div - 1) << MXC_CCM_CSCMR1_PERCLK_PODF_OFFSET;
1447         __raw_writel(reg, MXC_CCM_CSCMR1);
1448
1449         return 0;
1450 }
1451
1452
1453 static unsigned long _clk_ipg_perclk_round_rate(struct clk *clk,
1454                                                 unsigned long rate)
1455 {
1456         u32 div;
1457         u32 parent_rate = clk_get_rate(clk->parent);
1458
1459         div = parent_rate / rate;
1460
1461         /* Make sure rate is not greater than the maximum value for the clock.
1462          * Also prevent a div of 0.
1463          */
1464         if (div == 0)
1465                 div++;
1466
1467         if (div > 64)
1468                 div = 64;
1469
1470         return parent_rate / div;
1471 }
1472
1473 static struct clk ipg_perclk = {
1474         __INIT_CLK_DEBUG(ipg_perclk)
1475         .parent = &ipg_clk,
1476         .get_rate = _clk_ipg_perclk_get_rate,
1477         .set_rate = _clk_ipg_perclk_set_rate,
1478         .round_rate = _clk_ipg_perclk_round_rate,
1479 };
1480
1481 static struct clk spba_clk = {
1482         __INIT_CLK_DEBUG(spba_clk)
1483         .parent = &ipg_clk,
1484         .enable_reg = MXC_CCM_CCGR5,
1485         .enable_shift = MXC_CCM_CCGRx_CG6_OFFSET,
1486         .enable = _clk_enable,
1487         .disable = _clk_disable,
1488 };
1489
1490 static struct clk sdma_clk[] = {
1491         {
1492          __INIT_CLK_DEBUG(sdma_clk)
1493          .parent = &ahb_clk,
1494          .enable_reg = MXC_CCM_CCGR5,
1495          .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET,
1496          .enable = _clk_enable,
1497          .disable = _clk_disable,
1498          .secondary = &sdma_clk[1],
1499         },
1500         {
1501          .parent = &mx6per1_clk,
1502 #ifdef CONFIG_SDMA_IRAM
1503          .secondary = &ocram_clk,
1504 #else
1505         .secondary = &mmdc_ch0_axi_clk[0],
1506 #endif
1507         },
1508 };
1509
1510 static int _clk_gpu2d_axi_set_parent(struct clk *clk, struct clk *parent)
1511 {
1512         u32 reg = __raw_readl(MXC_CCM_CBCMR) & ~MXC_CCM_CBCMR_GPU2D_AXI_CLK_SEL;
1513
1514         if (parent == &ahb_clk)
1515                 reg |= MXC_CCM_CBCMR_GPU2D_AXI_CLK_SEL;
1516
1517         __raw_writel(reg, MXC_CCM_CBCMR);
1518
1519         return 0;
1520 }
1521
1522 static struct clk gpu2d_axi_clk = {
1523         __INIT_CLK_DEBUG(gpu2d_axi_clk)
1524         .parent = &axi_clk,
1525         .secondary = &mmdc_ch0_axi_clk[0],
1526         .set_parent = _clk_gpu2d_axi_set_parent,
1527 };
1528
1529 static int _clk_gpu3d_axi_set_parent(struct clk *clk, struct clk *parent)
1530 {
1531         u32 reg = __raw_readl(MXC_CCM_CBCMR) & ~MXC_CCM_CBCMR_GPU3D_AXI_CLK_SEL;
1532
1533         if (parent == &ahb_clk)
1534                 reg |= MXC_CCM_CBCMR_GPU3D_AXI_CLK_SEL;
1535
1536         __raw_writel(reg, MXC_CCM_CBCMR);
1537
1538         return 0;
1539 }
1540
1541 static struct clk gpu3d_axi_clk = {
1542         __INIT_CLK_DEBUG(gpu3d_axi_clk)
1543         .parent = &axi_clk,
1544         .secondary = &mmdc_ch0_axi_clk[0],
1545         .set_parent = _clk_gpu3d_axi_set_parent,
1546 };
1547
1548 static int _clk_pcie_axi_set_parent(struct clk *clk, struct clk *parent)
1549 {
1550         u32 reg = __raw_readl(MXC_CCM_CBCMR) & ~MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL;
1551
1552         if (parent == &ahb_clk)
1553                 reg |= MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL;
1554
1555         __raw_writel(reg, MXC_CCM_CBCMR);
1556
1557         return 0;
1558 }
1559
1560 static struct clk pcie_axi_clk = {
1561         __INIT_CLK_DEBUG(pcie_axi_clk)
1562         .parent = &axi_clk,
1563         .set_parent = _clk_pcie_axi_set_parent,
1564 };
1565
1566 static int _clk_vdo_axi_set_parent(struct clk *clk, struct clk *parent)
1567 {
1568         u32 reg = __raw_readl(MXC_CCM_CBCMR) & ~MXC_CCM_CBCMR_VDOAXI_CLK_SEL;
1569
1570         if (parent == &ahb_clk)
1571                 reg |= MXC_CCM_CBCMR_VDOAXI_CLK_SEL;
1572
1573         __raw_writel(reg, MXC_CCM_CBCMR);
1574
1575         return 0;
1576 }
1577
1578 static struct clk vdo_axi_clk = {
1579         __INIT_CLK_DEBUG(vdo_axi_clk)
1580         .parent = &axi_clk,
1581         .enable_reg = MXC_CCM_CCGR6,
1582         .enable_shift = MXC_CCM_CCGRx_CG6_OFFSET,
1583         .enable = _clk_enable,
1584         .disable = _clk_disable,
1585         .set_parent = _clk_vdo_axi_set_parent,
1586 };
1587
1588 static struct clk vdoa_clk = {
1589         __INIT_CLK_DEBUG(vdoa_clk)
1590         .id = 0,
1591         .parent = &axi_clk,
1592         .secondary = &mx6fast1_clk,
1593         .enable_reg = MXC_CCM_CCGR2,
1594         .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
1595         .enable = _clk_enable,
1596         .disable = _clk_disable,
1597 };
1598
1599 static struct clk gpt_clk[] = {
1600         {
1601         __INIT_CLK_DEBUG(gpt_clk)
1602          .parent = &ipg_perclk,
1603          .id = 0,
1604          .enable_reg = MXC_CCM_CCGR1,
1605          .enable_shift = MXC_CCM_CCGRx_CG10_OFFSET,
1606          .enable = _clk_enable,
1607          .disable = _clk_disable,
1608          .secondary = &gpt_clk[1],
1609          },
1610         {
1611         __INIT_CLK_DEBUG(gpt_serial_clk)
1612          .id = 0,
1613          .enable_reg = MXC_CCM_CCGR1,
1614          .enable_shift = MXC_CCM_CCGRx_CG11_OFFSET,
1615          .enable = _clk_enable,
1616          .disable = _clk_disable,
1617          },
1618 };
1619
1620 static struct clk iim_clk = {
1621         __INIT_CLK_DEBUG(iim_clk)
1622         .parent = &ipg_clk,
1623         .enable = _clk_enable,
1624         .enable_reg = MXC_CCM_CCGR2,
1625         .enable_shift = MXC_CCM_CCGRx_CG6_OFFSET,
1626         .disable = _clk_disable,
1627 };
1628
1629 static struct clk i2c_clk[] = {
1630         {
1631         __INIT_CLK_DEBUG(i2c_clk_0)
1632          .id = 0,
1633          .parent = &ipg_perclk,
1634          .enable_reg = MXC_CCM_CCGR2,
1635          .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET,
1636          .enable = _clk_enable,
1637          .disable = _clk_disable,
1638          },
1639         {
1640         __INIT_CLK_DEBUG(i2c_clk_1)
1641          .id = 1,
1642          .parent = &ipg_perclk,
1643          .enable_reg = MXC_CCM_CCGR2,
1644          .enable_shift = MXC_CCM_CCGRx_CG4_OFFSET,
1645          .enable = _clk_enable,
1646          .disable = _clk_disable,
1647          },
1648         {
1649         __INIT_CLK_DEBUG(i2c_clk_2)
1650          .id = 2,
1651          .parent = &ipg_perclk,
1652          .enable_reg = MXC_CCM_CCGR2,
1653          .enable_shift = MXC_CCM_CCGRx_CG5_OFFSET,
1654          .enable = _clk_enable,
1655          .disable = _clk_disable,
1656          },
1657 };
1658
1659 static int _clk_vpu_axi_set_parent(struct clk *clk, struct clk *parent)
1660 {
1661         int mux;
1662         u32 reg = __raw_readl(MXC_CCM_CBCMR)
1663                 & ~MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK;
1664
1665         mux = _get_mux6(parent, &axi_clk, &pll2_pfd_400M,
1666                 &pll2_pfd_352M, NULL, NULL, NULL);
1667
1668         reg |= (mux << MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET);
1669
1670         __raw_writel(reg, MXC_CCM_CBCMR);
1671
1672         return 0;
1673 }
1674
1675 static unsigned long _clk_vpu_axi_get_rate(struct clk *clk)
1676 {
1677         u32 reg, div;
1678
1679         reg = __raw_readl(MXC_CCM_CSCDR1);
1680         div = ((reg & MXC_CCM_CSCDR1_VPU_AXI_PODF_MASK) >>
1681                         MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET) + 1;
1682
1683         return clk_get_rate(clk->parent) / div;
1684 }
1685
1686 static int _clk_vpu_axi_set_rate(struct clk *clk, unsigned long rate)
1687 {
1688         u32 reg, div;
1689         u32 parent_rate = clk_get_rate(clk->parent);
1690
1691         div = parent_rate / rate;
1692         if (div == 0)
1693                 div++;
1694         if (((parent_rate / div) != rate) || (div > 8))
1695                 return -EINVAL;
1696
1697         reg = __raw_readl(MXC_CCM_CSCDR1);
1698         reg &= ~MXC_CCM_CSCDR1_VPU_AXI_PODF_MASK;
1699         reg |= (div - 1) << MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET;
1700         __raw_writel(reg, MXC_CCM_CSCDR1);
1701
1702         return 0;
1703 }
1704
1705 static unsigned long _clk_vpu_axi_round_rate(struct clk *clk,
1706                                                 unsigned long rate)
1707 {
1708         u32 div;
1709         u32 parent_rate = clk_get_rate(clk->parent);
1710
1711         div = parent_rate / rate;
1712
1713         /* Make sure rate is not greater than the maximum value for the clock.
1714          * Also prevent a div of 0.
1715          */
1716         if (div == 0)
1717                 div++;
1718
1719         if (div > 8)
1720                 div = 8;
1721
1722         return parent_rate / div;
1723 }
1724
1725 static struct clk vpu_clk[] = {
1726         {
1727         __INIT_CLK_DEBUG(vpu_clk)
1728         .parent = &axi_clk,
1729         .enable_reg = MXC_CCM_CCGR6,
1730         .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
1731         .enable = _clk_enable,
1732         .disable = _clk_disable,
1733         .set_parent = _clk_vpu_axi_set_parent,
1734         .round_rate = _clk_vpu_axi_round_rate,
1735         .set_rate = _clk_vpu_axi_set_rate,
1736         .get_rate = _clk_vpu_axi_get_rate,
1737         .secondary = &vpu_clk[1],
1738         },
1739         {
1740         .parent =  &mmdc_ch0_axi_clk[0],
1741         .secondary = &vpu_clk[2],
1742         },
1743         {
1744         .parent =  &mx6fast1_clk,
1745         .secondary = &ocram_clk,
1746         },
1747
1748 };
1749
1750 static int _clk_ipu1_set_parent(struct clk *clk, struct clk *parent)
1751 {
1752         int mux;
1753         u32 reg = __raw_readl(MXC_CCM_CSCDR3)
1754                 & ~MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_MASK;
1755
1756         mux = _get_mux6(parent, &mmdc_ch0_axi_clk[0],
1757                 &pll2_pfd_400M, &pll3_120M, &pll3_pfd_540M, NULL, NULL);
1758
1759         reg |= (mux << MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_OFFSET);
1760
1761         __raw_writel(reg, MXC_CCM_CSCDR3);
1762
1763         return 0;
1764 }
1765
1766 static unsigned long _clk_ipu1_get_rate(struct clk *clk)
1767 {
1768         u32 reg, div;
1769
1770         reg = __raw_readl(MXC_CCM_CSCDR3);
1771         div = ((reg & MXC_CCM_CSCDR3_IPU1_HSP_PODF_MASK) >>
1772                         MXC_CCM_CSCDR3_IPU1_HSP_PODF_OFFSET) + 1;
1773
1774         return clk_get_rate(clk->parent) / div;
1775 }
1776
1777 static int _clk_ipu1_set_rate(struct clk *clk, unsigned long rate)
1778 {
1779         u32 reg, div;
1780         u32 parent_rate = clk_get_rate(clk->parent);
1781
1782         div = parent_rate / rate;
1783         if (div == 0)
1784                 div++;
1785         if (((parent_rate / div) != rate) || (div > 8))
1786                 return -EINVAL;
1787
1788         reg = __raw_readl(MXC_CCM_CSCDR3);
1789         reg &= ~MXC_CCM_CSCDR3_IPU1_HSP_PODF_MASK;
1790         reg |= (div - 1) << MXC_CCM_CSCDR3_IPU1_HSP_PODF_OFFSET;
1791         __raw_writel(reg, MXC_CCM_CSCDR3);
1792
1793         return 0;
1794 }
1795
1796 static unsigned long _clk_ipu_round_rate(struct clk *clk,
1797                                                 unsigned long rate)
1798 {
1799         u32 div;
1800         u32 parent_rate = clk_get_rate(clk->parent);
1801
1802         div = parent_rate / rate;
1803
1804         /* Make sure rate is not greater than the maximum value for the clock.
1805          * Also prevent a div of 0.
1806          */
1807         if (div == 0)
1808                 div++;
1809
1810         if (div > 8)
1811                 div = 8;
1812
1813         return parent_rate / div;
1814 }
1815
1816 static struct clk ipu1_clk = {
1817         __INIT_CLK_DEBUG(ipu1_clk)
1818         .parent = &mmdc_ch0_axi_clk[0],
1819         .secondary = &mmdc_ch0_axi_clk[0],
1820         .enable_reg = MXC_CCM_CCGR3,
1821         .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET,
1822         .enable = _clk_enable,
1823         .disable = _clk_disable,
1824         .set_parent = _clk_ipu1_set_parent,
1825         .round_rate = _clk_ipu_round_rate,
1826         .set_rate = _clk_ipu1_set_rate,
1827         .get_rate = _clk_ipu1_get_rate,
1828         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
1829 };
1830
1831 static int _clk_cko1_clk0_set_parent(struct clk *clk, struct clk *parent)
1832 {
1833         u32 sel, reg;
1834
1835         if (parent == &pll3_sw_clk)
1836                 sel = 0;
1837         else if (parent == &pll2_528_bus_main_clk)
1838                 sel = 1;
1839         else if (parent == &pll1_sys_main_clk)
1840                 sel = 2;
1841         else if (parent == &pll5_video_main_clk)
1842                 sel = 3;
1843         else if (parent == &axi_clk)
1844                 sel = 5;
1845         else if (parent == &enfc_clk)
1846                 sel = 6;
1847         else if (parent == &ipu1_di_clk_root)
1848                 sel = 7;
1849         else if (parent == &ipu1_di_clk_root)
1850                 sel = 8;
1851         else if (parent == &ipu2_di_clk_root)
1852                 sel = 9;
1853         else if (parent == &ipu2_di_clk_root)
1854                 sel = 10;
1855         else if (parent == &ahb_clk)
1856                 sel = 11;
1857         else if (parent == &ipg_clk)
1858                 sel = 12;
1859         else if (parent == &ipg_perclk)
1860                 sel = 13;
1861         else if (parent == &ckil_clk)
1862                 sel = 14;
1863         else if (parent == &pll4_audio_main_clk)
1864                 sel = 15;
1865         else
1866                 return -EINVAL;
1867
1868         reg = __raw_readl(MXC_CCM_CCOSR);
1869         reg &= ~MXC_CCM_CCOSR_CKOL_SEL_MASK;
1870         reg |= sel << MXC_CCM_CCOSR_CKOL_SEL_OFFSET;
1871         __raw_writel(reg, MXC_CCM_CCOSR);
1872         return 0;
1873 }
1874
1875 static unsigned long _clk_cko1_round_rate(struct clk *clk,
1876                                                 unsigned long rate)
1877 {
1878         u32 div;
1879         u32 parent_rate = clk_get_rate(clk->parent);
1880
1881         div = parent_rate / rate;
1882
1883         /* Make sure rate is not greater than the maximum value for the clock.
1884          * Also prevent a div of 0.
1885          */
1886         if (div == 0)
1887                 div++;
1888
1889         if (div > 8)
1890                 div = 8;
1891
1892         return parent_rate / div;
1893 }
1894
1895 static int _clk_cko1_set_rate(struct clk *clk, unsigned long rate)
1896 {
1897         u32 reg, div;
1898         u32 parent_rate = clk_get_rate(clk->parent);
1899
1900         div = parent_rate / rate;
1901         if (div == 0)
1902                 div++;
1903         if (((parent_rate / div) != rate) || (div > 8))
1904                 return -EINVAL;
1905
1906         reg = __raw_readl(MXC_CCM_CCOSR);
1907         reg &= ~MXC_CCM_CCOSR_CKOL_DIV_MASK;
1908         reg |= div << MXC_CCM_CCOSR_CKOL_DIV_OFFSET;
1909         __raw_writel(reg, MXC_CCM_CCOSR);
1910
1911         return 0;
1912 }
1913
1914 static unsigned long _clk_cko1_get_rate(struct clk *clk)
1915 {
1916         u32 reg, div;
1917
1918         reg = __raw_readl(MXC_CCM_CCOSR);
1919         div = ((reg & MXC_CCM_CCOSR_CKOL_DIV_MASK) >>
1920                         MXC_CCM_CCOSR_CKOL_DIV_OFFSET) + 1;
1921
1922         return clk_get_rate(clk->parent) / div;
1923 }
1924
1925 static int cko1_clk_enable(struct clk *clk)
1926 {
1927         u32 reg;
1928         reg = __raw_readl(clk->enable_reg);
1929         reg |= clk->enable_shift;
1930         __raw_writel(reg, clk->enable_reg);
1931
1932         return 0;
1933 }
1934
1935 static struct clk cko1_clk0 = {
1936         __INIT_CLK_DEBUG(cko1_clk0)
1937         .parent = &ipg_clk,
1938         .enable_reg = MXC_CCM_CCOSR,
1939         .enable_shift = MXC_CCM_CCOSR_CKOL_EN,
1940         .enable = cko1_clk_enable,
1941         .disable = _clk_disable,
1942         .set_parent = _clk_cko1_clk0_set_parent,
1943         .round_rate = _clk_cko1_round_rate,
1944         .set_rate = _clk_cko1_set_rate,
1945         .get_rate = _clk_cko1_get_rate,
1946 };
1947
1948 static int _clk_ipu2_set_parent(struct clk *clk, struct clk *parent)
1949 {
1950         int mux;
1951         u32 reg = __raw_readl(MXC_CCM_CSCDR3)
1952                 & ~MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_MASK;
1953
1954         mux = _get_mux6(parent, &mmdc_ch0_axi_clk[0],
1955                 &pll2_pfd_400M, &pll3_120M, &pll3_pfd_540M, NULL, NULL);
1956
1957         reg |= (mux << MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_OFFSET);
1958
1959         __raw_writel(reg, MXC_CCM_CSCDR3);
1960
1961         return 0;
1962 }
1963
1964 static unsigned long _clk_ipu2_get_rate(struct clk *clk)
1965 {
1966         u32 reg, div;
1967
1968         reg = __raw_readl(MXC_CCM_CSCDR3);
1969         div = ((reg & MXC_CCM_CSCDR3_IPU2_HSP_PODF_MASK) >>
1970                         MXC_CCM_CSCDR3_IPU2_HSP_PODF_OFFSET) + 1;
1971
1972         return clk_get_rate(clk->parent) / div;
1973 }
1974
1975 static int _clk_ipu2_set_rate(struct clk *clk, unsigned long rate)
1976 {
1977         u32 reg, div;
1978         u32 parent_rate = clk_get_rate(clk->parent);
1979
1980         div = parent_rate / rate;
1981         if (div == 0)
1982                 div++;
1983         if (((parent_rate / div) != rate) || (div > 8))
1984                 return -EINVAL;
1985
1986         reg = __raw_readl(MXC_CCM_CSCDR3);
1987         reg &= ~MXC_CCM_CSCDR3_IPU2_HSP_PODF_MASK;
1988         reg |= (div - 1) << MXC_CCM_CSCDR3_IPU2_HSP_PODF_OFFSET;
1989         __raw_writel(reg, MXC_CCM_CSCDR3);
1990
1991         return 0;
1992 }
1993
1994 static struct clk ipu2_clk = {
1995         __INIT_CLK_DEBUG(ipu2_clk)
1996         .parent = &mmdc_ch0_axi_clk[0],
1997         .secondary = &mmdc_ch0_axi_clk[0],
1998         .enable_reg = MXC_CCM_CCGR3,
1999         .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET,
2000         .enable = _clk_enable,
2001         .disable = _clk_disable,
2002         .set_parent = _clk_ipu2_set_parent,
2003         .round_rate = _clk_ipu_round_rate,
2004         .set_rate = _clk_ipu2_set_rate,
2005         .get_rate = _clk_ipu2_get_rate,
2006         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
2007 };
2008
2009 static struct clk usdhc_dep_clk = {
2010         .parent = &mmdc_ch0_axi_clk[0],
2011         .secondary = &mx6per1_clk,
2012         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
2013         };
2014
2015 static unsigned long _clk_usdhc_round_rate(struct clk *clk,
2016                                                 unsigned long rate)
2017 {
2018         u32 div;
2019         u32 parent_rate = clk_get_rate(clk->parent);
2020
2021         div = parent_rate / rate;
2022
2023         /* Make sure rate is not greater than the maximum value for the clock.
2024          * Also prevent a div of 0.
2025          */
2026         if (div == 0)
2027                 div++;
2028
2029         if (div > 8)
2030                 div = 8;
2031
2032         return parent_rate / div;
2033 }
2034
2035 static int _clk_usdhc1_set_parent(struct clk *clk, struct clk *parent)
2036 {
2037         u32 reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_USDHC1_CLK_SEL;
2038
2039         if (parent == &pll2_pfd_352M)
2040                 reg |= (MXC_CCM_CSCMR1_USDHC1_CLK_SEL);
2041
2042         __raw_writel(reg, MXC_CCM_CSCMR1);
2043
2044         return 0;
2045 }
2046
2047 static unsigned long _clk_usdhc1_get_rate(struct clk *clk)
2048 {
2049         u32 reg, div;
2050
2051         reg = __raw_readl(MXC_CCM_CSCDR1);
2052         div = ((reg & MXC_CCM_CSCDR1_USDHC1_PODF_MASK) >>
2053                         MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET) + 1;
2054
2055         return clk_get_rate(clk->parent) / div;
2056 }
2057
2058 static int _clk_usdhc1_set_rate(struct clk *clk, unsigned long rate)
2059 {
2060         u32 reg, div;
2061         u32 parent_rate = clk_get_rate(clk->parent);
2062
2063         div = parent_rate / rate;
2064         if (div == 0)
2065                 div++;
2066         if (((parent_rate / div) != rate) || (div > 8))
2067                 return -EINVAL;
2068
2069         reg = __raw_readl(MXC_CCM_CSCDR1);
2070         reg &= ~MXC_CCM_CSCDR1_USDHC1_PODF_MASK;
2071         reg |= (div - 1) << MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET;
2072         __raw_writel(reg, MXC_CCM_CSCDR1);
2073
2074         return 0;
2075 }
2076
2077 static struct clk usdhc1_clk = {
2078         __INIT_CLK_DEBUG(usdhc1_clk)
2079         .id = 0,
2080         .parent = &pll2_pfd_400M,
2081         .secondary = &usdhc_dep_clk,
2082         .enable_reg = MXC_CCM_CCGR6,
2083         .enable_shift = MXC_CCM_CCGRx_CG1_OFFSET,
2084         .enable = _clk_enable,
2085         .disable = _clk_disable,
2086         .set_parent = _clk_usdhc1_set_parent,
2087         .round_rate = _clk_usdhc_round_rate,
2088         .set_rate = _clk_usdhc1_set_rate,
2089         .get_rate = _clk_usdhc1_get_rate,
2090         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
2091 };
2092
2093 static int _clk_usdhc2_set_parent(struct clk *clk, struct clk *parent)
2094 {
2095         u32 reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_USDHC2_CLK_SEL;
2096
2097         if (parent == &pll2_pfd_352M)
2098                 reg |= (MXC_CCM_CSCMR1_USDHC2_CLK_SEL);
2099
2100         __raw_writel(reg, MXC_CCM_CSCMR1);
2101
2102         return 0;
2103 }
2104
2105 static unsigned long _clk_usdhc2_get_rate(struct clk *clk)
2106 {
2107         u32 reg, div;
2108
2109         reg = __raw_readl(MXC_CCM_CSCDR1);
2110         div = ((reg & MXC_CCM_CSCDR1_USDHC2_PODF_MASK) >>
2111                         MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET) + 1;
2112
2113         return clk_get_rate(clk->parent) / div;
2114 }
2115
2116 static int _clk_usdhc2_set_rate(struct clk *clk, unsigned long rate)
2117 {
2118         u32 reg, div;
2119         u32 parent_rate = clk_get_rate(clk->parent);
2120
2121         div = parent_rate / rate;
2122         if (div == 0)
2123                 div++;
2124         if (((parent_rate / div) != rate) || (div > 8))
2125                 return -EINVAL;
2126
2127         reg = __raw_readl(MXC_CCM_CSCDR1);
2128         reg &= ~MXC_CCM_CSCDR1_USDHC2_PODF_MASK;
2129         reg |= (div - 1) << MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET;
2130         __raw_writel(reg, MXC_CCM_CSCDR1);
2131
2132         return 0;
2133 }
2134
2135 static struct clk usdhc2_clk = {
2136         __INIT_CLK_DEBUG(usdhc2_clk)
2137         .id = 1,
2138         .parent = &pll2_pfd_400M,
2139         .secondary = &usdhc_dep_clk,
2140         .enable_reg = MXC_CCM_CCGR6,
2141         .enable_shift = MXC_CCM_CCGRx_CG2_OFFSET,
2142         .enable = _clk_enable,
2143         .disable = _clk_disable,
2144         .set_parent = _clk_usdhc2_set_parent,
2145         .round_rate = _clk_usdhc_round_rate,
2146         .set_rate = _clk_usdhc2_set_rate,
2147         .get_rate = _clk_usdhc2_get_rate,
2148         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
2149 };
2150
2151 static int _clk_usdhc3_set_parent(struct clk *clk, struct clk *parent)
2152 {
2153         u32 reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_USDHC3_CLK_SEL;
2154
2155         if (parent == &pll2_pfd_352M)
2156                 reg |= (MXC_CCM_CSCMR1_USDHC3_CLK_SEL);
2157
2158         __raw_writel(reg, MXC_CCM_CSCMR1);
2159
2160         return 0;
2161 }
2162
2163 static unsigned long _clk_usdhc3_get_rate(struct clk *clk)
2164 {
2165         u32 reg, div;
2166
2167         reg = __raw_readl(MXC_CCM_CSCDR1);
2168         div = ((reg & MXC_CCM_CSCDR1_USDHC3_PODF_MASK) >>
2169                         MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET) + 1;
2170
2171         return clk_get_rate(clk->parent) / div;
2172 }
2173
2174 static int _clk_usdhc3_set_rate(struct clk *clk, unsigned long rate)
2175 {
2176         u32 reg, div;
2177         u32 parent_rate = clk_get_rate(clk->parent);
2178
2179         div = parent_rate / rate;
2180         if (div == 0)
2181                 div++;
2182         if (((parent_rate / div) != rate) || (div > 8))
2183                 return -EINVAL;
2184
2185         reg = __raw_readl(MXC_CCM_CSCDR1);
2186         reg &= ~MXC_CCM_CSCDR1_USDHC3_PODF_MASK;
2187         reg |= (div - 1) << MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET;
2188         __raw_writel(reg, MXC_CCM_CSCDR1);
2189
2190         return 0;
2191 }
2192
2193
2194 static struct clk usdhc3_clk = {
2195         __INIT_CLK_DEBUG(usdhc3_clk)
2196         .id = 2,
2197         .parent = &pll2_pfd_400M,
2198         .secondary = &usdhc_dep_clk,
2199         .enable_reg = MXC_CCM_CCGR6,
2200         .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET,
2201         .enable = _clk_enable,
2202         .disable = _clk_disable,
2203         .set_parent = _clk_usdhc3_set_parent,
2204         .round_rate = _clk_usdhc_round_rate,
2205         .set_rate = _clk_usdhc3_set_rate,
2206         .get_rate = _clk_usdhc3_get_rate,
2207         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
2208 };
2209
2210 static int _clk_usdhc4_set_parent(struct clk *clk, struct clk *parent)
2211 {
2212         u32 reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_USDHC4_CLK_SEL;
2213
2214         if (parent == &pll2_pfd_352M)
2215                 reg |= (MXC_CCM_CSCMR1_USDHC4_CLK_SEL);
2216
2217         __raw_writel(reg, MXC_CCM_CSCMR1);
2218
2219         return 0;
2220 }
2221
2222 static unsigned long _clk_usdhc4_get_rate(struct clk *clk)
2223 {
2224         u32 reg, div;
2225
2226         reg = __raw_readl(MXC_CCM_CSCDR1);
2227         div = ((reg & MXC_CCM_CSCDR1_USDHC4_PODF_MASK) >>
2228                         MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET) + 1;
2229
2230         return clk_get_rate(clk->parent) / div;
2231 }
2232
2233 static int _clk_usdhc4_set_rate(struct clk *clk, unsigned long rate)
2234 {
2235         u32 reg, div;
2236         u32 parent_rate = clk_get_rate(clk->parent);
2237
2238         div = parent_rate / rate;
2239         if (div == 0)
2240                 div++;
2241         if (((parent_rate / div) != rate) || (div > 8))
2242                 return -EINVAL;
2243
2244         reg = __raw_readl(MXC_CCM_CSCDR1);
2245         reg &= ~MXC_CCM_CSCDR1_USDHC4_PODF_MASK;
2246         reg |= (div - 1) << MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET;
2247         __raw_writel(reg, MXC_CCM_CSCDR1);
2248
2249         return 0;
2250 }
2251
2252
2253 static struct clk usdhc4_clk = {
2254         __INIT_CLK_DEBUG(usdhc4_clk)
2255         .id = 3,
2256         .parent = &pll2_pfd_400M,
2257         .secondary = &usdhc_dep_clk,
2258         .enable_reg = MXC_CCM_CCGR6,
2259         .enable_shift = MXC_CCM_CCGRx_CG4_OFFSET,
2260         .enable = _clk_enable,
2261         .disable = _clk_disable,
2262         .set_parent = _clk_usdhc4_set_parent,
2263         .round_rate = _clk_usdhc_round_rate,
2264         .set_rate = _clk_usdhc4_set_rate,
2265         .get_rate = _clk_usdhc4_get_rate,
2266         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
2267 };
2268
2269 static unsigned long _clk_ssi_round_rate(struct clk *clk,
2270                                                 unsigned long rate)
2271 {
2272         u32 pre, post;
2273         u32 parent_rate = clk_get_rate(clk->parent);
2274         u32 div = parent_rate / rate;
2275
2276         if (parent_rate % rate)
2277                 div++;
2278
2279         __calc_pre_post_dividers(1 << 6, div, &pre, &post);
2280
2281         return parent_rate / (pre * post);
2282 }
2283
2284 static unsigned long _clk_ssi1_get_rate(struct clk *clk)
2285 {
2286         u32 reg, prediv, podf;
2287
2288         reg = __raw_readl(MXC_CCM_CS1CDR);
2289
2290         prediv = ((reg & MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK)
2291                 >> MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET) + 1;
2292         podf = ((reg & MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK)
2293                 >> MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET) + 1;
2294
2295         return clk_get_rate(clk->parent) / (prediv * podf);
2296 }
2297
2298 static int _clk_ssi1_set_rate(struct clk *clk, unsigned long rate)
2299 {
2300         u32 reg, div, pre, post;
2301         u32 parent_rate = clk_get_rate(clk->parent);
2302
2303         div = parent_rate / rate;
2304         if (div == 0)
2305                 div++;
2306         if (((parent_rate / div) != rate) || div > 512)
2307                 return -EINVAL;
2308
2309         __calc_pre_post_dividers(1 << 6, div, &pre, &post);
2310
2311         reg = __raw_readl(MXC_CCM_CS1CDR);
2312         reg &= ~(MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK |
2313                  MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK);
2314         reg |= (post - 1) << MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET;
2315         reg |= (pre - 1) << MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET;
2316
2317         __raw_writel(reg, MXC_CCM_CS1CDR);
2318
2319         return 0;
2320 }
2321
2322
2323 static int _clk_ssi1_set_parent(struct clk *clk, struct clk *parent)
2324 {
2325         u32 reg, mux;
2326
2327         reg = __raw_readl(MXC_CCM_CSCMR1)
2328                 & ~MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK;
2329
2330         mux = _get_mux6(parent, &pll3_pfd_508M, &pll3_pfd_454M,
2331                         &pll4_audio_main_clk, NULL, NULL, NULL);
2332         reg |= (mux << MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET);
2333
2334         __raw_writel(reg, MXC_CCM_CSCMR1);
2335
2336         return 0;
2337 }
2338
2339 static struct clk ssi1_clk = {
2340         __INIT_CLK_DEBUG(ssi1_clk)
2341         .parent = &pll3_pfd_508M,
2342         .enable_reg = MXC_CCM_CCGR5,
2343         .enable_shift = MXC_CCM_CCGRx_CG9_OFFSET,
2344         .enable = _clk_enable,
2345         .disable = _clk_disable,
2346         .set_parent = _clk_ssi1_set_parent,
2347         .set_rate = _clk_ssi1_set_rate,
2348         .round_rate = _clk_ssi_round_rate,
2349         .get_rate = _clk_ssi1_get_rate,
2350 #ifdef CONFIG_SND_MXC_SOC_IRAM
2351          .secondary = &ocram_clk,
2352 #else
2353          .secondary = &mmdc_ch0_axi_clk[0],
2354 #endif
2355 };
2356
2357 static unsigned long _clk_ssi2_get_rate(struct clk *clk)
2358 {
2359         u32 reg, prediv, podf;
2360
2361         reg = __raw_readl(MXC_CCM_CS2CDR);
2362
2363         prediv = ((reg & MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK)
2364                 >> MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET) + 1;
2365         podf = ((reg & MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK)
2366                 >> MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET) + 1;
2367
2368         return clk_get_rate(clk->parent) / (prediv * podf);
2369 }
2370
2371 static int _clk_ssi2_set_rate(struct clk *clk, unsigned long rate)
2372 {
2373         u32 reg, div, pre, post;
2374         u32 parent_rate = clk_get_rate(clk->parent);
2375
2376         div = parent_rate / rate;
2377         if (div == 0)
2378                 div++;
2379         if (((parent_rate / div) != rate) || div > 512)
2380                 return -EINVAL;
2381
2382         __calc_pre_post_dividers(1 << 6, div, &pre, &post);
2383
2384         reg = __raw_readl(MXC_CCM_CS2CDR);
2385         reg &= ~(MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK |
2386                  MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK);
2387         reg |= (post - 1) << MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET;
2388         reg |= (pre - 1) << MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET;
2389
2390         __raw_writel(reg, MXC_CCM_CS2CDR);
2391
2392         return 0;
2393 }
2394
2395
2396 static int _clk_ssi2_set_parent(struct clk *clk, struct clk *parent)
2397 {
2398         u32 reg, mux;
2399
2400         reg = __raw_readl(MXC_CCM_CSCMR1)
2401                 & ~MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK;
2402
2403         mux = _get_mux6(parent, &pll3_pfd_508M, &pll3_pfd_454M,
2404                         &pll4_audio_main_clk, NULL, NULL, NULL);
2405         reg |= (mux << MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET);
2406
2407         __raw_writel(reg, MXC_CCM_CSCMR1);
2408
2409         return 0;
2410 }
2411
2412 static struct clk ssi2_clk = {
2413         __INIT_CLK_DEBUG(ssi2_clk)
2414         .parent = &pll3_pfd_508M,
2415         .enable_reg = MXC_CCM_CCGR5,
2416         .enable_shift = MXC_CCM_CCGRx_CG10_OFFSET,
2417         .enable = _clk_enable,
2418         .disable = _clk_disable,
2419         .set_parent = _clk_ssi2_set_parent,
2420         .set_rate = _clk_ssi2_set_rate,
2421         .round_rate = _clk_ssi_round_rate,
2422         .get_rate = _clk_ssi2_get_rate,
2423 #ifdef CONFIG_SND_MXC_SOC_IRAM
2424          .secondary = &ocram_clk,
2425 #else
2426          .secondary = &mmdc_ch0_axi_clk[0],
2427 #endif
2428 };
2429
2430 static unsigned long _clk_ssi3_get_rate(struct clk *clk)
2431 {
2432         u32 reg, prediv, podf;
2433
2434         reg = __raw_readl(MXC_CCM_CS1CDR);
2435
2436         prediv = ((reg & MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK)
2437                 >> MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET) + 1;
2438         podf = ((reg & MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK)
2439                 >> MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET) + 1;
2440
2441         return clk_get_rate(clk->parent) / (prediv * podf);
2442 }
2443
2444 static int _clk_ssi3_set_rate(struct clk *clk, unsigned long rate)
2445 {
2446         u32 reg, div, pre, post;
2447         u32 parent_rate = clk_get_rate(clk->parent);
2448
2449         div = parent_rate / rate;
2450         if (div == 0)
2451                 div++;
2452         if (((parent_rate / div) != rate) || div > 512)
2453                 return -EINVAL;
2454
2455         __calc_pre_post_dividers(1 << 6, div, &pre, &post);
2456
2457         reg = __raw_readl(MXC_CCM_CS1CDR);
2458         reg &= ~(MXC_CCM_CS1CDR_SSI3_CLK_PODF_MASK|
2459                  MXC_CCM_CS1CDR_SSI3_CLK_PRED_MASK);
2460         reg |= (post - 1) << MXC_CCM_CS1CDR_SSI3_CLK_PODF_OFFSET;
2461         reg |= (pre - 1) << MXC_CCM_CS1CDR_SSI3_CLK_PRED_OFFSET;
2462
2463         __raw_writel(reg, MXC_CCM_CS1CDR);
2464
2465         return 0;
2466 }
2467
2468
2469 static int _clk_ssi3_set_parent(struct clk *clk, struct clk *parent)
2470 {
2471         u32 reg, mux;
2472
2473         reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_SSI3_CLK_SEL_MASK;
2474
2475         mux = _get_mux6(parent, &pll3_pfd_508M, &pll3_pfd_454M,
2476                                 &pll4_audio_main_clk, NULL, NULL, NULL);
2477         reg |= (mux << MXC_CCM_CSCMR1_SSI3_CLK_SEL_OFFSET);
2478
2479         __raw_writel(reg, MXC_CCM_CSCMR1);
2480
2481         return 0;
2482 }
2483
2484 static struct clk ssi3_clk = {
2485         __INIT_CLK_DEBUG(ssi3_clk)
2486         .parent = &pll3_pfd_508M,
2487         .enable_reg = MXC_CCM_CCGR5,
2488         .enable_shift = MXC_CCM_CCGRx_CG11_OFFSET,
2489         .enable = _clk_enable,
2490         .disable = _clk_disable,
2491         .set_parent = _clk_ssi3_set_parent,
2492         .set_rate = _clk_ssi3_set_rate,
2493         .round_rate = _clk_ssi_round_rate,
2494         .get_rate = _clk_ssi3_get_rate,
2495 #ifdef CONFIG_SND_MXC_SOC_IRAM
2496          .secondary = &ocram_clk,
2497 #else
2498          .secondary = &mmdc_ch0_axi_clk[0],
2499 #endif
2500 };
2501
2502 static unsigned long _clk_ldb_di_round_rate(struct clk *clk,
2503                                                 unsigned long rate)
2504 {
2505         u32 parent_rate = clk_get_rate(clk->parent);
2506
2507         if (rate * 7 <= parent_rate + parent_rate/20)
2508                 return parent_rate / 7;
2509         else
2510                 return 2 * parent_rate / 7;
2511 }
2512
2513 static unsigned long _clk_ldb_di0_get_rate(struct clk *clk)
2514 {
2515         u32 div;
2516
2517         div = __raw_readl(MXC_CCM_CSCMR2) &
2518                 MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
2519
2520         if (div)
2521                 return clk_get_rate(clk->parent) / 7;
2522
2523         return (2 * clk_get_rate(clk->parent)) / 7;
2524 }
2525
2526 static int _clk_ldb_di0_set_rate(struct clk *clk, unsigned long rate)
2527 {
2528         u32 reg, div = 0;
2529         u32 parent_rate = clk_get_rate(clk->parent);
2530
2531         if (rate * 7 <= parent_rate + parent_rate/20) {
2532                 div = 7;
2533                 rate = parent_rate / 7;
2534         } else
2535                 rate = 2 * parent_rate / 7;
2536
2537         reg = __raw_readl(MXC_CCM_CSCMR2);
2538         if (div == 7)
2539                 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
2540         else
2541                 reg &= ~MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
2542
2543         __raw_writel(reg, MXC_CCM_CSCMR2);
2544
2545         return 0;
2546 }
2547
2548 static int _clk_ldb_di0_set_parent(struct clk *clk, struct clk *parent)
2549 {
2550         u32 reg, mux;
2551
2552         reg = __raw_readl(MXC_CCM_CS2CDR)
2553                 & ~MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK;
2554
2555         mux = _get_mux6(parent, &pll5_video_main_clk,
2556                 &pll2_pfd_352M, &pll2_pfd_400M, &pll3_pfd_540M,
2557                 &pll3_usb_otg_main_clk, NULL);
2558         reg |= (mux << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET);
2559
2560         __raw_writel(reg, MXC_CCM_CS2CDR);
2561
2562         return 0;
2563 }
2564
2565 static struct clk ldb_di0_clk = {
2566          __INIT_CLK_DEBUG(ldb_di0_clk)
2567         .id = 0,
2568         .parent = &pll3_pfd_540M,
2569         .enable_reg = MXC_CCM_CCGR3,
2570         .enable_shift = MXC_CCM_CCGRx_CG6_OFFSET,
2571         .enable = _clk_enable,
2572         .disable = _clk_disable,
2573         .set_parent = _clk_ldb_di0_set_parent,
2574         .set_rate = _clk_ldb_di0_set_rate,
2575         .round_rate = _clk_ldb_di_round_rate,
2576         .get_rate = _clk_ldb_di0_get_rate,
2577         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
2578 };
2579
2580 static unsigned long _clk_ldb_di1_get_rate(struct clk *clk)
2581 {
2582         u32 div;
2583
2584         div = __raw_readl(MXC_CCM_CSCMR2) &
2585                 MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
2586
2587         if (div)
2588                 return clk_get_rate(clk->parent) / 7;
2589
2590         return (2 * clk_get_rate(clk->parent)) / 7;
2591 }
2592
2593 static int _clk_ldb_di1_set_rate(struct clk *clk, unsigned long rate)
2594 {
2595         u32 reg, div = 0;
2596         u32 parent_rate = clk_get_rate(clk->parent);
2597
2598         if (rate * 7 <= parent_rate + parent_rate/20) {
2599                 div = 7;
2600                 rate = parent_rate / 7;
2601         } else
2602                 rate = 2 * parent_rate / 7;
2603
2604         reg = __raw_readl(MXC_CCM_CSCMR2);
2605         if (div == 7)
2606                 reg |= MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
2607         else
2608                 reg &= ~MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
2609
2610         __raw_writel(reg, MXC_CCM_CSCMR2);
2611
2612         return 0;
2613 }
2614
2615 static int _clk_ldb_di1_set_parent(struct clk *clk, struct clk *parent)
2616 {
2617         u32 reg, mux;
2618
2619         reg = __raw_readl(MXC_CCM_CS2CDR)
2620                 & ~MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK;
2621
2622         mux = _get_mux6(parent, &pll5_video_main_clk,
2623                 &pll2_pfd_352M, &pll2_pfd_400M, &pll3_pfd_540M,
2624                 &pll3_usb_otg_main_clk, NULL);
2625         reg |= (mux << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
2626
2627         __raw_writel(reg, MXC_CCM_CS2CDR);
2628
2629         return 0;
2630 }
2631
2632 static struct clk ldb_di1_clk = {
2633          __INIT_CLK_DEBUG(ldb_di1_clk)
2634         .id = 0,
2635         .parent = &pll3_pfd_540M,
2636         .enable_reg = MXC_CCM_CCGR3,
2637         .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
2638         .enable = _clk_enable,
2639         .disable = _clk_disable,
2640         .set_parent = _clk_ldb_di1_set_parent,
2641         .set_rate = _clk_ldb_di1_set_rate,
2642         .round_rate = _clk_ldb_di_round_rate,
2643         .get_rate = _clk_ldb_di1_get_rate,
2644         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
2645 };
2646
2647
2648 static unsigned long _clk_ipu_di_round_rate(struct clk *clk,
2649                                                 unsigned long rate)
2650 {
2651         u32 div;
2652         u32 parent_rate = clk_get_rate(clk->parent);
2653
2654         if ((clk->parent == &ldb_di0_clk) ||
2655                 (clk->parent == &ldb_di1_clk))
2656                 return parent_rate;
2657
2658         div = parent_rate / rate;
2659
2660         /* Make sure rate is not greater than the maximum value for the clock.
2661          * Also prevent a div of 0.
2662          */
2663         if (div == 0)
2664                 div++;
2665
2666         if (div > 8)
2667                 div = 8;
2668
2669         return parent_rate / div;
2670 }
2671
2672 static unsigned long _clk_ipu1_di0_get_rate(struct clk *clk)
2673 {
2674         u32 reg, div;
2675
2676         if ((clk->parent == &ldb_di0_clk) ||
2677                 (clk->parent == &ldb_di1_clk))
2678                 return clk_get_rate(clk->parent);
2679
2680         reg = __raw_readl(MXC_CCM_CHSCCDR);
2681
2682         div = ((reg & MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK) >>
2683                          MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET) + 1;
2684
2685         return clk_get_rate(clk->parent) / div;
2686 }
2687
2688 static int _clk_ipu1_di0_set_rate(struct clk *clk, unsigned long rate)
2689 {
2690         u32 reg, div;
2691         u32 parent_rate = clk_get_rate(clk->parent);
2692
2693         if ((clk->parent == &ldb_di0_clk) ||
2694                 (clk->parent == &ldb_di1_clk)) {
2695                 if (parent_rate == rate)
2696                         return 0;
2697                 else
2698                         return -EINVAL;
2699         }
2700
2701         div = parent_rate / rate;
2702         if (div == 0)
2703                 div++;
2704         if (((parent_rate / div) != rate) || (div > 8))
2705                 return -EINVAL;
2706
2707         reg = __raw_readl(MXC_CCM_CHSCCDR);
2708         reg &= ~MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK;
2709         reg |= (div - 1) << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET;
2710         __raw_writel(reg, MXC_CCM_CHSCCDR);
2711
2712         return 0;
2713 }
2714
2715
2716 static int _clk_ipu1_di0_set_parent(struct clk *clk, struct clk *parent)
2717 {
2718         u32 reg, mux;
2719
2720         if (parent == &ldb_di0_clk)
2721                 mux = 0x3;
2722         else if (parent == &ldb_di1_clk)
2723                 mux = 0x4;
2724         else {
2725                 reg = __raw_readl(MXC_CCM_CHSCCDR)
2726                         & ~MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK;
2727
2728                 mux = _get_mux6(parent, &mmdc_ch0_axi_clk[0],
2729                                 &pll3_usb_otg_main_clk, &pll5_video_main_clk,
2730                                 &pll2_pfd_352M, &pll2_pfd_400M, &pll3_pfd_540M);
2731                 reg |= (mux << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
2732
2733                 __raw_writel(reg, MXC_CCM_CHSCCDR);
2734
2735                 /* Derive clock from divided pre-muxed ipu1_di0 clock.*/
2736                 mux = 0;
2737         }
2738
2739         reg = __raw_readl(MXC_CCM_CHSCCDR)
2740                 & ~MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK;
2741         __raw_writel(reg | (mux << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET),
2742                 MXC_CCM_CHSCCDR);
2743
2744         return 0;
2745 }
2746
2747 static unsigned long _clk_ipu1_di1_get_rate(struct clk *clk)
2748 {
2749         u32 reg, div;
2750
2751         if ((clk->parent == &ldb_di0_clk) ||
2752                 (clk->parent == &ldb_di1_clk))
2753                 return clk_get_rate(clk->parent);
2754
2755         reg = __raw_readl(MXC_CCM_CHSCCDR);
2756
2757         div = ((reg & MXC_CCM_CHSCCDR_IPU1_DI1_PODF_MASK)
2758                         >> MXC_CCM_CHSCCDR_IPU1_DI1_PODF_OFFSET) + 1;
2759
2760         return clk_get_rate(clk->parent) / div;
2761 }
2762
2763 static int _clk_ipu1_di1_set_rate(struct clk *clk, unsigned long rate)
2764 {
2765         u32 reg, div;
2766         u32 parent_rate = clk_get_rate(clk->parent);
2767
2768         if ((clk->parent == &ldb_di0_clk) ||
2769                 (clk->parent == &ldb_di1_clk)) {
2770                 if (parent_rate == rate)
2771                         return 0;
2772                 else
2773                         return -EINVAL;
2774         }
2775
2776         div = parent_rate / rate;
2777         if (div == 0)
2778                 div++;
2779         if (((parent_rate / div) != rate) || (div > 8))
2780                 return -EINVAL;
2781
2782         reg = __raw_readl(MXC_CCM_CHSCCDR);
2783         reg &= ~MXC_CCM_CHSCCDR_IPU1_DI1_PODF_MASK;
2784         reg |= (div - 1) << MXC_CCM_CHSCCDR_IPU1_DI1_PODF_OFFSET;
2785         __raw_writel(reg, MXC_CCM_CHSCCDR);
2786
2787         return 0;
2788 }
2789
2790
2791 static int _clk_ipu1_di1_set_parent(struct clk *clk, struct clk *parent)
2792 {
2793         u32 reg, mux;
2794
2795         if (parent == &ldb_di0_clk)
2796                 mux = 0x3;
2797         else if (parent == &ldb_di1_clk)
2798                 mux = 0x4;
2799         else {
2800                 reg = __raw_readl(MXC_CCM_CHSCCDR)
2801                         & ~MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_MASK;
2802
2803                 mux = _get_mux6(parent, &mmdc_ch0_axi_clk[0],
2804                                 &pll3_usb_otg_main_clk, &pll5_video_main_clk,
2805                                 &pll2_pfd_352M, &pll2_pfd_400M, &pll3_pfd_540M);
2806                 reg |= (mux << MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_OFFSET);
2807
2808                 __raw_writel(reg, MXC_CCM_CHSCCDR);
2809
2810                 /* Derive clock from divided pre-muxed ipu1_di0 clock.*/
2811                 mux = 0;
2812         }
2813         reg = __raw_readl(MXC_CCM_CHSCCDR)
2814                 & ~MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_MASK;
2815         __raw_writel(reg | (mux << MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET),
2816                 MXC_CCM_CHSCCDR);
2817
2818         return 0;
2819 }
2820
2821 static struct clk ipu1_di_clk[] = {
2822         {
2823          __INIT_CLK_DEBUG(ipu1_di_clk_0)
2824         .id = 0,
2825         .parent = &pll5_video_main_clk,
2826         .enable_reg = MXC_CCM_CCGR3,
2827         .enable_shift = MXC_CCM_CCGRx_CG1_OFFSET,
2828         .enable = _clk_enable,
2829         .disable = _clk_disable,
2830         .set_parent = _clk_ipu1_di0_set_parent,
2831         .set_rate = _clk_ipu1_di0_set_rate,
2832         .round_rate = _clk_ipu_di_round_rate,
2833         .get_rate = _clk_ipu1_di0_get_rate,
2834         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
2835         },
2836         {
2837          __INIT_CLK_DEBUG(ipu1_di_clk_1)
2838         .id = 1,
2839         .parent = &pll5_video_main_clk,
2840         .enable_reg = MXC_CCM_CCGR3,
2841         .enable_shift = MXC_CCM_CCGRx_CG2_OFFSET,
2842         .enable = _clk_enable,
2843         .disable = _clk_disable,
2844         .set_parent = _clk_ipu1_di1_set_parent,
2845         .set_rate = _clk_ipu1_di1_set_rate,
2846         .round_rate = _clk_ipu_di_round_rate,
2847         .get_rate = _clk_ipu1_di1_get_rate,
2848         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
2849         },
2850 };
2851
2852 static unsigned long _clk_ipu2_di0_get_rate(struct clk *clk)
2853 {
2854         u32 reg, div;
2855
2856         if ((clk->parent == &ldb_di0_clk) ||
2857                 (clk->parent == &ldb_di1_clk))
2858                 return clk_get_rate(clk->parent);
2859
2860         reg = __raw_readl(MXC_CCM_CSCDR2);
2861
2862         div = ((reg & MXC_CCM_CSCDR2_IPU2_DI0_PODF_MASK) >>
2863                         MXC_CCM_CSCDR2_IPU2_DI0_PODF_OFFSET) + 1;
2864
2865         return clk_get_rate(clk->parent) / div;
2866 }
2867
2868 static int _clk_ipu2_di0_set_rate(struct clk *clk, unsigned long rate)
2869 {
2870         u32 reg, div;
2871         u32 parent_rate = clk_get_rate(clk->parent);
2872
2873         if ((clk->parent == &ldb_di0_clk) ||
2874                 (clk->parent == &ldb_di1_clk)) {
2875                 if (parent_rate == rate)
2876                         return 0;
2877                 else
2878                         return -EINVAL;
2879         }
2880
2881         div = parent_rate / rate;
2882         if (div == 0)
2883                 div++;
2884         if (((parent_rate / div) != rate) || (div > 8))
2885                 return -EINVAL;
2886
2887         reg = __raw_readl(MXC_CCM_CSCDR2);
2888         reg &= ~MXC_CCM_CSCDR2_IPU2_DI0_PODF_MASK;
2889         reg |= (div - 1) << MXC_CCM_CSCDR2_IPU2_DI0_PODF_OFFSET;
2890         __raw_writel(reg, MXC_CCM_CSCDR2);
2891
2892         return 0;
2893 }
2894
2895 static int _clk_ipu2_di0_set_parent(struct clk *clk, struct clk *parent)
2896 {
2897         u32 reg, mux;
2898
2899         if (parent == &ldb_di0_clk)
2900                 mux = 0x3;
2901         else if (parent == &ldb_di1_clk)
2902                 mux = 0x4;
2903         else {
2904                 reg = __raw_readl(MXC_CCM_CSCDR2)
2905                         & ~MXC_CCM_CSCDR2_IPU2_DI0_PRE_CLK_SEL_MASK;
2906
2907                 mux = _get_mux6(parent, &mmdc_ch0_axi_clk[0],
2908                                 &pll3_usb_otg_main_clk, &pll5_video_main_clk,
2909                                 &pll2_pfd_352M, &pll2_pfd_400M, &pll3_pfd_540M);
2910                 reg |= (mux << MXC_CCM_CSCDR2_IPU2_DI0_PRE_CLK_SEL_OFFSET);
2911
2912                 __raw_writel(reg, MXC_CCM_CSCDR2);
2913
2914                 /* Derive clock from divided pre-muxed ipu2_di0 clock.*/
2915                 mux = 0;
2916         }
2917         reg = __raw_readl(MXC_CCM_CSCDR2)
2918                 & ~MXC_CCM_CSCDR2_IPU2_DI0_CLK_SEL_MASK;
2919         __raw_writel(reg | (mux << MXC_CCM_CSCDR2_IPU2_DI0_CLK_SEL_OFFSET),
2920                 MXC_CCM_CSCDR2);
2921
2922         return 0;
2923 }
2924
2925 static unsigned long _clk_ipu2_di1_get_rate(struct clk *clk)
2926 {
2927         u32 reg, div;
2928
2929         if ((clk->parent == &ldb_di0_clk) ||
2930                 (clk->parent == &ldb_di1_clk))
2931                 return clk_get_rate(clk->parent);
2932
2933         reg = __raw_readl(MXC_CCM_CSCDR2);
2934
2935         div = ((reg & MXC_CCM_CSCDR2_IPU2_DI1_PODF_MASK)
2936                 >> MXC_CCM_CSCDR2_IPU2_DI1_PODF_OFFSET) + 1;
2937
2938         return clk_get_rate(clk->parent) / div;
2939 }
2940
2941 static int _clk_ipu2_di1_set_rate(struct clk *clk, unsigned long rate)
2942 {
2943         u32 reg, div;
2944         u32 parent_rate = clk_get_rate(clk->parent);
2945
2946         if ((clk->parent == &ldb_di0_clk) ||
2947                 (clk->parent == &ldb_di1_clk)) {
2948                 if (parent_rate == rate)
2949                         return 0;
2950                 else
2951                         return -EINVAL;
2952         }
2953
2954         div = parent_rate / rate;
2955         if (div == 0)
2956                 div++;
2957         if (((parent_rate / div) != rate) || (div > 8))
2958                 return -EINVAL;
2959
2960         reg = __raw_readl(MXC_CCM_CSCDR2);
2961         reg &= ~MXC_CCM_CSCDR2_IPU2_DI1_PODF_MASK;
2962         reg |= (div - 1) << MXC_CCM_CSCDR2_IPU2_DI1_PODF_OFFSET;
2963         __raw_writel(reg, MXC_CCM_CSCDR2);
2964
2965         return 0;
2966 }
2967
2968 static int _clk_ipu2_di1_set_parent(struct clk *clk, struct clk *parent)
2969 {
2970         u32 reg, mux;
2971
2972         if (parent == &ldb_di0_clk)
2973                 mux = 0x3;
2974         else if (parent == &ldb_di1_clk)
2975                 mux = 0x4;
2976         else {
2977                 reg = __raw_readl(MXC_CCM_CSCDR2)
2978                         & ~MXC_CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_MASK;
2979
2980                 mux = _get_mux6(parent, &mmdc_ch0_axi_clk[0],
2981                                 &pll3_usb_otg_main_clk, &pll5_video_main_clk,
2982                                 &pll2_pfd_352M, &pll2_pfd_400M, &pll3_pfd_540M);
2983                 reg |= (mux << MXC_CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_OFFSET);
2984
2985                 __raw_writel(reg, MXC_CCM_CSCDR2);
2986
2987                 /* Derive clock from divided pre-muxed ipu1_di0 clock.*/
2988                 mux = 0;
2989         }
2990         reg = __raw_readl(MXC_CCM_CSCDR2)
2991                 & ~MXC_CCM_CSCDR2_IPU2_DI1_CLK_SEL_MASK;
2992         __raw_writel(reg | (mux << MXC_CCM_CSCDR2_IPU2_DI1_CLK_SEL_OFFSET),
2993                 MXC_CCM_CSCDR2);
2994
2995         return 0;
2996 }
2997
2998 static struct clk ipu2_di_clk[] = {
2999         {
3000          __INIT_CLK_DEBUG(ipu2_di_clk_0)
3001         .id = 0,
3002         .parent = &pll5_video_main_clk,
3003         .enable_reg = MXC_CCM_CCGR3,
3004         .enable_shift = MXC_CCM_CCGRx_CG4_OFFSET,
3005         .enable = _clk_enable,
3006         .disable = _clk_disable,
3007         .set_parent = _clk_ipu2_di0_set_parent,
3008         .set_rate = _clk_ipu2_di0_set_rate,
3009         .round_rate = _clk_ipu_di_round_rate,
3010         .get_rate = _clk_ipu2_di0_get_rate,
3011         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
3012         },
3013         {
3014          __INIT_CLK_DEBUG(ipu2_di_clk_1)
3015         .id = 1,
3016         .parent = &pll5_video_main_clk,
3017         .enable_reg = MXC_CCM_CCGR3,
3018         .enable_shift = MXC_CCM_CCGRx_CG5_OFFSET,
3019         .enable = _clk_enable,
3020         .disable = _clk_disable,
3021         .set_parent = _clk_ipu2_di1_set_parent,
3022         .set_rate = _clk_ipu2_di1_set_rate,
3023         .round_rate = _clk_ipu_di_round_rate,
3024         .get_rate = _clk_ipu2_di1_get_rate,
3025         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
3026         },
3027 };
3028
3029 static struct clk can2_clk[] = {
3030         {
3031          __INIT_CLK_DEBUG(can2_module_clk)
3032         .id = 0,
3033         .parent = &pll3_60M,
3034         .enable_reg = MXC_CCM_CCGR0,
3035         .enable_shift = MXC_CCM_CCGRx_CG9_OFFSET,
3036         .enable = _clk_enable,
3037         .disable = _clk_disable,
3038         .secondary = &can2_clk[1],
3039         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
3040         },
3041         {
3042          __INIT_CLK_DEBUG(can2_serial_clk)
3043         .id = 1,
3044         .parent = &pll3_60M,
3045         .enable_reg = MXC_CCM_CCGR0,
3046         .enable_shift = MXC_CCM_CCGRx_CG10_OFFSET,
3047         .enable = _clk_enable,
3048         .disable = _clk_disable,
3049         },
3050 };
3051
3052
3053 static struct clk can1_clk[] = {
3054         {
3055          __INIT_CLK_DEBUG(can1_module_clk)
3056         .id = 0,
3057         .parent = &pll3_60M,
3058         .enable_reg = MXC_CCM_CCGR0,
3059         .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
3060         .enable = _clk_enable,
3061         .disable = _clk_disable,
3062         .secondary = &can1_clk[1],
3063         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
3064         },
3065         {
3066          __INIT_CLK_DEBUG(can1_serial_clk)
3067         .id = 1,
3068         .parent = &pll3_60M,
3069         .enable_reg = MXC_CCM_CCGR0,
3070         .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET,
3071         .enable = _clk_enable,
3072         .disable = _clk_disable,
3073         },
3074 };
3075
3076 static unsigned long _clk_spdif_round_rate(struct clk *clk,
3077                                                 unsigned long rate)
3078 {
3079         u32 pre, post;
3080         u32 parent_rate = clk_get_rate(clk->parent);
3081         u32 div = parent_rate / rate;
3082
3083         if (parent_rate % rate)
3084                 div++;
3085
3086         __calc_pre_post_dividers(1 << 3, div, &pre, &post);
3087
3088         return parent_rate / (pre * post);
3089 }
3090
3091 static int _clk_spdif0_set_parent(struct clk *clk, struct clk *parent)
3092 {
3093         u32 reg, mux;
3094
3095         reg = __raw_readl(MXC_CCM_CDCDR)
3096                 & ~MXC_CCM_CDCDR_SPDIF0_CLK_SEL_MASK;
3097
3098         mux = _get_mux6(parent, &pll4_audio_main_clk,
3099                 &pll3_pfd_508M, &pll3_pfd_454M,
3100                 &pll3_sw_clk, NULL, NULL);
3101         reg |= mux << MXC_CCM_CDCDR_SPDIF0_CLK_SEL_OFFSET;
3102
3103         __raw_writel(reg, MXC_CCM_CDCDR);
3104
3105         return 0;
3106 }
3107
3108 static unsigned long _clk_spdif0_get_rate(struct clk *clk)
3109 {
3110         u32 reg, pred, podf;
3111
3112         reg = __raw_readl(MXC_CCM_CDCDR);
3113
3114         pred = ((reg & MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK)
3115                 >> MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET) + 1;
3116         podf = ((reg & MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK)
3117                 >> MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET) + 1;
3118
3119         return clk_get_rate(clk->parent) / (pred * podf);
3120 }
3121
3122 static int _clk_spdif0_set_rate(struct clk *clk, unsigned long rate)
3123 {
3124         u32 reg, div, pre, post;
3125         u32 parent_rate = clk_get_rate(clk->parent);
3126
3127         div = parent_rate / rate;
3128         if (div == 0)
3129                 div++;
3130         if (((parent_rate / div) != rate) || div > 64)
3131                 return -EINVAL;
3132
3133         __calc_pre_post_dividers(1 << 3, div, &pre, &post);
3134
3135         reg = __raw_readl(MXC_CCM_CDCDR);
3136         reg &= ~(MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK|
3137                  MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK);
3138         reg |= (post - 1) << MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET;
3139         reg |= (pre - 1) << MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET;
3140
3141         __raw_writel(reg, MXC_CCM_CDCDR);
3142
3143         return 0;
3144 }
3145
3146 static struct clk spdif0_clk[] = {
3147         {
3148         __INIT_CLK_DEBUG(spdif0_clk_0)
3149         .id = 0,
3150         .parent = &pll3_sw_clk,
3151          .enable = _clk_enable,
3152          .enable_reg = MXC_CCM_CCGR5,
3153          .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
3154          .disable = _clk_disable,
3155          .secondary = &spdif0_clk[1],
3156          .set_rate = _clk_spdif0_set_rate,
3157          .get_rate = _clk_spdif0_get_rate,
3158          .set_parent = _clk_spdif0_set_parent,
3159          .round_rate = _clk_spdif_round_rate,
3160         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
3161         },
3162         {
3163         __INIT_CLK_DEBUG(spdif0_clk_1)
3164          .id = 1,
3165          .parent = &ipg_clk,
3166          .secondary = &spba_clk,
3167          },
3168 };
3169
3170 static unsigned long _clk_esai_round_rate(struct clk *clk,
3171                                                 unsigned long rate)
3172 {
3173         u32 pre, post;
3174         u32 parent_rate = clk_get_rate(clk->parent);
3175         u32 div = parent_rate / rate;
3176
3177         if (parent_rate % rate)
3178                 div++;
3179
3180         __calc_pre_post_dividers(1 << 3, div, &pre, &post);
3181
3182         return parent_rate / (pre * post);
3183 }
3184
3185 static int _clk_esai_set_parent(struct clk *clk, struct clk *parent)
3186 {
3187         u32 reg, mux;
3188
3189         reg = __raw_readl(MXC_CCM_CSCMR2) & ~MXC_CCM_CSCMR2_ESAI_CLK_SEL_MASK;
3190
3191         mux = _get_mux6(parent, &pll4_audio_main_clk, &pll3_pfd_508M,
3192                         &pll3_pfd_454M, &pll3_sw_clk, NULL, NULL);
3193         reg |= mux << MXC_CCM_CSCMR2_ESAI_CLK_SEL_OFFSET;
3194
3195         __raw_writel(reg, MXC_CCM_CSCMR2);
3196
3197         return 0;
3198 }
3199
3200 static unsigned long _clk_esai_get_rate(struct clk *clk)
3201 {
3202         u32 reg, pred, podf;
3203
3204         reg = __raw_readl(MXC_CCM_CS1CDR);
3205
3206         pred = ((reg & MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK)
3207                 >> MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET) + 1;
3208         podf = ((reg & MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK)
3209                 >> MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET) + 1;
3210
3211         return clk_get_rate(clk->parent) / (pred * podf);
3212 }
3213
3214 static int _clk_esai_set_rate(struct clk *clk, unsigned long rate)
3215 {
3216         u32 reg, div, pre, post;
3217         u32 parent_rate = clk_get_rate(clk->parent);
3218
3219         div = parent_rate / rate;
3220         if (div == 0)
3221                 div++;
3222         if (((parent_rate / div) != rate) || div > 64)
3223                 return -EINVAL;
3224
3225         __calc_pre_post_dividers(1 << 3, div, &pre, &post);
3226
3227         reg = __raw_readl(MXC_CCM_CS1CDR);
3228         reg &= ~(MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK|
3229                  MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK);
3230         reg |= (post - 1) << MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET;
3231         reg |= (pre - 1) << MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET;
3232
3233         __raw_writel(reg, MXC_CCM_CS1CDR);
3234
3235         return 0;
3236 }
3237
3238 static struct clk esai_clk = {
3239         __INIT_CLK_DEBUG(esai_clk)
3240          .id = 0,
3241          .parent = &pll3_sw_clk,
3242          .secondary = &spba_clk,
3243          .enable_reg = MXC_CCM_CCGR1,
3244          .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET,
3245          .enable = _clk_enable,
3246          .disable = _clk_disable,
3247          .set_rate = _clk_esai_set_rate,
3248          .get_rate = _clk_esai_get_rate,
3249          .set_parent = _clk_esai_set_parent,
3250          .round_rate = _clk_esai_round_rate,
3251 };
3252
3253 static int _clk_enet_enable(struct clk *clk)
3254 {
3255         unsigned int reg;
3256
3257         /* Enable ENET ref clock */
3258         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
3259         reg &= ~ANADIG_PLL_BYPASS;
3260         reg &= ~ANADIG_PLL_ENABLE;
3261         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
3262
3263         _clk_enable(clk);
3264         return 0;
3265 }
3266
3267 static void _clk_enet_disable(struct clk *clk)
3268 {
3269         unsigned int reg;
3270
3271         _clk_disable(clk);
3272
3273         /* Enable ENET ref clock */
3274         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
3275         reg |= ANADIG_PLL_BYPASS;
3276         reg |= ANADIG_PLL_ENABLE;
3277         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
3278 }
3279
3280 static int _clk_enet_set_rate(struct clk *clk, unsigned long rate)
3281 {
3282         unsigned int reg, div = 1;
3283
3284         switch (rate) {
3285         case 25000000:
3286                 div = 0;
3287                 break;
3288         case 50000000:
3289                 div = 1;
3290                 break;
3291         case 100000000:
3292                 div = 2;
3293                 break;
3294         case 125000000:
3295                 div = 3;
3296                 break;
3297         default:
3298                 return -EINVAL;
3299         }
3300         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
3301         reg &= ~ANADIG_PLL_ENET_DIV_SELECT_MASK;
3302         reg |= (div << ANADIG_PLL_ENET_DIV_SELECT_OFFSET);
3303         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
3304
3305         return 0;
3306 }
3307
3308 static unsigned long _clk_enet_get_rate(struct clk *clk)
3309 {
3310         unsigned int div;
3311
3312         div = (__raw_readl(PLL8_ENET_BASE_ADDR))
3313                 & ANADIG_PLL_ENET_DIV_SELECT_MASK;
3314
3315         return 500000000 / (div + 1);
3316 }
3317
3318 static struct clk enet_clk[] = {
3319         {
3320         __INIT_CLK_DEBUG(enet_clk)
3321          .id = 0,
3322          .parent = &pll8_enet_main_clk,
3323          .enable_reg = MXC_CCM_CCGR1,
3324          .enable_shift = MXC_CCM_CCGRx_CG5_OFFSET,
3325          .enable = _clk_enet_enable,
3326          .disable = _clk_enet_disable,
3327          .set_rate = _clk_enet_set_rate,
3328          .get_rate = _clk_enet_get_rate,
3329         .secondary = &enet_clk[1],
3330         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
3331         },
3332         {
3333         .parent = &mmdc_ch0_axi_clk[0],
3334         .secondary = &mx6per1_clk,
3335         },
3336 };
3337
3338 static struct clk ecspi_clk[] = {
3339         {
3340         __INIT_CLK_DEBUG(ecspi0_clk)
3341         .id = 0,
3342         .parent = &pll3_60M,
3343         .secondary = &spba_clk,
3344         .enable_reg = MXC_CCM_CCGR1,
3345         .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET,
3346         .enable = _clk_enable,
3347         .disable = _clk_disable,
3348         },
3349         {
3350         __INIT_CLK_DEBUG(ecspi1_clk)
3351         .id = 1,
3352         .parent = &pll3_60M,
3353         .secondary = &spba_clk,
3354         .enable_reg = MXC_CCM_CCGR1,
3355         .enable_shift = MXC_CCM_CCGRx_CG1_OFFSET,
3356         .enable = _clk_enable,
3357         .disable = _clk_disable,
3358         },
3359         {
3360         __INIT_CLK_DEBUG(ecspi2_clk)
3361         .id = 2,
3362         .parent = &pll3_60M,
3363         .secondary = &spba_clk,
3364         .enable_reg = MXC_CCM_CCGR1,
3365         .enable_shift = MXC_CCM_CCGRx_CG2_OFFSET,
3366         .enable = _clk_enable,
3367         .disable = _clk_disable,
3368         },
3369         {
3370         __INIT_CLK_DEBUG(ecspi3_clk)
3371         .id = 3,
3372         .parent = &pll3_60M,
3373         .secondary = &spba_clk,
3374         .enable_reg = MXC_CCM_CCGR1,
3375         .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET,
3376         .enable = _clk_enable,
3377         .disable = _clk_disable,
3378         },
3379         {
3380         __INIT_CLK_DEBUG(ecspi4_clk)
3381         .id = 4,
3382         .parent = &pll3_60M,
3383         .secondary = &spba_clk,
3384         .enable_reg = MXC_CCM_CCGR1,
3385         .enable_shift = MXC_CCM_CCGRx_CG4_OFFSET,
3386         .enable = _clk_enable,
3387         .disable = _clk_disable,
3388         },
3389 };
3390
3391 static unsigned long _clk_emi_slow_round_rate(struct clk *clk,
3392                                                 unsigned long rate)
3393 {
3394         u32 div;
3395         u32 parent_rate = clk_get_rate(clk->parent);
3396
3397         div = parent_rate / rate;
3398
3399         /* Make sure rate is not greater than the maximum value for the clock.
3400          * Also prevent a div of 0.
3401          */
3402         if (div == 0)
3403                 div++;
3404
3405         if (div > 8)
3406                 div = 8;
3407
3408         return parent_rate / div;
3409 }
3410
3411 static int _clk_emi_slow_set_parent(struct clk *clk, struct clk *parent)
3412 {
3413         int mux;
3414         u32 reg = __raw_readl(MXC_CCM_CSCMR1)
3415                 & ~MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK;
3416
3417         mux = _get_mux6(parent, &axi_clk, &pll3_usb_otg_main_clk,
3418                                 &pll2_pfd_400M, &pll2_pfd_352M, NULL, NULL);
3419         reg |= (mux << MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET);
3420         __raw_writel(reg, MXC_CCM_CSCMR1);
3421
3422         return 0;
3423 }
3424
3425 static unsigned long _clk_emi_slow_get_rate(struct clk *clk)
3426 {
3427         u32 reg, div;
3428
3429         reg = __raw_readl(MXC_CCM_CSCMR1);
3430         div = ((reg & MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK) >>
3431                         MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET) + 1;
3432
3433         return clk_get_rate(clk->parent) / div;
3434 }
3435
3436 static int _clk_emi_slow_set_rate(struct clk *clk, unsigned long rate)
3437 {
3438         u32 reg, div;
3439         u32 parent_rate = clk_get_rate(clk->parent);
3440
3441         div = parent_rate / rate;
3442         if (div == 0)
3443                 div++;
3444         if (((parent_rate / div) != rate) || (div > 8))
3445                 return -EINVAL;
3446
3447         reg = __raw_readl(MXC_CCM_CSCMR1);
3448         reg &= ~MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK;
3449         reg |= (div - 1) << MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET;
3450         __raw_writel(reg, MXC_CCM_CSCMR1);
3451
3452         return 0;
3453 }
3454
3455 static struct clk emi_slow_clk = {
3456         __INIT_CLK_DEBUG(emi_slow_clk)
3457          .id = 0,
3458          .parent = &axi_clk,
3459          .enable_reg = MXC_CCM_CCGR6,
3460          .enable_shift = MXC_CCM_CCGRx_CG5_OFFSET,
3461          .enable = _clk_enable,
3462          .disable = _clk_disable,
3463          .set_rate = _clk_emi_slow_set_rate,
3464          .get_rate = _clk_emi_slow_get_rate,
3465          .round_rate = _clk_emi_slow_round_rate,
3466          .set_parent = _clk_emi_slow_set_parent,
3467 };
3468
3469 static unsigned long _clk_emi_round_rate(struct clk *clk,
3470                                                 unsigned long rate)
3471 {
3472         u32 div;
3473         u32 parent_rate = clk_get_rate(clk->parent);
3474
3475         div = parent_rate / rate;
3476
3477         /* Make sure rate is not greater than the maximum value for the clock.
3478          * Also prevent a div of 0.
3479          */
3480         if (div == 0)
3481                 div++;
3482
3483         if (div > 8)
3484                 div = 8;
3485
3486         return parent_rate / div;
3487 }
3488
3489 static int _clk_emi_set_parent(struct clk *clk, struct clk *parent)
3490 {
3491         int mux;
3492         u32 reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_ACLK_EMI_MASK;
3493
3494         mux = _get_mux6(parent, &axi_clk, &pll3_usb_otg_main_clk,
3495                         &pll2_pfd_400M, &pll2_pfd_352M, NULL, NULL);
3496         reg |= (mux << MXC_CCM_CSCMR1_ACLK_EMI_OFFSET);
3497         __raw_writel(reg, MXC_CCM_CSCMR1);
3498
3499         return 0;
3500 }
3501
3502 static unsigned long _clk_emi_get_rate(struct clk *clk)
3503 {
3504         u32 reg, div;
3505
3506         reg = __raw_readl(MXC_CCM_CSCMR1);
3507         div = ((reg & MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK) >>
3508                         MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET) + 1;
3509
3510         return clk_get_rate(clk->parent) / div;
3511 }
3512
3513 static int _clk_emi_set_rate(struct clk *clk, unsigned long rate)
3514 {
3515         u32 reg, div;
3516         u32 parent_rate = clk_get_rate(clk->parent);
3517
3518         div = parent_rate / rate;
3519         if (div == 0)
3520                 div++;
3521         if (((parent_rate / div) != rate) || (div > 8))
3522                 return -EINVAL;
3523
3524         reg = __raw_readl(MXC_CCM_CSCMR1);
3525         reg &= ~MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK;
3526         reg |= (div - 1) << MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET;
3527         __raw_writel(reg, MXC_CCM_CSCMR1);
3528
3529         return 0;
3530 }
3531
3532 static struct clk emi_clk = {
3533         __INIT_CLK_DEBUG(emi_clk)
3534          .id = 0,
3535          .parent = &axi_clk,
3536          .set_rate = _clk_emi_set_rate,
3537          .get_rate = _clk_emi_get_rate,
3538          .round_rate = _clk_emi_round_rate,
3539          .set_parent = _clk_emi_set_parent,
3540 };
3541
3542 static unsigned long _clk_enfc_round_rate(struct clk *clk,
3543                                                 unsigned long rate)
3544 {
3545         u32 pre, post;
3546         u32 parent_rate = clk_get_rate(clk->parent);
3547         u32 div = parent_rate / rate;
3548
3549         if (parent_rate % rate)
3550                 div++;
3551
3552         __calc_pre_post_dividers(1 << 6, div, &pre, &post);
3553
3554         return parent_rate / (pre * post);
3555 }
3556
3557 static int _clk_enfc_set_parent(struct clk *clk, struct clk *parent)
3558 {
3559         u32 reg, mux;
3560
3561         reg = __raw_readl(MXC_CCM_CS2CDR)
3562                 & ~MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK;
3563
3564         mux = _get_mux6(parent, &pll2_pfd_352M,
3565                 &pll2_528_bus_main_clk, &pll3_usb_otg_main_clk,
3566                 &pll2_pfd_400M, NULL, NULL);
3567         reg |= mux << MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET;
3568
3569         __raw_writel(reg, MXC_CCM_CS2CDR);
3570
3571         return 0;
3572 }
3573
3574 static unsigned long _clk_enfc_get_rate(struct clk *clk)
3575 {
3576         u32 reg, pred, podf;
3577
3578         reg = __raw_readl(MXC_CCM_CS2CDR);
3579
3580         pred = ((reg & MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK)
3581                 >> MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET) + 1;
3582         podf = ((reg & MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK)
3583                 >> MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET) + 1;
3584
3585         return clk_get_rate(clk->parent) / (pred * podf);
3586 }
3587
3588 static int _clk_enfc_set_rate(struct clk *clk, unsigned long rate)
3589 {
3590         u32 reg, div, pre, post;
3591         u32 parent_rate = clk_get_rate(clk->parent);
3592
3593         div = parent_rate / rate;
3594         if (div == 0)
3595                 div++;
3596         if (((parent_rate / div) != rate) || div > 512)
3597                 return -EINVAL;
3598
3599         __calc_pre_post_dividers(1 << 6, div, &pre, &post);
3600
3601         reg = __raw_readl(MXC_CCM_CS2CDR);
3602         reg &= ~(MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK|
3603                  MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK);
3604         reg |= (post - 1) << MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET;
3605         reg |= (pre - 1) << MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET;
3606
3607         __raw_writel(reg, MXC_CCM_CS2CDR);
3608
3609         return 0;
3610 }
3611
3612 static struct clk enfc_clk = {
3613         __INIT_CLK_DEBUG(enfc_clk)
3614          .id = 0,
3615          .parent = &pll2_pfd_352M,
3616          .enable_reg = MXC_CCM_CCGR2,
3617          .enable_shift = MXC_CCM_CCGRx_CG7_OFFSET,
3618          .enable = _clk_enable,
3619          .disable = _clk_disable,
3620          .set_rate = _clk_enfc_set_rate,
3621          .get_rate = _clk_enfc_get_rate,
3622          .round_rate = _clk_enfc_round_rate,
3623          .set_parent = _clk_enfc_set_parent,
3624 };
3625
3626 static unsigned long _clk_uart_round_rate(struct clk *clk,
3627                                                 unsigned long rate)
3628 {
3629         u32 div;
3630         u32 parent_rate = clk_get_rate(clk->parent);
3631
3632         div = parent_rate / rate;
3633
3634         /* Make sure rate is not greater than the maximum value for the clock.
3635          * Also prevent a div of 0.
3636          */
3637         if (div == 0)
3638                 div++;
3639
3640         if (div > 64)
3641                 div = 64;
3642
3643         return parent_rate / div;
3644 }
3645
3646 static int _clk_uart_set_rate(struct clk *clk, unsigned long rate)
3647 {
3648         u32 reg, div;
3649         u32 parent_rate = clk_get_rate(clk->parent);
3650
3651         div = parent_rate / rate;
3652         if (div == 0)
3653                 div++;
3654         if (((parent_rate / div) != rate) || (div > 64))
3655                 return -EINVAL;
3656
3657         reg = __raw_readl(MXC_CCM_CSCDR1) & MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
3658         reg |= ((div - 1) << MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET);
3659
3660         __raw_writel(reg, MXC_CCM_CSCDR1);
3661
3662         return 0;
3663 }
3664
3665 static unsigned long _clk_uart_get_rate(struct clk *clk)
3666 {
3667         u32 reg, div;
3668         unsigned long val;
3669
3670         reg = __raw_readl(MXC_CCM_CSCDR1) & MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
3671         div = (reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET) + 1;
3672         val = clk_get_rate(clk->parent) / div;
3673
3674         return val;
3675 }
3676
3677 static struct clk uart_clk[] = {
3678         {
3679         __INIT_CLK_DEBUG(uart_clk)
3680          .id = 0,
3681          .parent = &pll3_80M,
3682          .enable_reg = MXC_CCM_CCGR5,
3683          .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET,
3684          .enable = _clk_enable,
3685          .disable = _clk_disable,
3686          .secondary = &uart_clk[1],
3687          .set_rate = _clk_uart_set_rate,
3688          .get_rate = _clk_uart_get_rate,
3689          .round_rate = _clk_uart_round_rate,
3690         },
3691         {
3692         __INIT_CLK_DEBUG(uart_serial_clk)
3693          .id = 1,
3694          .enable_reg = MXC_CCM_CCGR5,
3695          .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
3696          .enable = _clk_enable,
3697          .disable = _clk_disable,
3698         },
3699 };
3700
3701 static unsigned long _clk_hsi_tx_round_rate(struct clk *clk,
3702                                                 unsigned long rate)
3703 {
3704         u32 div;
3705         u32 parent_rate = clk_get_rate(clk->parent);
3706
3707         div = parent_rate / rate;
3708
3709         /* Make sure rate is not greater than the maximum value for the clock.
3710          * Also prevent a div of 0.
3711          */
3712         if (div == 0)
3713                 div++;
3714
3715         if (div > 8)
3716                 div = 8;
3717
3718         return parent_rate / div;
3719 }
3720
3721 static int _clk_hsi_tx_set_parent(struct clk *clk, struct clk *parent)
3722 {
3723         u32 reg = __raw_readl(MXC_CCM_CDCDR) & ~MXC_CCM_CDCDR_HSI_TX_CLK_SEL;
3724
3725         if (parent == &pll2_pfd_400M)
3726                 reg |= (MXC_CCM_CDCDR_HSI_TX_CLK_SEL);
3727
3728         __raw_writel(reg, MXC_CCM_CDCDR);
3729
3730         return 0;
3731 }
3732
3733 static unsigned long _clk_hsi_tx_get_rate(struct clk *clk)
3734 {
3735         u32 reg, div;
3736
3737         reg = __raw_readl(MXC_CCM_CDCDR);
3738         div = ((reg & MXC_CCM_CDCDR_HSI_TX_PODF_MASK) >>
3739                         MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET) + 1;
3740
3741         return clk_get_rate(clk->parent) / div;
3742 }
3743
3744 static int _clk_hsi_tx_set_rate(struct clk *clk, unsigned long rate)
3745 {
3746         u32 reg, div;
3747         u32 parent_rate = clk_get_rate(clk->parent);
3748
3749         div = parent_rate / rate;
3750         if (div == 0)
3751                 div++;
3752         if (((parent_rate / div) != rate) || (div > 8))
3753                 return -EINVAL;
3754
3755         reg = __raw_readl(MXC_CCM_CDCDR);
3756         reg &= ~MXC_CCM_CDCDR_HSI_TX_PODF_MASK;
3757         reg |= (div - 1) << MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET;
3758         __raw_writel(reg, MXC_CCM_CDCDR);
3759
3760         return 0;
3761 }
3762
3763 static struct clk hsi_tx_clk[] = {
3764         {
3765          __INIT_CLK_DEBUG(hsi_tx_clk)
3766         .id = 0,
3767          .parent = &pll2_pfd_400M,
3768         .enable_reg = MXC_CCM_CCGR3,
3769         .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET,
3770         .enable = _clk_enable,
3771         .disable = _clk_disable,
3772         .set_parent = _clk_hsi_tx_set_parent,
3773         .round_rate = _clk_hsi_tx_round_rate,
3774         .set_rate = _clk_hsi_tx_set_rate,
3775         .get_rate = _clk_hsi_tx_get_rate,
3776          .secondary = &hsi_tx_clk[1],
3777         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
3778         },
3779         {
3780         .parent = &mx6per1_clk,
3781         .secondary = &mx6per2_clk,
3782          },
3783 };
3784
3785 static struct clk hdmi_clk[] = {
3786         {
3787          __INIT_CLK_DEBUG(hdmi_isfr_clk)
3788         .id = 0,
3789         .parent = &pll3_pfd_540M,
3790         .enable_reg = MXC_CCM_CCGR2,
3791         .enable_shift = MXC_CCM_CCGRx_CG2_OFFSET,
3792         .enable = _clk_enable,
3793         .disable = _clk_disable,
3794         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
3795         },
3796         {
3797          __INIT_CLK_DEBUG(hdmi_iahb_clk)
3798         .id = 1,
3799          .parent = &ahb_clk,
3800         .enable_reg = MXC_CCM_CCGR2,
3801         .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET,
3802         .enable = _clk_enable,
3803         .disable = _clk_disable,
3804         },
3805 };
3806
3807 static struct clk caam_clk[] = {
3808         {
3809          __INIT_CLK_DEBUG(caam_mem_clk)
3810         .id = 0,
3811         .enable_reg = MXC_CCM_CCGR0,
3812         .enable_shift = MXC_CCM_CCGRx_CG4_OFFSET,
3813         .enable = _clk_enable,
3814         .disable = _clk_disable,
3815         .secondary = &caam_clk[1],
3816         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
3817         },
3818         {
3819          __INIT_CLK_DEBUG(caam_aclk_clk)
3820         .id = 1,
3821         .enable_reg = MXC_CCM_CCGR0,
3822         .enable_shift = MXC_CCM_CCGRx_CG5_OFFSET,
3823         .enable = _clk_enable,
3824         .disable = _clk_disable,
3825         .secondary = &caam_clk[2],
3826         },
3827         {
3828          __INIT_CLK_DEBUG(caam_ipg_clk)
3829         .id = 2,
3830         .enable_reg = MXC_CCM_CCGR0,
3831         .enable_shift = MXC_CCM_CCGRx_CG4_OFFSET,
3832         .enable = _clk_enable,
3833         .disable = _clk_disable,
3834         .parent = &mmdc_ch0_axi_clk[0],
3835         .secondary = &mx6per1_clk,
3836         },
3837 };
3838
3839 static int _clk_asrc_serial_set_parent(struct clk *clk, struct clk *parent)
3840 {
3841         u32 reg, mux;
3842
3843         reg = __raw_readl(MXC_CCM_CDCDR) & ~MXC_CCM_CDCDR_SPDIF1_CLK_SEL_MASK;
3844
3845         mux = _get_mux6(parent, &pll4_audio_main_clk, &pll3_pfd_508M,
3846                         &pll3_pfd_454M, &pll3_sw_clk, NULL, NULL);
3847         reg |= mux << MXC_CCM_CDCDR_SPDIF1_CLK_SEL_OFFSET;
3848
3849         __raw_writel(reg, MXC_CCM_CDCDR);
3850
3851         return 0;
3852 }
3853
3854 static unsigned long _clk_asrc_serial_get_rate(struct clk *clk)
3855 {
3856         u32 reg, pred, podf;
3857
3858         reg = __raw_readl(MXC_CCM_CDCDR);
3859
3860         pred = ((reg & MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK)
3861                 >> MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET) + 1;
3862         podf = ((reg & MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK)
3863                 >> MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET) + 1;
3864
3865         return clk_get_rate(clk->parent) / (pred * podf);
3866 }
3867
3868 static int _clk_asrc_serial_set_rate(struct clk *clk, unsigned long rate)
3869 {
3870         u32 reg, div, pre, post;
3871         u32 parent_rate = clk_get_rate(clk->parent);
3872
3873         div = parent_rate / rate;
3874         if (div == 0)
3875                 div++;
3876         if (((parent_rate / div) != rate) || div > 64)
3877                 return -EINVAL;
3878
3879         __calc_pre_post_dividers(1 << 3, div, &pre, &post);
3880
3881         reg = __raw_readl(MXC_CCM_CDCDR);
3882         reg &= ~(MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK|
3883                  MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK);
3884         reg |= (post - 1) << MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET;
3885         reg |= (pre - 1) << MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET;
3886
3887         __raw_writel(reg, MXC_CCM_CDCDR);
3888
3889         return 0;
3890 }
3891
3892 static unsigned long _clk_asrc_serial_round_rate(struct clk *clk,
3893                                                 unsigned long rate)
3894 {
3895         u32 pre, post;
3896         u32 parent_rate = clk_get_rate(clk->parent);
3897         u32 div = parent_rate / rate;
3898
3899         if (parent_rate % rate)
3900                 div++;
3901
3902         __calc_pre_post_dividers(1 << 3, div, &pre, &post);
3903
3904         return parent_rate / (pre * post);
3905 }
3906
3907 static struct clk asrc_clk[] = {
3908         {
3909         __INIT_CLK_DEBUG(asrc_clk)
3910         .id = 0,
3911         .parent = &pll4_audio_main_clk,
3912         .enable_reg = MXC_CCM_CCGR0,
3913         .enable_shift = MXC_CCM_CCGRx_CG3_OFFSET,
3914         .enable = _clk_enable,
3915         .disable = _clk_disable,
3916         .secondary = &spba_clk,
3917         },
3918         {
3919         /*In the MX6 spec, asrc_serial_clk is listed as SPDIF1 clk
3920          * This clock can never be gated and does  not have any
3921          * CCGR bits associated with it.
3922          */
3923         __INIT_CLK_DEBUG(asrc_serial_clk)
3924         .id = 1,
3925         .parent = &pll3_sw_clk,
3926          .set_rate = _clk_asrc_serial_set_rate,
3927          .get_rate = _clk_asrc_serial_get_rate,
3928          .set_parent = _clk_asrc_serial_set_parent,
3929          .round_rate = _clk_asrc_serial_round_rate,
3930         },
3931 };
3932
3933 static struct clk apbh_dma_clk = {
3934         __INIT_CLK_DEBUG(apbh_dma_clk)
3935         .parent = &usdhc3_clk,
3936         .secondary = &mx6per1_clk,
3937         .enable = _clk_enable,
3938         .disable = _clk_disable_inwait,
3939         .enable_reg = MXC_CCM_CCGR0,
3940         .enable_shift = MXC_CCM_CCGRx_CG2_OFFSET,
3941 };
3942
3943 static struct clk aips_tz2_clk = {
3944         __INIT_CLK_DEBUG(aips_tz2_clk)
3945         .parent = &ahb_clk,
3946         .enable_reg = MXC_CCM_CCGR0,
3947         .enable_shift = MXC_CCM_CCGRx_CG1_OFFSET,
3948         .enable = _clk_enable,
3949         .disable = _clk_disable_inwait,
3950 };
3951
3952 static struct clk aips_tz1_clk = {
3953         __INIT_CLK_DEBUG(aips_tz1_clk)
3954         .parent = &ahb_clk,
3955         .enable_reg = MXC_CCM_CCGR0,
3956         .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET,
3957         .enable = _clk_enable,
3958         .disable = _clk_disable_inwait,
3959 };
3960
3961
3962 static struct clk openvg_axi_clk = {
3963         __INIT_CLK_DEBUG(openvg_axi_clk)
3964         .parent = &gpu2d_axi_clk,
3965         .enable = _clk_enable,
3966         .enable_reg = MXC_CCM_CCGR3,
3967         .enable_shift = MXC_CCM_CCGRx_CG15_OFFSET,
3968         .disable = _clk_disable,
3969         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
3970 };
3971
3972 static unsigned long _clk_gpu3d_core_round_rate(struct clk *clk,
3973                                                 unsigned long rate)
3974 {
3975         u32 div;
3976         u32 parent_rate = clk_get_rate(clk->parent);
3977
3978         div = parent_rate / rate;
3979
3980         /* Make sure rate is not greater than the maximum value for the clock.
3981          * Also prevent a div of 0.
3982          */
3983         if (div == 0)
3984                 div++;
3985
3986         if (div > 8)
3987                 div = 8;
3988
3989         return parent_rate / div;
3990 }
3991
3992 static int _clk_gpu3d_core_set_parent(struct clk *clk, struct clk *parent)
3993 {
3994         int mux;
3995         u32 reg = __raw_readl(MXC_CCM_CBCMR)
3996                 & ~MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK;
3997
3998         mux = _get_mux6(parent, &mmdc_ch0_axi_clk[0],
3999                 &pll3_usb_otg_main_clk,
4000                 &pll2_pfd_594M, &pll2_pfd_400M, NULL, NULL);
4001         reg |= (mux << MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET);
4002         __raw_writel(reg, MXC_CCM_CBCMR);
4003
4004         return 0;
4005 }
4006
4007 static unsigned long _clk_gpu3d_core_get_rate(struct clk *clk)
4008 {
4009         u32 reg, div;
4010
4011         reg = __raw_readl(MXC_CCM_CBCMR);
4012         div = ((reg & MXC_CCM_CBCMR_GPU3D_CORE_PODF_MASK) >>
4013                         MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET) + 1;
4014
4015         return clk_get_rate(clk->parent) / div;
4016 }
4017
4018 static int _clk_gpu3d_core_set_rate(struct clk *clk, unsigned long rate)
4019 {
4020         u32 reg, div;
4021         u32 parent_rate = clk_get_rate(clk->parent);
4022
4023         div = parent_rate / rate;
4024         if (div == 0)
4025                 div++;
4026         if (div > 8)
4027                 div = 8;
4028
4029         reg = __raw_readl(MXC_CCM_CBCMR);
4030         reg &= ~MXC_CCM_CBCMR_GPU3D_CORE_PODF_MASK;
4031         reg |= (div - 1) << MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET;
4032         __raw_writel(reg, MXC_CCM_CBCMR);
4033
4034         return 0;
4035 }
4036
4037 static struct clk gpu3d_core_clk[] = {
4038         {
4039         __INIT_CLK_DEBUG(gpu3d_core_clk)
4040         .parent = &pll2_pfd_594M,
4041         .enable = _clk_enable,
4042         .enable_reg = MXC_CCM_CCGR1,
4043         .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
4044         .disable = _clk_disable,
4045         .set_parent = _clk_gpu3d_core_set_parent,
4046         .set_rate = _clk_gpu3d_core_set_rate,
4047         .get_rate = _clk_gpu3d_core_get_rate,
4048         .round_rate = _clk_gpu3d_core_round_rate,
4049         .secondary = &gpu3d_core_clk[1],
4050         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
4051         },
4052         {
4053         .parent = &gpu3d_axi_clk,
4054         .secondary = &mx6fast1_clk,
4055         },
4056 };
4057
4058 static unsigned long _clk_gpu2d_core_round_rate(struct clk *clk,
4059                                                 unsigned long rate)
4060 {
4061         u32 div;
4062         u32 parent_rate = clk_get_rate(clk->parent);
4063
4064         div = parent_rate / rate;
4065
4066         /* Make sure rate is not greater than the maximum value for the clock.
4067          * Also prevent a div of 0.
4068          */
4069         if (div == 0)
4070                 div++;
4071
4072         if (div > 8)
4073                 div = 8;
4074
4075         return parent_rate / div;
4076 }
4077
4078 static int _clk_gpu2d_core_set_parent(struct clk *clk, struct clk *parent)
4079 {
4080         int mux;
4081         u32 reg = __raw_readl(MXC_CCM_CBCMR) &
4082                                 ~MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK;
4083
4084         mux = _get_mux6(parent, &axi_clk, &pll3_usb_otg_main_clk,
4085                 &pll2_pfd_352M, &pll2_pfd_400M, NULL, NULL);
4086         reg |= (mux << MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET);
4087         __raw_writel(reg, MXC_CCM_CBCMR);
4088
4089         return 0;
4090 }
4091
4092 static unsigned long _clk_gpu2d_core_get_rate(struct clk *clk)
4093 {
4094         u32 reg, div;
4095
4096         reg = __raw_readl(MXC_CCM_CBCMR);
4097         div = ((reg & MXC_CCM_CBCMR_GPU2D_CORE_PODF_MASK) >>
4098                         MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET) + 1;
4099
4100         return clk_get_rate(clk->parent) / div;
4101 }
4102
4103 static int _clk_gpu2d_core_set_rate(struct clk *clk, unsigned long rate)
4104 {
4105         u32 reg, div;
4106         u32 parent_rate = clk_get_rate(clk->parent);
4107
4108         div = parent_rate / rate;
4109         if (div == 0)
4110                 div++;
4111         if (((parent_rate / div) != rate) || (div > 8))
4112                 return -EINVAL;
4113
4114         reg = __raw_readl(MXC_CCM_CBCMR);
4115         reg &= ~MXC_CCM_CBCMR_GPU3D_CORE_PODF_MASK;
4116         reg |= (div - 1) << MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET;
4117         __raw_writel(reg, MXC_CCM_CBCMR);
4118
4119         return 0;
4120 }
4121 static struct clk gpu2d_core_clk[] = {
4122         {
4123         __INIT_CLK_DEBUG(gpu2d_core_clk)
4124         .parent = &pll2_pfd_352M,
4125         .enable = _clk_enable,
4126         .enable_reg = MXC_CCM_CCGR1,
4127         .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET,
4128         .disable = _clk_disable,
4129         .set_parent = _clk_gpu2d_core_set_parent,
4130         .set_rate = _clk_gpu2d_core_set_rate,
4131         .get_rate = _clk_gpu2d_core_get_rate,
4132         .round_rate = _clk_gpu2d_core_round_rate,
4133         .secondary = &gpu2d_core_clk[0],
4134         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
4135         },
4136         {
4137         .parent = &gpu2d_axi_clk,
4138         .secondary = &mx6fast1_clk,
4139         },
4140 };
4141
4142 static unsigned long _clk_gpu3d_shader_round_rate(struct clk *clk,
4143                                                 unsigned long rate)
4144 {
4145         u32 div;
4146         u32 parent_rate = clk_get_rate(clk->parent);
4147
4148         div = parent_rate / rate;
4149
4150         /* Make sure rate is not greater than the maximum value for the clock.
4151          * Also prevent a div of 0.
4152          */
4153         if (div == 0)
4154                 div++;
4155
4156         if (div > 8)
4157                 div = 8;
4158
4159         return parent_rate / div;
4160 }
4161
4162 static int _clk_gpu3d_shader_set_parent(struct clk *clk, struct clk *parent)
4163 {
4164         int mux;
4165         u32 reg = __raw_readl(MXC_CCM_CBCMR)
4166                 & ~MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_MASK;
4167
4168         mux = _get_mux6(parent, &mmdc_ch0_axi_clk[0],
4169                 &pll3_usb_otg_main_clk,
4170                 &pll2_pfd_594M, &pll3_pfd_720M, NULL, NULL);
4171         reg |= (mux << MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET);
4172         __raw_writel(reg, MXC_CCM_CBCMR);
4173
4174         return 0;
4175 }
4176
4177 static unsigned long _clk_gpu3d_shader_get_rate(struct clk *clk)
4178 {
4179         u32 reg, div;
4180
4181         reg = __raw_readl(MXC_CCM_CBCMR);
4182         div = ((reg & MXC_CCM_CBCMR_GPU3D_SHADER_PODF_MASK) >>
4183                         MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET) + 1;
4184
4185         return clk_get_rate(clk->parent) / div;
4186 }
4187
4188 static int _clk_gpu3d_shader_set_rate(struct clk *clk, unsigned long rate)
4189 {
4190         u32 reg, div;
4191         u32 parent_rate = clk_get_rate(clk->parent);
4192
4193         div = parent_rate / rate;
4194         if (div == 0)
4195                 div++;
4196         if (div > 8)
4197                 div = 8;
4198
4199         reg = __raw_readl(MXC_CCM_CBCMR);
4200         reg &= ~MXC_CCM_CBCMR_GPU3D_SHADER_PODF_MASK;
4201         reg |= (div - 1) << MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET;
4202         __raw_writel(reg, MXC_CCM_CBCMR);
4203
4204         return 0;
4205 }
4206
4207
4208 static struct clk gpu3d_shader_clk = {
4209         __INIT_CLK_DEBUG(gpu3d_shader_clk)
4210         .parent = &pll3_pfd_720M,
4211         .secondary = &mmdc_ch0_axi_clk[0],
4212         .enable = _clk_enable,
4213         .enable_reg = MXC_CCM_CCGR1,
4214         .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
4215         .disable = _clk_disable,
4216         .set_parent = _clk_gpu3d_shader_set_parent,
4217         .set_rate = _clk_gpu3d_shader_set_rate,
4218         .get_rate = _clk_gpu3d_shader_get_rate,
4219         .round_rate = _clk_gpu3d_shader_round_rate,
4220         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
4221 };
4222
4223 /* set the parent by the ipcg table */
4224 static struct clk gpmi_nfc_clk[] = {
4225         {       /* gpmi_io_clk */
4226         __INIT_CLK_DEBUG(gpmi_io_clk)
4227         .parent = &enfc_clk,
4228         .secondary = &gpmi_nfc_clk[1],
4229         .enable = _clk_enable,
4230         .enable_reg = MXC_CCM_CCGR4,
4231         .enable_shift = MXC_CCM_CCGRx_CG14_OFFSET,
4232         .disable = _clk_disable,
4233         },
4234         {       /* gpmi_apb_clk */
4235         __INIT_CLK_DEBUG(gpmi_apb_clk)
4236         .parent = &usdhc3_clk,
4237         .secondary = &gpmi_nfc_clk[2],
4238         .enable = _clk_enable,
4239         .enable_reg = MXC_CCM_CCGR4,
4240         .enable_shift = MXC_CCM_CCGRx_CG15_OFFSET,
4241         .disable = _clk_disable,
4242         },
4243         {       /* bch_clk */
4244         __INIT_CLK_DEBUG(gpmi_bch_clk)
4245         .parent = &usdhc4_clk,
4246         .secondary = &gpmi_nfc_clk[3],
4247         .enable = _clk_enable,
4248         .enable_reg = MXC_CCM_CCGR4,
4249         .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
4250         .disable = _clk_disable,
4251         },
4252         {       /* bch_apb_clk */
4253         __INIT_CLK_DEBUG(gpmi_bch_apb_clk)
4254         .parent = &usdhc3_clk,
4255         .secondary = &gpmi_nfc_clk[4],
4256         .enable = _clk_enable,
4257         .enable_reg = MXC_CCM_CCGR4,
4258         .enable_shift = MXC_CCM_CCGRx_CG12_OFFSET,
4259         .disable = _clk_disable,
4260         },
4261         {       /* bch relative clk */
4262         __INIT_CLK_DEBUG(pl301_mx6qperl_bch)
4263         .parent = &mx6per1_clk,
4264         .secondary = &mmdc_ch0_axi_clk[0],
4265         },
4266 };
4267
4268 static struct clk pwm_clk[] = {
4269         {
4270         __INIT_CLK_DEBUG(pwm_clk_0)
4271          .parent = &ipg_perclk,
4272          .id = 0,
4273          .enable_reg = MXC_CCM_CCGR4,
4274          .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET,
4275          .enable = _clk_enable,
4276          .disable = _clk_disable,
4277          },
4278         {
4279         __INIT_CLK_DEBUG(pwm_clk_1)
4280          .parent = &ipg_perclk,
4281          .id = 1,
4282          .enable_reg = MXC_CCM_CCGR4,
4283          .enable_shift = MXC_CCM_CCGRx_CG9_OFFSET,
4284          .enable = _clk_enable,
4285          .disable = _clk_disable,
4286          },
4287         {
4288         __INIT_CLK_DEBUG(pwm_clk_2)
4289          .parent = &ipg_perclk,
4290          .id = 2,
4291          .enable_reg = MXC_CCM_CCGR4,
4292          .enable_shift = MXC_CCM_CCGRx_CG10_OFFSET,
4293          .enable = _clk_enable,
4294          .disable = _clk_disable,
4295          },
4296         {
4297         __INIT_CLK_DEBUG(pwm_clk_3)
4298          .parent = &ipg_perclk,
4299          .id = 3,
4300          .enable_reg = MXC_CCM_CCGR4,
4301          .enable_shift = MXC_CCM_CCGRx_CG11_OFFSET,
4302          .enable = _clk_enable,
4303          .disable = _clk_disable,
4304          },
4305 };
4306
4307 static int _clk_pcie_enable(struct clk *clk)
4308 {
4309         unsigned int reg;
4310
4311         /* Enable SATA ref clock */
4312         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
4313         reg |= ANADIG_PLL_ENET_EN_PCIE;
4314         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
4315
4316         _clk_enable(clk);
4317
4318         return 0;
4319 }
4320
4321 static void _clk_pcie_disable(struct clk *clk)
4322 {
4323         unsigned int reg;
4324
4325         _clk_disable(clk);
4326
4327         /* Disable SATA ref clock */
4328         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
4329         reg &= ~ANADIG_PLL_ENET_EN_PCIE;
4330         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
4331 }
4332
4333 static struct clk pcie_clk[] = {
4334         {
4335         __INIT_CLK_DEBUG(pcie_clk)
4336         .parent = &pcie_axi_clk,
4337         .enable = _clk_pcie_enable,
4338         .disable = _clk_pcie_disable,
4339         .enable_reg = MXC_CCM_CCGR4,
4340         .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET,
4341         .secondary = &pcie_clk[1],
4342         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
4343         },
4344         {
4345         .parent = &mmdc_ch0_axi_clk[0],
4346         .secondary = &mx6fast1_clk,
4347         },
4348 };
4349
4350 static int _clk_sata_enable(struct clk *clk)
4351 {
4352         unsigned int reg;
4353
4354         /* Clear Power Down and Enable PLLs */
4355         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
4356         reg &= ~ANADIG_PLL_ENET_POWER_DOWN;
4357         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
4358
4359         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
4360         reg |= ANADIG_PLL_ENET_EN;
4361         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
4362
4363         /* Waiting for the PLL is locked */
4364         if (!WAIT(ANADIG_PLL_ENET_LOCK & __raw_readl(PLL8_ENET_BASE_ADDR),
4365                                 SPIN_DELAY))
4366                 panic("pll8 lock failed\n");
4367
4368         /* Disable the bypass */
4369         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
4370         reg &= ~ANADIG_PLL_ENET_BYPASS;
4371         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
4372
4373         /* Enable SATA ref clock */
4374         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
4375         reg |= ANADIG_PLL_ENET_EN_SATA;
4376         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
4377
4378         _clk_enable(clk);
4379
4380         return 0;
4381 }
4382
4383 static void _clk_sata_disable(struct clk *clk)
4384 {
4385         unsigned int reg;
4386
4387         _clk_disable(clk);
4388
4389         /* Disable SATA ref clock */
4390         reg = __raw_readl(PLL8_ENET_BASE_ADDR);
4391         reg &= ~ANADIG_PLL_ENET_EN_SATA;
4392         __raw_writel(reg, PLL8_ENET_BASE_ADDR);
4393 }
4394
4395 static struct clk sata_clk[] = {
4396         {
4397         __INIT_CLK_DEBUG(sata_clk)
4398         .parent = &ipg_clk,
4399         .enable = _clk_sata_enable,
4400         .enable_reg = MXC_CCM_CCGR5,
4401         .enable_shift = MXC_CCM_CCGRx_CG2_OFFSET,
4402         .disable = _clk_sata_disable,
4403         .secondary = &sata_clk[1],
4404         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
4405         },
4406         {
4407         .parent = &mmdc_ch0_axi_clk[0],
4408         .secondary = &mx6per1_clk,
4409         }
4410 };
4411
4412 static struct clk usboh3_clk[] = {
4413         {
4414         __INIT_CLK_DEBUG(usboh3_clk)
4415         .parent = &ahb_clk,
4416         .enable = _clk_enable,
4417         .enable_reg = MXC_CCM_CCGR6,
4418         .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET,
4419         .disable = _clk_disable,
4420         .secondary = &usboh3_clk[1],
4421         .flags = AHB_HIGH_SET_POINT | CPU_FREQ_TRIG_UPDATE,
4422         },
4423         {
4424         .parent = &mmdc_ch0_axi_clk[0],
4425         .secondary = &mx6per1_clk,
4426         },
4427 };
4428
4429 static int _clk_enable1(struct clk *clk)
4430 {
4431         u32 reg;
4432         reg = __raw_readl(clk->enable_reg);
4433         reg |= 1 << clk->enable_shift;
4434         __raw_writel(reg, clk->enable_reg);
4435
4436         return 0;
4437 }
4438
4439 static void _clk_disable1(struct clk *clk)
4440 {
4441         u32 reg;
4442         reg = __raw_readl(clk->enable_reg);
4443         reg &= ~(1 << clk->enable_shift);
4444         __raw_writel(reg, clk->enable_reg);
4445 }
4446
4447 static int _clk_clko_set_parent(struct clk *clk, struct clk *parent)
4448 {
4449         u32 sel, reg;
4450
4451         if (parent == &pll3_usb_otg_main_clk)
4452                 sel = 0;
4453         else if (parent == &pll2_528_bus_main_clk)
4454                 sel = 1;
4455         else if (parent == &pll1_sys_main_clk)
4456                 sel = 2;
4457         else if (parent == &pll5_video_main_clk)
4458                 sel = 3;
4459         else if (parent == &axi_clk)
4460                 sel = 5;
4461         else if (parent == &enfc_clk)
4462                 sel = 6;
4463         else if (parent == &ipu1_di_clk[0])
4464                 sel = 7;
4465         else if (parent == &ipu1_di_clk[1])
4466                 sel = 8;
4467         else if (parent == &ipu2_di_clk[0])
4468                 sel = 9;
4469         else if (parent == &ipu2_di_clk[1])
4470                 sel = 10;
4471         else if (parent == &ahb_clk)
4472                 sel = 11;
4473         else if (parent == &ipg_clk)
4474                 sel = 12;
4475         else if (parent == &ipg_perclk)
4476                 sel = 13;
4477         else if (parent == &ckil_clk)
4478                 sel = 14;
4479         else if (parent == &pll4_audio_main_clk)
4480                 sel = 15;
4481         else
4482                 return -EINVAL;
4483
4484         reg = __raw_readl(MXC_CCM_CCOSR);
4485         reg &= ~MXC_CCM_CCOSR_CKOL_SEL_MASK;
4486         reg |= sel << MXC_CCM_CCOSR_CKOL_SEL_OFFSET;
4487         __raw_writel(reg, MXC_CCM_CCOSR);
4488         return 0;
4489 }
4490
4491 static unsigned long _clk_clko_get_rate(struct clk *clk)
4492 {
4493         u32 reg = __raw_readl(MXC_CCM_CCOSR);
4494         u32 div = ((reg & MXC_CCM_CCOSR_CKOL_DIV_MASK) >>
4495                         MXC_CCM_CCOSR_CKOL_DIV_OFFSET) + 1;
4496         return clk_get_rate(clk->parent) / div;
4497 }
4498
4499 static int _clk_clko_set_rate(struct clk *clk, unsigned long rate)
4500 {
4501         u32 reg;
4502         u32 parent_rate = clk_get_rate(clk->parent);
4503         u32 div = parent_rate / rate;
4504
4505         if (div == 0)
4506                 div++;
4507         if (((parent_rate / div) != rate) || (div > 8))
4508                 return -EINVAL;
4509
4510         reg = __raw_readl(MXC_CCM_CCOSR);
4511         reg &= ~MXC_CCM_CCOSR_CKOL_DIV_MASK;
4512         reg |= (div - 1) << MXC_CCM_CCOSR_CKOL_DIV_OFFSET;
4513         __raw_writel(reg, MXC_CCM_CCOSR);
4514         return 0;
4515 }
4516
4517 static unsigned long _clk_clko_round_rate(struct clk *clk,
4518                                                 unsigned long rate)
4519 {
4520         u32 parent_rate = clk_get_rate(clk->parent);
4521         u32 div = parent_rate / rate;
4522
4523         /* Make sure rate is not greater than the maximum value for the clock.
4524          * Also prevent a div of 0.
4525          */
4526         if (div == 0)
4527                 div++;
4528         if (div > 8)
4529                 div = 8;
4530         return parent_rate / div;
4531 }
4532
4533 static struct clk clko_clk = {
4534         __INIT_CLK_DEBUG(clko_clk)
4535         .parent = &pll2_528_bus_main_clk,
4536         .enable = _clk_enable1,
4537         .enable_reg = MXC_CCM_CCOSR,
4538         .enable_shift = MXC_CCM_CCOSR_CKOL_EN_OFFSET,
4539         .disable = _clk_disable1,
4540         .set_parent = _clk_clko_set_parent,
4541         .set_rate = _clk_clko_set_rate,
4542         .get_rate = _clk_clko_get_rate,
4543         .round_rate = _clk_clko_round_rate,
4544 };
4545
4546 static struct clk dummy_clk = {
4547         .id = 0,
4548 };
4549
4550 #define _REGISTER_CLOCK(d, n, c) \
4551         { \
4552                 .dev_id = d, \
4553                 .con_id = n, \
4554                 .clk = &c, \
4555         }
4556
4557
4558 static struct clk_lookup lookups[] = {
4559         _REGISTER_CLOCK(NULL, "osc", osc_clk),
4560         _REGISTER_CLOCK(NULL, "ckih", ckih_clk),
4561         _REGISTER_CLOCK(NULL, "ckih2", ckih2_clk),
4562         _REGISTER_CLOCK(NULL, "ckil", ckil_clk),
4563         _REGISTER_CLOCK(NULL, "pll1_main_clk", pll1_sys_main_clk),
4564         _REGISTER_CLOCK(NULL, "pll1_sw_clk", pll1_sw_clk),
4565         _REGISTER_CLOCK(NULL, "pll2", pll2_528_bus_main_clk),
4566         _REGISTER_CLOCK(NULL, "pll2_pfd_400M", pll2_pfd_400M),
4567         _REGISTER_CLOCK(NULL, "pll2_pfd_352M", pll2_pfd_352M),
4568         _REGISTER_CLOCK(NULL, "pll2_pfd_594M", pll2_pfd_594M),
4569         _REGISTER_CLOCK(NULL, "pll2_200M", pll2_200M),
4570         _REGISTER_CLOCK(NULL, "pll3_main_clk", pll3_usb_otg_main_clk),
4571         _REGISTER_CLOCK(NULL, "pll3_pfd_508M", pll3_pfd_508M),
4572         _REGISTER_CLOCK(NULL, "pll3_pfd_454M", pll3_pfd_454M),
4573         _REGISTER_CLOCK(NULL, "pll3_pfd_720M", pll3_pfd_720M),
4574         _REGISTER_CLOCK(NULL, "pll3_pfd_540M", pll3_pfd_540M),
4575         _REGISTER_CLOCK(NULL, "pll3_sw_clk", pll3_sw_clk),
4576         _REGISTER_CLOCK(NULL, "pll3_120M", pll3_120M),
4577         _REGISTER_CLOCK(NULL, "pll3_120M", pll3_80M),
4578         _REGISTER_CLOCK(NULL, "pll3_120M", pll3_60M),
4579         _REGISTER_CLOCK(NULL, "pll4", pll4_audio_main_clk),
4580         _REGISTER_CLOCK(NULL, "pll5", pll5_video_main_clk),
4581         _REGISTER_CLOCK(NULL, "pll4", pll6_MLB_main_clk),
4582         _REGISTER_CLOCK(NULL, "pll3", pll7_usb_host_main_clk),
4583         _REGISTER_CLOCK(NULL, "pll4", pll8_enet_main_clk),
4584         _REGISTER_CLOCK(NULL, "cpu_clk", cpu_clk),
4585         _REGISTER_CLOCK(NULL, "periph_clk", periph_clk),
4586         _REGISTER_CLOCK(NULL, "axi_clk", axi_clk),
4587         _REGISTER_CLOCK(NULL, "mmdc_ch0_axi", mmdc_ch0_axi_clk[0]),
4588         _REGISTER_CLOCK(NULL, "mmdc_ch1_axi", mmdc_ch1_axi_clk[0]),
4589         _REGISTER_CLOCK(NULL, "ahb", ahb_clk),
4590         _REGISTER_CLOCK(NULL, "ipg_clk", ipg_clk),
4591         _REGISTER_CLOCK(NULL, "ipg_perclk", ipg_perclk),
4592         _REGISTER_CLOCK(NULL, "spba", spba_clk),
4593         _REGISTER_CLOCK("imx-sdma", NULL, sdma_clk[0]),
4594         _REGISTER_CLOCK(NULL, "gpu2d_axi_clk", gpu2d_axi_clk),
4595         _REGISTER_CLOCK(NULL, "gpu3d_axi_clk", gpu3d_axi_clk),
4596         _REGISTER_CLOCK(NULL, "pcie_axi_clk", pcie_axi_clk),
4597         _REGISTER_CLOCK(NULL, "vdo_axi_clk", vdo_axi_clk),
4598         _REGISTER_CLOCK(NULL, "iim_clk", iim_clk),
4599         _REGISTER_CLOCK(NULL, "i2c_clk", i2c_clk[0]),
4600         _REGISTER_CLOCK("imx-i2c.1", NULL, i2c_clk[1]),
4601         _REGISTER_CLOCK("imx-i2c.2", NULL, i2c_clk[2]),
4602         _REGISTER_CLOCK(NULL, "vpu_clk", vpu_clk[0]),
4603         _REGISTER_CLOCK(NULL, "ipu1_clk", ipu1_clk),
4604         _REGISTER_CLOCK(NULL, "ipu2_clk", ipu2_clk),
4605         _REGISTER_CLOCK(NULL, "cko1_clk0", cko1_clk0),
4606         _REGISTER_CLOCK("sdhci-esdhc-imx.0", NULL, usdhc1_clk),
4607         _REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL, usdhc2_clk),
4608         _REGISTER_CLOCK("sdhci-esdhc-imx.2", NULL, usdhc3_clk),
4609         _REGISTER_CLOCK("sdhci-esdhc-imx.3", NULL, usdhc4_clk),
4610         _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk),
4611         _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk),
4612         _REGISTER_CLOCK("imx-ssi.2", NULL, ssi3_clk),
4613         _REGISTER_CLOCK(NULL, "ipu1_di0_clk", ipu1_di_clk[0]),
4614         _REGISTER_CLOCK(NULL, "ipu1_di1_clk", ipu1_di_clk[1]),
4615         _REGISTER_CLOCK(NULL, "ipu2_di0_clk", ipu2_di_clk[0]),
4616         _REGISTER_CLOCK(NULL, "ipu2_di1_clk", ipu2_di_clk[1]),
4617         _REGISTER_CLOCK("FlexCAN.0", "can_clk", can1_clk[0]),
4618         _REGISTER_CLOCK("FlexCAN.1", "can_clk", can2_clk[0]),
4619         _REGISTER_CLOCK(NULL, "ldb_di0_clk", ldb_di0_clk),
4620         _REGISTER_CLOCK(NULL, "ldb_di1_clk", ldb_di1_clk),
4621         _REGISTER_CLOCK("mxc_spdif.0", NULL, spdif0_clk[0]),
4622         _REGISTER_CLOCK(NULL, "esai_clk", esai_clk),
4623         _REGISTER_CLOCK("imx6q-ecspi.0", NULL, ecspi_clk[0]),
4624         _REGISTER_CLOCK("imx6q-ecspi.1", NULL, ecspi_clk[1]),
4625         _REGISTER_CLOCK("imx6q-ecspi.2", NULL, ecspi_clk[2]),
4626         _REGISTER_CLOCK("imx6q-ecspi.3", NULL, ecspi_clk[3]),
4627         _REGISTER_CLOCK("imx6q-ecspi.4", NULL, ecspi_clk[4]),
4628         _REGISTER_CLOCK(NULL, "emi_slow_clk", emi_slow_clk),
4629         _REGISTER_CLOCK(NULL, "emi_clk", emi_clk),
4630         _REGISTER_CLOCK(NULL, "enfc_clk", enfc_clk),
4631         _REGISTER_CLOCK("imx-uart.0", NULL, uart_clk[0]),
4632         _REGISTER_CLOCK("imx-uart.1", NULL, uart_clk[0]),
4633         _REGISTER_CLOCK("imx-uart.2", NULL, uart_clk[0]),
4634         _REGISTER_CLOCK("imx-uart.3", NULL, uart_clk[0]),
4635         _REGISTER_CLOCK(NULL, "hsi_tx", hsi_tx_clk[0]),
4636         _REGISTER_CLOCK(NULL, "caam_clk", caam_clk[0]),
4637         _REGISTER_CLOCK(NULL, "asrc_clk", asrc_clk[0]),
4638         _REGISTER_CLOCK(NULL, "asrc_serial_clk", asrc_clk[1]),
4639         _REGISTER_CLOCK("mxs-dma-apbh", NULL, apbh_dma_clk),
4640         _REGISTER_CLOCK(NULL, "openvg_axi_clk", openvg_axi_clk),
4641         _REGISTER_CLOCK(NULL, "gpu3d_clk", gpu3d_core_clk[0]),
4642         _REGISTER_CLOCK(NULL, "gpu2d_clk", gpu2d_core_clk[0]),
4643         _REGISTER_CLOCK(NULL, "gpu3d_shader_clk", gpu3d_shader_clk),
4644         _REGISTER_CLOCK(NULL, "gpt", gpt_clk[0]),
4645         _REGISTER_CLOCK("imx6q-gpmi-nfc.0", NULL, gpmi_nfc_clk[0]),
4646         _REGISTER_CLOCK(NULL, "gpmi-apb", gpmi_nfc_clk[1]),
4647         _REGISTER_CLOCK(NULL, "bch", gpmi_nfc_clk[2]),
4648         _REGISTER_CLOCK(NULL, "bch-apb", gpmi_nfc_clk[3]),
4649         _REGISTER_CLOCK(NULL, "pl301_mx6qperl-bch", gpmi_nfc_clk[4]),
4650         _REGISTER_CLOCK("mxc_pwm.0", NULL, pwm_clk[0]),
4651         _REGISTER_CLOCK("mxc_pwm.1", NULL, pwm_clk[1]),
4652         _REGISTER_CLOCK("mxc_pwm.2", NULL, pwm_clk[2]),
4653         _REGISTER_CLOCK("mxc_pwm.3", NULL, pwm_clk[3]),
4654         _REGISTER_CLOCK(NULL, "pcie_clk", pcie_clk[0]),
4655         _REGISTER_CLOCK("fec.0", NULL, enet_clk[0]),
4656         _REGISTER_CLOCK(NULL, "imx_sata_clk", sata_clk[0]),
4657         _REGISTER_CLOCK(NULL, "usboh3_clk", usboh3_clk[0]),
4658         _REGISTER_CLOCK(NULL, "usb_phy1_clk", usb_phy1_clk),
4659         _REGISTER_CLOCK("imx2-wdt.0", NULL, dummy_clk),
4660         _REGISTER_CLOCK("imx2-wdt.1", NULL, dummy_clk),
4661         _REGISTER_CLOCK(NULL, "hdmi_isfr_clk", hdmi_clk[0]),
4662         _REGISTER_CLOCK(NULL, "hdmi_iahb_clk", hdmi_clk[1]),
4663         _REGISTER_CLOCK(NULL, NULL, vdoa_clk),
4664         _REGISTER_CLOCK(NULL, NULL, aips_tz2_clk),
4665         _REGISTER_CLOCK(NULL, NULL, aips_tz1_clk),
4666         _REGISTER_CLOCK(NULL, "clko_clk", clko_clk),
4667 };
4668
4669
4670 static void clk_tree_init(void)
4671
4672 {
4673         unsigned int reg;
4674
4675         reg = __raw_readl(MMDC_MDMISC_OFFSET);
4676         if ((reg & MMDC_MDMISC_DDR_TYPE_MASK) ==
4677                 (0x1 << MMDC_MDMISC_DDR_TYPE_OFFSET)) {
4678                 clk_set_parent(&periph_clk, &pll2_pfd_400M);
4679                 printk(KERN_INFO "Set periph_clk's parent to pll2_pfd_400M!\n");
4680         }
4681 }
4682
4683
4684 int __init mx6_clocks_init(unsigned long ckil, unsigned long osc,
4685         unsigned long ckih1, unsigned long ckih2)
4686 {
4687         __iomem void *base;
4688         int i;
4689
4690         external_low_reference = ckil;
4691         external_high_reference = ckih1;
4692         ckih2_reference = ckih2;
4693         oscillator_reference = osc;
4694
4695         apll_base = ioremap(ANATOP_BASE_ADDR, SZ_4K);
4696
4697         for (i = 0; i < ARRAY_SIZE(lookups); i++) {
4698                 clkdev_add(&lookups[i]);
4699                 clk_debug_register(lookups[i].clk);
4700         }
4701
4702         /* Disable un-necessary PFDs & PLLs */
4703
4704         /* keep correct count. */
4705         clk_enable(&cpu_clk);
4706         clk_enable(&periph_clk);
4707
4708         clk_tree_init();
4709
4710         if (pll2_pfd_400M.usecount == 0)
4711                 pll2_pfd_400M.disable(&pll2_pfd_400M);
4712         pll2_pfd_352M.disable(&pll2_pfd_352M);
4713         pll2_pfd_594M.disable(&pll2_pfd_594M);
4714
4715         pll3_pfd_454M.disable(&pll3_pfd_454M);
4716         pll3_pfd_508M.disable(&pll3_pfd_508M);
4717         pll3_pfd_540M.disable(&pll3_pfd_540M);
4718         pll3_pfd_720M.disable(&pll3_pfd_720M);
4719
4720         pll3_usb_otg_main_clk.disable(&pll3_usb_otg_main_clk);
4721         pll4_audio_main_clk.disable(&pll4_audio_main_clk);
4722         pll5_video_main_clk.disable(&pll5_video_main_clk);
4723         pll6_MLB_main_clk.disable(&pll6_MLB_main_clk);
4724         pll7_usb_host_main_clk.disable(&pll7_usb_host_main_clk);
4725         pll8_enet_main_clk.disable(&pll8_enet_main_clk);
4726
4727         sata_clk[0].disable(&sata_clk[0]);
4728         pcie_clk[0].disable(&pcie_clk[0]);
4729
4730         /* Initialize Audio and Video PLLs to valid frequency (650MHz). */
4731         clk_set_rate(&pll4_audio_main_clk, 650000000);
4732         clk_set_rate(&pll5_video_main_clk, 650000000);
4733
4734         clk_set_parent(&ipu1_di_clk[0], &pll5_video_main_clk);
4735         clk_set_parent(&ipu1_di_clk[1], &pll5_video_main_clk);
4736         clk_set_parent(&ipu2_di_clk[0], &pll5_video_main_clk);
4737         clk_set_parent(&ipu2_di_clk[1], &pll5_video_main_clk);
4738
4739         clk_set_parent(&cko1_clk0, &ipg_clk);
4740         clk_set_rate(&cko1_clk0, 22000000);
4741         clk_enable(&cko1_clk0);
4742
4743         clk_set_parent(&gpu3d_shader_clk, &pll2_pfd_594M);
4744         clk_set_rate(&gpu3d_shader_clk, 594000000);
4745         clk_set_parent(&gpu3d_core_clk[0], &mmdc_ch0_axi_clk[0]);
4746         clk_set_rate(&gpu3d_core_clk[0], 528000000);
4747
4748         /*
4749          * FIXME: asrc needs to use asrc_serial(spdif1) clock to do sample rate convertion,
4750          * however we found it only works when set to 1.5M clock and the
4751          * parent is pll3_sw_clk.
4752          */
4753         clk_set_parent(&asrc_clk[1], &pll3_sw_clk);
4754         clk_set_rate(&asrc_clk[1], 1500000);
4755
4756         /* set the NAND to 11MHz. Too fast will cause dma timeout. */
4757         clk_set_rate(&enfc_clk, enfc_clk.round_rate(&enfc_clk, 11000000));
4758
4759         mx6_cpu_op_init();
4760         cpu_op_tbl = get_cpu_op(&cpu_op_nr);
4761
4762         /* Gate off all possible clocks */
4763         if (mxc_jtag_enabled) {
4764                 __raw_writel(3 << MXC_CCM_CCGRx_CG11_OFFSET |
4765                              3 << MXC_CCM_CCGRx_CG2_OFFSET |
4766                              3 << MXC_CCM_CCGRx_CG1_OFFSET |
4767                              3 << MXC_CCM_CCGRx_CG0_OFFSET, MXC_CCM_CCGR0);
4768         } else {
4769                 __raw_writel(1 << MXC_CCM_CCGRx_CG11_OFFSET |
4770                              3 << MXC_CCM_CCGRx_CG2_OFFSET |
4771                              3 << MXC_CCM_CCGRx_CG1_OFFSET |
4772                              3 << MXC_CCM_CCGRx_CG0_OFFSET, MXC_CCM_CCGR0);
4773         }
4774         __raw_writel(3 << MXC_CCM_CCGRx_CG10_OFFSET, MXC_CCM_CCGR1);
4775         __raw_writel(1 << MXC_CCM_CCGRx_CG12_OFFSET |
4776                      1 << MXC_CCM_CCGRx_CG11_OFFSET |
4777                      3 << MXC_CCM_CCGRx_CG10_OFFSET |
4778                      3 << MXC_CCM_CCGRx_CG9_OFFSET |
4779                      3 << MXC_CCM_CCGRx_CG8_OFFSET, MXC_CCM_CCGR2);
4780         __raw_writel(1 << MXC_CCM_CCGRx_CG14_OFFSET |
4781                      3 << MXC_CCM_CCGRx_CG13_OFFSET |
4782                      3 << MXC_CCM_CCGRx_CG12_OFFSET |
4783                      3 << MXC_CCM_CCGRx_CG11_OFFSET |
4784                      3 << MXC_CCM_CCGRx_CG10_OFFSET, MXC_CCM_CCGR3);
4785         __raw_writel(3 << MXC_CCM_CCGRx_CG7_OFFSET |
4786                         1 << MXC_CCM_CCGRx_CG6_OFFSET |
4787                         1 << MXC_CCM_CCGRx_CG4_OFFSET, MXC_CCM_CCGR4);
4788         __raw_writel(1 << MXC_CCM_CCGRx_CG0_OFFSET, MXC_CCM_CCGR5);
4789
4790         __raw_writel(0, MXC_CCM_CCGR6);
4791
4792         /* Lower the ipg_perclk frequency to 8.25MHz. */
4793         clk_set_rate(&ipg_perclk, 8250000);
4794
4795         /* S/PDIF */
4796         clk_set_parent(&spdif0_clk[0], &pll3_pfd_454M);
4797
4798         base = ioremap(GPT_BASE_ADDR, SZ_4K);
4799         mxc_timer_init(&gpt_clk[0], base, MXC_INT_GPT);
4800
4801         lp_high_freq = 0;
4802         lp_med_freq = 0;
4803
4804         return 0;
4805
4806 }