arch/arm/mach-mx6/cpu_op-mx6.c

   1 /*
   2  * Copyright (C) 2010-2012 Freescale Semiconductor, Inc. All Rights Reserved.
   3  */
   4
   5 /*
   6  * The code contained herein is licensed under the GNU General Public
   7  * License. You may obtain a copy of the GNU General Public License
   8  * Version 2 or later at the following locations:
   9  *
  10  * http://www.opensource.org/licenses/gpl-license.html
  11  * http://www.gnu.org/copyleft/gpl.html
  12  */
  13
  14 #include <linux/types.h>
  15 #include <linux/kernel.h>
  16 #include <mach/hardware.h>
  17 #include <mach/mxc_dvfs.h>
  18 #include "cpu_op-mx6.h"
  19
  20 extern struct cpu_op *(*get_cpu_op)(int *op);
  21 extern struct dvfs_op *(*get_dvfs_core_op)(int *wp);
  22 extern void (*set_num_cpu_op)(int num);
  23 extern u32 arm_max_freq;
  24 static int num_cpu_op;
  25
  26 /* working point(wp): 0 - 1.2GHz; 1 - 800MHz, 2 - 624MHz 3 - 400MHz, 4  - 200MHz */
  27 static struct cpu_op mx6_cpu_op_1_2G[] = {
  28         {
  29          .pll_rate = 1200000000,
  30          .cpu_rate = 1200000000,
  31          .cpu_podf = 0,
  32          .cpu_voltage = 1275000,},
  33         {
  34          .pll_rate = 792000000,
  35          .cpu_rate = 792000000,
  36          .cpu_podf = 0,
  37          .cpu_voltage = 1100000,},
  38         {
  39          .pll_rate = 624000000,
  40          .cpu_rate = 624000000,
  41          .cpu_voltage = 1100000,},
  42          {
  43           .pll_rate = 792000000,
  44           .cpu_rate = 396000000,
  45           .cpu_podf = 1,
  46           .cpu_voltage = 950000,},
  47         {
  48          .pll_rate = 792000000,
  49          .cpu_rate = 198000000,
  50          .cpu_podf = 3,
  51          .cpu_voltage = 850000,},
  52 };
  53
  54 /* working point(wp): 0 - 1GHz; 1 - 800MHz, 2 - 624MHz 3 - 400MHz, 4  - 200MHz */
  55 static struct cpu_op mx6_cpu_op_1G[] = {
  56         {
  57          .pll_rate = 996000000,
  58          .cpu_rate = 996000000,
  59          .cpu_podf = 0,
  60          .cpu_voltage = 1225000,},
  61         {
  62          .pll_rate = 792000000,
  63          .cpu_rate = 792000000,
  64          .cpu_podf = 0,
  65          .cpu_voltage = 1100000,},
  66         {
  67          .pll_rate = 624000000,
  68          .cpu_rate = 624000000,
  69          .cpu_voltage = 1100000,},
  70          {
  71           .pll_rate = 792000000,
  72           .cpu_rate = 396000000,
  73           .cpu_podf = 1,
  74           .cpu_voltage = 950000,},
  75         {
  76          .pll_rate = 792000000,
  77          .cpu_rate = 198000000,
  78          .cpu_podf = 3,
  79          .cpu_voltage = 850000,},
  80 };
  81
  82 static struct cpu_op mx6_cpu_op[] = {
  83         {
  84          .pll_rate = 792000000,
  85          .cpu_rate = 792000000,
  86          .cpu_podf = 0,
  87          .cpu_voltage = 1100000,},
  88          {
  89           .pll_rate = 792000000,
  90           .cpu_rate = 396000000,
  91           .cpu_podf = 1,
  92           .cpu_voltage = 950000,},
  93         {
  94          .pll_rate = 792000000,
  95          .cpu_rate = 198000000,
  96          .cpu_podf = 3,
  97          .cpu_voltage = 850000,},
  98 };
  99
 100 /* working point(wp): 0 - 1.2GHz; 1 - 800MHz, 2 - 400MHz, 3  - 200MHz */
 101 static struct cpu_op mx6dl_cpu_op_1_2G[] = {
 102         {
 103          .pll_rate = 1200000000,
 104          .cpu_rate = 1200000000,
 105          .cpu_podf = 0,
 106          .cpu_voltage = 1275000,},
 107         {
 108          .pll_rate = 792000000,
 109          .cpu_rate = 792000000,
 110          .cpu_podf = 0,
 111          .cpu_voltage = 1100000,},
 112          {
 113           .pll_rate = 792000000,
 114           .cpu_rate = 396000000,
 115           .cpu_podf = 1,
 116           .cpu_voltage = 1000000,},
 117         {
 118          .pll_rate = 792000000,
 119          .cpu_rate = 198000000,
 120          .cpu_podf = 3,
 121          .cpu_voltage = 1000000,},
 122 };
 123 /* working point(wp): 0 - 1GHz; 1 - 800MHz, 2 - 400MHz, 3  - 200MHz */
 124 static struct cpu_op mx6dl_cpu_op_1G[] = {
 125         {
 126          .pll_rate = 996000000,
 127          .cpu_rate = 996000000,
 128          .cpu_podf = 0,
 129          .cpu_voltage = 1225000,},
 130         {
 131          .pll_rate = 792000000,
 132          .cpu_rate = 792000000,
 133          .cpu_podf = 0,
 134          .cpu_voltage = 1100000,},
 135          {
 136           .pll_rate = 792000000,
 137           .cpu_rate = 396000000,
 138           .cpu_podf = 1,
 139           .cpu_voltage = 1000000,},
 140         {
 141          .pll_rate = 792000000,
 142          .cpu_rate = 198000000,
 143          .cpu_podf = 3,
 144          .cpu_voltage = 1000000,},
 145 };
 146
 147 static struct cpu_op mx6dl_cpu_op[] = {
 148         {
 149          .pll_rate = 792000000,
 150          .cpu_rate = 792000000,
 151          .cpu_podf = 0,
 152          .cpu_voltage = 1100000,},
 153          {
 154           .pll_rate = 792000000,
 155           .cpu_rate = 396000000,
 156           .cpu_podf = 1,
 157           .cpu_voltage = 1000000,},
 158         {
 159          .pll_rate = 792000000,
 160          .cpu_rate = 198000000,
 161          .cpu_podf = 3,
 162          .cpu_voltage = 1000000,},
 163 };
 164
 165 static struct dvfs_op dvfs_core_setpoint_1_2G[] = {
 166         {33, 14, 33, 10, 128, 0x10},     /* 1.2GHz*/
 167         {30, 12, 33, 100, 200, 0x10},   /* 800MHz */
 168         {28, 12, 33, 100, 200, 0x10},   /* 624MHz */
 169         {26, 8, 33, 100, 200, 0x10},   /* 400MHz */
 170         {20, 0, 33, 20, 10, 0x10} };   /* 200MHz*/
 171
 172 static struct dvfs_op dvfs_core_setpoint_1G[] = {
 173         {33, 14, 33, 10, 128, 0x10}, /* 1GHz*/
 174         {30, 12, 33, 100, 200, 0x10},   /* 800MHz */
 175         {28, 12, 33, 100, 200, 0x10},   /* 624MHz */
 176         {26, 8, 33, 100, 200, 0x10},   /* 400MHz */
 177         {20, 0, 33, 20, 10, 0x10} };   /* 200MHz*/
 178
 179 static struct dvfs_op dvfs_core_setpoint[] = {
 180         {33, 14, 33, 10, 128, 0x08},   /* 800MHz */
 181         {26, 8, 33, 100, 200, 0x08},   /* 400MHz */
 182         {20, 0, 33, 20, 10, 0x08} };   /* 200MHz*/
 183
 184 static struct dvfs_op *mx6_get_dvfs_core_table(int *wp)
 185 {
 186         if (arm_max_freq == CPU_AT_1_2GHz) {
 187                 *wp = ARRAY_SIZE(dvfs_core_setpoint_1_2G);
 188                 return dvfs_core_setpoint_1_2G;
 189         } else if (arm_max_freq == CPU_AT_1GHz) {
 190                 *wp = ARRAY_SIZE(dvfs_core_setpoint_1G);
 191                 return dvfs_core_setpoint_1G;
 192         } else {
 193                 *wp = ARRAY_SIZE(dvfs_core_setpoint);
 194                 return dvfs_core_setpoint;
 195         }
 196 }
 197
 198 struct cpu_op *mx6_get_cpu_op(int *op)
 199 {
 200         if (cpu_is_mx6dl()) {
 201                 if (arm_max_freq == CPU_AT_1_2GHz) {
 202                         *op =  num_cpu_op = ARRAY_SIZE(mx6dl_cpu_op_1_2G);
 203                         return mx6dl_cpu_op_1_2G;
 204                 } else if (arm_max_freq == CPU_AT_1GHz) {
 205                         *op =  num_cpu_op = ARRAY_SIZE(mx6dl_cpu_op_1G);
 206                         return mx6dl_cpu_op_1G;
 207                 } else {
 208                         *op =  num_cpu_op = ARRAY_SIZE(mx6dl_cpu_op);
 209                         return mx6dl_cpu_op;
 210                 }
 211         } else {
 212                 if (arm_max_freq == CPU_AT_1_2GHz) {
 213                         *op =  num_cpu_op = ARRAY_SIZE(mx6_cpu_op_1_2G);
 214                         return mx6_cpu_op_1_2G;
 215                 } else if (arm_max_freq == CPU_AT_1GHz) {
 216                         *op =  num_cpu_op = ARRAY_SIZE(mx6_cpu_op_1G);
 217                         return mx6_cpu_op_1G;
 218                 } else {
 219                         *op =  num_cpu_op = ARRAY_SIZE(mx6_cpu_op);
 220                         return mx6_cpu_op;
 221                 }
 222         }
 223 }
 224
 225 void mx6_set_num_cpu_op(int num)
 226 {
 227         num_cpu_op = num;
 228         return;
 229 }
 230
 231 void mx6_cpu_op_init(void)
 232 {
 233         get_cpu_op = mx6_get_cpu_op;
 234         set_num_cpu_op = mx6_set_num_cpu_op;
 235
 236         get_dvfs_core_op = mx6_get_dvfs_core_table;
 237 }
 238