2 * Copyright (C) 2010-2012 Freescale Semiconductor, Inc. All Rights Reserved.
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
14 #include <linux/types.h>
15 #include <linux/kernel.h>
16 #include <mach/hardware.h>
17 #include <mach/mxc_dvfs.h>
18 #include "cpu_op-mx6.h"
20 extern struct cpu_op *(*get_cpu_op)(int *op);
21 extern struct dvfs_op *(*get_dvfs_core_op)(int *wp);
22 extern void (*set_num_cpu_op)(int num);
23 extern u32 arm_max_freq;
24 static int num_cpu_op;
26 /* working point(wp): 0 - 1.2GHz; 1 - 800MHz, 2 - 624MHz 3 - 400MHz, 4 - 200MHz */
27 static struct cpu_op mx6_cpu_op_1_2G[] = {
29 .pll_rate = 1200000000,
30 .cpu_rate = 1200000000,
32 .cpu_voltage = 1275000,},
34 .pll_rate = 792000000,
35 .cpu_rate = 792000000,
37 .cpu_voltage = 1100000,},
39 .pll_rate = 624000000,
40 .cpu_rate = 624000000,
41 .cpu_voltage = 1100000,},
43 .pll_rate = 792000000,
44 .cpu_rate = 396000000,
46 .cpu_voltage = 950000,},
48 .pll_rate = 792000000,
49 .cpu_rate = 198000000,
51 .cpu_voltage = 850000,},
54 /* working point(wp): 0 - 1GHz; 1 - 800MHz, 2 - 624MHz 3 - 400MHz, 4 - 200MHz */
55 static struct cpu_op mx6_cpu_op_1G[] = {
57 .pll_rate = 996000000,
58 .cpu_rate = 996000000,
60 .cpu_voltage = 1225000,},
62 .pll_rate = 792000000,
63 .cpu_rate = 792000000,
65 .cpu_voltage = 1100000,},
67 .pll_rate = 624000000,
68 .cpu_rate = 624000000,
69 .cpu_voltage = 1100000,},
71 .pll_rate = 792000000,
72 .cpu_rate = 396000000,
74 .cpu_voltage = 950000,},
76 .pll_rate = 792000000,
77 .cpu_rate = 198000000,
79 .cpu_voltage = 850000,},
82 static struct cpu_op mx6_cpu_op[] = {
84 .pll_rate = 792000000,
85 .cpu_rate = 792000000,
87 .cpu_voltage = 1100000,},
89 .pll_rate = 792000000,
90 .cpu_rate = 396000000,
92 .cpu_voltage = 950000,},
94 .pll_rate = 792000000,
95 .cpu_rate = 198000000,
97 .cpu_voltage = 850000,},
100 /* working point(wp): 0 - 1GHzMHz; 1 - 800MHz, 3 - 400MHz, 4 - 200MHz */
101 static struct cpu_op mx6dl_cpu_op_1G[] = {
103 .pll_rate = 996000000,
104 .cpu_rate = 996000000,
106 .cpu_voltage = 1225000,},
108 .pll_rate = 792000000,
109 .cpu_rate = 792000000,
111 .cpu_voltage = 1100000,},
113 .pll_rate = 792000000,
114 .cpu_rate = 396000000,
116 .cpu_voltage = 1000000,},
118 .pll_rate = 792000000,
119 .cpu_rate = 198000000,
121 .cpu_voltage = 1000000,},
124 static struct cpu_op mx6dl_cpu_op[] = {
126 .pll_rate = 792000000,
127 .cpu_rate = 792000000,
129 .cpu_voltage = 1100000,},
131 .pll_rate = 792000000,
132 .cpu_rate = 396000000,
134 .cpu_voltage = 1000000,},
136 .pll_rate = 792000000,
137 .cpu_rate = 198000000,
139 .cpu_voltage = 1000000,},
142 static struct dvfs_op dvfs_core_setpoint_1_2G[] = {
143 {33, 14, 33, 10, 128, 0x10}, /* 1.2GHz*/
144 {30, 12, 33, 100, 200, 0x10}, /* 800MHz */
145 {28, 12, 33, 100, 200, 0x10}, /* 624MHz */
146 {26, 8, 33, 100, 200, 0x10}, /* 400MHz */
147 {20, 0, 33, 20, 10, 0x10} }; /* 200MHz*/
149 static struct dvfs_op dvfs_core_setpoint_1G[] = {
150 {33, 14, 33, 10, 128, 0x10}, /* 1GHz*/
151 {30, 12, 33, 100, 200, 0x10}, /* 800MHz */
152 {28, 12, 33, 100, 200, 0x10}, /* 624MHz */
153 {26, 8, 33, 100, 200, 0x10}, /* 400MHz */
154 {20, 0, 33, 20, 10, 0x10} }; /* 200MHz*/
156 static struct dvfs_op dvfs_core_setpoint[] = {
157 {33, 14, 33, 10, 128, 0x08}, /* 800MHz */
158 {26, 8, 33, 100, 200, 0x08}, /* 400MHz */
159 {20, 0, 33, 20, 10, 0x08} }; /* 200MHz*/
161 static struct dvfs_op *mx6_get_dvfs_core_table(int *wp)
163 if (arm_max_freq == CPU_AT_1_2GHz) {
164 *wp = ARRAY_SIZE(dvfs_core_setpoint_1_2G);
165 return dvfs_core_setpoint_1_2G;
166 } else if (arm_max_freq == CPU_AT_1GHz) {
167 *wp = ARRAY_SIZE(dvfs_core_setpoint_1G);
168 return dvfs_core_setpoint_1G;
170 *wp = ARRAY_SIZE(dvfs_core_setpoint);
171 return dvfs_core_setpoint;
175 struct cpu_op *mx6_get_cpu_op(int *op)
177 if (cpu_is_mx6dl()) {
178 if (arm_max_freq == CPU_AT_1GHz) {
179 *op = num_cpu_op = ARRAY_SIZE(mx6dl_cpu_op_1G);
180 return mx6dl_cpu_op_1G;
182 *op = num_cpu_op = ARRAY_SIZE(mx6dl_cpu_op);
186 if (arm_max_freq == CPU_AT_1_2GHz) {
187 *op = num_cpu_op = ARRAY_SIZE(mx6_cpu_op_1_2G);
188 return mx6_cpu_op_1_2G;
189 } else if (arm_max_freq == CPU_AT_1GHz) {
190 *op = num_cpu_op = ARRAY_SIZE(mx6_cpu_op_1G);
191 return mx6_cpu_op_1G;
193 *op = num_cpu_op = ARRAY_SIZE(mx6_cpu_op);
199 void mx6_set_num_cpu_op(int num)
205 void mx6_cpu_op_init(void)
207 get_cpu_op = mx6_get_cpu_op;
208 set_num_cpu_op = mx6_set_num_cpu_op;
210 get_dvfs_core_op = mx6_get_dvfs_core_table;