arch/arm/mach-mx6/usb_dr.c

   1 /*
   2  * Copyright (C) 2013 Freescale Semiconductor, Inc. All Rights Reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13
  14  * You should have received a copy of the GNU General Public License along
  15  * with this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  17  */
  18
  19 #include <linux/kernel.h>
  20 #include <linux/types.h>
  21 #include <linux/clk.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/fsl_devices.h>
  24 #include <linux/delay.h>
  25 #include <linux/io.h>
  26 #include <mach/arc_otg.h>
  27 #include <mach/hardware.h>
  28 #include "devices-imx6q.h"
  29 #include "regs-anadig.h"
  30 #include "usb.h"
  31
  32 DEFINE_MUTEX(otg_wakeup_enable_mutex);
  33 static int usbotg_init_ext(struct platform_device *pdev);
  34 static void usbotg_uninit_ext(struct platform_device *pdev);
  35 static void usbotg_clock_gate(bool on);
  36 static void _dr_discharge_line(bool enable);
  37 extern bool usb_icbug_swfix_need(void);
  38 static void enter_phy_lowpower_suspend(struct fsl_usb2_platform_data *pdata, \
  39                                                                 bool enable);
  40
  41 /* The usb_phy1_clk do not have enable/disable function at clock.c
  42  * and PLL output for usb1's phy should be always enabled.
  43  * usb_phy1_clk only stands for usb uses pll3 as its parent.
  44  */
  45 static struct clk *usb_phy1_clk;
  46 static struct clk *usb_oh3_clk;
  47 static u8 otg_used;
  48
  49 static void usbotg_wakeup_event_clear(void);
  50 extern int clk_get_usecount(struct clk *clk);
  51 /* Beginning of Common operation for DR port */
  52
  53 /*
  54  * platform data structs
  55  *      - Which one to use is determined by CONFIG options in usb.h
  56  *      - operating_mode plugged at run time
  57  */
  58 static struct fsl_usb2_platform_data dr_utmi_config = {
  59         .name              = "DR",
  60         .init              = usbotg_init_ext,
  61         .exit              = usbotg_uninit_ext,
  62         .phy_mode          = FSL_USB2_PHY_UTMI_WIDE,
  63         .power_budget      = 500,               /* 500 mA max power */
  64         .usb_clock_for_pm  = usbotg_clock_gate,
  65         .transceiver       = "utmi",
  66         .phy_regs = USB_PHY0_BASE_ADDR,
  67         .dr_discharge_line = _dr_discharge_line,
  68         .lowpower          = true, /* Default driver low power is true */
  69 };
  70
  71 /* Platform data for wakeup operation */
  72 static struct fsl_usb2_wakeup_platform_data dr_wakeup_config = {
  73         .name = "DR wakeup",
  74         .usb_clock_for_pm  = usbotg_clock_gate,
  75         .usb_wakeup_exhandle = usbotg_wakeup_event_clear,
  76 };
  77
  78 static void usbotg_internal_phy_clock_gate(bool on)
  79 {
  80         void __iomem *phy_reg = MX6_IO_ADDRESS(USB_PHY0_BASE_ADDR);
  81         if (on) {
  82                 __raw_writel(BM_USBPHY_CTRL_CLKGATE, phy_reg + HW_USBPHY_CTRL_CLR);
  83         } else {
  84                 __raw_writel(BM_USBPHY_CTRL_CLKGATE, phy_reg + HW_USBPHY_CTRL_SET);
  85         }
  86 }
  87
  88 static int usb_phy_enable(struct fsl_usb2_platform_data *pdata)
  89 {
  90         u32 tmp;
  91         void __iomem *phy_reg = MX6_IO_ADDRESS(USB_PHY0_BASE_ADDR);
  92         void __iomem *phy_ctrl;
  93
  94         /* Stop then Reset */
  95         UOG_USBCMD &= ~UCMD_RUN_STOP;
  96         while (UOG_USBCMD & UCMD_RUN_STOP)
  97                 ;
  98
  99         UOG_USBCMD |= UCMD_RESET;
 100         while ((UOG_USBCMD) & (UCMD_RESET))
 101                 ;
 102
 103         /*
 104          * If the controller reset does not put the PHY be out of
 105          * low power mode, do it manually.
 106          */
 107         if (UOG_PORTSC1 & PORTSC_PHCD) {
 108                 UOG_PORTSC1 &= ~PORTSC_PHCD;
 109                 mdelay(1);
 110         }
 111
 112         /* Reset USBPHY module */
 113         phy_ctrl = phy_reg + HW_USBPHY_CTRL;
 114         tmp = __raw_readl(phy_ctrl);
 115         tmp |= BM_USBPHY_CTRL_SFTRST;
 116         __raw_writel(tmp, phy_ctrl);
 117         udelay(10);
 118
 119         /* Remove CLKGATE and SFTRST */
 120         tmp = __raw_readl(phy_ctrl);
 121         tmp &= ~(BM_USBPHY_CTRL_CLKGATE | BM_USBPHY_CTRL_SFTRST);
 122         __raw_writel(tmp, phy_ctrl);
 123         udelay(10);
 124
 125         /* Power up the PHY */
 126         __raw_writel(0, phy_reg + HW_USBPHY_PWD);
 127         if ((pdata->operating_mode == FSL_USB2_DR_HOST) ||
 128                         (pdata->operating_mode == FSL_USB2_DR_OTG)) {
 129                 /* enable FS/LS device */
 130                 __raw_writel(BM_USBPHY_CTRL_ENUTMILEVEL2 | BM_USBPHY_CTRL_ENUTMILEVEL3
 131                                 , phy_reg + HW_USBPHY_CTRL_SET);
 132         }
 133
 134         if (!usb_icbug_swfix_need())
 135                 __raw_writel((1 << 17), phy_reg + HW_USBPHY_IP_SET);
 136         if (cpu_is_mx6sl())
 137                 __raw_writel((1 << 18), phy_reg + HW_USBPHY_IP_SET);
 138         return 0;
 139 }
 140 /* Notes: configure USB clock*/
 141 static int usbotg_init_ext(struct platform_device *pdev)
 142 {
 143         struct clk *usb_clk;
 144         u32 ret;
 145
 146         /* at mx6q: this clock is AHB clock for usb core */
 147         usb_clk = clk_get(NULL, "usboh3_clk");
 148         clk_enable(usb_clk);
 149         usb_oh3_clk = usb_clk;
 150
 151         usb_clk = clk_get(NULL, "usb_phy1_clk");
 152         clk_enable(usb_clk);
 153         usb_phy1_clk = usb_clk;
 154
 155         ret = usbotg_init(pdev);
 156         if (ret) {
 157                 clk_disable(usb_oh3_clk);
 158                 clk_put(usb_oh3_clk);
 159                 clk_disable(usb_phy1_clk);
 160                 clk_put(usb_phy1_clk);
 161                 printk(KERN_ERR "otg init fails......\n");
 162                 return ret;
 163         }
 164         if (!otg_used) {
 165                 usb_phy_enable(pdev->dev.platform_data);
 166                 enter_phy_lowpower_suspend(pdev->dev.platform_data, false);
 167                 /*after the phy reset,can not read the readingvalue for id/vbus at
 168                 * the register of otgsc ,cannot  read at once ,need delay 3 ms
 169                 */
 170                 mdelay(3);
 171         }
 172         otg_used++;
 173
 174         return ret;
 175 }
 176
 177 static void usbotg_uninit_ext(struct platform_device *pdev)
 178 {
 179         otg_used--;
 180         if (!otg_used) {
 181                 clk_disable(usb_phy1_clk);
 182                 clk_put(usb_phy1_clk);
 183
 184                 clk_disable(usb_oh3_clk);
 185                 clk_put(usb_oh3_clk);
 186         }
 187 }
 188
 189 static void usbotg_clock_gate(bool on)
 190 {
 191         pr_debug("%s: on is %d\n", __func__, on);
 192         if (on) {
 193                 clk_enable(usb_oh3_clk);
 194                 clk_enable(usb_phy1_clk);
 195         } else {
 196                 clk_disable(usb_phy1_clk);
 197                 clk_disable(usb_oh3_clk);
 198         }
 199         pr_debug("usb_oh3_clk:%d, usb_phy_clk1_ref_count:%d\n", clk_get_usecount(usb_oh3_clk), clk_get_usecount(usb_phy1_clk));
 200 }
 201
 202 static void dr_platform_phy_power_on(void)
 203 {
 204         void __iomem *anatop_base_addr = MX6_IO_ADDRESS(ANATOP_BASE_ADDR);
 205         __raw_writel(BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG,
 206                                 anatop_base_addr + HW_ANADIG_ANA_MISC0_SET);
 207 }
 208
 209
 210 static void _dr_discharge_line(bool enable)
 211 {
 212         void __iomem *anatop_base_addr = MX6_IO_ADDRESS(ANATOP_BASE_ADDR);
 213         void __iomem *phy_reg = MX6_IO_ADDRESS(USB_PHY0_BASE_ADDR);
 214
 215         pr_debug("DR: %s  enable is %d\n", __func__, enable);
 216         if (enable) {
 217                 __raw_writel(BM_USBPHY_DEBUG_CLKGATE, phy_reg + HW_USBPHY_DEBUG_CLR);
 218                 __raw_writel(BM_ANADIG_USB1_LOOPBACK_UTMI_DIG_TST1
 219                                         |BM_ANADIG_USB1_LOOPBACK_TSTI_TX_EN,
 220                         anatop_base_addr + HW_ANADIG_USB1_LOOPBACK);
 221         } else {
 222                 __raw_writel(0x0,
 223                         anatop_base_addr + HW_ANADIG_USB1_LOOPBACK);
 224                 __raw_writel(BM_USBPHY_DEBUG_CLKGATE, phy_reg + HW_USBPHY_DEBUG_SET);
 225         }
 226 }
 227
 228 /* Below two macros are used at otg mode to indicate usb mode*/
 229 #define ENABLED_BY_HOST   (0x1 << 0)
 230 #define ENABLED_BY_DEVICE (0x1 << 1)
 231 static u32 low_power_enable_src; /* only useful at otg mode */
 232 static void enter_phy_lowpower_suspend(struct fsl_usb2_platform_data *pdata, bool enable)
 233 {
 234         void __iomem *phy_reg = MX6_IO_ADDRESS(USB_PHY0_BASE_ADDR);
 235         u32 tmp;
 236         pr_debug("DR: %s begins, enable is %d\n", __func__, enable);
 237
 238         if (enable) {
 239                 UOG_PORTSC1 |= PORTSC_PHCD;
 240                 tmp = (BM_USBPHY_PWD_TXPWDFS
 241                         | BM_USBPHY_PWD_TXPWDIBIAS
 242                         | BM_USBPHY_PWD_TXPWDV2I
 243                         | BM_USBPHY_PWD_RXPWDENV
 244                         | BM_USBPHY_PWD_RXPWD1PT1
 245                         | BM_USBPHY_PWD_RXPWDDIFF
 246                         | BM_USBPHY_PWD_RXPWDRX);
 247                 __raw_writel(tmp, phy_reg + HW_USBPHY_PWD_SET);
 248                 usbotg_internal_phy_clock_gate(false);
 249
 250         } else {
 251                 if (UOG_PORTSC1 & PORTSC_PHCD) {
 252                         UOG_PORTSC1 &= ~PORTSC_PHCD;
 253                         mdelay(1);
 254                 }
 255                 usbotg_internal_phy_clock_gate(true);
 256                 tmp = (BM_USBPHY_PWD_TXPWDFS
 257                         | BM_USBPHY_PWD_TXPWDIBIAS
 258                         | BM_USBPHY_PWD_TXPWDV2I
 259                         | BM_USBPHY_PWD_RXPWDENV
 260                         | BM_USBPHY_PWD_RXPWD1PT1
 261                         | BM_USBPHY_PWD_RXPWDDIFF
 262                         | BM_USBPHY_PWD_RXPWDRX);
 263                 __raw_writel(tmp, phy_reg + HW_USBPHY_PWD_CLR);
 264                 /*
 265                  * The PHY works at 32Khz clock when it is at low power mode,
 266                  * it needs 10 clocks from 32Khz to normal work state, so
 267                  * 500us is the safe value for PHY enters stable status
 268                  * according to IC engineer.
 269                  */
 270                 udelay(500);
 271
 272         }
 273         pr_debug("DR: %s ends, enable is %d\n", __func__, enable);
 274 }
 275
 276 static void __phy_lowpower_suspend(struct fsl_usb2_platform_data *pdata, bool enable, int source)
 277 {
 278         if (enable) {
 279                 low_power_enable_src |= source;
 280 #ifdef CONFIG_USB_OTG
 281                 if (low_power_enable_src == (ENABLED_BY_HOST | ENABLED_BY_DEVICE)) {
 282                         pr_debug("phy lowpower enabled\n");
 283                         enter_phy_lowpower_suspend(pdata, enable);
 284                 }
 285 #else
 286                 enter_phy_lowpower_suspend(pdata, enable);
 287 #endif
 288         } else {
 289                 pr_debug("phy lowpower disable\n");
 290                 enter_phy_lowpower_suspend(pdata, enable);
 291                 low_power_enable_src &= ~source;
 292         }
 293 }
 294
 295 static void otg_wake_up_enable(struct fsl_usb2_platform_data *pdata, bool enable)
 296 {
 297         void __iomem *phy_reg = MX6_IO_ADDRESS(USB_PHY0_BASE_ADDR);
 298
 299         pr_debug("%s, enable is %d\n", __func__, enable);
 300         if (enable) {
 301                 __raw_writel(BM_USBPHY_CTRL_ENDPDMCHG_WKUP
 302                                 | BM_USBPHY_CTRL_ENAUTOSET_USBCLKS
 303                                 | BM_USBPHY_CTRL_ENAUTOCLR_PHY_PWD
 304                                 | BM_USBPHY_CTRL_ENAUTOCLR_CLKGATE
 305                                 | BM_USBPHY_CTRL_ENAUTOCLR_USBCLKGATE
 306                                 | BM_USBPHY_CTRL_ENAUTO_PWRON_PLL , phy_reg + HW_USBPHY_CTRL_SET);
 307                 USB_OTG_CTRL |= UCTRL_OWIE;
 308         } else {
 309                 __raw_writel(BM_USBPHY_CTRL_ENDPDMCHG_WKUP
 310                                 | BM_USBPHY_CTRL_ENAUTOSET_USBCLKS
 311                                 | BM_USBPHY_CTRL_ENAUTOCLR_PHY_PWD
 312                                 | BM_USBPHY_CTRL_ENAUTOCLR_CLKGATE
 313                                 | BM_USBPHY_CTRL_ENAUTOCLR_USBCLKGATE
 314                                 | BM_USBPHY_CTRL_ENAUTO_PWRON_PLL , phy_reg + HW_USBPHY_CTRL_CLR);
 315                 USB_OTG_CTRL &= ~UCTRL_OWIE;
 316                 /* The interrupt must be disabled for at least 3 clock
 317                  * cycles of the standby clock(32k Hz) , that is 0.094 ms*/
 318                 udelay(100);
 319         }
 320 }
 321
 322 static u32 wakeup_irq_enable_src; /* only useful at otg mode */
 323 static void __wakeup_irq_enable(struct fsl_usb2_platform_data *pdata, bool on, int source)
 324  {
 325         /* otg host and device share the OWIE bit, only when host and device
 326          * all enable the wakeup irq, we can enable the OWIE bit
 327          */
 328         mutex_lock(&otg_wakeup_enable_mutex);
 329         if (on) {
 330 #ifdef CONFIG_USB_OTG
 331                 wakeup_irq_enable_src |= source;
 332                 if (wakeup_irq_enable_src == (ENABLED_BY_HOST | ENABLED_BY_DEVICE)) {
 333                         otg_wake_up_enable(pdata, on);
 334                 }
 335 #else
 336                 otg_wake_up_enable(pdata, on);
 337 #endif
 338         } else {
 339                 otg_wake_up_enable(pdata, on);
 340                 wakeup_irq_enable_src &= ~source;
 341                 /* The interrupt must be disabled for at least 3 clock
 342                  * cycles of the standby clock(32k Hz) , that is 0.094 ms*/
 343                 udelay(100);
 344         }
 345         mutex_unlock(&otg_wakeup_enable_mutex);
 346 }
 347
 348 /* The wakeup operation for DR port, it will clear the wakeup irq status
 349  * and re-enable the wakeup
 350  */
 351 static void usbotg_wakeup_event_clear(void)
 352 {
 353         int wakeup_req = USB_OTG_CTRL & UCTRL_OWIR;
 354
 355         if (wakeup_req != 0) {
 356                 printk(KERN_INFO "Unknown wakeup.(OTGSC 0x%x)\n", UOG_OTGSC);
 357                 /* Disable OWIE to clear OWIR, wait 3 clock
 358                  * cycles of standly clock(32KHz)
 359                  */
 360                 USB_OTG_CTRL &= ~UCTRL_OWIE;
 361                 udelay(100);
 362                 USB_OTG_CTRL |= UCTRL_OWIE;
 363         }
 364 }
 365
 366 /* End of Common operation for DR port */
 367
 368 #ifdef CONFIG_USB_EHCI_ARC_OTG
 369 /* Beginning of host related operation for DR port */
 370 static void fsl_platform_otg_set_usb_phy_dis(
 371                 struct fsl_usb2_platform_data *pdata, bool enable)
 372 {
 373         u32 usb_phy_ctrl_dcdt = 0;
 374         void __iomem *anatop_base_addr = MX6_IO_ADDRESS(ANATOP_BASE_ADDR);
 375         usb_phy_ctrl_dcdt = __raw_readl(
 376                         MX6_IO_ADDRESS(pdata->phy_regs) + HW_USBPHY_CTRL) &
 377                         BM_USBPHY_CTRL_ENHOSTDISCONDETECT;
 378         if (enable) {
 379                 if (usb_phy_ctrl_dcdt == 0) {
 380                         __raw_writel(BM_ANADIG_USB1_PLL_480_CTRL_EN_USB_CLKS,
 381                                         anatop_base_addr + HW_ANADIG_USB1_PLL_480_CTRL_CLR);
 382
 383                         __raw_writel(BM_USBPHY_PWD_RXPWDENV,
 384                                         MX6_IO_ADDRESS(pdata->phy_regs) + HW_USBPHY_PWD_SET);
 385
 386                         udelay(300);
 387
 388                         __raw_writel(BM_USBPHY_CTRL_ENHOSTDISCONDETECT,
 389                                 MX6_IO_ADDRESS(pdata->phy_regs)
 390                                 + HW_USBPHY_CTRL_SET);
 391
 392                         UOG_USBSTS |= (1 << 7);
 393
 394                         while ((UOG_USBSTS & (1 << 7)) == 0)
 395                                 ;
 396
 397                         udelay(2);
 398
 399                         __raw_writel(BM_USBPHY_PWD_RXPWDENV,
 400                                         MX6_IO_ADDRESS(pdata->phy_regs) + HW_USBPHY_PWD_CLR);
 401
 402                         __raw_writel(BM_ANADIG_USB1_PLL_480_CTRL_EN_USB_CLKS,
 403                                         anatop_base_addr + HW_ANADIG_USB1_PLL_480_CTRL_SET);
 404
 405                 }
 406         } else {
 407                 if (usb_phy_ctrl_dcdt
 408                                 == BM_USBPHY_CTRL_ENHOSTDISCONDETECT)
 409                         __raw_writel(BM_USBPHY_CTRL_ENHOSTDISCONDETECT,
 410                                 MX6_IO_ADDRESS(pdata->phy_regs)
 411                                 + HW_USBPHY_CTRL_CLR);
 412         }
 413 }
 414
 415 static void _host_platform_rh_suspend_swfix(struct fsl_usb2_platform_data *pdata)
 416 {
 417         void __iomem *phy_reg = MX6_IO_ADDRESS(USB_PHY0_BASE_ADDR);
 418         u32 tmp;
 419         u32 index = 0;
 420
 421         /* before we set and then clear PWD bit,
 422          * we must wait LS to be suspend */
 423         if ((UOG_PORTSC1 & (3 << 26)) != (1 << 26)) {
 424                 while (((UOG_PORTSC1 & PORTSC_LS_MASK) != PORTSC_LS_J_STATE) &&
 425                                 (index < 1000)) {
 426                         index++;
 427                         udelay(4);
 428                 }
 429         } else {
 430                 while (((UOG_PORTSC1 & PORTSC_LS_MASK) != PORTSC_LS_K_STATE) &&
 431                                 (index < 1000)) {
 432                         index++;
 433                         udelay(4);
 434                 }
 435         }
 436
 437         if (index >= 1000)
 438                 printk(KERN_INFO "%s big error\n", __func__);
 439
 440         tmp = (BM_USBPHY_PWD_TXPWDFS
 441                 | BM_USBPHY_PWD_TXPWDIBIAS
 442                 | BM_USBPHY_PWD_TXPWDV2I
 443                 | BM_USBPHY_PWD_RXPWDENV
 444                 | BM_USBPHY_PWD_RXPWD1PT1
 445                 | BM_USBPHY_PWD_RXPWDDIFF
 446                 | BM_USBPHY_PWD_RXPWDRX);
 447         __raw_writel(tmp, phy_reg + HW_USBPHY_PWD_SET);
 448
 449         __raw_writel(tmp, phy_reg + HW_USBPHY_PWD_CLR);
 450
 451         fsl_platform_otg_set_usb_phy_dis(pdata, 0);
 452 }
 453
 454 static void _host_platform_rh_resume_swfix(struct fsl_usb2_platform_data *pdata)
 455 {
 456         u32 index = 0;
 457
 458         if ((UOG_PORTSC1 & (PORTSC_PORT_SPEED_MASK)) != PORTSC_PORT_SPEED_HIGH)
 459                 return ;
 460         while ((UOG_PORTSC1 & PORTSC_PORT_FORCE_RESUME)
 461                         && (index < 1000)) {
 462                 udelay(500);
 463                 index++;
 464         }
 465         if (index >= 1000)
 466                 printk(KERN_ERR "failed to wait for the resume finished in %s() line:%d\n",
 467                 __func__, __LINE__);
 468         /* We should add some delay to wait for the device switch to
 469           * High-Speed 45ohm termination resistors mode. */
 470         udelay(500);
 471         fsl_platform_otg_set_usb_phy_dis(pdata, 1);
 472 }
 473 static void _host_platform_rh_suspend(struct fsl_usb2_platform_data *pdata)
 474 {
 475         /*for mx6sl ,we do not need any sw fix*/
 476         if (cpu_is_mx6sl())
 477                 return ;
 478         __raw_writel(BM_USBPHY_CTRL_ENHOSTDISCONDETECT,
 479                 MX6_IO_ADDRESS(pdata->phy_regs)
 480                 + HW_USBPHY_CTRL_CLR);
 481 }
 482
 483 static void _host_platform_rh_resume(struct fsl_usb2_platform_data *pdata)
 484 {
 485         u32 index = 0;
 486
 487         /*for mx6sl ,we do not need any sw fix*/
 488         if (cpu_is_mx6sl())
 489                 return ;
 490         if ((UOG_PORTSC1 & (PORTSC_PORT_SPEED_MASK)) != PORTSC_PORT_SPEED_HIGH)
 491                 return ;
 492         while ((UOG_PORTSC1 & PORTSC_PORT_FORCE_RESUME)
 493                         && (index < 1000)) {
 494                 udelay(500);
 495                 index++;
 496         }
 497         if (index >= 1000)
 498                 printk(KERN_ERR "failed to wait for the resume finished in %s() line:%d\n",
 499                 __func__, __LINE__);
 500         /* We should add some delay to wait for the device switch to
 501           * High-Speed 45ohm termination resistors mode. */
 502         udelay(500);
 503         __raw_writel(BM_USBPHY_CTRL_ENHOSTDISCONDETECT,
 504                 MX6_IO_ADDRESS(pdata->phy_regs)
 505                 + HW_USBPHY_CTRL_SET);
 506 }
 507
 508 static void _host_phy_lowpower_suspend(struct fsl_usb2_platform_data *pdata, bool enable)
 509 {
 510         __phy_lowpower_suspend(pdata, enable, ENABLED_BY_HOST);
 511 }
 512
 513 static void _host_wakeup_enable(struct fsl_usb2_platform_data *pdata, bool enable)
 514 {
 515         void __iomem *phy_reg = MX6_IO_ADDRESS(USB_PHY0_BASE_ADDR);
 516         __wakeup_irq_enable(pdata, enable, ENABLED_BY_HOST);
 517         if (enable) {
 518                 pr_debug("host wakeup enable\n");
 519                 USB_OTG_CTRL |= UCTRL_WKUP_ID_EN;
 520                 __raw_writel(BM_USBPHY_CTRL_ENIDCHG_WKUP, phy_reg + HW_USBPHY_CTRL_SET);
 521         } else {
 522                 pr_debug("host wakeup disable\n");
 523                 __raw_writel(BM_USBPHY_CTRL_ENIDCHG_WKUP, phy_reg + HW_USBPHY_CTRL_CLR);
 524                 USB_OTG_CTRL &= ~UCTRL_WKUP_ID_EN;
 525                 /* The interrupt must be disabled for at least 3 clock
 526                  * cycles of the standby clock(32k Hz) , that is 0.094 ms*/
 527                 udelay(100);
 528         }
 529         pr_debug("the otgsc is 0x%x, usbsts is 0x%x, portsc is 0x%x, otgctrl: 0x%x\n", UOG_OTGSC, UOG_USBSTS, UOG_PORTSC1, USB_OTG_CTRL);
 530 }
 531
 532 static enum usb_wakeup_event _is_host_wakeup(struct fsl_usb2_platform_data *pdata)
 533 {
 534         u32 wakeup_req = USB_OTG_CTRL & UCTRL_OWIR;
 535         u32 otgsc = UOG_OTGSC;
 536
 537         if (wakeup_req) {
 538                 pr_debug("the otgsc is 0x%x, usbsts is 0x%x, portsc is 0x%x, wakeup_irq is 0x%x\n", UOG_OTGSC, UOG_USBSTS, UOG_PORTSC1, wakeup_req);
 539         }
 540         /* if ID change sts, it is a host wakeup event */
 541         if (otgsc & OTGSC_IS_USB_ID) {
 542                 pr_debug("otg host ID wakeup\n");
 543                 /* if host ID wakeup, we must clear the ID change sts */
 544                 otgsc |= OTGSC_IS_USB_ID;
 545                 return WAKEUP_EVENT_ID;
 546         }
 547         if (wakeup_req  && (!(otgsc & OTGSC_STS_USB_ID))) {
 548                 pr_debug("otg host Remote wakeup\n");
 549                 return WAKEUP_EVENT_DPDM;
 550         }
 551         return WAKEUP_EVENT_INVALID;
 552 }
 553
 554 static void host_wakeup_handler(struct fsl_usb2_platform_data *pdata)
 555 {
 556         _host_phy_lowpower_suspend(pdata, false);
 557         _host_wakeup_enable(pdata, false);
 558 }
 559 /* End of host related operation for DR port */
 560 #endif /* CONFIG_USB_EHCI_ARC_OTG */
 561
 562
 563 #ifdef CONFIG_USB_GADGET_ARC
 564 /* Beginning of device related operation for DR port */
 565 static void _device_phy_lowpower_suspend(struct fsl_usb2_platform_data *pdata, bool enable)
 566 {
 567         __phy_lowpower_suspend(pdata, enable, ENABLED_BY_DEVICE);
 568 }
 569
 570 static void _device_wakeup_enable(struct fsl_usb2_platform_data *pdata, bool enable)
 571 {
 572         void __iomem *phy_reg = MX6_IO_ADDRESS(USB_PHY0_BASE_ADDR);
 573         __wakeup_irq_enable(pdata, enable, ENABLED_BY_DEVICE);
 574         /* if udc is not used by any gadget, we can not enable the vbus wakeup */
 575         if (!pdata->port_enables) {
 576                 USB_OTG_CTRL &= ~UCTRL_WKUP_VBUS_EN;
 577                 return;
 578         }
 579         if (enable) {
 580                 pr_debug("device wakeup enable\n");
 581                 USB_OTG_CTRL |= UCTRL_WKUP_VBUS_EN;
 582                 __raw_writel(BM_USBPHY_CTRL_ENVBUSCHG_WKUP, phy_reg + HW_USBPHY_CTRL_SET);
 583         } else {
 584                 pr_debug("device wakeup disable\n");
 585                 __raw_writel(BM_USBPHY_CTRL_ENVBUSCHG_WKUP, phy_reg + HW_USBPHY_CTRL_CLR);
 586                 USB_OTG_CTRL &= ~UCTRL_WKUP_VBUS_EN;
 587         }
 588 }
 589
 590 static enum usb_wakeup_event _is_device_wakeup(struct fsl_usb2_platform_data *pdata)
 591 {
 592         int wakeup_req = USB_OTG_CTRL & UCTRL_OWIR;
 593         pr_debug("%s\n", __func__);
 594
 595         /* if ID=1, it is a device wakeup event */
 596         if (wakeup_req && (UOG_OTGSC & OTGSC_STS_USB_ID) && (UOG_USBSTS & USBSTS_URI)) {
 597                 printk(KERN_INFO "otg udc wakeup, host sends reset signal\n");
 598                 return WAKEUP_EVENT_DPDM;
 599         }
 600         if (wakeup_req && (UOG_OTGSC & OTGSC_STS_USB_ID) &&  \
 601                 ((UOG_USBSTS & USBSTS_PCI) || (UOG_PORTSC1 & PORTSC_PORT_FORCE_RESUME))) {
 602                 /*
 603                  * When the line state from J to K, the Port Change Detect bit
 604                  * in the USBSTS register is also set to '1'.
 605                  */
 606                 printk(KERN_INFO "otg udc wakeup, host sends resume signal\n");
 607                 return WAKEUP_EVENT_DPDM;
 608         }
 609         if (wakeup_req && (UOG_OTGSC & OTGSC_STS_USB_ID) && (UOG_OTGSC & OTGSC_STS_A_VBUS_VALID) \
 610                 && (UOG_OTGSC & OTGSC_IS_B_SESSION_VALID)) {
 611                 printk(KERN_INFO "otg udc vbus rising wakeup\n");
 612                 return WAKEUP_EVENT_VBUS;
 613         }
 614         if (wakeup_req && (UOG_OTGSC & OTGSC_STS_USB_ID) && !(UOG_OTGSC & OTGSC_STS_A_VBUS_VALID)) {
 615                 printk(KERN_INFO "otg udc vbus falling wakeup\n");
 616                 return WAKEUP_EVENT_VBUS;
 617         }
 618
 619         return WAKEUP_EVENT_INVALID;
 620 }
 621
 622 static void device_wakeup_handler(struct fsl_usb2_platform_data *pdata)
 623 {
 624         _device_phy_lowpower_suspend(pdata, false);
 625         _device_wakeup_enable(pdata, false);
 626 }
 627
 628 /* end of device related operation for DR port */
 629 #endif /* CONFIG_USB_GADGET_ARC */
 630
 631 static struct platform_device *pdev[3], *pdev_wakeup;
 632 static driver_vbus_func  mx6_set_usb_otg_vbus;
 633 static int devnum;
 634 static int  __init mx6_usb_dr_init(void)
 635 {
 636         int i = 0;
 637         void __iomem *anatop_base_addr = MX6_IO_ADDRESS(ANATOP_BASE_ADDR);
 638         struct imx_fsl_usb2_wakeup_data imx6q_fsl_otg_wakeup_data =
 639                 imx_fsl_usb2_wakeup_data_entry_single(MX6Q, 0, OTG);
 640         struct imx_mxc_ehci_data __maybe_unused imx6q_mxc_ehci_otg_data =
 641                 imx_mxc_ehci_data_entry_single(MX6Q, 0, OTG);
 642         struct imx_fsl_usb2_udc_data __maybe_unused imx6q_fsl_usb2_udc_data =
 643                 imx_fsl_usb2_udc_data_entry_single(MX6Q);
 644         struct imx_fsl_usb2_otg_data __maybe_unused imx6q_fsl_usb2_otg_data  =
 645                 imx_fsl_usb2_otg_data_entry_single(MX6Q);
 646
 647         /* Some phy and power's special controls for otg
 648          * 1. The external charger detector needs to be disabled
 649          * or the signal at DP will be poor
 650          * 2. The EN_USB_CLKS is always enabled.
 651          * The PLL's power is controlled by usb and others who
 652          * use pll3 too.
 653          */
 654         __raw_writel(BM_ANADIG_USB1_CHRG_DETECT_EN_B  \
 655                         | BM_ANADIG_USB1_CHRG_DETECT_CHK_CHRG_B,  \
 656                         anatop_base_addr + HW_ANADIG_USB1_CHRG_DETECT);
 657         __raw_writel(BM_ANADIG_USB1_PLL_480_CTRL_EN_USB_CLKS,
 658                         anatop_base_addr + HW_ANADIG_USB1_PLL_480_CTRL_SET);
 659         mx6_get_otghost_vbus_func(&mx6_set_usb_otg_vbus);
 660         dr_utmi_config.platform_driver_vbus = mx6_set_usb_otg_vbus;
 661
 662 #ifdef CONFIG_USB_OTG
 663         /* wake_up_enable is useless, just for usb_register_remote_wakeup execution*/
 664         dr_utmi_config.wake_up_enable = _device_wakeup_enable;
 665         dr_utmi_config.operating_mode = FSL_USB2_DR_OTG;
 666         dr_utmi_config.wakeup_pdata = &dr_wakeup_config;
 667         pdev[i] = imx6q_add_fsl_usb2_otg(&dr_utmi_config);
 668         dr_wakeup_config.usb_pdata[i] = pdev[i]->dev.platform_data;
 669         i++;
 670 #endif
 671 #ifdef CONFIG_USB_EHCI_ARC_OTG
 672         dr_utmi_config.operating_mode = DR_HOST_MODE;
 673         dr_utmi_config.wake_up_enable = _host_wakeup_enable;
 674         if (usb_icbug_swfix_need()) {
 675                 dr_utmi_config.platform_rh_suspend = _host_platform_rh_suspend_swfix;
 676                 dr_utmi_config.platform_rh_resume  = _host_platform_rh_resume_swfix;
 677         } else {
 678                 dr_utmi_config.platform_rh_suspend = _host_platform_rh_suspend;
 679                 dr_utmi_config.platform_rh_resume  = _host_platform_rh_resume;
 680         }
 681         dr_utmi_config.platform_set_disconnect_det = fsl_platform_otg_set_usb_phy_dis;
 682         dr_utmi_config.phy_lowpower_suspend = _host_phy_lowpower_suspend;
 683         dr_utmi_config.is_wakeup_event = _is_host_wakeup;
 684         dr_utmi_config.wakeup_pdata = &dr_wakeup_config;
 685         dr_utmi_config.wakeup_handler = host_wakeup_handler;
 686         dr_utmi_config.platform_phy_power_on = dr_platform_phy_power_on;
 687         pdev[i] = imx6q_add_fsl_ehci_otg(&dr_utmi_config);
 688         dr_wakeup_config.usb_pdata[i] = pdev[i]->dev.platform_data;
 689         i++;
 690 #endif
 691 #ifdef CONFIG_USB_GADGET_ARC
 692         dr_utmi_config.operating_mode = DR_UDC_MODE;
 693         dr_utmi_config.wake_up_enable = _device_wakeup_enable;
 694         dr_utmi_config.platform_rh_suspend = NULL;
 695         dr_utmi_config.platform_rh_resume  = NULL;
 696         dr_utmi_config.platform_set_disconnect_det = NULL;
 697         dr_utmi_config.phy_lowpower_suspend = _device_phy_lowpower_suspend;
 698         dr_utmi_config.is_wakeup_event = _is_device_wakeup;
 699         dr_utmi_config.wakeup_pdata = &dr_wakeup_config;
 700         dr_utmi_config.wakeup_handler = device_wakeup_handler;
 701         dr_utmi_config.charger_base_addr = anatop_base_addr;
 702         dr_utmi_config.platform_phy_power_on = dr_platform_phy_power_on;
 703         pdev[i] = imx6q_add_fsl_usb2_udc(&dr_utmi_config);
 704         dr_wakeup_config.usb_pdata[i] = pdev[i]->dev.platform_data;
 705         i++;
 706 #endif
 707         devnum = i;
 708         /* register wakeup device */
 709         pdev_wakeup = imx6q_add_fsl_usb2_otg_wakeup(&dr_wakeup_config);
 710         for (i = 0; i < devnum; i++) {
 711                 platform_device_add(pdev[i]);
 712                 ((struct fsl_usb2_platform_data *)(pdev[i]->dev.platform_data))->wakeup_pdata =
 713                         (struct fsl_usb2_wakeup_platform_data *)(pdev_wakeup->dev.platform_data);
 714         }
 715
 716         return 0;
 717 }
 718 module_init(mx6_usb_dr_init);
 719
 720 static void __exit mx6_usb_dr_exit(void)
 721 {
 722         int i;
 723         void __iomem *anatop_base_addr = MX6_IO_ADDRESS(ANATOP_BASE_ADDR);
 724
 725         for (i = 0; i < devnum; i++)
 726                 platform_device_del(pdev[devnum-i-1]);
 727         platform_device_unregister(pdev_wakeup);
 728         otg_used = 0;
 729
 730         __raw_writel(BM_ANADIG_USB1_PLL_480_CTRL_EN_USB_CLKS,
 731                         anatop_base_addr + HW_ANADIG_USB1_PLL_480_CTRL_CLR);
 732         return ;
 733 }
 734 module_exit(mx6_usb_dr_exit);
 735
 736 MODULE_AUTHOR("Freescale Semiconductor");
 737 MODULE_LICENSE("GPL");