2 * Copyright (C) 2013 Freescale Semiconductor, Inc. All Rights Reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 #include <linux/kernel.h>
20 #include <linux/types.h>
21 #include <linux/clk.h>
22 #include <linux/platform_device.h>
23 #include <linux/fsl_devices.h>
24 #include <linux/delay.h>
26 #include <mach/arc_otg.h>
27 #include <mach/hardware.h>
28 #include "devices-imx6q.h"
29 #include "regs-anadig.h"
32 DEFINE_MUTEX(otg_wakeup_enable_mutex);
33 static int usbotg_init_ext(struct platform_device *pdev);
34 static void usbotg_uninit_ext(struct platform_device *pdev);
35 static void usbotg_clock_gate(bool on);
36 static void _dr_discharge_line(bool enable);
37 extern bool usb_icbug_swfix_need(void);
38 static void enter_phy_lowpower_suspend(struct fsl_usb2_platform_data *pdata, \
40 static u32 wakeup_irq_enable_src; /* only useful at otg mode */
41 static u32 low_power_enable_src; /* only useful at otg mode */
43 /* The usb_phy1_clk do not have enable/disable function at clock.c
44 * and PLL output for usb1's phy should be always enabled.
45 * usb_phy1_clk only stands for usb uses pll3 as its parent.
47 static struct clk *usb_phy1_clk;
48 static struct clk *usb_oh3_clk;
51 static void usbotg_wakeup_event_clear(void);
52 extern int clk_get_usecount(struct clk *clk);
53 /* Beginning of Common operation for DR port */
56 * platform data structs
57 * - Which one to use is determined by CONFIG options in usb.h
58 * - operating_mode plugged at run time
60 static struct fsl_usb2_platform_data dr_utmi_config = {
62 .init = usbotg_init_ext,
63 .exit = usbotg_uninit_ext,
64 .phy_mode = FSL_USB2_PHY_UTMI_WIDE,
65 .power_budget = 500, /* 500 mA max power */
66 .usb_clock_for_pm = usbotg_clock_gate,
67 .transceiver = "utmi",
68 .phy_regs = USB_PHY0_BASE_ADDR,
69 .dr_discharge_line = _dr_discharge_line,
70 .lowpower = true, /* Default driver low power is true */
73 /* Platform data for wakeup operation */
74 static struct fsl_usb2_wakeup_platform_data dr_wakeup_config = {
76 .usb_clock_for_pm = usbotg_clock_gate,
77 .usb_wakeup_exhandle = usbotg_wakeup_event_clear,
80 static void usbotg_internal_phy_clock_gate(bool on)
82 void __iomem *phy_reg = MX6_IO_ADDRESS(USB_PHY0_BASE_ADDR);
84 __raw_writel(BM_USBPHY_CTRL_CLKGATE, phy_reg + HW_USBPHY_CTRL_CLR);
86 __raw_writel(BM_USBPHY_CTRL_CLKGATE, phy_reg + HW_USBPHY_CTRL_SET);
90 static int usb_phy_enable(struct fsl_usb2_platform_data *pdata)
93 void __iomem *phy_reg = MX6_IO_ADDRESS(USB_PHY0_BASE_ADDR);
94 void __iomem *phy_ctrl;
97 UOG_USBCMD &= ~UCMD_RUN_STOP;
98 while (UOG_USBCMD & UCMD_RUN_STOP)
101 UOG_USBCMD |= UCMD_RESET;
102 while ((UOG_USBCMD) & (UCMD_RESET))
106 * If the controller reset does not put the PHY be out of
107 * low power mode, do it manually.
109 if (UOG_PORTSC1 & PORTSC_PHCD) {
110 UOG_PORTSC1 &= ~PORTSC_PHCD;
114 /* Reset USBPHY module */
115 phy_ctrl = phy_reg + HW_USBPHY_CTRL;
116 tmp = __raw_readl(phy_ctrl);
117 tmp |= BM_USBPHY_CTRL_SFTRST;
118 __raw_writel(tmp, phy_ctrl);
121 /* Remove CLKGATE and SFTRST */
122 tmp = __raw_readl(phy_ctrl);
123 tmp &= ~(BM_USBPHY_CTRL_CLKGATE | BM_USBPHY_CTRL_SFTRST);
124 __raw_writel(tmp, phy_ctrl);
127 /* Power up the PHY */
128 __raw_writel(0, phy_reg + HW_USBPHY_PWD);
129 if ((pdata->operating_mode == FSL_USB2_DR_HOST) ||
130 (pdata->operating_mode == FSL_USB2_DR_OTG)) {
131 /* enable FS/LS device */
132 __raw_writel(BM_USBPHY_CTRL_ENUTMILEVEL2 | BM_USBPHY_CTRL_ENUTMILEVEL3
133 , phy_reg + HW_USBPHY_CTRL_SET);
136 if (!usb_icbug_swfix_need())
137 __raw_writel((1 << 17), phy_reg + HW_USBPHY_IP_SET);
139 __raw_writel((1 << 18), phy_reg + HW_USBPHY_IP_SET);
142 /* Notes: configure USB clock*/
143 static int usbotg_init_ext(struct platform_device *pdev)
148 /* at mx6q: this clock is AHB clock for usb core */
149 usb_clk = clk_get(NULL, "usboh3_clk");
151 usb_oh3_clk = usb_clk;
153 usb_clk = clk_get(NULL, "usb_phy1_clk");
155 usb_phy1_clk = usb_clk;
157 ret = usbotg_init(pdev);
159 clk_disable(usb_oh3_clk);
160 clk_put(usb_oh3_clk);
161 clk_disable(usb_phy1_clk);
162 clk_put(usb_phy1_clk);
163 printk(KERN_ERR "otg init fails......\n");
167 wakeup_irq_enable_src = 0;
168 low_power_enable_src = 0;
169 usb_phy_enable(pdev->dev.platform_data);
170 enter_phy_lowpower_suspend(pdev->dev.platform_data, false);
171 /*after the phy reset,can not read the readingvalue for id/vbus at
172 * the register of otgsc ,cannot read at once ,need delay 3 ms
181 static void usbotg_uninit_ext(struct platform_device *pdev)
185 clk_put(usb_phy1_clk);
186 clk_put(usb_oh3_clk);
190 static void usbotg_clock_gate(bool on)
192 pr_debug("%s: on is %d\n", __func__, on);
194 clk_enable(usb_oh3_clk);
195 clk_enable(usb_phy1_clk);
197 clk_disable(usb_phy1_clk);
198 clk_disable(usb_oh3_clk);
200 pr_debug("usb_oh3_clk:%d, usb_phy_clk1_ref_count:%d\n", clk_get_usecount(usb_oh3_clk), clk_get_usecount(usb_phy1_clk));
203 static void dr_platform_phy_power_on(void)
205 void __iomem *anatop_base_addr = MX6_IO_ADDRESS(ANATOP_BASE_ADDR);
206 __raw_writel(BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG,
207 anatop_base_addr + HW_ANADIG_ANA_MISC0_SET);
211 static void _dr_discharge_line(bool enable)
213 void __iomem *anatop_base_addr = MX6_IO_ADDRESS(ANATOP_BASE_ADDR);
214 void __iomem *phy_reg = MX6_IO_ADDRESS(USB_PHY0_BASE_ADDR);
216 pr_debug("DR: %s enable is %d\n", __func__, enable);
218 __raw_writel(BM_USBPHY_DEBUG_CLKGATE, phy_reg + HW_USBPHY_DEBUG_CLR);
219 __raw_writel(BM_ANADIG_USB1_LOOPBACK_UTMI_DIG_TST1
220 |BM_ANADIG_USB1_LOOPBACK_TSTI_TX_EN,
221 anatop_base_addr + HW_ANADIG_USB1_LOOPBACK);
224 anatop_base_addr + HW_ANADIG_USB1_LOOPBACK);
225 __raw_writel(BM_USBPHY_DEBUG_CLKGATE, phy_reg + HW_USBPHY_DEBUG_SET);
229 /* Below two macros are used at otg mode to indicate usb mode*/
230 #define ENABLED_BY_HOST (0x1 << 0)
231 #define ENABLED_BY_DEVICE (0x1 << 1)
232 static void enter_phy_lowpower_suspend(struct fsl_usb2_platform_data *pdata, bool enable)
234 void __iomem *phy_reg = MX6_IO_ADDRESS(USB_PHY0_BASE_ADDR);
236 pr_debug("DR: %s begins, enable is %d\n", __func__, enable);
239 UOG_PORTSC1 |= PORTSC_PHCD;
240 tmp = (BM_USBPHY_PWD_TXPWDFS
241 | BM_USBPHY_PWD_TXPWDIBIAS
242 | BM_USBPHY_PWD_TXPWDV2I
243 | BM_USBPHY_PWD_RXPWDENV
244 | BM_USBPHY_PWD_RXPWD1PT1
245 | BM_USBPHY_PWD_RXPWDDIFF
246 | BM_USBPHY_PWD_RXPWDRX);
247 __raw_writel(tmp, phy_reg + HW_USBPHY_PWD_SET);
248 usbotg_internal_phy_clock_gate(false);
251 if (UOG_PORTSC1 & PORTSC_PHCD) {
252 UOG_PORTSC1 &= ~PORTSC_PHCD;
255 usbotg_internal_phy_clock_gate(true);
256 tmp = (BM_USBPHY_PWD_TXPWDFS
257 | BM_USBPHY_PWD_TXPWDIBIAS
258 | BM_USBPHY_PWD_TXPWDV2I
259 | BM_USBPHY_PWD_RXPWDENV
260 | BM_USBPHY_PWD_RXPWD1PT1
261 | BM_USBPHY_PWD_RXPWDDIFF
262 | BM_USBPHY_PWD_RXPWDRX);
263 __raw_writel(tmp, phy_reg + HW_USBPHY_PWD_CLR);
265 * The PHY works at 32Khz clock when it is at low power mode,
266 * it needs 10 clocks from 32Khz to normal work state, so
267 * 500us is the safe value for PHY enters stable status
268 * according to IC engineer.
270 * Besides, the digital value needs 1ms debounce time to
271 * wait the value to be stable. We have expected the
272 * value from OTGSC is correct after calling this API.
274 * So delay 2ms is a save value.
279 pr_debug("DR: %s ends, enable is %d\n", __func__, enable);
282 static void __phy_lowpower_suspend(struct fsl_usb2_platform_data *pdata, bool enable, int source)
285 low_power_enable_src |= source;
286 #ifdef CONFIG_USB_OTG
287 if (low_power_enable_src == (ENABLED_BY_HOST | ENABLED_BY_DEVICE)) {
288 pr_debug("phy lowpower enabled\n");
289 enter_phy_lowpower_suspend(pdata, enable);
292 enter_phy_lowpower_suspend(pdata, enable);
295 pr_debug("phy lowpower disable\n");
296 enter_phy_lowpower_suspend(pdata, enable);
297 low_power_enable_src &= ~source;
301 static void otg_wake_up_enable(struct fsl_usb2_platform_data *pdata, bool enable)
303 void __iomem *phy_reg = MX6_IO_ADDRESS(USB_PHY0_BASE_ADDR);
305 pr_debug("%s, enable is %d\n", __func__, enable);
307 __raw_writel(BM_USBPHY_CTRL_ENDPDMCHG_WKUP
308 | BM_USBPHY_CTRL_ENAUTOSET_USBCLKS
309 | BM_USBPHY_CTRL_ENAUTOCLR_PHY_PWD
310 | BM_USBPHY_CTRL_ENAUTOCLR_CLKGATE
311 | BM_USBPHY_CTRL_ENAUTOCLR_USBCLKGATE
312 | BM_USBPHY_CTRL_ENAUTO_PWRON_PLL , phy_reg + HW_USBPHY_CTRL_SET);
313 USB_OTG_CTRL |= UCTRL_OWIE;
315 __raw_writel(BM_USBPHY_CTRL_ENDPDMCHG_WKUP
316 | BM_USBPHY_CTRL_ENAUTOSET_USBCLKS
317 | BM_USBPHY_CTRL_ENAUTOCLR_PHY_PWD
318 | BM_USBPHY_CTRL_ENAUTOCLR_CLKGATE
319 | BM_USBPHY_CTRL_ENAUTOCLR_USBCLKGATE
320 | BM_USBPHY_CTRL_ENAUTO_PWRON_PLL , phy_reg + HW_USBPHY_CTRL_CLR);
321 USB_OTG_CTRL &= ~UCTRL_OWIE;
322 /* The interrupt must be disabled for at least 3 clock
323 * cycles of the standby clock(32k Hz) , that is 0.094 ms*/
328 static void __wakeup_irq_enable(struct fsl_usb2_platform_data *pdata, bool on, int source)
330 /* otg host and device share the OWIE bit, only when host and device
331 * all enable the wakeup irq, we can enable the OWIE bit
333 mutex_lock(&otg_wakeup_enable_mutex);
335 #ifdef CONFIG_USB_OTG
336 wakeup_irq_enable_src |= source;
337 if (wakeup_irq_enable_src == (ENABLED_BY_HOST | ENABLED_BY_DEVICE)) {
338 otg_wake_up_enable(pdata, on);
341 otg_wake_up_enable(pdata, on);
344 otg_wake_up_enable(pdata, on);
345 wakeup_irq_enable_src &= ~source;
346 /* The interrupt must be disabled for at least 3 clock
347 * cycles of the standby clock(32k Hz) , that is 0.094 ms*/
350 mutex_unlock(&otg_wakeup_enable_mutex);
353 /* The wakeup operation for DR port, it will clear the wakeup irq status
354 * and re-enable the wakeup
356 static void usbotg_wakeup_event_clear(void)
358 int wakeup_req = USB_OTG_CTRL & UCTRL_OWIR;
360 if (wakeup_req != 0) {
361 printk(KERN_INFO "Unknown wakeup.(OTGSC 0x%x)\n", UOG_OTGSC);
362 /* Disable OWIE to clear OWIR, wait 3 clock
363 * cycles of standly clock(32KHz)
365 USB_OTG_CTRL &= ~UCTRL_OWIE;
367 USB_OTG_CTRL |= UCTRL_OWIE;
371 /* End of Common operation for DR port */
373 #ifdef CONFIG_USB_EHCI_ARC_OTG
374 /* Beginning of host related operation for DR port */
375 static void fsl_platform_otg_set_usb_phy_dis(
376 struct fsl_usb2_platform_data *pdata, bool enable)
378 u32 usb_phy_ctrl_dcdt = 0;
379 void __iomem *anatop_base_addr = MX6_IO_ADDRESS(ANATOP_BASE_ADDR);
380 usb_phy_ctrl_dcdt = __raw_readl(
381 MX6_IO_ADDRESS(pdata->phy_regs) + HW_USBPHY_CTRL) &
382 BM_USBPHY_CTRL_ENHOSTDISCONDETECT;
384 if (usb_phy_ctrl_dcdt == 0) {
385 __raw_writel(BM_ANADIG_USB1_PLL_480_CTRL_EN_USB_CLKS,
386 anatop_base_addr + HW_ANADIG_USB1_PLL_480_CTRL_CLR);
388 __raw_writel(BM_USBPHY_PWD_RXPWDENV,
389 MX6_IO_ADDRESS(pdata->phy_regs) + HW_USBPHY_PWD_SET);
393 __raw_writel(BM_USBPHY_CTRL_ENHOSTDISCONDETECT,
394 MX6_IO_ADDRESS(pdata->phy_regs)
395 + HW_USBPHY_CTRL_SET);
397 UOG_USBSTS |= (1 << 7);
399 while ((UOG_USBSTS & (1 << 7)) == 0)
404 __raw_writel(BM_USBPHY_PWD_RXPWDENV,
405 MX6_IO_ADDRESS(pdata->phy_regs) + HW_USBPHY_PWD_CLR);
407 __raw_writel(BM_ANADIG_USB1_PLL_480_CTRL_EN_USB_CLKS,
408 anatop_base_addr + HW_ANADIG_USB1_PLL_480_CTRL_SET);
412 if (usb_phy_ctrl_dcdt
413 == BM_USBPHY_CTRL_ENHOSTDISCONDETECT)
414 __raw_writel(BM_USBPHY_CTRL_ENHOSTDISCONDETECT,
415 MX6_IO_ADDRESS(pdata->phy_regs)
416 + HW_USBPHY_CTRL_CLR);
420 static void _host_platform_rh_suspend_swfix(struct fsl_usb2_platform_data *pdata)
422 void __iomem *phy_reg = MX6_IO_ADDRESS(USB_PHY0_BASE_ADDR);
426 /* before we set and then clear PWD bit,
427 * we must wait LS to be suspend */
428 if ((UOG_PORTSC1 & (3 << 26)) != (1 << 26)) {
429 while (((UOG_PORTSC1 & PORTSC_LS_MASK) != PORTSC_LS_J_STATE) &&
435 while (((UOG_PORTSC1 & PORTSC_LS_MASK) != PORTSC_LS_K_STATE) &&
443 printk(KERN_INFO "%s big error\n", __func__);
445 tmp = (BM_USBPHY_PWD_TXPWDFS
446 | BM_USBPHY_PWD_TXPWDIBIAS
447 | BM_USBPHY_PWD_TXPWDV2I
448 | BM_USBPHY_PWD_RXPWDENV
449 | BM_USBPHY_PWD_RXPWD1PT1
450 | BM_USBPHY_PWD_RXPWDDIFF
451 | BM_USBPHY_PWD_RXPWDRX);
452 __raw_writel(tmp, phy_reg + HW_USBPHY_PWD_SET);
454 __raw_writel(tmp, phy_reg + HW_USBPHY_PWD_CLR);
456 fsl_platform_otg_set_usb_phy_dis(pdata, 0);
459 static void _host_platform_rh_resume_swfix(struct fsl_usb2_platform_data *pdata)
463 if ((UOG_PORTSC1 & (PORTSC_PORT_SPEED_MASK)) != PORTSC_PORT_SPEED_HIGH)
465 while ((UOG_PORTSC1 & PORTSC_PORT_FORCE_RESUME)
471 printk(KERN_ERR "failed to wait for the resume finished in %s() line:%d\n",
473 /* We should add some delay to wait for the device switch to
474 * High-Speed 45ohm termination resistors mode. */
476 fsl_platform_otg_set_usb_phy_dis(pdata, 1);
478 static void _host_platform_rh_suspend(struct fsl_usb2_platform_data *pdata)
480 /*for mx6sl ,we do not need any sw fix*/
483 __raw_writel(BM_USBPHY_CTRL_ENHOSTDISCONDETECT,
484 MX6_IO_ADDRESS(pdata->phy_regs)
485 + HW_USBPHY_CTRL_CLR);
488 static void _host_platform_rh_resume(struct fsl_usb2_platform_data *pdata)
492 /*for mx6sl ,we do not need any sw fix*/
495 if ((UOG_PORTSC1 & (PORTSC_PORT_SPEED_MASK)) != PORTSC_PORT_SPEED_HIGH)
497 while ((UOG_PORTSC1 & PORTSC_PORT_FORCE_RESUME)
503 printk(KERN_ERR "failed to wait for the resume finished in %s() line:%d\n",
505 /* We should add some delay to wait for the device switch to
506 * High-Speed 45ohm termination resistors mode. */
508 __raw_writel(BM_USBPHY_CTRL_ENHOSTDISCONDETECT,
509 MX6_IO_ADDRESS(pdata->phy_regs)
510 + HW_USBPHY_CTRL_SET);
513 static void _host_phy_lowpower_suspend(struct fsl_usb2_platform_data *pdata, bool enable)
515 __phy_lowpower_suspend(pdata, enable, ENABLED_BY_HOST);
518 static void _host_wakeup_enable(struct fsl_usb2_platform_data *pdata, bool enable)
520 void __iomem *phy_reg = MX6_IO_ADDRESS(USB_PHY0_BASE_ADDR);
521 __wakeup_irq_enable(pdata, enable, ENABLED_BY_HOST);
522 #ifdef CONFIG_USB_OTG
524 pr_debug("host wakeup enable\n");
525 USB_OTG_CTRL |= UCTRL_WKUP_ID_EN;
526 __raw_writel(BM_USBPHY_CTRL_ENIDCHG_WKUP, phy_reg + HW_USBPHY_CTRL_SET);
528 pr_debug("host wakeup disable\n");
529 __raw_writel(BM_USBPHY_CTRL_ENIDCHG_WKUP, phy_reg + HW_USBPHY_CTRL_CLR);
530 USB_OTG_CTRL &= ~UCTRL_WKUP_ID_EN;
531 /* The interrupt must be disabled for at least 3 clock
532 * cycles of the standby clock(32k Hz) , that is 0.094 ms*/
535 pr_debug("the otgsc is 0x%x, usbsts is 0x%x, portsc is 0x%x, otgctrl: 0x%x\n", UOG_OTGSC, UOG_USBSTS, UOG_PORTSC1, USB_OTG_CTRL);
539 static enum usb_wakeup_event _is_host_wakeup(struct fsl_usb2_platform_data *pdata)
541 u32 wakeup_req = USB_OTG_CTRL & UCTRL_OWIR;
542 u32 otgsc = UOG_OTGSC;
545 pr_debug("the otgsc is 0x%x, usbsts is 0x%x, portsc is 0x%x, wakeup_irq is 0x%x\n", UOG_OTGSC, UOG_USBSTS, UOG_PORTSC1, wakeup_req);
547 /* if ID change sts, it is a host wakeup event */
548 if (otgsc & OTGSC_IS_USB_ID) {
549 pr_debug("otg host ID wakeup\n");
550 return WAKEUP_EVENT_ID;
552 if (wakeup_req && (!(otgsc & OTGSC_STS_USB_ID))) {
553 pr_debug("otg host Remote wakeup\n");
554 return WAKEUP_EVENT_DPDM;
556 return WAKEUP_EVENT_INVALID;
559 static void host_wakeup_handler(struct fsl_usb2_platform_data *pdata)
561 _host_phy_lowpower_suspend(pdata, false);
562 _host_wakeup_enable(pdata, false);
564 /* End of host related operation for DR port */
565 #endif /* CONFIG_USB_EHCI_ARC_OTG */
568 #ifdef CONFIG_USB_GADGET_ARC
569 /* Beginning of device related operation for DR port */
570 static void _device_phy_lowpower_suspend(struct fsl_usb2_platform_data *pdata, bool enable)
572 __phy_lowpower_suspend(pdata, enable, ENABLED_BY_DEVICE);
575 static void _device_wakeup_enable(struct fsl_usb2_platform_data *pdata, bool enable)
577 void __iomem *phy_reg = MX6_IO_ADDRESS(USB_PHY0_BASE_ADDR);
578 __wakeup_irq_enable(pdata, enable, ENABLED_BY_DEVICE);
579 /* if udc is not used by any gadget, we can not enable the vbus wakeup */
580 if (!pdata->port_enables) {
581 USB_OTG_CTRL &= ~UCTRL_WKUP_VBUS_EN;
585 pr_debug("device wakeup enable\n");
586 USB_OTG_CTRL |= UCTRL_WKUP_VBUS_EN;
587 __raw_writel(BM_USBPHY_CTRL_ENVBUSCHG_WKUP, phy_reg + HW_USBPHY_CTRL_SET);
589 pr_debug("device wakeup disable\n");
590 __raw_writel(BM_USBPHY_CTRL_ENVBUSCHG_WKUP, phy_reg + HW_USBPHY_CTRL_CLR);
591 USB_OTG_CTRL &= ~UCTRL_WKUP_VBUS_EN;
595 static enum usb_wakeup_event _is_device_wakeup(struct fsl_usb2_platform_data *pdata)
597 int wakeup_req = USB_OTG_CTRL & UCTRL_OWIR;
598 pr_debug("%s\n", __func__);
600 /* if ID=1, it is a device wakeup event */
601 if (wakeup_req && (UOG_OTGSC & OTGSC_STS_USB_ID) && (UOG_USBSTS & USBSTS_URI)) {
602 printk(KERN_INFO "otg udc wakeup, host sends reset signal\n");
603 return WAKEUP_EVENT_DPDM;
605 if (wakeup_req && (UOG_OTGSC & OTGSC_STS_USB_ID) && \
606 ((UOG_USBSTS & USBSTS_PCI) || (UOG_PORTSC1 & PORTSC_PORT_FORCE_RESUME))) {
608 * When the line state from J to K, the Port Change Detect bit
609 * in the USBSTS register is also set to '1'.
611 printk(KERN_INFO "otg udc wakeup, host sends resume signal\n");
612 return WAKEUP_EVENT_DPDM;
614 if (wakeup_req && (UOG_OTGSC & OTGSC_STS_USB_ID) && (UOG_OTGSC & OTGSC_STS_A_VBUS_VALID) \
615 && (UOG_OTGSC & OTGSC_IS_B_SESSION_VALID)) {
616 printk(KERN_INFO "otg udc vbus rising wakeup\n");
617 return WAKEUP_EVENT_VBUS;
619 if (wakeup_req && (UOG_OTGSC & OTGSC_STS_USB_ID) && !(UOG_OTGSC & OTGSC_STS_A_VBUS_VALID)) {
620 printk(KERN_INFO "otg udc vbus falling wakeup\n");
621 return WAKEUP_EVENT_VBUS;
624 return WAKEUP_EVENT_INVALID;
627 static void device_wakeup_handler(struct fsl_usb2_platform_data *pdata)
629 _device_phy_lowpower_suspend(pdata, false);
630 _device_wakeup_enable(pdata, false);
633 /* end of device related operation for DR port */
634 #endif /* CONFIG_USB_GADGET_ARC */
636 static struct platform_device *pdev[3], *pdev_wakeup;
637 static driver_vbus_func mx6_set_usb_otg_vbus;
639 static int __init mx6_usb_dr_init(void)
642 void __iomem *anatop_base_addr = MX6_IO_ADDRESS(ANATOP_BASE_ADDR);
643 struct imx_fsl_usb2_wakeup_data imx6q_fsl_otg_wakeup_data =
644 imx_fsl_usb2_wakeup_data_entry_single(MX6Q, 0, OTG);
645 struct imx_mxc_ehci_data __maybe_unused imx6q_mxc_ehci_otg_data =
646 imx_mxc_ehci_data_entry_single(MX6Q, 0, OTG);
647 struct imx_fsl_usb2_udc_data __maybe_unused imx6q_fsl_usb2_udc_data =
648 imx_fsl_usb2_udc_data_entry_single(MX6Q);
649 struct imx_fsl_usb2_otg_data __maybe_unused imx6q_fsl_usb2_otg_data =
650 imx_fsl_usb2_otg_data_entry_single(MX6Q);
652 /* Some phy and power's special controls for otg
653 * 1. The external charger detector needs to be disabled
654 * or the signal at DP will be poor
655 * 2. The EN_USB_CLKS is always enabled.
656 * The PLL's power is controlled by usb and others who
659 __raw_writel(BM_ANADIG_USB1_CHRG_DETECT_EN_B \
660 | BM_ANADIG_USB1_CHRG_DETECT_CHK_CHRG_B, \
661 anatop_base_addr + HW_ANADIG_USB1_CHRG_DETECT);
662 __raw_writel(BM_ANADIG_USB1_PLL_480_CTRL_EN_USB_CLKS,
663 anatop_base_addr + HW_ANADIG_USB1_PLL_480_CTRL_SET);
664 mx6_get_otghost_vbus_func(&mx6_set_usb_otg_vbus);
665 dr_utmi_config.platform_driver_vbus = mx6_set_usb_otg_vbus;
667 #ifdef CONFIG_USB_OTG
668 /* wake_up_enable is useless, just for usb_register_remote_wakeup execution*/
669 dr_utmi_config.wake_up_enable = _device_wakeup_enable;
670 dr_utmi_config.operating_mode = FSL_USB2_DR_OTG;
671 dr_utmi_config.wakeup_pdata = &dr_wakeup_config;
672 pdev[i] = imx6q_add_fsl_usb2_otg(&dr_utmi_config);
673 dr_wakeup_config.usb_pdata[i] = pdev[i]->dev.platform_data;
676 #ifdef CONFIG_USB_EHCI_ARC_OTG
677 dr_utmi_config.operating_mode = DR_HOST_MODE;
678 dr_utmi_config.wake_up_enable = _host_wakeup_enable;
679 if (usb_icbug_swfix_need()) {
680 dr_utmi_config.platform_rh_suspend = _host_platform_rh_suspend_swfix;
681 dr_utmi_config.platform_rh_resume = _host_platform_rh_resume_swfix;
683 dr_utmi_config.platform_rh_suspend = _host_platform_rh_suspend;
684 dr_utmi_config.platform_rh_resume = _host_platform_rh_resume;
686 dr_utmi_config.platform_set_disconnect_det = fsl_platform_otg_set_usb_phy_dis;
687 dr_utmi_config.phy_lowpower_suspend = _host_phy_lowpower_suspend;
688 dr_utmi_config.is_wakeup_event = _is_host_wakeup;
689 dr_utmi_config.wakeup_pdata = &dr_wakeup_config;
690 dr_utmi_config.wakeup_handler = host_wakeup_handler;
691 dr_utmi_config.platform_phy_power_on = dr_platform_phy_power_on;
692 pdev[i] = imx6q_add_fsl_ehci_otg(&dr_utmi_config);
693 dr_wakeup_config.usb_pdata[i] = pdev[i]->dev.platform_data;
696 #ifdef CONFIG_USB_GADGET_ARC
697 dr_utmi_config.operating_mode = DR_UDC_MODE;
698 dr_utmi_config.wake_up_enable = _device_wakeup_enable;
699 dr_utmi_config.platform_rh_suspend = NULL;
700 dr_utmi_config.platform_rh_resume = NULL;
701 dr_utmi_config.platform_set_disconnect_det = NULL;
702 dr_utmi_config.phy_lowpower_suspend = _device_phy_lowpower_suspend;
703 dr_utmi_config.is_wakeup_event = _is_device_wakeup;
704 dr_utmi_config.wakeup_pdata = &dr_wakeup_config;
705 dr_utmi_config.wakeup_handler = device_wakeup_handler;
706 dr_utmi_config.charger_base_addr = anatop_base_addr;
707 dr_utmi_config.platform_phy_power_on = dr_platform_phy_power_on;
708 pdev[i] = imx6q_add_fsl_usb2_udc(&dr_utmi_config);
709 dr_wakeup_config.usb_pdata[i] = pdev[i]->dev.platform_data;
713 /* register wakeup device */
714 pdev_wakeup = imx6q_add_fsl_usb2_otg_wakeup(&dr_wakeup_config);
715 for (i = 0; i < devnum; i++) {
716 platform_device_add(pdev[i]);
717 ((struct fsl_usb2_platform_data *)(pdev[i]->dev.platform_data))->wakeup_pdata =
718 (struct fsl_usb2_wakeup_platform_data *)(pdev_wakeup->dev.platform_data);
723 module_init(mx6_usb_dr_init);
725 static void __exit mx6_usb_dr_exit(void)
728 void __iomem *anatop_base_addr = MX6_IO_ADDRESS(ANATOP_BASE_ADDR);
730 for (i = 0; i < devnum; i++)
731 platform_device_del(pdev[devnum-i-1]);
732 platform_device_unregister(pdev_wakeup);
735 __raw_writel(BM_ANADIG_USB1_PLL_480_CTRL_EN_USB_CLKS,
736 anatop_base_addr + HW_ANADIG_USB1_PLL_480_CTRL_CLR);
739 module_exit(mx6_usb_dr_exit);
741 MODULE_AUTHOR("Freescale Semiconductor");
742 MODULE_LICENSE("GPL");