2 * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
20 #include <linux/delay.h>
21 #include <linux/clk.h>
23 #include <linux/jiffies.h>
25 #include <asm/clkdev.h>
26 #include <asm/div64.h>
28 #include <mach/mx28.h>
29 #include <mach/common.h>
30 #include <mach/clock.h>
32 #include "regs-clkctrl-mx28.h"
34 #define CLKCTRL_BASE_ADDR MX28_IO_ADDRESS(MX28_CLKCTRL_BASE_ADDR)
35 #define DIGCTRL_BASE_ADDR MX28_IO_ADDRESS(MX28_DIGCTL_BASE_ADDR)
37 #define PARENT_RATE_SHIFT 8
39 static struct clk pll2_clk;
40 static struct clk cpu_clk;
41 static struct clk emi_clk;
42 static struct clk saif0_clk;
43 static struct clk saif1_clk;
44 static struct clk clk32k_clk;
46 static int _raw_clk_enable(struct clk *clk)
50 if (clk->enable_reg) {
51 reg = __raw_readl(clk->enable_reg);
52 reg &= ~(1 << clk->enable_shift);
53 __raw_writel(reg, clk->enable_reg);
59 static void _raw_clk_disable(struct clk *clk)
63 if (clk->enable_reg) {
64 reg = __raw_readl(clk->enable_reg);
65 reg |= 1 << clk->enable_shift;
66 __raw_writel(reg, clk->enable_reg);
73 static unsigned long ref_xtal_clk_get_rate(struct clk *clk)
78 static struct clk ref_xtal_clk = {
79 .get_rate = ref_xtal_clk_get_rate,
85 static unsigned long pll0_clk_get_rate(struct clk *clk)
90 static unsigned long pll1_clk_get_rate(struct clk *clk)
95 static unsigned long pll2_clk_get_rate(struct clk *clk)
100 #define _CLK_ENABLE_PLL(name, r, g) \
101 static int name##_enable(struct clk *clk) \
103 __raw_writel(BM_CLKCTRL_##r##CTRL0_POWER, \
104 CLKCTRL_BASE_ADDR + HW_CLKCTRL_##r##CTRL0_SET); \
107 if (clk == &pll2_clk) \
108 __raw_writel(BM_CLKCTRL_##r##CTRL0_##g, \
109 CLKCTRL_BASE_ADDR + HW_CLKCTRL_##r##CTRL0_CLR); \
111 __raw_writel(BM_CLKCTRL_##r##CTRL0_##g, \
112 CLKCTRL_BASE_ADDR + HW_CLKCTRL_##r##CTRL0_SET); \
117 _CLK_ENABLE_PLL(pll0_clk, PLL0, EN_USB_CLKS)
118 _CLK_ENABLE_PLL(pll1_clk, PLL1, EN_USB_CLKS)
119 _CLK_ENABLE_PLL(pll2_clk, PLL2, CLKGATE)
121 #define _CLK_DISABLE_PLL(name, r, g) \
122 static void name##_disable(struct clk *clk) \
124 __raw_writel(BM_CLKCTRL_##r##CTRL0_POWER, \
125 CLKCTRL_BASE_ADDR + HW_CLKCTRL_##r##CTRL0_CLR); \
127 if (clk == &pll2_clk) \
128 __raw_writel(BM_CLKCTRL_##r##CTRL0_##g, \
129 CLKCTRL_BASE_ADDR + HW_CLKCTRL_##r##CTRL0_SET); \
131 __raw_writel(BM_CLKCTRL_##r##CTRL0_##g, \
132 CLKCTRL_BASE_ADDR + HW_CLKCTRL_##r##CTRL0_CLR); \
136 _CLK_DISABLE_PLL(pll0_clk, PLL0, EN_USB_CLKS)
137 _CLK_DISABLE_PLL(pll1_clk, PLL1, EN_USB_CLKS)
138 _CLK_DISABLE_PLL(pll2_clk, PLL2, CLKGATE)
140 #define _DEFINE_CLOCK_PLL(name) \
141 static struct clk name = { \
142 .get_rate = name##_get_rate, \
143 .enable = name##_enable, \
144 .disable = name##_disable, \
145 .parent = &ref_xtal_clk, \
148 _DEFINE_CLOCK_PLL(pll0_clk);
149 _DEFINE_CLOCK_PLL(pll1_clk);
150 _DEFINE_CLOCK_PLL(pll2_clk);
155 #define _CLK_GET_RATE_REF(name, sr, ss) \
156 static unsigned long name##_get_rate(struct clk *clk) \
158 unsigned long parent_rate; \
161 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##sr); \
162 div = (reg >> BP_CLKCTRL_##sr##_##ss##FRAC) & 0x3f; \
163 parent_rate = clk_get_rate(clk->parent); \
165 return SH_DIV((parent_rate >> PARENT_RATE_SHIFT) * 18, \
166 div, PARENT_RATE_SHIFT); \
169 _CLK_GET_RATE_REF(ref_cpu_clk, FRAC0, CPU)
170 _CLK_GET_RATE_REF(ref_emi_clk, FRAC0, EMI)
171 _CLK_GET_RATE_REF(ref_io0_clk, FRAC0, IO0)
172 _CLK_GET_RATE_REF(ref_io1_clk, FRAC0, IO1)
173 _CLK_GET_RATE_REF(ref_pix_clk, FRAC1, PIX)
174 _CLK_GET_RATE_REF(ref_gpmi_clk, FRAC1, GPMI)
176 #define _DEFINE_CLOCK_REF(name, er, es) \
177 static struct clk name = { \
178 .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_##er, \
179 .enable_shift = BP_CLKCTRL_##er##_CLKGATE##es, \
180 .get_rate = name##_get_rate, \
181 .enable = _raw_clk_enable, \
182 .disable = _raw_clk_disable, \
183 .parent = &pll0_clk, \
186 _DEFINE_CLOCK_REF(ref_cpu_clk, FRAC0, CPU);
187 _DEFINE_CLOCK_REF(ref_emi_clk, FRAC0, EMI);
188 _DEFINE_CLOCK_REF(ref_io0_clk, FRAC0, IO0);
189 _DEFINE_CLOCK_REF(ref_io1_clk, FRAC0, IO1);
190 _DEFINE_CLOCK_REF(ref_pix_clk, FRAC1, PIX);
191 _DEFINE_CLOCK_REF(ref_gpmi_clk, FRAC1, GPMI);
198 static unsigned long lradc_clk_get_rate(struct clk *clk)
200 return clk_get_rate(clk->parent) / 16;
203 static unsigned long rtc_clk_get_rate(struct clk *clk)
205 /* ref_xtal_clk is implemented as the only parent */
206 return clk_get_rate(clk->parent) / 768;
209 static unsigned long clk32k_clk_get_rate(struct clk *clk)
211 return clk->parent->get_rate(clk->parent) / 750;
214 static unsigned long spdif_clk_get_rate(struct clk *clk)
216 return clk_get_rate(clk->parent) / 4;
219 #define _CLK_GET_RATE(name, rs) \
220 static unsigned long name##_get_rate(struct clk *clk) \
224 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs); \
226 if (clk->parent == &ref_xtal_clk) \
227 div = (reg & BM_CLKCTRL_##rs##_DIV_XTAL) >> \
228 BP_CLKCTRL_##rs##_DIV_XTAL; \
230 div = (reg & BM_CLKCTRL_##rs##_DIV_##rs) >> \
231 BP_CLKCTRL_##rs##_DIV_##rs; \
236 return clk_get_rate(clk->parent) / div; \
239 _CLK_GET_RATE(cpu_clk, CPU)
240 _CLK_GET_RATE(emi_clk, EMI)
242 #define _CLK_GET_RATE1(name, rs) \
243 static unsigned long name##_get_rate(struct clk *clk) \
247 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs); \
248 div = (reg & BM_CLKCTRL_##rs##_DIV) >> BP_CLKCTRL_##rs##_DIV; \
253 if (clk == &saif0_clk || clk == &saif1_clk) \
254 return clk_get_rate(clk->parent) >> 16 * div; \
256 return clk_get_rate(clk->parent) / div; \
259 _CLK_GET_RATE1(hbus_clk, HBUS)
260 _CLK_GET_RATE1(xbus_clk, XBUS)
261 _CLK_GET_RATE1(ssp0_clk, SSP0)
262 _CLK_GET_RATE1(ssp1_clk, SSP1)
263 _CLK_GET_RATE1(ssp2_clk, SSP2)
264 _CLK_GET_RATE1(ssp3_clk, SSP3)
265 _CLK_GET_RATE1(gpmi_clk, GPMI)
266 _CLK_GET_RATE1(lcdif_clk, DIS_LCDIF)
267 _CLK_GET_RATE1(saif0_clk, SAIF0)
268 _CLK_GET_RATE1(saif1_clk, SAIF1)
270 #define _CLK_GET_RATE_STUB(name) \
271 static unsigned long name##_get_rate(struct clk *clk) \
273 return clk_get_rate(clk->parent); \
276 _CLK_GET_RATE_STUB(uart_clk)
277 _CLK_GET_RATE_STUB(pwm_clk)
278 _CLK_GET_RATE_STUB(can0_clk)
279 _CLK_GET_RATE_STUB(can1_clk)
280 _CLK_GET_RATE_STUB(fec_clk)
286 #define BM_CLKCTRL_CPU_DIV 0
287 #define BP_CLKCTRL_CPU_DIV 0
288 #define BM_CLKCTRL_CPU_BUSY 0
290 #define _CLK_SET_RATE(name, dr, fr, fs) \
291 static int name##_set_rate(struct clk *clk, unsigned long rate) \
293 u32 reg, bm_busy, div_max, d, f, div, frac; \
294 unsigned long diff, parent_rate, calc_rate; \
297 parent_rate = clk_get_rate(clk->parent); \
298 div_max = BM_CLKCTRL_##dr##_DIV >> BP_CLKCTRL_##dr##_DIV; \
299 bm_busy = BM_CLKCTRL_##dr##_BUSY; \
301 if (clk->parent == &ref_xtal_clk) { \
302 div = DIV_ROUND_UP(parent_rate, rate); \
303 if (clk == &cpu_clk) { \
304 div_max = BM_CLKCTRL_CPU_DIV_XTAL >> \
305 BP_CLKCTRL_CPU_DIV_XTAL; \
306 bm_busy = BM_CLKCTRL_CPU_BUSY_REF_XTAL; \
308 if (div == 0 || div > div_max) \
311 rate >>= PARENT_RATE_SHIFT; \
312 parent_rate >>= PARENT_RATE_SHIFT; \
313 diff = parent_rate; \
315 if (clk == &cpu_clk) { \
316 div_max = BM_CLKCTRL_CPU_DIV_CPU >> \
317 BP_CLKCTRL_CPU_DIV_CPU; \
318 bm_busy = BM_CLKCTRL_CPU_BUSY_REF_CPU; \
320 for (d = 1; d <= div_max; d++) { \
321 f = parent_rate * 18 / d / rate; \
322 if ((parent_rate * 18 / d) % rate) \
324 if (f < 18 || f > 35) \
327 calc_rate = parent_rate * 18 / f / d; \
328 if (calc_rate > rate) \
331 if (rate - calc_rate < diff) { \
334 diff = rate - calc_rate; \
341 if (diff == parent_rate) \
344 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##fr); \
345 reg &= ~BM_CLKCTRL_##fr##_##fs##FRAC; \
347 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_##fr); \
350 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##dr); \
351 if (clk == &cpu_clk) { \
352 reg &= ~BM_CLKCTRL_CPU_DIV_CPU; \
353 reg |= div << BP_CLKCTRL_CPU_DIV_CPU; \
355 reg &= ~BM_CLKCTRL_##dr##_DIV; \
356 reg |= div << BP_CLKCTRL_##dr##_DIV; \
357 if (reg | (1 << clk->enable_shift)) { \
358 pr_err("%s: clock is gated\n", __func__); \
362 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU); \
364 for (i = 10000; i; i--) \
365 if (!(__raw_readl(CLKCTRL_BASE_ADDR + \
366 HW_CLKCTRL_##dr) & bm_busy)) \
369 pr_err("%s: divider writing timeout\n", __func__); \
376 _CLK_SET_RATE(cpu_clk, CPU, FRAC0, CPU)
377 _CLK_SET_RATE(ssp0_clk, SSP0, FRAC0, IO0)
378 _CLK_SET_RATE(ssp1_clk, SSP1, FRAC0, IO0)
379 _CLK_SET_RATE(ssp2_clk, SSP2, FRAC0, IO1)
380 _CLK_SET_RATE(ssp3_clk, SSP3, FRAC0, IO1)
381 _CLK_SET_RATE(lcdif_clk, DIS_LCDIF, FRAC1, PIX)
382 _CLK_SET_RATE(gpmi_clk, GPMI, FRAC1, GPMI)
384 #define _CLK_SET_RATE1(name, dr) \
385 static int name##_set_rate(struct clk *clk, unsigned long rate) \
387 u32 reg, div_max, div; \
388 unsigned long parent_rate; \
391 parent_rate = clk_get_rate(clk->parent); \
392 div_max = BM_CLKCTRL_##dr##_DIV >> BP_CLKCTRL_##dr##_DIV; \
394 div = DIV_ROUND_UP(parent_rate, rate); \
395 if (div == 0 || div > div_max) \
398 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##dr); \
399 reg &= ~BM_CLKCTRL_##dr##_DIV; \
400 reg |= div << BP_CLKCTRL_##dr##_DIV; \
401 if (reg | (1 << clk->enable_shift)) { \
402 pr_err("%s: clock is gated\n", __func__); \
405 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_##dr); \
407 for (i = 10000; i; i--) \
408 if (!(__raw_readl(CLKCTRL_BASE_ADDR + \
409 HW_CLKCTRL_##dr) & BM_CLKCTRL_##dr##_BUSY)) \
412 pr_err("%s: divider writing timeout\n", __func__); \
419 _CLK_SET_RATE1(xbus_clk, XBUS)
421 /* saif clock uses 16 bits frac div */
422 #define _CLK_SET_RATE_SAIF(name, rs) \
423 static int name##_set_rate(struct clk *clk, unsigned long rate) \
428 unsigned long parent_rate; \
431 parent_rate = clk_get_rate(clk->parent); \
432 if (rate > parent_rate) \
435 lrate = (u64)rate << 16; \
436 do_div(lrate, parent_rate); \
442 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs); \
443 reg &= ~BM_CLKCTRL_##rs##_DIV; \
444 reg |= div << BP_CLKCTRL_##rs##_DIV; \
445 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs); \
447 for (i = 10000; i; i--) \
448 if (!(__raw_readl(CLKCTRL_BASE_ADDR + \
449 HW_CLKCTRL_##rs) & BM_CLKCTRL_##rs##_BUSY)) \
452 pr_err("%s: divider writing timeout\n", __func__); \
459 _CLK_SET_RATE_SAIF(saif0_clk, SAIF0)
460 _CLK_SET_RATE_SAIF(saif1_clk, SAIF1)
462 #define _CLK_SET_RATE_STUB(name) \
463 static int name##_set_rate(struct clk *clk, unsigned long rate) \
468 _CLK_SET_RATE_STUB(emi_clk)
469 _CLK_SET_RATE_STUB(uart_clk)
470 _CLK_SET_RATE_STUB(pwm_clk)
471 _CLK_SET_RATE_STUB(spdif_clk)
472 _CLK_SET_RATE_STUB(clk32k_clk)
473 _CLK_SET_RATE_STUB(can0_clk)
474 _CLK_SET_RATE_STUB(can1_clk)
475 _CLK_SET_RATE_STUB(fec_clk)
480 #define _CLK_SET_PARENT(name, bit) \
481 static int name##_set_parent(struct clk *clk, struct clk *parent) \
483 if (parent != clk->parent) { \
484 __raw_writel(BM_CLKCTRL_CLKSEQ_BYPASS_##bit, \
485 HW_CLKCTRL_CLKSEQ_TOG); \
486 clk->parent = parent; \
492 _CLK_SET_PARENT(cpu_clk, CPU)
493 _CLK_SET_PARENT(emi_clk, EMI)
494 _CLK_SET_PARENT(ssp0_clk, SSP0)
495 _CLK_SET_PARENT(ssp1_clk, SSP1)
496 _CLK_SET_PARENT(ssp2_clk, SSP2)
497 _CLK_SET_PARENT(ssp3_clk, SSP3)
498 _CLK_SET_PARENT(lcdif_clk, DIS_LCDIF)
499 _CLK_SET_PARENT(gpmi_clk, GPMI)
500 _CLK_SET_PARENT(saif0_clk, SAIF0)
501 _CLK_SET_PARENT(saif1_clk, SAIF1)
503 #define _CLK_SET_PARENT_STUB(name) \
504 static int name##_set_parent(struct clk *clk, struct clk *parent) \
506 if (parent != clk->parent) \
512 _CLK_SET_PARENT_STUB(pwm_clk)
513 _CLK_SET_PARENT_STUB(uart_clk)
514 _CLK_SET_PARENT_STUB(clk32k_clk)
515 _CLK_SET_PARENT_STUB(spdif_clk)
516 _CLK_SET_PARENT_STUB(fec_clk)
517 _CLK_SET_PARENT_STUB(can0_clk)
518 _CLK_SET_PARENT_STUB(can1_clk)
523 static struct clk cpu_clk = {
524 .get_rate = cpu_clk_get_rate,
525 .set_rate = cpu_clk_set_rate,
526 .set_parent = cpu_clk_set_parent,
527 .parent = &ref_cpu_clk,
530 static struct clk hbus_clk = {
531 .get_rate = hbus_clk_get_rate,
535 static struct clk xbus_clk = {
536 .get_rate = xbus_clk_get_rate,
537 .set_rate = xbus_clk_set_rate,
538 .parent = &ref_xtal_clk,
541 static struct clk lradc_clk = {
542 .get_rate = lradc_clk_get_rate,
543 .parent = &clk32k_clk,
546 static struct clk rtc_clk = {
547 .get_rate = rtc_clk_get_rate,
548 .parent = &ref_xtal_clk,
551 /* usb_clk gate is controlled in DIGCTRL other than CLKCTRL */
552 static struct clk usb0_clk = {
553 .enable_reg = DIGCTRL_BASE_ADDR,
555 .enable = _raw_clk_enable,
556 .disable = _raw_clk_disable,
560 static struct clk usb1_clk = {
561 .enable_reg = DIGCTRL_BASE_ADDR,
563 .enable = _raw_clk_enable,
564 .disable = _raw_clk_disable,
568 #define _DEFINE_CLOCK(name, er, es, p) \
569 static struct clk name = { \
570 .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_##er, \
571 .enable_shift = BP_CLKCTRL_##er##_##es, \
572 .get_rate = name##_get_rate, \
573 .set_rate = name##_set_rate, \
574 .set_parent = name##_set_parent, \
575 .enable = _raw_clk_enable, \
576 .disable = _raw_clk_disable, \
580 _DEFINE_CLOCK(emi_clk, EMI, CLKGATE, &ref_xtal_clk);
581 _DEFINE_CLOCK(ssp0_clk, SSP0, CLKGATE, &ref_xtal_clk);
582 _DEFINE_CLOCK(ssp1_clk, SSP1, CLKGATE, &ref_xtal_clk);
583 _DEFINE_CLOCK(ssp2_clk, SSP2, CLKGATE, &ref_xtal_clk);
584 _DEFINE_CLOCK(ssp3_clk, SSP3, CLKGATE, &ref_xtal_clk);
585 _DEFINE_CLOCK(lcdif_clk, DIS_LCDIF, CLKGATE, &ref_xtal_clk);
586 _DEFINE_CLOCK(gpmi_clk, GPMI, CLKGATE, &ref_xtal_clk);
587 _DEFINE_CLOCK(saif0_clk, SAIF0, CLKGATE, &ref_xtal_clk);
588 _DEFINE_CLOCK(saif1_clk, SAIF1, CLKGATE, &ref_xtal_clk);
589 _DEFINE_CLOCK(can0_clk, FLEXCAN, STOP_CAN0, &ref_xtal_clk);
590 _DEFINE_CLOCK(can1_clk, FLEXCAN, STOP_CAN1, &ref_xtal_clk);
591 _DEFINE_CLOCK(pwm_clk, XTAL, PWM_CLK24M_GATE, &ref_xtal_clk);
592 _DEFINE_CLOCK(uart_clk, XTAL, UART_CLK_GATE, &ref_xtal_clk);
593 _DEFINE_CLOCK(clk32k_clk, XTAL, TIMROT_CLK32K_GATE, &ref_xtal_clk);
594 _DEFINE_CLOCK(spdif_clk, SPDIF, CLKGATE, &pll0_clk);
595 _DEFINE_CLOCK(fec_clk, ENET, DISABLE, &hbus_clk);
597 #define _REGISTER_CLOCK(d, n, c) \
604 static struct clk_lookup lookups[] = {
605 _REGISTER_CLOCK("mxs-duart.0", NULL, uart_clk)
606 _REGISTER_CLOCK("fec.0", NULL, fec_clk)
607 _REGISTER_CLOCK("rtc", NULL, rtc_clk)
608 _REGISTER_CLOCK("pll2", NULL, pll2_clk)
609 _REGISTER_CLOCK(NULL, "hclk", hbus_clk)
610 _REGISTER_CLOCK(NULL, "xclk", xbus_clk)
611 _REGISTER_CLOCK(NULL, "can0", can0_clk)
612 _REGISTER_CLOCK(NULL, "can1", can1_clk)
613 _REGISTER_CLOCK(NULL, "usb0", usb0_clk)
614 _REGISTER_CLOCK(NULL, "usb1", usb1_clk)
615 _REGISTER_CLOCK(NULL, "pwm", pwm_clk)
616 _REGISTER_CLOCK(NULL, "lradc", lradc_clk)
617 _REGISTER_CLOCK(NULL, "spdif", spdif_clk)
620 static int clk_misc_init(void)
625 /* Fix up parent per register setting */
626 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ);
627 cpu_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_CPU) ?
628 &ref_xtal_clk : &ref_cpu_clk;
629 emi_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_EMI) ?
630 &ref_xtal_clk : &ref_emi_clk;
631 ssp0_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SSP0) ?
632 &ref_xtal_clk : &ref_io0_clk;
633 ssp1_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SSP1) ?
634 &ref_xtal_clk : &ref_io0_clk;
635 ssp2_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SSP2) ?
636 &ref_xtal_clk : &ref_io1_clk;
637 ssp3_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SSP3) ?
638 &ref_xtal_clk : &ref_io1_clk;
639 lcdif_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF) ?
640 &ref_xtal_clk : &ref_pix_clk;
641 gpmi_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_GPMI) ?
642 &ref_xtal_clk : &ref_gpmi_clk;
643 saif0_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SAIF0) ?
644 &ref_xtal_clk : &pll0_clk;
645 saif1_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SAIF1) ?
646 &ref_xtal_clk : &pll0_clk;
648 /* Use int div over frac when both are available */
649 __raw_writel(BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN,
650 CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_CLR);
651 __raw_writel(BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN,
652 CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_CLR);
653 __raw_writel(BM_CLKCTRL_HBUS_DIV_FRAC_EN,
654 CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS_CLR);
656 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_XBUS);
657 reg &= ~BM_CLKCTRL_XBUS_DIV_FRAC_EN;
658 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_XBUS);
660 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP0);
661 reg &= ~BM_CLKCTRL_SSP0_DIV_FRAC_EN;
662 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP0);
664 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP1);
665 reg &= ~BM_CLKCTRL_SSP1_DIV_FRAC_EN;
666 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP1);
668 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP2);
669 reg &= ~BM_CLKCTRL_SSP2_DIV_FRAC_EN;
670 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP2);
672 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP3);
673 reg &= ~BM_CLKCTRL_SSP3_DIV_FRAC_EN;
674 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP3);
676 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_GPMI);
677 reg &= ~BM_CLKCTRL_GPMI_DIV_FRAC_EN;
678 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_GPMI);
680 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_DIS_LCDIF);
681 reg &= ~BM_CLKCTRL_DIS_LCDIF_DIV_FRAC_EN;
682 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_DIS_LCDIF);
684 /* SAIF has to use frac div for functional operation */
685 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF0);
686 reg &= ~BM_CLKCTRL_SAIF0_DIV_FRAC_EN;
687 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF0);
689 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF1);
690 reg &= ~BM_CLKCTRL_SAIF1_DIV_FRAC_EN;
691 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF1);
694 * Set safe hbus clock divider. A divider of 3 ensure that
695 * the Vddd voltage required for the cpu clock is sufficiently
696 * high for the hbus clock.
698 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS);
699 reg &= BM_CLKCTRL_HBUS_DIV;
700 reg |= 3 << BP_CLKCTRL_HBUS_DIV;
701 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS);
703 for (i = 10000; i; i--)
704 if (!(__raw_readl(CLKCTRL_BASE_ADDR +
705 HW_CLKCTRL_HBUS) & BM_CLKCTRL_HBUS_ASM_BUSY))
708 pr_err("%s: divider writing timeout\n", __func__);
712 /* Gate off cpu clock in WFI for power saving */
713 __raw_writel(BM_CLKCTRL_CPU_INTERRUPT_WAIT,
714 CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_SET);
716 /* Extra fec clock setting */
717 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_ENET);
718 reg &= ~BM_CLKCTRL_ENET_SLEEP;
719 reg |= BM_CLKCTRL_ENET_CLK_OUT_EN;
720 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_ENET);
725 int __init mx28_clocks_init(void)
729 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
731 mxs_timer_init(&clk32k_clk, MX28_INT_TIMER0);