2 * Copyright 2012 Freescale Semiconductor, Inc.
3 * Copyright 2012 Linaro Ltd.
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
13 #include <linux/clk.h>
14 #include <linux/clk/mxs.h>
15 #include <linux/clkdev.h>
16 #include <linux/clocksource.h>
17 #include <linux/can/platform/flexcan.h>
18 #include <linux/delay.h>
19 #include <linux/err.h>
20 #include <linux/gpio.h>
21 #include <linux/init.h>
22 #include <linux/irqchip.h>
23 #include <linux/irqchip/mxs.h>
24 #include <linux/micrel_phy.h>
25 #include <linux/of_address.h>
26 #include <linux/of_platform.h>
27 #include <linux/phy.h>
28 #include <linux/pinctrl/consumer.h>
29 #include <asm/mach/arch.h>
30 #include <asm/mach/map.h>
31 #include <asm/mach/time.h>
32 #include <asm/system_misc.h>
36 /* MXS DIGCTL SAIF CLKMUX */
37 #define MXS_DIGCTL_SAIF_CLKMUX_DIRECT 0x0
38 #define MXS_DIGCTL_SAIF_CLKMUX_CROSSINPUT 0x1
39 #define MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR0 0x2
40 #define MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR1 0x3
42 #define MXS_GPIO_NR(bank, nr) ((bank) * 32 + (nr))
44 #define MXS_SET_ADDR 0x4
45 #define MXS_CLR_ADDR 0x8
46 #define MXS_TOG_ADDR 0xc
48 static inline void __mxs_setl(u32 mask, void __iomem *reg)
50 __raw_writel(mask, reg + MXS_SET_ADDR);
53 static inline void __mxs_clrl(u32 mask, void __iomem *reg)
55 __raw_writel(mask, reg + MXS_CLR_ADDR);
58 static inline void __mxs_togl(u32 mask, void __iomem *reg)
60 __raw_writel(mask, reg + MXS_TOG_ADDR);
64 * MX28EVK_FLEXCAN_SWITCH is shared between both flexcan controllers
66 #define MX28EVK_FLEXCAN_SWITCH MXS_GPIO_NR(2, 13)
68 static int flexcan0_en, flexcan1_en;
70 static void mx28evk_flexcan_switch(void)
72 if (flexcan0_en || flexcan1_en)
73 gpio_set_value(MX28EVK_FLEXCAN_SWITCH, 1);
75 gpio_set_value(MX28EVK_FLEXCAN_SWITCH, 0);
78 static void mx28evk_flexcan0_switch(int enable)
81 mx28evk_flexcan_switch();
84 static void mx28evk_flexcan1_switch(int enable)
87 mx28evk_flexcan_switch();
90 static struct flexcan_platform_data flexcan_pdata[2];
92 static struct of_dev_auxdata mxs_auxdata_lookup[] __initdata = {
93 OF_DEV_AUXDATA("fsl,imx28-flexcan", 0x80032000, NULL, &flexcan_pdata[0]),
94 OF_DEV_AUXDATA("fsl,imx28-flexcan", 0x80034000, NULL, &flexcan_pdata[1]),
98 #define OCOTP_WORD_OFFSET 0x20
99 #define OCOTP_WORD_COUNT 0x20
101 #define BM_OCOTP_CTRL_BUSY (1 << 8)
102 #define BM_OCOTP_CTRL_ERROR (1 << 9)
103 #define BM_OCOTP_CTRL_RD_BANK_OPEN (1 << 12)
105 static DEFINE_MUTEX(ocotp_mutex);
106 static u32 ocotp_words[OCOTP_WORD_COUNT];
108 static const u32 *mxs_get_ocotp(void)
110 struct device_node *np;
111 void __iomem *ocotp_base;
119 np = of_find_compatible_node(NULL, NULL, "fsl,ocotp");
120 ocotp_base = of_iomap(np, 0);
121 WARN_ON(!ocotp_base);
123 mutex_lock(&ocotp_mutex);
126 * clk_enable(hbus_clk) for ocotp can be skipped
127 * as it must be on when system is running.
130 /* try to clear ERROR bit */
131 __mxs_clrl(BM_OCOTP_CTRL_ERROR, ocotp_base);
133 /* check both BUSY and ERROR cleared */
134 while ((__raw_readl(ocotp_base) &
135 (BM_OCOTP_CTRL_BUSY | BM_OCOTP_CTRL_ERROR)) && --timeout)
138 if (unlikely(!timeout))
141 /* open OCOTP banks for read */
142 __mxs_setl(BM_OCOTP_CTRL_RD_BANK_OPEN, ocotp_base);
144 /* approximately wait 32 hclk cycles */
147 /* poll BUSY bit becoming cleared */
149 while ((__raw_readl(ocotp_base) & BM_OCOTP_CTRL_BUSY) && --timeout)
152 if (unlikely(!timeout))
155 for (i = 0; i < OCOTP_WORD_COUNT; i++)
156 ocotp_words[i] = __raw_readl(ocotp_base + OCOTP_WORD_OFFSET +
159 /* close banks for power saving */
160 __mxs_clrl(BM_OCOTP_CTRL_RD_BANK_OPEN, ocotp_base);
164 mutex_unlock(&ocotp_mutex);
169 mutex_unlock(&ocotp_mutex);
170 pr_err("%s: timeout in reading OCOTP\n", __func__);
180 static void __init update_fec_mac_prop(enum mac_oui oui)
182 struct device_node *np, *from = NULL;
183 struct property *newmac;
184 const u32 *ocotp = mxs_get_ocotp();
189 for (i = 0; i < 2; i++) {
190 np = of_find_compatible_node(from, NULL, "fsl,imx28-fec");
196 if (of_get_property(np, "local-mac-address", NULL))
199 newmac = kzalloc(sizeof(*newmac) + 6, GFP_KERNEL);
202 newmac->value = newmac + 1;
205 newmac->name = kstrdup("local-mac-address", GFP_KERNEL);
212 * OCOTP only stores the last 4 octets for each mac address,
213 * so hard-code OUI here.
215 macaddr = newmac->value;
227 case OUI_CRYSTALFONTZ:
234 macaddr[3] = (val >> 16) & 0xff;
235 macaddr[4] = (val >> 8) & 0xff;
236 macaddr[5] = (val >> 0) & 0xff;
238 of_update_property(np, newmac);
242 static inline void enable_clk_enet_out(void)
244 struct clk *clk = clk_get_sys("enet_out", NULL);
247 clk_prepare_enable(clk);
250 static void __init imx28_evk_init(void)
252 update_fec_mac_prop(OUI_FSL);
254 mxs_saif_clkmux_select(MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR0);
257 static void __init imx28_evk_post_init(void)
259 if (!gpio_request_one(MX28EVK_FLEXCAN_SWITCH, GPIOF_DIR_OUT,
261 flexcan_pdata[0].transceiver_switch = mx28evk_flexcan0_switch;
262 flexcan_pdata[1].transceiver_switch = mx28evk_flexcan1_switch;
266 static int apx4devkit_phy_fixup(struct phy_device *phy)
268 phy->dev_flags |= MICREL_PHY_50MHZ_CLK;
272 static void __init apx4devkit_init(void)
274 enable_clk_enet_out();
276 if (IS_BUILTIN(CONFIG_PHYLIB))
277 phy_register_fixup_for_uid(PHY_ID_KSZ8051, MICREL_PHY_ID_MASK,
278 apx4devkit_phy_fixup);
281 #define ENET0_MDC__GPIO_4_0 MXS_GPIO_NR(4, 0)
282 #define ENET0_MDIO__GPIO_4_1 MXS_GPIO_NR(4, 1)
283 #define ENET0_RX_EN__GPIO_4_2 MXS_GPIO_NR(4, 2)
284 #define ENET0_RXD0__GPIO_4_3 MXS_GPIO_NR(4, 3)
285 #define ENET0_RXD1__GPIO_4_4 MXS_GPIO_NR(4, 4)
286 #define ENET0_TX_EN__GPIO_4_6 MXS_GPIO_NR(4, 6)
287 #define ENET0_TXD0__GPIO_4_7 MXS_GPIO_NR(4, 7)
288 #define ENET0_TXD1__GPIO_4_8 MXS_GPIO_NR(4, 8)
289 #define ENET_CLK__GPIO_4_16 MXS_GPIO_NR(4, 16)
291 #define TX28_FEC_PHY_POWER MXS_GPIO_NR(3, 29)
292 #define TX28_FEC_PHY_RESET MXS_GPIO_NR(4, 13)
293 #define TX28_FEC_nINT MXS_GPIO_NR(4, 5)
295 static const struct gpio tx28_gpios[] __initconst = {
296 { ENET0_MDC__GPIO_4_0, GPIOF_OUT_INIT_LOW, "GPIO_4_0" },
297 { ENET0_MDIO__GPIO_4_1, GPIOF_OUT_INIT_LOW, "GPIO_4_1" },
298 { ENET0_RX_EN__GPIO_4_2, GPIOF_OUT_INIT_LOW, "GPIO_4_2" },
299 { ENET0_RXD0__GPIO_4_3, GPIOF_OUT_INIT_LOW, "GPIO_4_3" },
300 { ENET0_RXD1__GPIO_4_4, GPIOF_OUT_INIT_LOW, "GPIO_4_4" },
301 { ENET0_TX_EN__GPIO_4_6, GPIOF_OUT_INIT_LOW, "GPIO_4_6" },
302 { ENET0_TXD0__GPIO_4_7, GPIOF_OUT_INIT_LOW, "GPIO_4_7" },
303 { ENET0_TXD1__GPIO_4_8, GPIOF_OUT_INIT_LOW, "GPIO_4_8" },
304 { ENET_CLK__GPIO_4_16, GPIOF_OUT_INIT_LOW, "GPIO_4_16" },
305 { TX28_FEC_PHY_POWER, GPIOF_OUT_INIT_LOW, "fec-phy-power" },
306 { TX28_FEC_PHY_RESET, GPIOF_OUT_INIT_LOW, "fec-phy-reset" },
307 { TX28_FEC_nINT, GPIOF_DIR_IN, "fec-int" },
310 static void __init tx28_post_init(void)
312 struct device_node *np;
313 struct platform_device *pdev;
314 struct pinctrl *pctl;
317 enable_clk_enet_out();
319 np = of_find_compatible_node(NULL, NULL, "fsl,imx28-fec");
320 pdev = of_find_device_by_node(np);
322 pr_err("%s: failed to find fec device\n", __func__);
326 pctl = pinctrl_get_select(&pdev->dev, "gpio_mode");
328 pr_err("%s: failed to get pinctrl state\n", __func__);
332 ret = gpio_request_array(tx28_gpios, ARRAY_SIZE(tx28_gpios));
334 pr_err("%s: failed to request gpios: %d\n", __func__, ret);
338 /* Power up fec phy */
339 gpio_set_value(TX28_FEC_PHY_POWER, 1);
340 msleep(26); /* 25ms according to data sheet */
342 /* Mode strap pins */
343 gpio_set_value(ENET0_RX_EN__GPIO_4_2, 1);
344 gpio_set_value(ENET0_RXD0__GPIO_4_3, 1);
345 gpio_set_value(ENET0_RXD1__GPIO_4_4, 1);
347 udelay(100); /* minimum assertion time for nRST */
349 /* Deasserting FEC PHY RESET */
350 gpio_set_value(TX28_FEC_PHY_RESET, 1);
355 static void __init cfa10049_init(void)
357 update_fec_mac_prop(OUI_CRYSTALFONTZ);
360 static void __init cfa10037_init(void)
362 update_fec_mac_prop(OUI_CRYSTALFONTZ);
365 static void __init mxs_machine_init(void)
367 if (of_machine_is_compatible("fsl,imx28-evk"))
369 else if (of_machine_is_compatible("bluegiga,apx4devkit"))
371 else if (of_machine_is_compatible("crystalfontz,cfa10037"))
373 else if (of_machine_is_compatible("crystalfontz,cfa10049"))
376 of_platform_populate(NULL, of_default_bus_match_table,
377 mxs_auxdata_lookup, NULL);
379 if (of_machine_is_compatible("karo,tx28"))
382 if (of_machine_is_compatible("fsl,imx28-evk"))
383 imx28_evk_post_init();
386 #define MX23_CLKCTRL_RESET_OFFSET 0x120
387 #define MX28_CLKCTRL_RESET_OFFSET 0x1e0
388 #define MXS_CLKCTRL_RESET_CHIP (1 << 1)
391 * Reset the system. It is called by machine_restart().
393 static void mxs_restart(char mode, const char *cmd)
395 struct device_node *np;
396 void __iomem *reset_addr;
398 np = of_find_compatible_node(NULL, NULL, "fsl,clkctrl");
399 reset_addr = of_iomap(np, 0);
403 if (of_device_is_compatible(np, "fsl,imx23-clkctrl"))
404 reset_addr += MX23_CLKCTRL_RESET_OFFSET;
406 reset_addr += MX28_CLKCTRL_RESET_OFFSET;
409 __mxs_setl(MXS_CLKCTRL_RESET_CHIP, reset_addr);
411 pr_err("Failed to assert the chip reset\n");
413 /* Delay to allow the serial port to show the message */
417 /* We'll take a jump through zero as a poor second */
421 static void __init mxs_timer_init(void)
423 if (of_machine_is_compatible("fsl,imx23"))
427 clocksource_of_init();
430 static const char *mxs_dt_compat[] __initdata = {
436 DT_MACHINE_START(MXS, "Freescale MXS (Device Tree)")
437 .map_io = debug_ll_io_init,
438 .init_irq = irqchip_init,
439 .handle_irq = icoll_handle_irq,
440 .init_time = mxs_timer_init,
441 .init_machine = mxs_machine_init,
442 .init_late = mxs_pm_init,
443 .dt_compat = mxs_dt_compat,
444 .restart = mxs_restart,