2 * linux/arch/arm/mach-omap1/clock_data.c
4 * Copyright (C) 2004 - 2005, 2009-2010 Nokia Corporation
5 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
6 * Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/kernel.h>
14 #include <linux/clk.h>
17 #include <asm/mach-types.h> /* for machine_is_* */
19 #include <plat/clock.h>
21 #include <plat/clkdev_omap.h>
22 #include <plat/usb.h> /* for OTG_BASE */
26 /*------------------------------------------------------------------------
28 *-------------------------------------------------------------------------*/
30 static struct clk ck_ref = {
36 static struct clk ck_dpll1 = {
43 * FIXME: This clock seems to be necessary but no-one has asked for its
44 * activation. [ FIX: SoSSI, SSR ]
46 static struct arm_idlect1_clk ck_dpll1out = {
48 .name = "ck_dpll1out",
49 .ops = &clkops_generic,
51 .flags = CLOCK_IDLE_CONTROL | ENABLE_REG_32BIT |
53 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
54 .enable_bit = EN_CKOUT_ARM,
55 .recalc = &followparent_recalc,
60 static struct clk sossi_ck = {
62 .ops = &clkops_generic,
63 .parent = &ck_dpll1out.clk,
64 .flags = CLOCK_NO_IDLE_PARENT | ENABLE_REG_32BIT,
65 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_1),
67 .recalc = &omap1_sossi_recalc,
68 .set_rate = &omap1_set_sossi_rate,
71 static struct clk arm_ck = {
75 .rate_offset = CKCTL_ARMDIV_OFFSET,
76 .recalc = &omap1_ckctl_recalc,
77 .round_rate = omap1_clk_round_rate_ckctl_arm,
78 .set_rate = omap1_clk_set_rate_ckctl_arm,
81 static struct arm_idlect1_clk armper_ck = {
84 .ops = &clkops_generic,
86 .flags = CLOCK_IDLE_CONTROL,
87 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
88 .enable_bit = EN_PERCK,
89 .rate_offset = CKCTL_PERDIV_OFFSET,
90 .recalc = &omap1_ckctl_recalc,
91 .round_rate = omap1_clk_round_rate_ckctl_arm,
92 .set_rate = omap1_clk_set_rate_ckctl_arm,
98 * FIXME: This clock seems to be necessary but no-one has asked for its
99 * activation. [ GPIO code for 1510 ]
101 static struct clk arm_gpio_ck = {
102 .name = "arm_gpio_ck",
103 .ops = &clkops_generic,
105 .flags = ENABLE_ON_INIT,
106 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
107 .enable_bit = EN_GPIOCK,
108 .recalc = &followparent_recalc,
111 static struct arm_idlect1_clk armxor_ck = {
114 .ops = &clkops_generic,
116 .flags = CLOCK_IDLE_CONTROL,
117 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
118 .enable_bit = EN_XORPCK,
119 .recalc = &followparent_recalc,
124 static struct arm_idlect1_clk armtim_ck = {
127 .ops = &clkops_generic,
129 .flags = CLOCK_IDLE_CONTROL,
130 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
131 .enable_bit = EN_TIMCK,
132 .recalc = &followparent_recalc,
137 static struct arm_idlect1_clk armwdt_ck = {
140 .ops = &clkops_generic,
142 .flags = CLOCK_IDLE_CONTROL,
143 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
144 .enable_bit = EN_WDTCK,
146 .recalc = &omap_fixed_divisor_recalc,
151 static struct clk arminth_ck16xx = {
152 .name = "arminth_ck",
155 .recalc = &followparent_recalc,
156 /* Note: On 16xx the frequency can be divided by 2 by programming
157 * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1
159 * 1510 version is in TC clocks.
163 static struct clk dsp_ck = {
165 .ops = &clkops_generic,
167 .enable_reg = OMAP1_IO_ADDRESS(ARM_CKCTL),
168 .enable_bit = EN_DSPCK,
169 .rate_offset = CKCTL_DSPDIV_OFFSET,
170 .recalc = &omap1_ckctl_recalc,
171 .round_rate = omap1_clk_round_rate_ckctl_arm,
172 .set_rate = omap1_clk_set_rate_ckctl_arm,
175 static struct clk dspmmu_ck = {
179 .rate_offset = CKCTL_DSPMMUDIV_OFFSET,
180 .recalc = &omap1_ckctl_recalc,
181 .round_rate = omap1_clk_round_rate_ckctl_arm,
182 .set_rate = omap1_clk_set_rate_ckctl_arm,
185 static struct clk dspper_ck = {
187 .ops = &clkops_dspck,
189 .enable_reg = DSP_IDLECT2,
190 .enable_bit = EN_PERCK,
191 .rate_offset = CKCTL_PERDIV_OFFSET,
192 .recalc = &omap1_ckctl_recalc_dsp_domain,
193 .round_rate = omap1_clk_round_rate_ckctl_arm,
194 .set_rate = &omap1_clk_set_rate_dsp_domain,
197 static struct clk dspxor_ck = {
199 .ops = &clkops_dspck,
201 .enable_reg = DSP_IDLECT2,
202 .enable_bit = EN_XORPCK,
203 .recalc = &followparent_recalc,
206 static struct clk dsptim_ck = {
208 .ops = &clkops_dspck,
210 .enable_reg = DSP_IDLECT2,
211 .enable_bit = EN_DSPTIMCK,
212 .recalc = &followparent_recalc,
215 /* Tie ARM_IDLECT1:IDLIF_ARM to this logical clock structure */
216 static struct arm_idlect1_clk tc_ck = {
221 .flags = CLOCK_IDLE_CONTROL,
222 .rate_offset = CKCTL_TCDIV_OFFSET,
223 .recalc = &omap1_ckctl_recalc,
224 .round_rate = omap1_clk_round_rate_ckctl_arm,
225 .set_rate = omap1_clk_set_rate_ckctl_arm,
230 static struct clk arminth_ck1510 = {
231 .name = "arminth_ck",
233 .parent = &tc_ck.clk,
234 .recalc = &followparent_recalc,
235 /* Note: On 1510 the frequency follows TC_CK
237 * 16xx version is in MPU clocks.
241 static struct clk tipb_ck = {
242 /* No-idle controlled by "tc_ck" */
245 .parent = &tc_ck.clk,
246 .recalc = &followparent_recalc,
249 static struct clk l3_ocpi_ck = {
250 /* No-idle controlled by "tc_ck" */
251 .name = "l3_ocpi_ck",
252 .ops = &clkops_generic,
253 .parent = &tc_ck.clk,
254 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3),
255 .enable_bit = EN_OCPI_CK,
256 .recalc = &followparent_recalc,
259 static struct clk tc1_ck = {
261 .ops = &clkops_generic,
262 .parent = &tc_ck.clk,
263 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3),
264 .enable_bit = EN_TC1_CK,
265 .recalc = &followparent_recalc,
269 * FIXME: This clock seems to be necessary but no-one has asked for its
270 * activation. [ pm.c (SRAM), CCP, Camera ]
272 static struct clk tc2_ck = {
274 .ops = &clkops_generic,
275 .parent = &tc_ck.clk,
276 .flags = ENABLE_ON_INIT,
277 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT3),
278 .enable_bit = EN_TC2_CK,
279 .recalc = &followparent_recalc,
282 static struct clk dma_ck = {
283 /* No-idle controlled by "tc_ck" */
286 .parent = &tc_ck.clk,
287 .recalc = &followparent_recalc,
290 static struct clk dma_lcdfree_ck = {
291 .name = "dma_lcdfree_ck",
293 .parent = &tc_ck.clk,
294 .recalc = &followparent_recalc,
297 static struct arm_idlect1_clk api_ck = {
300 .ops = &clkops_generic,
301 .parent = &tc_ck.clk,
302 .flags = CLOCK_IDLE_CONTROL,
303 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
304 .enable_bit = EN_APICK,
305 .recalc = &followparent_recalc,
310 static struct arm_idlect1_clk lb_ck = {
313 .ops = &clkops_generic,
314 .parent = &tc_ck.clk,
315 .flags = CLOCK_IDLE_CONTROL,
316 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
317 .enable_bit = EN_LBCK,
318 .recalc = &followparent_recalc,
323 static struct clk rhea1_ck = {
326 .parent = &tc_ck.clk,
327 .recalc = &followparent_recalc,
330 static struct clk rhea2_ck = {
333 .parent = &tc_ck.clk,
334 .recalc = &followparent_recalc,
337 static struct clk lcd_ck_16xx = {
339 .ops = &clkops_generic,
341 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
342 .enable_bit = EN_LCDCK,
343 .rate_offset = CKCTL_LCDDIV_OFFSET,
344 .recalc = &omap1_ckctl_recalc,
345 .round_rate = omap1_clk_round_rate_ckctl_arm,
346 .set_rate = omap1_clk_set_rate_ckctl_arm,
349 static struct arm_idlect1_clk lcd_ck_1510 = {
352 .ops = &clkops_generic,
354 .flags = CLOCK_IDLE_CONTROL,
355 .enable_reg = OMAP1_IO_ADDRESS(ARM_IDLECT2),
356 .enable_bit = EN_LCDCK,
357 .rate_offset = CKCTL_LCDDIV_OFFSET,
358 .recalc = &omap1_ckctl_recalc,
359 .round_rate = omap1_clk_round_rate_ckctl_arm,
360 .set_rate = omap1_clk_set_rate_ckctl_arm,
365 static struct clk uart1_1510 = {
368 /* Direct from ULPD, no real parent */
369 .parent = &armper_ck.clk,
371 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
372 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
373 .enable_bit = 29, /* Chooses between 12MHz and 48MHz */
374 .set_rate = &omap1_set_uart_rate,
375 .recalc = &omap1_uart_recalc,
378 static struct uart_clk uart1_16xx = {
382 /* Direct from ULPD, no real parent */
383 .parent = &armper_ck.clk,
385 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
386 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
389 .sysc_addr = 0xfffb0054,
392 static struct clk uart2_ck = {
395 /* Direct from ULPD, no real parent */
396 .parent = &armper_ck.clk,
398 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
399 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
400 .enable_bit = 30, /* Chooses between 12MHz and 48MHz */
401 .set_rate = &omap1_set_uart_rate,
402 .recalc = &omap1_uart_recalc,
405 static struct clk uart3_1510 = {
408 /* Direct from ULPD, no real parent */
409 .parent = &armper_ck.clk,
411 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
412 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
413 .enable_bit = 31, /* Chooses between 12MHz and 48MHz */
414 .set_rate = &omap1_set_uart_rate,
415 .recalc = &omap1_uart_recalc,
418 static struct uart_clk uart3_16xx = {
422 /* Direct from ULPD, no real parent */
423 .parent = &armper_ck.clk,
425 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
426 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
429 .sysc_addr = 0xfffb9854,
432 static struct clk usb_clko = { /* 6 MHz output on W4_USB_CLKO */
434 .ops = &clkops_generic,
435 /* Direct from ULPD, no parent */
437 .flags = ENABLE_REG_32BIT,
438 .enable_reg = OMAP1_IO_ADDRESS(ULPD_CLOCK_CTRL),
439 .enable_bit = USB_MCLK_EN_BIT,
442 static struct clk usb_hhc_ck1510 = {
443 .name = "usb_hhc_ck",
444 .ops = &clkops_generic,
445 /* Direct from ULPD, no parent */
446 .rate = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */
447 .flags = ENABLE_REG_32BIT,
448 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
449 .enable_bit = USB_HOST_HHC_UHOST_EN,
452 static struct clk usb_hhc_ck16xx = {
453 .name = "usb_hhc_ck",
454 .ops = &clkops_generic,
455 /* Direct from ULPD, no parent */
457 /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */
458 .flags = ENABLE_REG_32BIT,
459 .enable_reg = OMAP1_IO_ADDRESS(OTG_BASE + 0x08), /* OTG_SYSCON_2 */
460 .enable_bit = 8 /* UHOST_EN */,
463 static struct clk usb_dc_ck = {
465 .ops = &clkops_generic,
466 /* Direct from ULPD, no parent */
468 .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
472 static struct clk usb_dc_ck7xx = {
474 .ops = &clkops_generic,
475 /* Direct from ULPD, no parent */
477 .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
481 static struct clk uart1_7xx = {
483 .ops = &clkops_generic,
484 /* Direct from ULPD, no parent */
486 .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
490 static struct clk uart2_7xx = {
492 .ops = &clkops_generic,
493 /* Direct from ULPD, no parent */
495 .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
499 static struct clk mclk_1510 = {
501 .ops = &clkops_generic,
502 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
504 .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
508 static struct clk mclk_16xx = {
510 .ops = &clkops_generic,
511 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
512 .enable_reg = OMAP1_IO_ADDRESS(COM_CLK_DIV_CTRL_SEL),
513 .enable_bit = COM_ULPD_PLL_CLK_REQ,
514 .set_rate = &omap1_set_ext_clk_rate,
515 .round_rate = &omap1_round_ext_clk_rate,
516 .init = &omap1_init_ext_clk,
519 static struct clk bclk_1510 = {
521 .ops = &clkops_generic,
522 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
526 static struct clk bclk_16xx = {
528 .ops = &clkops_generic,
529 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
530 .enable_reg = OMAP1_IO_ADDRESS(SWD_CLK_DIV_CTRL_SEL),
531 .enable_bit = SWD_ULPD_PLL_CLK_REQ,
532 .set_rate = &omap1_set_ext_clk_rate,
533 .round_rate = &omap1_round_ext_clk_rate,
534 .init = &omap1_init_ext_clk,
537 static struct clk mmc1_ck = {
539 .ops = &clkops_generic,
540 /* Functional clock is direct from ULPD, interface clock is ARMPER */
541 .parent = &armper_ck.clk,
543 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
544 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
548 static struct clk mmc2_ck = {
550 .ops = &clkops_generic,
551 /* Functional clock is direct from ULPD, interface clock is ARMPER */
552 .parent = &armper_ck.clk,
554 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
555 .enable_reg = OMAP1_IO_ADDRESS(MOD_CONF_CTRL_0),
559 static struct clk mmc3_ck = {
561 .ops = &clkops_generic,
562 /* Functional clock is direct from ULPD, interface clock is ARMPER */
563 .parent = &armper_ck.clk,
565 .flags = ENABLE_REG_32BIT | CLOCK_NO_IDLE_PARENT,
566 .enable_reg = OMAP1_IO_ADDRESS(SOFT_REQ_REG),
570 static struct clk virtual_ck_mpu = {
573 .parent = &arm_ck, /* Is smarter alias for */
574 .recalc = &followparent_recalc,
575 .set_rate = &omap1_select_table_rate,
576 .round_rate = &omap1_round_to_table_rate,
579 /* virtual functional clock domain for I2C. Just for making sure that ARMXOR_CK
580 remains active during MPU idle whenever this is enabled */
581 static struct clk i2c_fck = {
584 .flags = CLOCK_NO_IDLE_PARENT,
585 .parent = &armxor_ck.clk,
586 .recalc = &followparent_recalc,
589 static struct clk i2c_ick = {
592 .flags = CLOCK_NO_IDLE_PARENT,
593 .parent = &armper_ck.clk,
594 .recalc = &followparent_recalc,
601 static struct omap_clk omap_clks[] = {
602 /* non-ULPD clocks */
603 CLK(NULL, "ck_ref", &ck_ref, CK_16XX | CK_1510 | CK_310 | CK_7XX),
604 CLK(NULL, "ck_dpll1", &ck_dpll1, CK_16XX | CK_1510 | CK_310 | CK_7XX),
606 CLK(NULL, "ck_dpll1out", &ck_dpll1out.clk, CK_16XX),
607 CLK(NULL, "ck_sossi", &sossi_ck, CK_16XX),
608 CLK(NULL, "arm_ck", &arm_ck, CK_16XX | CK_1510 | CK_310),
609 CLK(NULL, "armper_ck", &armper_ck.clk, CK_16XX | CK_1510 | CK_310),
610 CLK(NULL, "arm_gpio_ck", &arm_gpio_ck, CK_1510 | CK_310),
611 CLK(NULL, "armxor_ck", &armxor_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
612 CLK(NULL, "armtim_ck", &armtim_ck.clk, CK_16XX | CK_1510 | CK_310),
613 CLK("omap_wdt", "fck", &armwdt_ck.clk, CK_16XX | CK_1510 | CK_310),
614 CLK("omap_wdt", "ick", &armper_ck.clk, CK_16XX),
615 CLK("omap_wdt", "ick", &dummy_ck, CK_1510 | CK_310),
616 CLK(NULL, "arminth_ck", &arminth_ck1510, CK_1510 | CK_310),
617 CLK(NULL, "arminth_ck", &arminth_ck16xx, CK_16XX),
619 CLK(NULL, "dsp_ck", &dsp_ck, CK_16XX | CK_1510 | CK_310),
620 CLK(NULL, "dspmmu_ck", &dspmmu_ck, CK_16XX | CK_1510 | CK_310),
621 CLK(NULL, "dspper_ck", &dspper_ck, CK_16XX | CK_1510 | CK_310),
622 CLK(NULL, "dspxor_ck", &dspxor_ck, CK_16XX | CK_1510 | CK_310),
623 CLK(NULL, "dsptim_ck", &dsptim_ck, CK_16XX | CK_1510 | CK_310),
625 CLK(NULL, "tc_ck", &tc_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
626 CLK(NULL, "tipb_ck", &tipb_ck, CK_1510 | CK_310),
627 CLK(NULL, "l3_ocpi_ck", &l3_ocpi_ck, CK_16XX | CK_7XX),
628 CLK(NULL, "tc1_ck", &tc1_ck, CK_16XX),
629 CLK(NULL, "tc2_ck", &tc2_ck, CK_16XX),
630 CLK(NULL, "dma_ck", &dma_ck, CK_16XX | CK_1510 | CK_310),
631 CLK(NULL, "dma_lcdfree_ck", &dma_lcdfree_ck, CK_16XX),
632 CLK(NULL, "api_ck", &api_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
633 CLK(NULL, "lb_ck", &lb_ck.clk, CK_1510 | CK_310),
634 CLK(NULL, "rhea1_ck", &rhea1_ck, CK_16XX),
635 CLK(NULL, "rhea2_ck", &rhea2_ck, CK_16XX),
636 CLK(NULL, "lcd_ck", &lcd_ck_16xx, CK_16XX | CK_7XX),
637 CLK(NULL, "lcd_ck", &lcd_ck_1510.clk, CK_1510 | CK_310),
639 CLK(NULL, "uart1_ck", &uart1_1510, CK_1510 | CK_310),
640 CLK(NULL, "uart1_ck", &uart1_16xx.clk, CK_16XX),
641 CLK(NULL, "uart1_ck", &uart1_7xx, CK_7XX),
642 CLK(NULL, "uart2_ck", &uart2_ck, CK_16XX | CK_1510 | CK_310),
643 CLK(NULL, "uart2_ck", &uart2_7xx, CK_7XX),
644 CLK(NULL, "uart3_ck", &uart3_1510, CK_1510 | CK_310),
645 CLK(NULL, "uart3_ck", &uart3_16xx.clk, CK_16XX),
646 CLK(NULL, "usb_clko", &usb_clko, CK_16XX | CK_1510 | CK_310),
647 CLK(NULL, "usb_hhc_ck", &usb_hhc_ck1510, CK_1510 | CK_310),
648 CLK(NULL, "usb_hhc_ck", &usb_hhc_ck16xx, CK_16XX),
649 CLK(NULL, "usb_dc_ck", &usb_dc_ck, CK_16XX),
650 CLK(NULL, "usb_dc_ck", &usb_dc_ck7xx, CK_7XX),
651 CLK(NULL, "mclk", &mclk_1510, CK_1510 | CK_310),
652 CLK(NULL, "mclk", &mclk_16xx, CK_16XX),
653 CLK(NULL, "bclk", &bclk_1510, CK_1510 | CK_310),
654 CLK(NULL, "bclk", &bclk_16xx, CK_16XX),
655 CLK("mmci-omap.0", "fck", &mmc1_ck, CK_16XX | CK_1510 | CK_310),
656 CLK("mmci-omap.0", "fck", &mmc3_ck, CK_7XX),
657 CLK("mmci-omap.0", "ick", &armper_ck.clk, CK_16XX | CK_1510 | CK_310 | CK_7XX),
658 CLK("mmci-omap.1", "fck", &mmc2_ck, CK_16XX),
659 CLK("mmci-omap.1", "ick", &armper_ck.clk, CK_16XX),
661 CLK(NULL, "mpu", &virtual_ck_mpu, CK_16XX | CK_1510 | CK_310),
662 CLK("i2c_omap.1", "fck", &i2c_fck, CK_16XX | CK_1510 | CK_310 | CK_7XX),
663 CLK("i2c_omap.1", "ick", &i2c_ick, CK_16XX),
664 CLK("i2c_omap.1", "ick", &dummy_ck, CK_1510 | CK_310 | CK_7XX),
665 CLK("omap1_spi100k.1", "fck", &dummy_ck, CK_7XX),
666 CLK("omap1_spi100k.1", "ick", &dummy_ck, CK_7XX),
667 CLK("omap1_spi100k.2", "fck", &dummy_ck, CK_7XX),
668 CLK("omap1_spi100k.2", "ick", &dummy_ck, CK_7XX),
669 CLK("omap_uwire", "fck", &armxor_ck.clk, CK_16XX | CK_1510 | CK_310),
670 CLK("omap-mcbsp.1", "ick", &dspper_ck, CK_16XX),
671 CLK("omap-mcbsp.1", "ick", &dummy_ck, CK_1510 | CK_310),
672 CLK("omap-mcbsp.2", "ick", &armper_ck.clk, CK_16XX),
673 CLK("omap-mcbsp.2", "ick", &dummy_ck, CK_1510 | CK_310),
674 CLK("omap-mcbsp.3", "ick", &dspper_ck, CK_16XX),
675 CLK("omap-mcbsp.3", "ick", &dummy_ck, CK_1510 | CK_310),
676 CLK("omap-mcbsp.1", "fck", &dspxor_ck, CK_16XX | CK_1510 | CK_310),
677 CLK("omap-mcbsp.2", "fck", &armper_ck.clk, CK_16XX | CK_1510 | CK_310),
678 CLK("omap-mcbsp.3", "fck", &dspxor_ck, CK_16XX | CK_1510 | CK_310),
685 static struct clk_functions omap1_clk_functions = {
686 .clk_enable = omap1_clk_enable,
687 .clk_disable = omap1_clk_disable,
688 .clk_round_rate = omap1_clk_round_rate,
689 .clk_set_rate = omap1_clk_set_rate,
690 .clk_disable_unused = omap1_clk_disable_unused,
693 int __init omap1_clk_init(void)
696 const struct omap_clock_config *info;
697 int crystal_type = 0; /* Default 12 MHz */
700 #ifdef CONFIG_DEBUG_LL
702 * Resets some clocks that may be left on from bootloader,
703 * but leaves serial clocks on.
705 omap_writel(0x3 << 29, MOD_CONF_CTRL_0);
708 /* USB_REQ_EN will be disabled later if necessary (usb_dc_ck) */
709 reg = omap_readw(SOFT_REQ_REG) & (1 << 4);
710 omap_writew(reg, SOFT_REQ_REG);
711 if (!cpu_is_omap15xx())
712 omap_writew(0, SOFT_REQ_REG2);
714 clk_init(&omap1_clk_functions);
716 /* By default all idlect1 clocks are allowed to idle */
717 arm_idlect1_mask = ~0;
719 for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++)
720 clk_preinit(c->lk.clk);
723 if (cpu_is_omap16xx())
725 if (cpu_is_omap1510())
727 if (cpu_is_omap7xx())
729 if (cpu_is_omap310())
732 for (c = omap_clks; c < omap_clks + ARRAY_SIZE(omap_clks); c++)
733 if (c->cpu & cpu_mask) {
735 clk_register(c->lk.clk);
738 /* Pointers to these clocks are needed by code in clock.c */
739 api_ck_p = clk_get(NULL, "api_ck");
740 ck_dpll1_p = clk_get(NULL, "ck_dpll1");
741 ck_ref_p = clk_get(NULL, "ck_ref");
743 info = omap_get_config(OMAP_TAG_CLOCK, struct omap_clock_config);
745 if (!cpu_is_omap15xx())
746 crystal_type = info->system_clock_type;
749 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
750 ck_ref.rate = 13000000;
751 #elif defined(CONFIG_ARCH_OMAP16XX)
752 if (crystal_type == 2)
753 ck_ref.rate = 19200000;
756 pr_info("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: "
757 "0x%04x\n", omap_readw(ARM_SYSST), omap_readw(DPLL_CTL),
758 omap_readw(ARM_CKCTL));
760 /* We want to be in syncronous scalable mode */
761 omap_writew(0x1000, ARM_SYSST);
763 #ifdef CONFIG_OMAP_CLOCKS_SET_BY_BOOTLOADER
764 /* Use values set by bootloader. Determine PLL rate and recalculate
765 * dependent clocks as if kernel had changed PLL or divisors.
768 unsigned pll_ctl_val = omap_readw(DPLL_CTL);
770 ck_dpll1.rate = ck_ref.rate; /* Base xtal rate */
771 if (pll_ctl_val & 0x10) {
772 /* PLL enabled, apply multiplier and divisor */
773 if (pll_ctl_val & 0xf80)
774 ck_dpll1.rate *= (pll_ctl_val & 0xf80) >> 7;
775 ck_dpll1.rate /= ((pll_ctl_val & 0x60) >> 5) + 1;
777 /* PLL disabled, apply bypass divisor */
778 switch (pll_ctl_val & 0xc) {
791 /* Find the highest supported frequency and enable it */
792 if (omap1_select_table_rate(&virtual_ck_mpu, ~0)) {
793 printk(KERN_ERR "System frequencies not set. Check your config.\n");
794 /* Guess sane values (60MHz) */
795 omap_writew(0x2290, DPLL_CTL);
796 omap_writew(cpu_is_omap7xx() ? 0x3005 : 0x1005, ARM_CKCTL);
797 ck_dpll1.rate = 60000000;
800 propagate_rate(&ck_dpll1);
801 /* Cache rates for clocks connected to ck_ref (not dpll1) */
802 propagate_rate(&ck_ref);
803 printk(KERN_INFO "Clocking rate (xtal/DPLL1/MPU): "
804 "%ld.%01ld/%ld.%01ld/%ld.%01ld MHz\n",
805 ck_ref.rate / 1000000, (ck_ref.rate / 100000) % 10,
806 ck_dpll1.rate / 1000000, (ck_dpll1.rate / 100000) % 10,
807 arm_ck.rate / 1000000, (arm_ck.rate / 100000) % 10);
809 #if defined(CONFIG_MACH_OMAP_PERSEUS2) || defined(CONFIG_MACH_OMAP_FSAMPLE)
810 /* Select slicer output as OMAP input clock */
811 omap_writew(omap_readw(OMAP7XX_PCC_UPLD_CTRL) & ~0x1, OMAP7XX_PCC_UPLD_CTRL);
814 /* Amstrad Delta wants BCLK high when inactive */
815 if (machine_is_ams_delta())
816 omap_writel(omap_readl(ULPD_CLOCK_CTRL) |
817 (1 << SDW_MCLK_INV_BIT),
820 /* Turn off DSP and ARM_TIMXO. Make sure ARM_INTHCK is not divided */
821 /* (on 730, bit 13 must not be cleared) */
822 if (cpu_is_omap7xx())
823 omap_writew(omap_readw(ARM_CKCTL) & 0x2fff, ARM_CKCTL);
825 omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL);
827 /* Put DSP/MPUI into reset until needed */
828 omap_writew(0, ARM_RSTCT1);
829 omap_writew(1, ARM_RSTCT2);
830 omap_writew(0x400, ARM_IDLECT1);
833 * According to OMAP5910 Erratum SYS_DMA_1, bit DMACK_REQ (bit 8)
834 * of the ARM_IDLECT2 register must be set to zero. The power-on
835 * default value of this bit is one.
837 omap_writew(0x0000, ARM_IDLECT2); /* Turn LCD clock off also */
840 * Only enable those clocks we will need, let the drivers
841 * enable other clocks as necessary
843 clk_enable(&armper_ck.clk);
844 clk_enable(&armxor_ck.clk);
845 clk_enable(&armtim_ck.clk); /* This should be done by timer code */
847 if (cpu_is_omap15xx())
848 clk_enable(&arm_gpio_ck);