2 * OMAP1/OMAP7xx - specific DMA driver
4 * Copyright (C) 2003 - 2008 Nokia Corporation
5 * Author: Juha Yrjölä <juha.yrjola@nokia.com>
6 * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
7 * Graphics DMA and LCD DMA graphics tranformations
8 * by Imre Deak <imre.deak@nokia.com>
9 * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
10 * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
12 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
13 * Converted DMA library into platform driver
14 * - G, Manjunath Kondaiah <manjugk@ti.com>
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
21 #include <linux/err.h>
22 #include <linux/slab.h>
23 #include <linux/module.h>
24 #include <linux/init.h>
25 #include <linux/device.h>
30 #include <plat/irqs.h>
32 #define OMAP1_DMA_BASE (0xfffed800)
33 #define OMAP1_LOGICAL_DMA_CH_COUNT 17
34 #define OMAP1_DMA_STRIDE 0x40
37 static u32 enable_1510_mode;
39 static enum omap_reg_offsets dma_common_ch_start, dma_common_ch_end;
41 static u16 reg_map[] = {
61 /* Common Registers */
70 [CPC] = 0x18, /* 15xx only */
77 /* Channel specific register offsets */
85 static struct resource res[] __initdata = {
87 .start = OMAP1_DMA_BASE,
88 .end = OMAP1_DMA_BASE + SZ_2K - 1,
89 .flags = IORESOURCE_MEM,
93 .start = INT_DMA_CH0_6,
94 .flags = IORESOURCE_IRQ,
98 .start = INT_DMA_CH1_7,
99 .flags = IORESOURCE_IRQ,
103 .start = INT_DMA_CH2_8,
104 .flags = IORESOURCE_IRQ,
108 .start = INT_DMA_CH3,
109 .flags = IORESOURCE_IRQ,
113 .start = INT_DMA_CH4,
114 .flags = IORESOURCE_IRQ,
118 .start = INT_DMA_CH5,
119 .flags = IORESOURCE_IRQ,
121 /* Handled in lcd_dma.c */
124 .start = INT_1610_DMA_CH6,
125 .flags = IORESOURCE_IRQ,
127 /* irq's for omap16xx and omap7xx */
130 .start = INT_1610_DMA_CH7,
131 .flags = IORESOURCE_IRQ,
135 .start = INT_1610_DMA_CH8,
136 .flags = IORESOURCE_IRQ,
140 .start = INT_1610_DMA_CH9,
141 .flags = IORESOURCE_IRQ,
145 .start = INT_1610_DMA_CH10,
146 .flags = IORESOURCE_IRQ,
150 .start = INT_1610_DMA_CH11,
151 .flags = IORESOURCE_IRQ,
155 .start = INT_1610_DMA_CH12,
156 .flags = IORESOURCE_IRQ,
160 .start = INT_1610_DMA_CH13,
161 .flags = IORESOURCE_IRQ,
165 .start = INT_1610_DMA_CH14,
166 .flags = IORESOURCE_IRQ,
170 .start = INT_1610_DMA_CH15,
171 .flags = IORESOURCE_IRQ,
175 .start = INT_DMA_LCD,
176 .flags = IORESOURCE_IRQ,
180 static void __iomem *dma_base;
181 static inline void dma_write(u32 val, int reg, int lch)
186 stride = (reg >= dma_common_ch_start) ? dma_stride : 0;
187 offset = reg_map[reg] + (stride * lch);
189 __raw_writew(val, dma_base + offset);
190 if ((reg > CLNK_CTRL && reg < CCEN) ||
191 (reg > PCHD_ID && reg < CAPS_2)) {
192 u32 offset2 = reg_map[reg] + 2 + (stride * lch);
193 __raw_writew(val >> 16, dma_base + offset2);
197 static inline u32 dma_read(int reg, int lch)
202 stride = (reg >= dma_common_ch_start) ? dma_stride : 0;
203 offset = reg_map[reg] + (stride * lch);
205 val = __raw_readw(dma_base + offset);
206 if ((reg > CLNK_CTRL && reg < CCEN) ||
207 (reg > PCHD_ID && reg < CAPS_2)) {
209 u32 offset2 = reg_map[reg] + 2 + (stride * lch);
210 upper = __raw_readw(dma_base + offset2);
211 val |= (upper << 16);
216 static void omap1_clear_lch_regs(int lch)
218 int i = dma_common_ch_start;
220 for (; i <= dma_common_ch_end; i += 1)
221 dma_write(0, i, lch);
224 static void omap1_clear_dma(int lch)
228 l = dma_read(CCR, lch);
229 l &= ~OMAP_DMA_CCR_EN;
230 dma_write(l, CCR, lch);
232 /* Clear pending interrupts */
233 l = dma_read(CSR, lch);
236 static void omap1_show_dma_caps(void)
238 if (enable_1510_mode) {
239 printk(KERN_INFO "DMA support for OMAP15xx initialized\n");
242 printk(KERN_INFO "OMAP DMA hardware version %d\n",
244 printk(KERN_INFO "DMA capabilities: %08x:%08x:%04x:%04x:%04x\n",
245 dma_read(CAPS_0, 0), dma_read(CAPS_1, 0),
246 dma_read(CAPS_2, 0), dma_read(CAPS_3, 0),
247 dma_read(CAPS_4, 0));
249 /* Disable OMAP 3.0/3.1 compatibility mode. */
250 w = dma_read(GSCR, 0);
252 dma_write(w, GSCR, 0);
257 static u32 configure_dma_errata(void)
261 * Erratum 3.2/3.3: sometimes 0 is returned if CSAC/CDAC is
262 * read before the DMA controller finished disabling the channel.
264 if (!cpu_is_omap15xx())
265 SET_DMA_ERRATA(DMA_ERRATA_3_3);
270 static int __init omap1_system_dma_init(void)
272 struct omap_system_dma_plat_info *p;
273 struct omap_dma_dev_attr *d;
274 struct platform_device *pdev;
277 pdev = platform_device_alloc("omap_dma_system", 0);
279 pr_err("%s: Unable to device alloc for dma\n",
284 dma_base = ioremap(res[0].start, resource_size(&res[0]));
286 pr_err("%s: Unable to ioremap\n", __func__);
288 goto exit_device_put;
291 ret = platform_device_add_resources(pdev, res, ARRAY_SIZE(res));
293 dev_err(&pdev->dev, "%s: Unable to add resources for %s%d\n",
294 __func__, pdev->name, pdev->id);
295 goto exit_device_put;
298 p = kzalloc(sizeof(struct omap_system_dma_plat_info), GFP_KERNEL);
300 dev_err(&pdev->dev, "%s: Unable to allocate 'p' for %s\n",
301 __func__, pdev->name);
303 goto exit_device_del;
306 d = kzalloc(sizeof(struct omap_dma_dev_attr), GFP_KERNEL);
308 dev_err(&pdev->dev, "%s: Unable to allocate 'd' for %s\n",
309 __func__, pdev->name);
314 d->lch_count = OMAP1_LOGICAL_DMA_CH_COUNT;
316 /* Valid attributes for omap1 plus processors */
317 if (cpu_is_omap15xx())
318 d->dev_caps = ENABLE_1510_MODE;
319 enable_1510_mode = d->dev_caps & ENABLE_1510_MODE;
321 d->dev_caps |= SRC_PORT;
322 d->dev_caps |= DST_PORT;
323 d->dev_caps |= SRC_INDEX;
324 d->dev_caps |= DST_INDEX;
325 d->dev_caps |= IS_BURST_ONLY4;
326 d->dev_caps |= CLEAR_CSR_ON_READ;
327 d->dev_caps |= IS_WORD_16;
330 d->chan = kzalloc(sizeof(struct omap_dma_lch) *
331 (d->lch_count), GFP_KERNEL);
333 dev_err(&pdev->dev, "%s: Memory allocation failed"
334 "for d->chan!!!\n", __func__);
338 if (cpu_is_omap15xx())
340 else if (cpu_is_omap16xx() || cpu_is_omap7xx()) {
341 if (!(d->dev_caps & ENABLE_1510_MODE))
349 p->show_dma_caps = omap1_show_dma_caps;
350 p->clear_lch_regs = omap1_clear_lch_regs;
351 p->clear_dma = omap1_clear_dma;
352 p->dma_write = dma_write;
353 p->dma_read = dma_read;
354 p->disable_irq_lch = NULL;
356 p->errata = configure_dma_errata();
358 ret = platform_device_add_data(pdev, p, sizeof(*p));
360 dev_err(&pdev->dev, "%s: Unable to add resources for %s%d\n",
361 __func__, pdev->name, pdev->id);
362 goto exit_release_chan;
365 ret = platform_device_add(pdev);
367 dev_err(&pdev->dev, "%s: Unable to add resources for %s%d\n",
368 __func__, pdev->name, pdev->id);
369 goto exit_release_chan;
372 dma_stride = OMAP1_DMA_STRIDE;
373 dma_common_ch_start = CPC;
374 dma_common_ch_end = COLOR;
385 platform_device_del(pdev);
387 platform_device_put(pdev);
391 arch_initcall(omap1_system_dma_init);