arch/arm/mach-omap2/cclock33xx_data.c

   1 /*
   2  * AM33XX Clock data
   3  *
   4  * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
   5  * Vaibhav Hiremath <hvaibhav@ti.com>
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation version 2.
  10  *
  11  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  12  * kind, whether express or implied; without even the implied warranty
  13  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <linux/kernel.h>
  18 #include <linux/list.h>
  19 #include <linux/clk-private.h>
  20 #include <linux/clkdev.h>
  21 #include <linux/io.h>
  22
  23 #include "am33xx.h"
  24 #include "soc.h"
  25 #include "iomap.h"
  26 #include "clock.h"
  27 #include "control.h"
  28 #include "cm.h"
  29 #include "cm33xx.h"
  30 #include "cm-regbits-33xx.h"
  31 #include "prm.h"
  32
  33 /* Modulemode control */
  34 #define AM33XX_MODULEMODE_HWCTRL_SHIFT          0
  35 #define AM33XX_MODULEMODE_SWCTRL_SHIFT          1
  36
  37 /*LIST_HEAD(clocks);*/
  38
  39 /* Root clocks */
  40
  41 /* RTC 32k */
  42 DEFINE_CLK_FIXED_RATE(clk_32768_ck, CLK_IS_ROOT, 32768, 0x0);
  43
  44 /* On-Chip 32KHz RC OSC */
  45 DEFINE_CLK_FIXED_RATE(clk_rc32k_ck, CLK_IS_ROOT, 32000, 0x0);
  46
  47 /* Crystal input clks */
  48 DEFINE_CLK_FIXED_RATE(virt_19200000_ck, CLK_IS_ROOT, 19200000, 0x0);
  49
  50 DEFINE_CLK_FIXED_RATE(virt_24000000_ck, CLK_IS_ROOT, 24000000, 0x0);
  51
  52 DEFINE_CLK_FIXED_RATE(virt_25000000_ck, CLK_IS_ROOT, 25000000, 0x0);
  53
  54 DEFINE_CLK_FIXED_RATE(virt_26000000_ck, CLK_IS_ROOT, 26000000, 0x0);
  55
  56 /* Oscillator clock */
  57 /* 19.2, 24, 25 or 26 MHz */
  58 static const char *sys_clkin_ck_parents[] = {
  59         "virt_19200000_ck", "virt_24000000_ck", "virt_25000000_ck",
  60         "virt_26000000_ck",
  61 };
  62
  63 /*
  64  * sys_clk in: input to the dpll and also used as funtional clock for,
  65  *   adc_tsc, smartreflex0-1, timer1-7, mcasp0-1, dcan0-1, cefuse
  66  *
  67  */
  68 DEFINE_CLK_MUX(sys_clkin_ck, sys_clkin_ck_parents, NULL, 0x0,
  69                AM33XX_CTRL_REGADDR(AM33XX_CONTROL_STATUS),
  70                AM33XX_CONTROL_STATUS_SYSBOOT1_SHIFT,
  71                AM33XX_CONTROL_STATUS_SYSBOOT1_WIDTH,
  72                0, NULL);
  73
  74 /* External clock - 12 MHz */
  75 DEFINE_CLK_FIXED_RATE(tclkin_ck, CLK_IS_ROOT, 12000000, 0x0);
  76
  77 /* Module clocks and DPLL outputs */
  78
  79 /* DPLL_CORE */
  80 static struct dpll_data dpll_core_dd = {
  81         .mult_div1_reg  = AM33XX_CM_CLKSEL_DPLL_CORE,
  82         .clk_bypass     = &sys_clkin_ck,
  83         .clk_ref        = &sys_clkin_ck,
  84         .control_reg    = AM33XX_CM_CLKMODE_DPLL_CORE,
  85         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
  86         .idlest_reg     = AM33XX_CM_IDLEST_DPLL_CORE,
  87         .mult_mask      = AM33XX_DPLL_MULT_MASK,
  88         .div1_mask      = AM33XX_DPLL_DIV_MASK,
  89         .enable_mask    = AM33XX_DPLL_EN_MASK,
  90         .idlest_mask    = AM33XX_ST_DPLL_CLK_MASK,
  91         .max_multiplier = 2047,
  92         .max_divider    = 128,
  93         .min_divider    = 1,
  94 };
  95
  96 /* CLKDCOLDO output */
  97 static const char *dpll_core_ck_parents[] = {
  98         "sys_clkin_ck",
  99 };
 100
 101 static struct clk dpll_core_ck;
 102
 103 static const struct clk_ops dpll_core_ck_ops = {
 104         .recalc_rate    = &omap3_dpll_recalc,
 105         .get_parent     = &omap2_init_dpll_parent,
 106 };
 107
 108 static struct clk_hw_omap dpll_core_ck_hw = {
 109         .hw     = {
 110                 .clk    = &dpll_core_ck,
 111         },
 112         .dpll_data      = &dpll_core_dd,
 113         .ops            = &clkhwops_omap3_dpll,
 114 };
 115
 116 DEFINE_STRUCT_CLK(dpll_core_ck, dpll_core_ck_parents, dpll_core_ck_ops);
 117
 118 static const char *dpll_core_x2_ck_parents[] = {
 119         "dpll_core_ck",
 120 };
 121
 122 static struct clk dpll_core_x2_ck;
 123
 124 static const struct clk_ops dpll_x2_ck_ops = {
 125         .recalc_rate    = &omap3_clkoutx2_recalc,
 126 };
 127
 128 static struct clk_hw_omap dpll_core_x2_ck_hw = {
 129         .hw     = {
 130                 .clk    = &dpll_core_x2_ck,
 131         },
 132         .flags          = CLOCK_CLKOUTX2,
 133 };
 134
 135 DEFINE_STRUCT_CLK(dpll_core_x2_ck, dpll_core_x2_ck_parents, dpll_x2_ck_ops);
 136
 137 DEFINE_CLK_DIVIDER(dpll_core_m4_ck, "dpll_core_x2_ck", &dpll_core_x2_ck,
 138                    0x0, AM33XX_CM_DIV_M4_DPLL_CORE,
 139                    AM33XX_HSDIVIDER_CLKOUT1_DIV_SHIFT,
 140                    AM33XX_HSDIVIDER_CLKOUT1_DIV_WIDTH, CLK_DIVIDER_ONE_BASED,
 141                    NULL);
 142
 143 DEFINE_CLK_DIVIDER(dpll_core_m5_ck, "dpll_core_x2_ck", &dpll_core_x2_ck,
 144                    0x0, AM33XX_CM_DIV_M5_DPLL_CORE,
 145                    AM33XX_HSDIVIDER_CLKOUT2_DIV_SHIFT,
 146                    AM33XX_HSDIVIDER_CLKOUT2_DIV_WIDTH,
 147                    CLK_DIVIDER_ONE_BASED, NULL);
 148
 149 DEFINE_CLK_DIVIDER(dpll_core_m6_ck, "dpll_core_x2_ck", &dpll_core_x2_ck,
 150                    0x0, AM33XX_CM_DIV_M6_DPLL_CORE,
 151                    AM33XX_HSDIVIDER_CLKOUT3_DIV_SHIFT,
 152                    AM33XX_HSDIVIDER_CLKOUT3_DIV_WIDTH,
 153                    CLK_DIVIDER_ONE_BASED, NULL);
 154
 155
 156 /* DPLL_MPU */
 157 static struct dpll_data dpll_mpu_dd = {
 158         .mult_div1_reg  = AM33XX_CM_CLKSEL_DPLL_MPU,
 159         .clk_bypass     = &sys_clkin_ck,
 160         .clk_ref        = &sys_clkin_ck,
 161         .control_reg    = AM33XX_CM_CLKMODE_DPLL_MPU,
 162         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 163         .idlest_reg     = AM33XX_CM_IDLEST_DPLL_MPU,
 164         .mult_mask      = AM33XX_DPLL_MULT_MASK,
 165         .div1_mask      = AM33XX_DPLL_DIV_MASK,
 166         .enable_mask    = AM33XX_DPLL_EN_MASK,
 167         .idlest_mask    = AM33XX_ST_DPLL_CLK_MASK,
 168         .max_multiplier = 2047,
 169         .max_divider    = 128,
 170         .min_divider    = 1,
 171 };
 172
 173 /* CLKOUT: fdpll/M2 */
 174 static struct clk dpll_mpu_ck;
 175
 176 static const struct clk_ops dpll_mpu_ck_ops = {
 177         .enable         = &omap3_noncore_dpll_enable,
 178         .disable        = &omap3_noncore_dpll_disable,
 179         .recalc_rate    = &omap3_dpll_recalc,
 180         .round_rate     = &omap2_dpll_round_rate,
 181         .set_rate       = &omap3_noncore_dpll_set_rate,
 182         .get_parent     = &omap2_init_dpll_parent,
 183 };
 184
 185 static struct clk_hw_omap dpll_mpu_ck_hw = {
 186         .hw = {
 187                 .clk    = &dpll_mpu_ck,
 188         },
 189         .dpll_data      = &dpll_mpu_dd,
 190         .ops            = &clkhwops_omap3_dpll,
 191 };
 192
 193 DEFINE_STRUCT_CLK(dpll_mpu_ck, dpll_core_ck_parents, dpll_mpu_ck_ops);
 194
 195 /*
 196  * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2
 197  * and ALT_CLK1/2)
 198  */
 199 DEFINE_CLK_DIVIDER(dpll_mpu_m2_ck, "dpll_mpu_ck", &dpll_mpu_ck,
 200                    0x0, AM33XX_CM_DIV_M2_DPLL_MPU, AM33XX_DPLL_CLKOUT_DIV_SHIFT,
 201                    AM33XX_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL);
 202
 203 /* DPLL_DDR */
 204 static struct dpll_data dpll_ddr_dd = {
 205         .mult_div1_reg  = AM33XX_CM_CLKSEL_DPLL_DDR,
 206         .clk_bypass     = &sys_clkin_ck,
 207         .clk_ref        = &sys_clkin_ck,
 208         .control_reg    = AM33XX_CM_CLKMODE_DPLL_DDR,
 209         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 210         .idlest_reg     = AM33XX_CM_IDLEST_DPLL_DDR,
 211         .mult_mask      = AM33XX_DPLL_MULT_MASK,
 212         .div1_mask      = AM33XX_DPLL_DIV_MASK,
 213         .enable_mask    = AM33XX_DPLL_EN_MASK,
 214         .idlest_mask    = AM33XX_ST_DPLL_CLK_MASK,
 215         .max_multiplier = 2047,
 216         .max_divider    = 128,
 217         .min_divider    = 1,
 218 };
 219
 220 /* CLKOUT: fdpll/M2 */
 221 static struct clk dpll_ddr_ck;
 222
 223 static const struct clk_ops dpll_ddr_ck_ops = {
 224         .recalc_rate    = &omap3_dpll_recalc,
 225         .get_parent     = &omap2_init_dpll_parent,
 226         .round_rate     = &omap2_dpll_round_rate,
 227         .set_rate       = &omap3_noncore_dpll_set_rate,
 228 };
 229
 230 static struct clk_hw_omap dpll_ddr_ck_hw = {
 231         .hw = {
 232                 .clk    = &dpll_ddr_ck,
 233         },
 234         .dpll_data      = &dpll_ddr_dd,
 235         .ops            = &clkhwops_omap3_dpll,
 236 };
 237
 238 DEFINE_STRUCT_CLK(dpll_ddr_ck, dpll_core_ck_parents, dpll_ddr_ck_ops);
 239
 240 /*
 241  * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2
 242  * and ALT_CLK1/2)
 243  */
 244 DEFINE_CLK_DIVIDER(dpll_ddr_m2_ck, "dpll_ddr_ck", &dpll_ddr_ck,
 245                    0x0, AM33XX_CM_DIV_M2_DPLL_DDR,
 246                    AM33XX_DPLL_CLKOUT_DIV_SHIFT, AM33XX_DPLL_CLKOUT_DIV_WIDTH,
 247                    CLK_DIVIDER_ONE_BASED, NULL);
 248
 249 /* emif_fck functional clock */
 250 DEFINE_CLK_FIXED_FACTOR(dpll_ddr_m2_div2_ck, "dpll_ddr_m2_ck", &dpll_ddr_m2_ck,
 251                         0x0, 1, 2);
 252
 253 /* DPLL_DISP */
 254 static struct dpll_data dpll_disp_dd = {
 255         .mult_div1_reg  = AM33XX_CM_CLKSEL_DPLL_DISP,
 256         .clk_bypass     = &sys_clkin_ck,
 257         .clk_ref        = &sys_clkin_ck,
 258         .control_reg    = AM33XX_CM_CLKMODE_DPLL_DISP,
 259         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 260         .idlest_reg     = AM33XX_CM_IDLEST_DPLL_DISP,
 261         .mult_mask      = AM33XX_DPLL_MULT_MASK,
 262         .div1_mask      = AM33XX_DPLL_DIV_MASK,
 263         .enable_mask    = AM33XX_DPLL_EN_MASK,
 264         .idlest_mask    = AM33XX_ST_DPLL_CLK_MASK,
 265         .max_multiplier = 2047,
 266         .max_divider    = 128,
 267         .min_divider    = 1,
 268 };
 269
 270 /* CLKOUT: fdpll/M2 */
 271 static struct clk dpll_disp_ck;
 272
 273 static struct clk_hw_omap dpll_disp_ck_hw = {
 274         .hw = {
 275                 .clk    = &dpll_disp_ck,
 276         },
 277         .dpll_data      = &dpll_disp_dd,
 278         .ops            = &clkhwops_omap3_dpll,
 279 };
 280
 281 DEFINE_STRUCT_CLK(dpll_disp_ck, dpll_core_ck_parents, dpll_ddr_ck_ops);
 282
 283 /*
 284  * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2
 285  * and ALT_CLK1/2)
 286  */
 287 DEFINE_CLK_DIVIDER(dpll_disp_m2_ck, "dpll_disp_ck", &dpll_disp_ck,
 288                    CLK_SET_RATE_PARENT, AM33XX_CM_DIV_M2_DPLL_DISP,
 289                    AM33XX_DPLL_CLKOUT_DIV_SHIFT, AM33XX_DPLL_CLKOUT_DIV_WIDTH,
 290                    CLK_DIVIDER_ONE_BASED, NULL);
 291
 292 /* DPLL_PER */
 293 static struct dpll_data dpll_per_dd = {
 294         .mult_div1_reg  = AM33XX_CM_CLKSEL_DPLL_PERIPH,
 295         .clk_bypass     = &sys_clkin_ck,
 296         .clk_ref        = &sys_clkin_ck,
 297         .control_reg    = AM33XX_CM_CLKMODE_DPLL_PER,
 298         .modes          = (1 << DPLL_LOW_POWER_BYPASS) | (1 << DPLL_LOCKED),
 299         .idlest_reg     = AM33XX_CM_IDLEST_DPLL_PER,
 300         .mult_mask      = AM33XX_DPLL_MULT_PERIPH_MASK,
 301         .div1_mask      = AM33XX_DPLL_PER_DIV_MASK,
 302         .enable_mask    = AM33XX_DPLL_EN_MASK,
 303         .idlest_mask    = AM33XX_ST_DPLL_CLK_MASK,
 304         .max_multiplier = 2047,
 305         .max_divider    = 128,
 306         .min_divider    = 1,
 307         .flags          = DPLL_J_TYPE,
 308 };
 309
 310 /* CLKDCOLDO */
 311 static struct clk dpll_per_ck;
 312
 313 static struct clk_hw_omap dpll_per_ck_hw = {
 314         .hw     = {
 315                 .clk    = &dpll_per_ck,
 316         },
 317         .dpll_data      = &dpll_per_dd,
 318         .ops            = &clkhwops_omap3_dpll,
 319 };
 320
 321 DEFINE_STRUCT_CLK(dpll_per_ck, dpll_core_ck_parents, dpll_ddr_ck_ops);
 322
 323 /* CLKOUT: fdpll/M2 */
 324 DEFINE_CLK_DIVIDER(dpll_per_m2_ck, "dpll_per_ck", &dpll_per_ck, 0x0,
 325                    AM33XX_CM_DIV_M2_DPLL_PER, AM33XX_DPLL_CLKOUT_DIV_SHIFT,
 326                    AM33XX_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED,
 327                    NULL);
 328
 329 DEFINE_CLK_FIXED_FACTOR(dpll_per_m2_div4_wkupdm_ck, "dpll_per_m2_ck",
 330                         &dpll_per_m2_ck, 0x0, 1, 4);
 331
 332 DEFINE_CLK_FIXED_FACTOR(dpll_per_m2_div4_ck, "dpll_per_m2_ck",
 333                         &dpll_per_m2_ck, 0x0, 1, 4);
 334
 335 DEFINE_CLK_FIXED_FACTOR(dpll_core_m4_div2_ck, "dpll_core_m4_ck",
 336                         &dpll_core_m4_ck, 0x0, 1, 2);
 337
 338 DEFINE_CLK_FIXED_FACTOR(l4_rtc_gclk, "dpll_core_m4_ck", &dpll_core_m4_ck, 0x0,
 339                         1, 2);
 340
 341 DEFINE_CLK_FIXED_FACTOR(clk_24mhz, "dpll_per_m2_ck", &dpll_per_m2_ck, 0x0, 1,
 342                         8);
 343
 344 /*
 345  * Below clock nodes describes clockdomains derived out
 346  * of core clock.
 347  */
 348 static const struct clk_ops clk_ops_null = {
 349 };
 350
 351 static const char *l3_gclk_parents[] = {
 352         "dpll_core_m4_ck"
 353 };
 354
 355 static struct clk l3_gclk;
 356 DEFINE_STRUCT_CLK_HW_OMAP(l3_gclk, NULL);
 357 DEFINE_STRUCT_CLK(l3_gclk, l3_gclk_parents, clk_ops_null);
 358
 359 static struct clk l4hs_gclk;
 360 DEFINE_STRUCT_CLK_HW_OMAP(l4hs_gclk, NULL);
 361 DEFINE_STRUCT_CLK(l4hs_gclk, l3_gclk_parents, clk_ops_null);
 362
 363 static const char *l3s_gclk_parents[] = {
 364         "dpll_core_m4_div2_ck"
 365 };
 366
 367 static struct clk l3s_gclk;
 368 DEFINE_STRUCT_CLK_HW_OMAP(l3s_gclk, NULL);
 369 DEFINE_STRUCT_CLK(l3s_gclk, l3s_gclk_parents, clk_ops_null);
 370
 371 static struct clk l4fw_gclk;
 372 DEFINE_STRUCT_CLK_HW_OMAP(l4fw_gclk, NULL);
 373 DEFINE_STRUCT_CLK(l4fw_gclk, l3s_gclk_parents, clk_ops_null);
 374
 375 static struct clk l4ls_gclk;
 376 DEFINE_STRUCT_CLK_HW_OMAP(l4ls_gclk, NULL);
 377 DEFINE_STRUCT_CLK(l4ls_gclk, l3s_gclk_parents, clk_ops_null);
 378
 379 static struct clk sysclk_div_ck;
 380 DEFINE_STRUCT_CLK_HW_OMAP(sysclk_div_ck, NULL);
 381 DEFINE_STRUCT_CLK(sysclk_div_ck, l3_gclk_parents, clk_ops_null);
 382
 383 /*
 384  * In order to match the clock domain with hwmod clockdomain entry,
 385  * separate clock nodes is required for the modules which are
 386  * directly getting their funtioncal clock from sys_clkin.
 387  */
 388 static struct clk adc_tsc_fck;
 389 DEFINE_STRUCT_CLK_HW_OMAP(adc_tsc_fck, NULL);
 390 DEFINE_STRUCT_CLK(adc_tsc_fck, dpll_core_ck_parents, clk_ops_null);
 391
 392 static struct clk dcan0_fck;
 393 DEFINE_STRUCT_CLK_HW_OMAP(dcan0_fck, NULL);
 394 DEFINE_STRUCT_CLK(dcan0_fck, dpll_core_ck_parents, clk_ops_null);
 395
 396 static struct clk dcan1_fck;
 397 DEFINE_STRUCT_CLK_HW_OMAP(dcan1_fck, NULL);
 398 DEFINE_STRUCT_CLK(dcan1_fck, dpll_core_ck_parents, clk_ops_null);
 399
 400 static struct clk mcasp0_fck;
 401 DEFINE_STRUCT_CLK_HW_OMAP(mcasp0_fck, NULL);
 402 DEFINE_STRUCT_CLK(mcasp0_fck, dpll_core_ck_parents, clk_ops_null);
 403
 404 static struct clk mcasp1_fck;
 405 DEFINE_STRUCT_CLK_HW_OMAP(mcasp1_fck, NULL);
 406 DEFINE_STRUCT_CLK(mcasp1_fck, dpll_core_ck_parents, clk_ops_null);
 407
 408 static struct clk smartreflex0_fck;
 409 DEFINE_STRUCT_CLK_HW_OMAP(smartreflex0_fck, NULL);
 410 DEFINE_STRUCT_CLK(smartreflex0_fck, dpll_core_ck_parents, clk_ops_null);
 411
 412 static struct clk smartreflex1_fck;
 413 DEFINE_STRUCT_CLK_HW_OMAP(smartreflex1_fck, NULL);
 414 DEFINE_STRUCT_CLK(smartreflex1_fck, dpll_core_ck_parents, clk_ops_null);
 415
 416 static struct clk sha0_fck;
 417 DEFINE_STRUCT_CLK_HW_OMAP(sha0_fck, NULL);
 418 DEFINE_STRUCT_CLK(sha0_fck, dpll_core_ck_parents, clk_ops_null);
 419
 420 static struct clk aes0_fck;
 421 DEFINE_STRUCT_CLK_HW_OMAP(aes0_fck, NULL);
 422 DEFINE_STRUCT_CLK(aes0_fck, dpll_core_ck_parents, clk_ops_null);
 423
 424 /*
 425  * Modules clock nodes
 426  *
 427  * The following clock leaf nodes are added for the moment because:
 428  *
 429  *  - hwmod data is not present for these modules, either hwmod
 430  *    control is not required or its not populated.
 431  *  - Driver code is not yet migrated to use hwmod/runtime pm
 432  *  - Modules outside kernel access (to disable them by default)
 433  *
 434  *     - mmu (gfx domain)
 435  *     - cefuse
 436  *     - usbotg_fck (its additional clock and not really a modulemode)
 437  *     - ieee5000
 438  */
 439
 440 DEFINE_CLK_GATE(mmu_fck, "dpll_core_m4_ck", &dpll_core_m4_ck, 0x0,
 441                 AM33XX_CM_GFX_MMUDATA_CLKCTRL, AM33XX_MODULEMODE_SWCTRL_SHIFT,
 442                 0x0, NULL);
 443
 444 DEFINE_CLK_GATE(cefuse_fck, "sys_clkin_ck", &sys_clkin_ck, 0x0,
 445                 AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL, AM33XX_MODULEMODE_SWCTRL_SHIFT,
 446                 0x0, NULL);
 447
 448 /*
 449  * clkdiv32 is generated from fixed division of 732.4219
 450  */
 451 DEFINE_CLK_FIXED_FACTOR(clkdiv32k_ck, "clk_24mhz", &clk_24mhz, 0x0, 1, 732);
 452
 453 static struct clk clkdiv32k_ick;
 454
 455 static const char *clkdiv32k_ick_parent_names[] = {
 456         "clkdiv32k_ck",
 457 };
 458
 459 static const struct clk_ops clkdiv32k_ick_ops = {
 460         .enable         = &omap2_dflt_clk_enable,
 461         .disable        = &omap2_dflt_clk_disable,
 462         .is_enabled     = &omap2_dflt_clk_is_enabled,
 463         .init           = &omap2_init_clk_clkdm,
 464 };
 465
 466 static struct clk_hw_omap clkdiv32k_ick_hw = {
 467         .hw     = {
 468                 .clk    = &clkdiv32k_ick,
 469         },
 470         .enable_reg     = AM33XX_CM_PER_CLKDIV32K_CLKCTRL,
 471         .enable_bit     = AM33XX_MODULEMODE_SWCTRL_SHIFT,
 472         .clkdm_name     = "clk_24mhz_clkdm",
 473 };
 474
 475 DEFINE_STRUCT_CLK(clkdiv32k_ick, clkdiv32k_ick_parent_names, clkdiv32k_ick_ops);
 476
 477 /* "usbotg_fck" is an additional clock and not really a modulemode */
 478 DEFINE_CLK_GATE(usbotg_fck, "dpll_per_ck", &dpll_per_ck, 0x0,
 479                 AM33XX_CM_CLKDCOLDO_DPLL_PER, AM33XX_ST_DPLL_CLKDCOLDO_SHIFT,
 480                 0x0, NULL);
 481
 482 DEFINE_CLK_GATE(ieee5000_fck, "dpll_core_m4_div2_ck", &dpll_core_m4_div2_ck,
 483                 0x0, AM33XX_CM_PER_IEEE5000_CLKCTRL,
 484                 AM33XX_MODULEMODE_SWCTRL_SHIFT, 0x0, NULL);
 485
 486 /* Timers */
 487 static const struct clksel timer1_clkmux_sel[] = {
 488         { .parent = &sys_clkin_ck, .rates = div_1_0_rates },
 489         { .parent = &clkdiv32k_ick, .rates = div_1_1_rates },
 490         { .parent = &tclkin_ck, .rates = div_1_2_rates },
 491         { .parent = &clk_rc32k_ck, .rates = div_1_3_rates },
 492         { .parent = &clk_32768_ck, .rates = div_1_4_rates },
 493         { .parent = NULL },
 494 };
 495
 496 static const char *timer1_ck_parents[] = {
 497         "sys_clkin_ck", "clkdiv32k_ick", "tclkin_ck", "clk_rc32k_ck",
 498         "clk_32768_ck",
 499 };
 500
 501 static struct clk timer1_fck;
 502
 503 static const struct clk_ops timer1_fck_ops = {
 504         .recalc_rate    = &omap2_clksel_recalc,
 505         .get_parent     = &omap2_clksel_find_parent_index,
 506         .set_parent     = &omap2_clksel_set_parent,
 507         .init           = &omap2_init_clk_clkdm,
 508 };
 509
 510 static struct clk_hw_omap timer1_fck_hw = {
 511         .hw     = {
 512                 .clk    = &timer1_fck,
 513         },
 514         .clkdm_name     = "l4ls_clkdm",
 515         .clksel         = timer1_clkmux_sel,
 516         .clksel_reg     = AM33XX_CLKSEL_TIMER1MS_CLK,
 517         .clksel_mask    = AM33XX_CLKSEL_0_2_MASK,
 518 };
 519
 520 DEFINE_STRUCT_CLK(timer1_fck, timer1_ck_parents, timer1_fck_ops);
 521
 522 static const struct clksel timer2_to_7_clk_sel[] = {
 523         { .parent = &tclkin_ck, .rates = div_1_0_rates },
 524         { .parent = &sys_clkin_ck, .rates = div_1_1_rates },
 525         { .parent = &clkdiv32k_ick, .rates = div_1_2_rates },
 526         { .parent = NULL },
 527 };
 528
 529 static const char *timer2_to_7_ck_parents[] = {
 530         "tclkin_ck", "sys_clkin_ck", "clkdiv32k_ick",
 531 };
 532
 533 static struct clk timer2_fck;
 534
 535 static struct clk_hw_omap timer2_fck_hw = {
 536         .hw     = {
 537                 .clk    = &timer2_fck,
 538         },
 539         .clkdm_name     = "l4ls_clkdm",
 540         .clksel         = timer2_to_7_clk_sel,
 541         .clksel_reg     = AM33XX_CLKSEL_TIMER2_CLK,
 542         .clksel_mask    = AM33XX_CLKSEL_0_1_MASK,
 543 };
 544
 545 DEFINE_STRUCT_CLK(timer2_fck, timer2_to_7_ck_parents, timer1_fck_ops);
 546
 547 static struct clk timer3_fck;
 548
 549 static struct clk_hw_omap timer3_fck_hw = {
 550         .hw     = {
 551                 .clk    = &timer3_fck,
 552         },
 553         .clkdm_name     = "l4ls_clkdm",
 554         .clksel         = timer2_to_7_clk_sel,
 555         .clksel_reg     = AM33XX_CLKSEL_TIMER3_CLK,
 556         .clksel_mask    = AM33XX_CLKSEL_0_1_MASK,
 557 };
 558
 559 DEFINE_STRUCT_CLK(timer3_fck, timer2_to_7_ck_parents, timer1_fck_ops);
 560
 561 static struct clk timer4_fck;
 562
 563 static struct clk_hw_omap timer4_fck_hw = {
 564         .hw     = {
 565                 .clk    = &timer4_fck,
 566         },
 567         .clkdm_name     = "l4ls_clkdm",
 568         .clksel         = timer2_to_7_clk_sel,
 569         .clksel_reg     = AM33XX_CLKSEL_TIMER4_CLK,
 570         .clksel_mask    = AM33XX_CLKSEL_0_1_MASK,
 571 };
 572
 573 DEFINE_STRUCT_CLK(timer4_fck, timer2_to_7_ck_parents, timer1_fck_ops);
 574
 575 static struct clk timer5_fck;
 576
 577 static struct clk_hw_omap timer5_fck_hw = {
 578         .hw     = {
 579                 .clk    = &timer5_fck,
 580         },
 581         .clkdm_name     = "l4ls_clkdm",
 582         .clksel         = timer2_to_7_clk_sel,
 583         .clksel_reg     = AM33XX_CLKSEL_TIMER5_CLK,
 584         .clksel_mask    = AM33XX_CLKSEL_0_1_MASK,
 585 };
 586
 587 DEFINE_STRUCT_CLK(timer5_fck, timer2_to_7_ck_parents, timer1_fck_ops);
 588
 589 static struct clk timer6_fck;
 590
 591 static struct clk_hw_omap timer6_fck_hw = {
 592         .hw     = {
 593                 .clk    = &timer6_fck,
 594         },
 595         .clkdm_name     = "l4ls_clkdm",
 596         .clksel         = timer2_to_7_clk_sel,
 597         .clksel_reg     = AM33XX_CLKSEL_TIMER6_CLK,
 598         .clksel_mask    = AM33XX_CLKSEL_0_1_MASK,
 599 };
 600
 601 DEFINE_STRUCT_CLK(timer6_fck, timer2_to_7_ck_parents, timer1_fck_ops);
 602
 603 static struct clk timer7_fck;
 604
 605 static struct clk_hw_omap timer7_fck_hw = {
 606         .hw     = {
 607                 .clk    = &timer7_fck,
 608         },
 609         .clkdm_name     = "l4ls_clkdm",
 610         .clksel         = timer2_to_7_clk_sel,
 611         .clksel_reg     = AM33XX_CLKSEL_TIMER7_CLK,
 612         .clksel_mask    = AM33XX_CLKSEL_0_1_MASK,
 613 };
 614
 615 DEFINE_STRUCT_CLK(timer7_fck, timer2_to_7_ck_parents, timer1_fck_ops);
 616
 617 DEFINE_CLK_FIXED_FACTOR(cpsw_125mhz_gclk,
 618                         "dpll_core_m5_ck",
 619                         &dpll_core_m5_ck,
 620                         0x0,
 621                         1, 2);
 622
 623 static const struct clk_ops cpsw_fck_ops = {
 624         .recalc_rate    = &omap2_clksel_recalc,
 625         .get_parent     = &omap2_clksel_find_parent_index,
 626         .set_parent     = &omap2_clksel_set_parent,
 627 };
 628
 629 static const struct clksel cpsw_cpts_rft_clkmux_sel[] = {
 630         { .parent = &dpll_core_m5_ck, .rates = div_1_0_rates },
 631         { .parent = &dpll_core_m4_ck, .rates = div_1_1_rates },
 632         { .parent = NULL },
 633 };
 634
 635 static const char *cpsw_cpts_rft_ck_parents[] = {
 636         "dpll_core_m5_ck", "dpll_core_m4_ck",
 637 };
 638
 639 static struct clk cpsw_cpts_rft_clk;
 640
 641 static struct clk_hw_omap cpsw_cpts_rft_clk_hw = {
 642         .hw     = {
 643                 .clk    = &cpsw_cpts_rft_clk,
 644         },
 645         .clkdm_name     = "cpsw_125mhz_clkdm",
 646         .clksel         = cpsw_cpts_rft_clkmux_sel,
 647         .clksel_reg     = AM33XX_CM_CPTS_RFT_CLKSEL,
 648         .clksel_mask    = AM33XX_CLKSEL_0_0_MASK,
 649 };
 650
 651 DEFINE_STRUCT_CLK(cpsw_cpts_rft_clk, cpsw_cpts_rft_ck_parents, cpsw_fck_ops);
 652
 653
 654 /* gpio */
 655 static const char *gpio0_ck_parents[] = {
 656         "clk_rc32k_ck", "clk_32768_ck", "clkdiv32k_ick",
 657 };
 658
 659 static const struct clksel gpio0_dbclk_mux_sel[] = {
 660         { .parent = &clk_rc32k_ck, .rates = div_1_0_rates },
 661         { .parent = &clk_32768_ck, .rates = div_1_1_rates },
 662         { .parent = &clkdiv32k_ick, .rates = div_1_2_rates },
 663         { .parent = NULL },
 664 };
 665
 666 static const struct clk_ops gpio_fck_ops = {
 667         .recalc_rate    = &omap2_clksel_recalc,
 668         .get_parent     = &omap2_clksel_find_parent_index,
 669         .set_parent     = &omap2_clksel_set_parent,
 670         .init           = &omap2_init_clk_clkdm,
 671 };
 672
 673 static struct clk gpio0_dbclk_mux_ck;
 674
 675 static struct clk_hw_omap gpio0_dbclk_mux_ck_hw = {
 676         .hw     = {
 677                 .clk    = &gpio0_dbclk_mux_ck,
 678         },
 679         .clkdm_name     = "l4_wkup_clkdm",
 680         .clksel         = gpio0_dbclk_mux_sel,
 681         .clksel_reg     = AM33XX_CLKSEL_GPIO0_DBCLK,
 682         .clksel_mask    = AM33XX_CLKSEL_0_1_MASK,
 683 };
 684
 685 DEFINE_STRUCT_CLK(gpio0_dbclk_mux_ck, gpio0_ck_parents, gpio_fck_ops);
 686
 687 DEFINE_CLK_GATE(gpio0_dbclk, "gpio0_dbclk_mux_ck", &gpio0_dbclk_mux_ck, 0x0,
 688                 AM33XX_CM_WKUP_GPIO0_CLKCTRL,
 689                 AM33XX_OPTFCLKEN_GPIO0_GDBCLK_SHIFT, 0x0, NULL);
 690
 691 DEFINE_CLK_GATE(gpio1_dbclk, "clkdiv32k_ick", &clkdiv32k_ick, 0x0,
 692                 AM33XX_CM_PER_GPIO1_CLKCTRL,
 693                 AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_SHIFT, 0x0, NULL);
 694
 695 DEFINE_CLK_GATE(gpio2_dbclk, "clkdiv32k_ick", &clkdiv32k_ick, 0x0,
 696                 AM33XX_CM_PER_GPIO2_CLKCTRL,
 697                 AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_SHIFT, 0x0, NULL);
 698
 699 DEFINE_CLK_GATE(gpio3_dbclk, "clkdiv32k_ick", &clkdiv32k_ick, 0x0,
 700                 AM33XX_CM_PER_GPIO3_CLKCTRL,
 701                 AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_SHIFT, 0x0, NULL);
 702
 703
 704 static const char *pruss_ck_parents[] = {
 705         "l3_gclk", "dpll_disp_m2_ck",
 706 };
 707
 708 static const struct clksel pruss_ocp_clk_mux_sel[] = {
 709         { .parent = &l3_gclk, .rates = div_1_0_rates },
 710         { .parent = &dpll_disp_m2_ck, .rates = div_1_1_rates },
 711         { .parent = NULL },
 712 };
 713
 714 static struct clk pruss_ocp_gclk;
 715
 716 static struct clk_hw_omap pruss_ocp_gclk_hw = {
 717         .hw     = {
 718                 .clk    = &pruss_ocp_gclk,
 719         },
 720         .clkdm_name     = "pruss_ocp_clkdm",
 721         .clksel         = pruss_ocp_clk_mux_sel,
 722         .clksel_reg     = AM33XX_CLKSEL_PRUSS_OCP_CLK,
 723         .clksel_mask    = AM33XX_CLKSEL_0_0_MASK,
 724 };
 725
 726 DEFINE_STRUCT_CLK(pruss_ocp_gclk, pruss_ck_parents, gpio_fck_ops);
 727
 728 static const char *lcd_ck_parents[] = {
 729         "dpll_disp_m2_ck", "dpll_core_m5_ck", "dpll_per_m2_ck",
 730 };
 731
 732 static const struct clksel lcd_clk_mux_sel[] = {
 733         { .parent = &dpll_disp_m2_ck, .rates = div_1_0_rates },
 734         { .parent = &dpll_core_m5_ck, .rates = div_1_1_rates },
 735         { .parent = &dpll_per_m2_ck, .rates = div_1_2_rates },
 736         { .parent = NULL },
 737 };
 738
 739 static struct clk lcd_gclk;
 740
 741 static struct clk_hw_omap lcd_gclk_hw = {
 742         .hw     = {
 743                 .clk    = &lcd_gclk,
 744         },
 745         .clkdm_name     = "lcdc_clkdm",
 746         .clksel         = lcd_clk_mux_sel,
 747         .clksel_reg     = AM33XX_CLKSEL_LCDC_PIXEL_CLK,
 748         .clksel_mask    = AM33XX_CLKSEL_0_1_MASK,
 749 };
 750
 751 DEFINE_STRUCT_CLK_FLAGS(lcd_gclk, lcd_ck_parents,
 752                         gpio_fck_ops, CLK_SET_RATE_PARENT);
 753
 754 DEFINE_CLK_FIXED_FACTOR(mmc_clk, "dpll_per_m2_ck", &dpll_per_m2_ck, 0x0, 1, 2);
 755
 756 static const char *gfx_ck_parents[] = {
 757         "dpll_core_m4_ck", "dpll_per_m2_ck",
 758 };
 759
 760 static const struct clksel gfx_clksel_sel[] = {
 761         { .parent = &dpll_core_m4_ck, .rates = div_1_0_rates },
 762         { .parent = &dpll_per_m2_ck, .rates = div_1_1_rates },
 763         { .parent = NULL },
 764 };
 765
 766 static struct clk gfx_fclk_clksel_ck;
 767
 768 static struct clk_hw_omap gfx_fclk_clksel_ck_hw = {
 769         .hw     = {
 770                 .clk    = &gfx_fclk_clksel_ck,
 771         },
 772         .clksel         = gfx_clksel_sel,
 773         .clksel_reg     = AM33XX_CLKSEL_GFX_FCLK,
 774         .clksel_mask    = AM33XX_CLKSEL_GFX_FCLK_MASK,
 775 };
 776
 777 DEFINE_STRUCT_CLK(gfx_fclk_clksel_ck, gfx_ck_parents, gpio_fck_ops);
 778
 779 static const struct clk_div_table div_1_0_2_1_rates[] = {
 780         { .div = 1, .val = 0, },
 781         { .div = 2, .val = 1, },
 782         { .div = 0 },
 783 };
 784
 785 DEFINE_CLK_DIVIDER_TABLE(gfx_fck_div_ck, "gfx_fclk_clksel_ck",
 786                          &gfx_fclk_clksel_ck, 0x0, AM33XX_CLKSEL_GFX_FCLK,
 787                          AM33XX_CLKSEL_0_0_SHIFT, AM33XX_CLKSEL_0_0_WIDTH,
 788                          0x0, div_1_0_2_1_rates, NULL);
 789
 790 static const char *sysclkout_ck_parents[] = {
 791         "clk_32768_ck", "l3_gclk", "dpll_ddr_m2_ck", "dpll_per_m2_ck",
 792         "lcd_gclk",
 793 };
 794
 795 static const struct clksel sysclkout_pre_sel[] = {
 796         { .parent = &clk_32768_ck, .rates = div_1_0_rates },
 797         { .parent = &l3_gclk, .rates = div_1_1_rates },
 798         { .parent = &dpll_ddr_m2_ck, .rates = div_1_2_rates },
 799         { .parent = &dpll_per_m2_ck, .rates = div_1_3_rates },
 800         { .parent = &lcd_gclk, .rates = div_1_4_rates },
 801         { .parent = NULL },
 802 };
 803
 804 static struct clk sysclkout_pre_ck;
 805
 806 static struct clk_hw_omap sysclkout_pre_ck_hw = {
 807         .hw     = {
 808                 .clk    = &sysclkout_pre_ck,
 809         },
 810         .clksel         = sysclkout_pre_sel,
 811         .clksel_reg     = AM33XX_CM_CLKOUT_CTRL,
 812         .clksel_mask    = AM33XX_CLKOUT2SOURCE_MASK,
 813 };
 814
 815 DEFINE_STRUCT_CLK(sysclkout_pre_ck, sysclkout_ck_parents, gpio_fck_ops);
 816
 817 /* Divide by 8 clock rates with default clock is 1/1*/
 818 static const struct clk_div_table div8_rates[] = {
 819         { .div = 1, .val = 0, },
 820         { .div = 2, .val = 1, },
 821         { .div = 3, .val = 2, },
 822         { .div = 4, .val = 3, },
 823         { .div = 5, .val = 4, },
 824         { .div = 6, .val = 5, },
 825         { .div = 7, .val = 6, },
 826         { .div = 8, .val = 7, },
 827         { .div = 0 },
 828 };
 829
 830 DEFINE_CLK_DIVIDER_TABLE(clkout2_div_ck, "sysclkout_pre_ck", &sysclkout_pre_ck,
 831                          0x0, AM33XX_CM_CLKOUT_CTRL, AM33XX_CLKOUT2DIV_SHIFT,
 832                          AM33XX_CLKOUT2DIV_WIDTH, 0x0, div8_rates, NULL);
 833
 834 DEFINE_CLK_GATE(clkout2_ck, "clkout2_div_ck", &clkout2_div_ck, 0x0,
 835                 AM33XX_CM_CLKOUT_CTRL, AM33XX_CLKOUT2EN_SHIFT, 0x0, NULL);
 836
 837 static const char *wdt_ck_parents[] = {
 838         "clk_rc32k_ck", "clkdiv32k_ick",
 839 };
 840
 841 static const struct clksel wdt_clkmux_sel[] = {
 842         { .parent = &clk_rc32k_ck, .rates = div_1_0_rates },
 843         { .parent = &clkdiv32k_ick, .rates = div_1_1_rates },
 844         { .parent = NULL },
 845 };
 846
 847 static struct clk wdt1_fck;
 848
 849 static struct clk_hw_omap wdt1_fck_hw = {
 850         .hw     = {
 851                 .clk    = &wdt1_fck,
 852         },
 853         .clkdm_name     = "l4_wkup_clkdm",
 854         .clksel         = wdt_clkmux_sel,
 855         .clksel_reg     = AM33XX_CLKSEL_WDT1_CLK,
 856         .clksel_mask    = AM33XX_CLKSEL_0_1_MASK,
 857 };
 858
 859 DEFINE_STRUCT_CLK(wdt1_fck, wdt_ck_parents, gpio_fck_ops);
 860
 861 static const char *pwmss_clk_parents[] = {
 862         "dpll_per_m2_ck",
 863 };
 864
 865 static const struct clk_ops ehrpwm_tbclk_ops = {
 866         .enable         = &omap2_dflt_clk_enable,
 867         .disable        = &omap2_dflt_clk_disable,
 868 };
 869
 870 DEFINE_CLK_OMAP_MUX_GATE(ehrpwm0_tbclk, "l4ls_clkdm",
 871                          NULL, NULL, 0,
 872                          AM33XX_CTRL_REGADDR(AM33XX_PWMSS_TBCLK_CLKCTRL),
 873                          AM33XX_PWMSS0_TBCLKEN_SHIFT,
 874                          NULL, pwmss_clk_parents, ehrpwm_tbclk_ops);
 875
 876 DEFINE_CLK_OMAP_MUX_GATE(ehrpwm1_tbclk, "l4ls_clkdm",
 877                          NULL, NULL, 0,
 878                          AM33XX_CTRL_REGADDR(AM33XX_PWMSS_TBCLK_CLKCTRL),
 879                          AM33XX_PWMSS1_TBCLKEN_SHIFT,
 880                          NULL, pwmss_clk_parents, ehrpwm_tbclk_ops);
 881
 882 DEFINE_CLK_OMAP_MUX_GATE(ehrpwm2_tbclk, "l4ls_clkdm",
 883                          NULL, NULL, 0,
 884                          AM33XX_CTRL_REGADDR(AM33XX_PWMSS_TBCLK_CLKCTRL),
 885                          AM33XX_PWMSS2_TBCLKEN_SHIFT,
 886                          NULL, pwmss_clk_parents, ehrpwm_tbclk_ops);
 887
 888 /*
 889  * debugss optional clocks
 890  */
 891 DEFINE_CLK_GATE(dbg_sysclk_ck, "sys_clkin_ck", &sys_clkin_ck,
 892                 0x0, AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
 893                 AM33XX_OPTFCLKEN_DBGSYSCLK_SHIFT, 0x0, NULL);
 894
 895 DEFINE_CLK_GATE(dbg_clka_ck, "dpll_core_m4_ck", &dpll_core_m4_ck,
 896                 0x0, AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
 897                 AM33XX_OPTCLK_DEBUG_CLKA_SHIFT, 0x0, NULL);
 898
 899 static const char *stm_pmd_clock_mux_ck_parents[] = {
 900         "dbg_sysclk_ck", "dbg_clka_ck",
 901 };
 902
 903 DEFINE_CLK_MUX(stm_pmd_clock_mux_ck, stm_pmd_clock_mux_ck_parents, NULL, 0x0,
 904                AM33XX_CM_WKUP_DEBUGSS_CLKCTRL, AM33XX_STM_PMD_CLKSEL_SHIFT,
 905                AM33XX_STM_PMD_CLKSEL_WIDTH, 0x0, NULL);
 906
 907 DEFINE_CLK_MUX(trace_pmd_clk_mux_ck, stm_pmd_clock_mux_ck_parents, NULL, 0x0,
 908                AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
 909                AM33XX_TRC_PMD_CLKSEL_SHIFT,
 910                AM33XX_TRC_PMD_CLKSEL_WIDTH, 0x0, NULL);
 911
 912 DEFINE_CLK_DIVIDER(stm_clk_div_ck, "stm_pmd_clock_mux_ck",
 913                    &stm_pmd_clock_mux_ck, 0x0, AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
 914                    AM33XX_STM_PMD_CLKDIVSEL_SHIFT,
 915                    AM33XX_STM_PMD_CLKDIVSEL_WIDTH, CLK_DIVIDER_POWER_OF_TWO,
 916                    NULL);
 917
 918 DEFINE_CLK_DIVIDER(trace_clk_div_ck, "trace_pmd_clk_mux_ck",
 919                    &trace_pmd_clk_mux_ck, 0x0, AM33XX_CM_WKUP_DEBUGSS_CLKCTRL,
 920                    AM33XX_TRC_PMD_CLKDIVSEL_SHIFT,
 921                    AM33XX_TRC_PMD_CLKDIVSEL_WIDTH, CLK_DIVIDER_POWER_OF_TWO,
 922                    NULL);
 923
 924 /*
 925  * clkdev
 926  */
 927 static struct omap_clk am33xx_clks[] = {
 928         CLK(NULL,       "clk_32768_ck",         &clk_32768_ck),
 929         CLK(NULL,       "clk_rc32k_ck",         &clk_rc32k_ck),
 930         CLK(NULL,       "virt_19200000_ck",     &virt_19200000_ck),
 931         CLK(NULL,       "virt_24000000_ck",     &virt_24000000_ck),
 932         CLK(NULL,       "virt_25000000_ck",     &virt_25000000_ck),
 933         CLK(NULL,       "virt_26000000_ck",     &virt_26000000_ck),
 934         CLK(NULL,       "sys_clkin_ck",         &sys_clkin_ck),
 935         CLK(NULL,       "tclkin_ck",            &tclkin_ck),
 936         CLK(NULL,       "dpll_core_ck",         &dpll_core_ck),
 937         CLK(NULL,       "dpll_core_x2_ck",      &dpll_core_x2_ck),
 938         CLK(NULL,       "dpll_core_m4_ck",      &dpll_core_m4_ck),
 939         CLK(NULL,       "dpll_core_m5_ck",      &dpll_core_m5_ck),
 940         CLK(NULL,       "dpll_core_m6_ck",      &dpll_core_m6_ck),
 941         CLK(NULL,       "dpll_mpu_ck",          &dpll_mpu_ck),
 942         CLK("cpu0",     NULL,                   &dpll_mpu_ck),
 943         CLK(NULL,       "dpll_mpu_m2_ck",       &dpll_mpu_m2_ck),
 944         CLK(NULL,       "dpll_ddr_ck",          &dpll_ddr_ck),
 945         CLK(NULL,       "dpll_ddr_m2_ck",       &dpll_ddr_m2_ck),
 946         CLK(NULL,       "dpll_ddr_m2_div2_ck",  &dpll_ddr_m2_div2_ck),
 947         CLK(NULL,       "dpll_disp_ck",         &dpll_disp_ck),
 948         CLK(NULL,       "dpll_disp_m2_ck",      &dpll_disp_m2_ck),
 949         CLK(NULL,       "dpll_per_ck",          &dpll_per_ck),
 950         CLK(NULL,       "dpll_per_m2_ck",       &dpll_per_m2_ck),
 951         CLK(NULL,       "dpll_per_m2_div4_wkupdm_ck",   &dpll_per_m2_div4_wkupdm_ck),
 952         CLK(NULL,       "dpll_per_m2_div4_ck",  &dpll_per_m2_div4_ck),
 953         CLK(NULL,       "adc_tsc_fck",          &adc_tsc_fck),
 954         CLK(NULL,       "cefuse_fck",           &cefuse_fck),
 955         CLK(NULL,       "clkdiv32k_ck",         &clkdiv32k_ck),
 956         CLK(NULL,       "clkdiv32k_ick",        &clkdiv32k_ick),
 957         CLK(NULL,       "dcan0_fck",            &dcan0_fck),
 958         CLK("481cc000.d_can",   NULL,           &dcan0_fck),
 959         CLK(NULL,       "dcan1_fck",            &dcan1_fck),
 960         CLK("481d0000.d_can",   NULL,           &dcan1_fck),
 961         CLK(NULL,       "pruss_ocp_gclk",       &pruss_ocp_gclk),
 962         CLK(NULL,       "mcasp0_fck",           &mcasp0_fck),
 963         CLK(NULL,       "mcasp1_fck",           &mcasp1_fck),
 964         CLK(NULL,       "mmu_fck",              &mmu_fck),
 965         CLK(NULL,       "smartreflex0_fck",     &smartreflex0_fck),
 966         CLK(NULL,       "smartreflex1_fck",     &smartreflex1_fck),
 967         CLK(NULL,       "sha0_fck",             &sha0_fck),
 968         CLK(NULL,       "aes0_fck",             &aes0_fck),
 969         CLK(NULL,       "timer1_fck",           &timer1_fck),
 970         CLK(NULL,       "timer2_fck",           &timer2_fck),
 971         CLK(NULL,       "timer3_fck",           &timer3_fck),
 972         CLK(NULL,       "timer4_fck",           &timer4_fck),
 973         CLK(NULL,       "timer5_fck",           &timer5_fck),
 974         CLK(NULL,       "timer6_fck",           &timer6_fck),
 975         CLK(NULL,       "timer7_fck",           &timer7_fck),
 976         CLK(NULL,       "usbotg_fck",           &usbotg_fck),
 977         CLK(NULL,       "ieee5000_fck",         &ieee5000_fck),
 978         CLK(NULL,       "wdt1_fck",             &wdt1_fck),
 979         CLK(NULL,       "l4_rtc_gclk",          &l4_rtc_gclk),
 980         CLK(NULL,       "l3_gclk",              &l3_gclk),
 981         CLK(NULL,       "dpll_core_m4_div2_ck", &dpll_core_m4_div2_ck),
 982         CLK(NULL,       "l4hs_gclk",            &l4hs_gclk),
 983         CLK(NULL,       "l3s_gclk",             &l3s_gclk),
 984         CLK(NULL,       "l4fw_gclk",            &l4fw_gclk),
 985         CLK(NULL,       "l4ls_gclk",            &l4ls_gclk),
 986         CLK(NULL,       "clk_24mhz",            &clk_24mhz),
 987         CLK(NULL,       "sysclk_div_ck",        &sysclk_div_ck),
 988         CLK(NULL,       "cpsw_125mhz_gclk",     &cpsw_125mhz_gclk),
 989         CLK(NULL,       "cpsw_cpts_rft_clk",    &cpsw_cpts_rft_clk),
 990         CLK(NULL,       "gpio0_dbclk_mux_ck",   &gpio0_dbclk_mux_ck),
 991         CLK(NULL,       "gpio0_dbclk",          &gpio0_dbclk),
 992         CLK(NULL,       "gpio1_dbclk",          &gpio1_dbclk),
 993         CLK(NULL,       "gpio2_dbclk",          &gpio2_dbclk),
 994         CLK(NULL,       "gpio3_dbclk",          &gpio3_dbclk),
 995         CLK(NULL,       "lcd_gclk",             &lcd_gclk),
 996         CLK(NULL,       "mmc_clk",              &mmc_clk),
 997         CLK(NULL,       "gfx_fclk_clksel_ck",   &gfx_fclk_clksel_ck),
 998         CLK(NULL,       "gfx_fck_div_ck",       &gfx_fck_div_ck),
 999         CLK(NULL,       "sysclkout_pre_ck",     &sysclkout_pre_ck),
1000         CLK(NULL,       "clkout2_div_ck",       &clkout2_div_ck),
1001         CLK(NULL,       "timer_32k_ck",         &clkdiv32k_ick),
1002         CLK(NULL,       "timer_sys_ck",         &sys_clkin_ck),
1003         CLK(NULL,       "dbg_sysclk_ck",        &dbg_sysclk_ck),
1004         CLK(NULL,       "dbg_clka_ck",          &dbg_clka_ck),
1005         CLK(NULL,       "stm_pmd_clock_mux_ck", &stm_pmd_clock_mux_ck),
1006         CLK(NULL,       "trace_pmd_clk_mux_ck", &trace_pmd_clk_mux_ck),
1007         CLK(NULL,       "stm_clk_div_ck",       &stm_clk_div_ck),
1008         CLK(NULL,       "trace_clk_div_ck",     &trace_clk_div_ck),
1009         CLK(NULL,       "clkout2_ck",           &clkout2_ck),
1010         CLK("48300200.ehrpwm",  "tbclk",        &ehrpwm0_tbclk),
1011         CLK("48302200.ehrpwm",  "tbclk",        &ehrpwm1_tbclk),
1012         CLK("48304200.ehrpwm",  "tbclk",        &ehrpwm2_tbclk),
1013 };
1014
1015
1016 static const char *enable_init_clks[] = {
1017         "dpll_ddr_m2_ck",
1018         "dpll_mpu_m2_ck",
1019         "l3_gclk",
1020         "l4hs_gclk",
1021         "l4fw_gclk",
1022         "l4ls_gclk",
1023         "clkout2_ck",   /* Required for external peripherals like, Audio codecs */
1024 };
1025
1026 int __init am33xx_clk_init(void)
1027 {
1028         if (soc_is_am33xx())
1029                 cpu_mask = RATE_IN_AM33XX;
1030
1031         omap_clocks_register(am33xx_clks, ARRAY_SIZE(am33xx_clks));
1032
1033         omap2_clk_disable_autoidle_all();
1034
1035         omap2_clk_enable_init_clocks(enable_init_clks,
1036                                      ARRAY_SIZE(enable_init_clks));
1037
1038         /* TRM ERRATA: Timer 3 & 6 default parent (TCLKIN) may not be always
1039          *    physically present, in such a case HWMOD enabling of
1040          *    clock would be failure with default parent. And timer
1041          *    probe thinks clock is already enabled, this leads to
1042          *    crash upon accessing timer 3 & 6 registers in probe.
1043          *    Fix by setting parent of both these timers to master
1044          *    oscillator clock.
1045          */
1046
1047         clk_set_parent(&timer3_fck, &sys_clkin_ck);
1048         clk_set_parent(&timer6_fck, &sys_clkin_ck);
1049         /*
1050          * The On-Chip 32K RC Osc clock is not an accurate clock-source as per
1051          * the design/spec, so as a result, for example, timer which supposed
1052          * to get expired @60Sec, but will expire somewhere ~@40Sec, which is
1053          * not expected by any use-case, so change WDT1 clock source to PRCM
1054          * 32KHz clock.
1055          */
1056         clk_set_parent(&wdt1_fck, &clkdiv32k_ick);
1057
1058         return 0;
1059 }