2 * clkt_clksel.c - OMAP2/3/4 clksel clock functions
4 * Copyright (C) 2005-2008 Texas Instruments, Inc.
5 * Copyright (C) 2004-2010 Nokia Corporation
8 * Richard Woodruff <r-woodruff2@ti.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
15 * XXX At some point these clksel clocks should be split into
16 * "divider" clocks and "mux" clocks to better match the hardware.
18 * XXX Currently these clocks are only used in the OMAP2/3/4 code, but
19 * many of the OMAP1 clocks should be convertible to use this
24 #include <linux/kernel.h>
25 #include <linux/errno.h>
26 #include <linux/clk.h>
29 #include <plat/clock.h>
33 #include "cm-regbits-24xx.h"
34 #include "cm-regbits-34xx.h"
36 /* Private functions */
39 * _omap2_get_clksel_by_parent - return clksel struct for a given clk & parent
40 * @clk: OMAP struct clk ptr to inspect
41 * @src_clk: OMAP struct clk ptr of the parent clk to search for
43 * Scan the struct clksel array associated with the clock to find
44 * the element associated with the supplied parent clock address.
45 * Returns a pointer to the struct clksel on success or NULL on error.
47 static const struct clksel *_omap2_get_clksel_by_parent(struct clk *clk,
50 const struct clksel *clks;
55 for (clks = clk->clksel; clks->parent; clks++) {
56 if (clks->parent == src_clk)
57 break; /* Found the requested parent */
61 printk(KERN_ERR "clock: Could not find parent clock %s in "
62 "clksel array of clock %s\n", src_clk->name,
71 * Converts encoded control register address into a full address
72 * On error, the return value (parent_div) will be 0.
74 static u32 _omap2_clksel_get_src_field(struct clk *src_clk, struct clk *clk,
77 const struct clksel *clks;
78 const struct clksel_rate *clkr;
80 clks = _omap2_get_clksel_by_parent(clk, src_clk);
84 for (clkr = clks->rates; clkr->div; clkr++) {
85 if (clkr->flags & cpu_mask && clkr->flags & DEFAULT_RATE)
86 break; /* Found the default rate for this platform */
90 printk(KERN_ERR "clock: Could not find default rate for "
91 "clock %s parent %s\n", clk->name,
92 src_clk->parent->name);
96 /* Should never happen. Add a clksel mask to the struct clk. */
97 WARN_ON(clk->clksel_mask == 0);
99 *field_val = clkr->val;
105 /* Public functions */
108 * omap2_init_clksel_parent - set a clksel clk's parent field from the hardware
109 * @clk: OMAP clock struct ptr to use
111 * Given a pointer to a source-selectable struct clk, read the hardware
112 * register and determine what its parent is currently set to. Update the
113 * clk->parent field with the appropriate clk ptr.
115 void omap2_init_clksel_parent(struct clk *clk)
117 const struct clksel *clks;
118 const struct clksel_rate *clkr;
124 r = __raw_readl(clk->clksel_reg) & clk->clksel_mask;
125 r >>= __ffs(clk->clksel_mask);
127 for (clks = clk->clksel; clks->parent && !found; clks++) {
128 for (clkr = clks->rates; clkr->div && !found; clkr++) {
129 if ((clkr->flags & cpu_mask) && (clkr->val == r)) {
130 if (clk->parent != clks->parent) {
131 pr_debug("clock: inited %s parent "
133 clk->name, clks->parent->name,
135 clk->parent->name : "NULL"));
136 clk_reparent(clk, clks->parent);
144 printk(KERN_ERR "clock: init parent: could not find "
145 "regval %0x for clock %s\n", r, clk->name);
151 * Used for clocks that are part of CLKSEL_xyz governed clocks.
152 * REVISIT: Maybe change to use clk->enable() functions like on omap1?
154 unsigned long omap2_clksel_recalc(struct clk *clk)
159 pr_debug("clock: recalc'ing clksel clk %s\n", clk->name);
161 div = omap2_clksel_get_divisor(clk);
165 rate = clk->parent->rate / div;
167 pr_debug("clock: new clock rate is %ld (div %d)\n", rate, div);
173 * omap2_clksel_round_rate_div - find divisor for the given clock and rate
174 * @clk: OMAP struct clk to use
175 * @target_rate: desired clock rate
176 * @new_div: ptr to where we should store the divisor
178 * Finds 'best' divider value in an array based on the source and target
179 * rates. The divider array must be sorted with smallest divider first.
180 * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT,
181 * they are only settable as part of virtual_prcm set.
183 * Returns the rounded clock rate or returns 0xffffffff on error.
185 u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
188 unsigned long test_rate;
189 const struct clksel *clks;
190 const struct clksel_rate *clkr;
193 pr_debug("clock: clksel_round_rate_div: %s target_rate %ld\n",
194 clk->name, target_rate);
198 clks = _omap2_get_clksel_by_parent(clk, clk->parent);
202 for (clkr = clks->rates; clkr->div; clkr++) {
203 if (!(clkr->flags & cpu_mask))
207 if (clkr->div <= last_div)
208 pr_err("clock: clksel_rate table not sorted "
209 "for clock %s", clk->name);
211 last_div = clkr->div;
213 test_rate = clk->parent->rate / clkr->div;
215 if (test_rate <= target_rate)
216 break; /* found it */
220 pr_err("clock: Could not find divisor for target "
221 "rate %ld for clock %s parent %s\n", target_rate,
222 clk->name, clk->parent->name);
226 *new_div = clkr->div;
228 pr_debug("clock: new_div = %d, new_rate = %ld\n", *new_div,
229 (clk->parent->rate / clkr->div));
231 return clk->parent->rate / clkr->div;
235 * omap2_clksel_round_rate - find rounded rate for the given clock and rate
236 * @clk: OMAP struct clk to use
237 * @target_rate: desired clock rate
239 * Compatibility wrapper for OMAP clock framework
240 * Finds best target rate based on the source clock and possible dividers.
241 * rates. The divider array must be sorted with smallest divider first.
242 * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT,
243 * they are only settable as part of virtual_prcm set.
245 * Returns the rounded clock rate or returns 0xffffffff on error.
247 long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate)
251 return omap2_clksel_round_rate_div(clk, target_rate, &new_div);
255 /* Given a clock and a rate apply a clock specific rounding function */
256 long omap2_clk_round_rate(struct clk *clk, unsigned long rate)
259 return clk->round_rate(clk, rate);
261 if (clk->flags & RATE_FIXED)
262 printk(KERN_ERR "clock: generic omap2_clk_round_rate called "
263 "on fixed-rate clock %s\n", clk->name);
269 * omap2_clksel_to_divisor() - turn clksel field value into integer divider
270 * @clk: OMAP struct clk to use
271 * @field_val: register field value to find
273 * Given a struct clk of a rate-selectable clksel clock, and a register field
274 * value to search for, find the corresponding clock divisor. The register
275 * field value should be pre-masked and shifted down so the LSB is at bit 0
276 * before calling. Returns 0 on error
278 u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val)
280 const struct clksel *clks;
281 const struct clksel_rate *clkr;
283 clks = _omap2_get_clksel_by_parent(clk, clk->parent);
287 for (clkr = clks->rates; clkr->div; clkr++) {
288 if ((clkr->flags & cpu_mask) && (clkr->val == field_val))
293 printk(KERN_ERR "clock: Could not find fieldval %d for "
294 "clock %s parent %s\n", field_val, clk->name,
303 * omap2_divisor_to_clksel() - turn clksel integer divisor into a field value
304 * @clk: OMAP struct clk to use
305 * @div: integer divisor to search for
307 * Given a struct clk of a rate-selectable clksel clock, and a clock divisor,
308 * find the corresponding register field value. The return register value is
309 * the value before left-shifting. Returns ~0 on error
311 u32 omap2_divisor_to_clksel(struct clk *clk, u32 div)
313 const struct clksel *clks;
314 const struct clksel_rate *clkr;
316 /* should never happen */
319 clks = _omap2_get_clksel_by_parent(clk, clk->parent);
323 for (clkr = clks->rates; clkr->div; clkr++) {
324 if ((clkr->flags & cpu_mask) && (clkr->div == div))
329 printk(KERN_ERR "clock: Could not find divisor %d for "
330 "clock %s parent %s\n", div, clk->name,
339 * omap2_clksel_get_divisor - get current divider applied to parent clock.
340 * @clk: OMAP struct clk to use.
342 * Returns the integer divisor upon success or 0 on error.
344 u32 omap2_clksel_get_divisor(struct clk *clk)
348 if (!clk->clksel_mask)
351 v = __raw_readl(clk->clksel_reg) & clk->clksel_mask;
352 v >>= __ffs(clk->clksel_mask);
354 return omap2_clksel_to_divisor(clk, v);
357 int omap2_clksel_set_rate(struct clk *clk, unsigned long rate)
359 u32 v, field_val, validrate, new_div = 0;
361 if (!clk->clksel_mask)
364 validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
365 if (validrate != rate)
368 field_val = omap2_divisor_to_clksel(clk, new_div);
372 v = __raw_readl(clk->clksel_reg);
373 v &= ~clk->clksel_mask;
374 v |= field_val << __ffs(clk->clksel_mask);
375 __raw_writel(v, clk->clksel_reg);
376 v = __raw_readl(clk->clksel_reg); /* OCP barrier */
378 clk->rate = clk->parent->rate / new_div;
380 omap2xxx_clk_commit(clk);
385 int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent)
387 u32 field_val, v, parent_div;
392 parent_div = _omap2_clksel_get_src_field(new_parent, clk, &field_val);
396 /* Set new source value (previous dividers if any in effect) */
397 v = __raw_readl(clk->clksel_reg);
398 v &= ~clk->clksel_mask;
399 v |= field_val << __ffs(clk->clksel_mask);
400 __raw_writel(v, clk->clksel_reg);
401 v = __raw_readl(clk->clksel_reg); /* OCP barrier */
403 omap2xxx_clk_commit(clk);
405 clk_reparent(clk, new_parent);
407 /* CLKSEL clocks follow their parents' rates, divided by a divisor */
408 clk->rate = new_parent->rate;
411 clk->rate /= parent_div;
413 pr_debug("clock: set parent of %s to %s (new rate %ld)\n",
414 clk->name, clk->parent->name, clk->rate);