2 * linux/arch/arm/mach-omap2/clock.c
4 * Copyright (C) 2005-2008 Texas Instruments, Inc.
5 * Copyright (C) 2004-2008 Nokia Corporation
8 * Richard Woodruff <r-woodruff2@ti.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
17 #include <linux/module.h>
18 #include <linux/kernel.h>
19 #include <linux/device.h>
20 #include <linux/list.h>
21 #include <linux/errno.h>
22 #include <linux/delay.h>
23 #include <linux/clk.h>
24 #include <asm/bitops.h>
28 #include <mach/clock.h>
29 #include <mach/clockdomain.h>
30 #include <mach/sram.h>
32 #include <asm/div64.h>
38 #include "prm-regbits-24xx.h"
40 #include "cm-regbits-24xx.h"
41 #include "cm-regbits-34xx.h"
43 #define MAX_CLOCK_ENABLE_WAIT 100000
45 /* DPLL rate rounding: minimum DPLL multiplier, divider values */
46 #define DPLL_MIN_MULTIPLIER 1
47 #define DPLL_MIN_DIVIDER 1
49 /* Possible error results from _dpll_test_mult */
50 #define DPLL_MULT_UNDERFLOW (1 << 0)
53 * Scale factor to mitigate roundoff errors in DPLL rate rounding.
54 * The higher the scale factor, the greater the risk of arithmetic overflow,
55 * but the closer the rounded rate to the target rate. DPLL_SCALE_FACTOR
56 * must be a power of DPLL_SCALE_BASE.
58 #define DPLL_SCALE_FACTOR 64
59 #define DPLL_SCALE_BASE 2
60 #define DPLL_ROUNDING_VAL ((DPLL_SCALE_BASE / 2) * \
61 (DPLL_SCALE_FACTOR / DPLL_SCALE_BASE))
65 /*-------------------------------------------------------------------------
66 * OMAP2/3 specific clock functions
67 *-------------------------------------------------------------------------*/
70 * omap2_init_clk_clkdm - look up a clockdomain name, store pointer in clk
71 * @clk: OMAP clock struct ptr to use
73 * Convert a clockdomain name stored in a struct clk 'clk' into a
74 * clockdomain pointer, and save it into the struct clk. Intended to be
75 * called during clk_register(). No return value.
77 void omap2_init_clk_clkdm(struct clk *clk)
79 struct clockdomain *clkdm;
84 clkdm = clkdm_lookup(clk->clkdm_name);
86 pr_debug("clock: associated clk %s to clkdm %s\n",
87 clk->name, clk->clkdm_name);
90 pr_debug("clock: could not associate clk %s to "
91 "clkdm %s\n", clk->name, clk->clkdm_name);
96 * omap2_init_clksel_parent - set a clksel clk's parent field from the hardware
97 * @clk: OMAP clock struct ptr to use
99 * Given a pointer to a source-selectable struct clk, read the hardware
100 * register and determine what its parent is currently set to. Update the
101 * clk->parent field with the appropriate clk ptr.
103 void omap2_init_clksel_parent(struct clk *clk)
105 const struct clksel *clks;
106 const struct clksel_rate *clkr;
112 r = __raw_readl(clk->clksel_reg) & clk->clksel_mask;
113 r >>= __ffs(clk->clksel_mask);
115 for (clks = clk->clksel; clks->parent && !found; clks++) {
116 for (clkr = clks->rates; clkr->div && !found; clkr++) {
117 if ((clkr->flags & cpu_mask) && (clkr->val == r)) {
118 if (clk->parent != clks->parent) {
119 pr_debug("clock: inited %s parent "
121 clk->name, clks->parent->name,
123 clk->parent->name : "NULL"));
124 clk->parent = clks->parent;
132 printk(KERN_ERR "clock: init parent: could not find "
133 "regval %0x for clock %s\n", r, clk->name);
138 /* Returns the DPLL rate */
139 u32 omap2_get_dpll_rate(struct clk *clk)
142 u32 dpll_mult, dpll_div, dpll;
143 struct dpll_data *dd;
146 /* REVISIT: What do we return on error? */
150 dpll = __raw_readl(dd->mult_div1_reg);
151 dpll_mult = dpll & dd->mult_mask;
152 dpll_mult >>= __ffs(dd->mult_mask);
153 dpll_div = dpll & dd->div1_mask;
154 dpll_div >>= __ffs(dd->div1_mask);
156 dpll_clk = (long long)clk->parent->rate * dpll_mult;
157 do_div(dpll_clk, dpll_div + 1);
163 * Used for clocks that have the same value as the parent clock,
164 * divided by some factor
166 void omap2_fixed_divisor_recalc(struct clk *clk)
168 WARN_ON(!clk->fixed_div);
170 clk->rate = clk->parent->rate / clk->fixed_div;
172 if (clk->flags & RATE_PROPAGATES)
177 * omap2_wait_clock_ready - wait for clock to enable
178 * @reg: physical address of clock IDLEST register
179 * @mask: value to mask against to determine if the clock is active
180 * @name: name of the clock (for printk)
182 * Returns 1 if the clock enabled in time, or 0 if it failed to enable
183 * in roughly MAX_CLOCK_ENABLE_WAIT microseconds.
185 int omap2_wait_clock_ready(void __iomem *reg, u32 mask, const char *name)
191 * 24xx uses 0 to indicate not ready, and 1 to indicate ready.
192 * 34xx reverses this, just to keep us on our toes
194 if (cpu_mask & (RATE_IN_242X | RATE_IN_243X)) {
196 } else if (cpu_mask & RATE_IN_343X) {
201 while (((__raw_readl(reg) & mask) != ena) &&
202 (i++ < MAX_CLOCK_ENABLE_WAIT)) {
206 if (i < MAX_CLOCK_ENABLE_WAIT)
207 pr_debug("Clock %s stable after %d loops\n", name, i);
209 printk(KERN_ERR "Clock %s didn't enable in %d tries\n",
210 name, MAX_CLOCK_ENABLE_WAIT);
213 return (i < MAX_CLOCK_ENABLE_WAIT) ? 1 : 0;
218 * Note: We don't need special code here for INVERT_ENABLE
219 * for the time being since INVERT_ENABLE only applies to clocks enabled by
222 static void omap2_clk_wait_ready(struct clk *clk)
224 void __iomem *reg, *other_reg, *st_reg;
228 * REVISIT: This code is pretty ugly. It would be nice to generalize
229 * it and pull it into struct clk itself somehow.
231 reg = clk->enable_reg;
232 if ((((u32)reg & 0xff) >= CM_FCLKEN1) &&
233 (((u32)reg & 0xff) <= OMAP24XX_CM_FCLKEN2))
234 other_reg = (void __iomem *)(((u32)reg & ~0xf0) | 0x10); /* CM_ICLKEN* */
235 else if ((((u32)reg & 0xff) >= CM_ICLKEN1) &&
236 (((u32)reg & 0xff) <= OMAP24XX_CM_ICLKEN4))
237 other_reg = (void __iomem *)(((u32)reg & ~0xf0) | 0x00); /* CM_FCLKEN* */
241 /* REVISIT: What are the appropriate exclusions for 34XX? */
242 /* No check for DSS or cam clocks */
243 if (cpu_is_omap24xx() && ((u32)reg & 0x0f) == 0) { /* CM_{F,I}CLKEN1 */
244 if (clk->enable_bit == OMAP24XX_EN_DSS2_SHIFT ||
245 clk->enable_bit == OMAP24XX_EN_DSS1_SHIFT ||
246 clk->enable_bit == OMAP24XX_EN_CAM_SHIFT)
250 /* REVISIT: What are the appropriate exclusions for 34XX? */
251 /* OMAP3: ignore DSS-mod clocks */
252 if (cpu_is_omap34xx() &&
253 (((u32)reg & ~0xff) == (u32)OMAP_CM_REGADDR(OMAP3430_DSS_MOD, 0) ||
254 ((((u32)reg & ~0xff) == (u32)OMAP_CM_REGADDR(CORE_MOD, 0)) &&
255 clk->enable_bit == OMAP3430_EN_SSI_SHIFT)))
258 /* Check if both functional and interface clocks
260 bit = 1 << clk->enable_bit;
261 if (!(__raw_readl(other_reg) & bit))
263 st_reg = (void __iomem *)(((u32)other_reg & ~0xf0) | 0x20); /* CM_IDLEST* */
265 omap2_wait_clock_ready(st_reg, bit, clk->name);
268 /* Enables clock without considering parent dependencies or use count
269 * REVISIT: Maybe change this to use clk->enable like on omap1?
271 int _omap2_clk_enable(struct clk *clk)
275 if (clk->flags & (ALWAYS_ENABLED | PARENT_CONTROLS_CLOCK))
279 return clk->enable(clk);
281 if (unlikely(clk->enable_reg == NULL)) {
282 printk(KERN_ERR "clock.c: Enable for %s without enable code\n",
284 return 0; /* REVISIT: -EINVAL */
287 regval32 = __raw_readl(clk->enable_reg);
288 if (clk->flags & INVERT_ENABLE)
289 regval32 &= ~(1 << clk->enable_bit);
291 regval32 |= (1 << clk->enable_bit);
292 __raw_writel(regval32, clk->enable_reg);
295 omap2_clk_wait_ready(clk);
300 /* Disables clock without considering parent dependencies or use count */
301 void _omap2_clk_disable(struct clk *clk)
305 if (clk->flags & (ALWAYS_ENABLED | PARENT_CONTROLS_CLOCK))
313 if (clk->enable_reg == NULL) {
315 * 'Independent' here refers to a clock which is not
316 * controlled by its parent.
318 printk(KERN_ERR "clock: clk_disable called on independent "
319 "clock %s which has no enable_reg\n", clk->name);
323 regval32 = __raw_readl(clk->enable_reg);
324 if (clk->flags & INVERT_ENABLE)
325 regval32 |= (1 << clk->enable_bit);
327 regval32 &= ~(1 << clk->enable_bit);
328 __raw_writel(regval32, clk->enable_reg);
332 void omap2_clk_disable(struct clk *clk)
334 if (clk->usecount > 0 && !(--clk->usecount)) {
335 _omap2_clk_disable(clk);
336 if (likely((u32)clk->parent))
337 omap2_clk_disable(clk->parent);
339 omap2_clkdm_clk_disable(clk->clkdm, clk);
344 int omap2_clk_enable(struct clk *clk)
348 if (clk->usecount++ == 0) {
349 if (likely((u32)clk->parent))
350 ret = omap2_clk_enable(clk->parent);
352 if (unlikely(ret != 0)) {
358 omap2_clkdm_clk_enable(clk->clkdm, clk);
360 ret = _omap2_clk_enable(clk);
362 if (unlikely(ret != 0)) {
364 omap2_clkdm_clk_disable(clk->clkdm, clk);
367 omap2_clk_disable(clk->parent);
377 * Used for clocks that are part of CLKSEL_xyz governed clocks.
378 * REVISIT: Maybe change to use clk->enable() functions like on omap1?
380 void omap2_clksel_recalc(struct clk *clk)
384 pr_debug("clock: recalc'ing clksel clk %s\n", clk->name);
386 div = omap2_clksel_get_divisor(clk);
390 if (unlikely(clk->rate == clk->parent->rate / div))
392 clk->rate = clk->parent->rate / div;
394 pr_debug("clock: new clock rate is %ld (div %d)\n", clk->rate, div);
396 if (unlikely(clk->flags & RATE_PROPAGATES))
401 * omap2_get_clksel_by_parent - return clksel struct for a given clk & parent
402 * @clk: OMAP struct clk ptr to inspect
403 * @src_clk: OMAP struct clk ptr of the parent clk to search for
405 * Scan the struct clksel array associated with the clock to find
406 * the element associated with the supplied parent clock address.
407 * Returns a pointer to the struct clksel on success or NULL on error.
409 const struct clksel *omap2_get_clksel_by_parent(struct clk *clk,
412 const struct clksel *clks;
417 for (clks = clk->clksel; clks->parent; clks++) {
418 if (clks->parent == src_clk)
419 break; /* Found the requested parent */
423 printk(KERN_ERR "clock: Could not find parent clock %s in "
424 "clksel array of clock %s\n", src_clk->name,
433 * omap2_clksel_round_rate_div - find divisor for the given clock and rate
434 * @clk: OMAP struct clk to use
435 * @target_rate: desired clock rate
436 * @new_div: ptr to where we should store the divisor
438 * Finds 'best' divider value in an array based on the source and target
439 * rates. The divider array must be sorted with smallest divider first.
440 * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT,
441 * they are only settable as part of virtual_prcm set.
443 * Returns the rounded clock rate or returns 0xffffffff on error.
445 u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
448 unsigned long test_rate;
449 const struct clksel *clks;
450 const struct clksel_rate *clkr;
453 printk(KERN_INFO "clock: clksel_round_rate_div: %s target_rate %ld\n",
454 clk->name, target_rate);
458 clks = omap2_get_clksel_by_parent(clk, clk->parent);
462 for (clkr = clks->rates; clkr->div; clkr++) {
463 if (!(clkr->flags & cpu_mask))
467 if (clkr->div <= last_div)
468 printk(KERN_ERR "clock: clksel_rate table not sorted "
469 "for clock %s", clk->name);
471 last_div = clkr->div;
473 test_rate = clk->parent->rate / clkr->div;
475 if (test_rate <= target_rate)
476 break; /* found it */
480 printk(KERN_ERR "clock: Could not find divisor for target "
481 "rate %ld for clock %s parent %s\n", target_rate,
482 clk->name, clk->parent->name);
486 *new_div = clkr->div;
488 printk(KERN_INFO "clock: new_div = %d, new_rate = %ld\n", *new_div,
489 (clk->parent->rate / clkr->div));
491 return (clk->parent->rate / clkr->div);
495 * omap2_clksel_round_rate - find rounded rate for the given clock and rate
496 * @clk: OMAP struct clk to use
497 * @target_rate: desired clock rate
499 * Compatibility wrapper for OMAP clock framework
500 * Finds best target rate based on the source clock and possible dividers.
501 * rates. The divider array must be sorted with smallest divider first.
502 * Note that this will not work for clocks which are part of CONFIG_PARTICIPANT,
503 * they are only settable as part of virtual_prcm set.
505 * Returns the rounded clock rate or returns 0xffffffff on error.
507 long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate)
511 return omap2_clksel_round_rate_div(clk, target_rate, &new_div);
515 /* Given a clock and a rate apply a clock specific rounding function */
516 long omap2_clk_round_rate(struct clk *clk, unsigned long rate)
518 if (clk->round_rate != NULL)
519 return clk->round_rate(clk, rate);
521 if (clk->flags & RATE_FIXED)
522 printk(KERN_ERR "clock: generic omap2_clk_round_rate called "
523 "on fixed-rate clock %s\n", clk->name);
529 * omap2_clksel_to_divisor() - turn clksel field value into integer divider
530 * @clk: OMAP struct clk to use
531 * @field_val: register field value to find
533 * Given a struct clk of a rate-selectable clksel clock, and a register field
534 * value to search for, find the corresponding clock divisor. The register
535 * field value should be pre-masked and shifted down so the LSB is at bit 0
536 * before calling. Returns 0 on error
538 u32 omap2_clksel_to_divisor(struct clk *clk, u32 field_val)
540 const struct clksel *clks;
541 const struct clksel_rate *clkr;
543 clks = omap2_get_clksel_by_parent(clk, clk->parent);
547 for (clkr = clks->rates; clkr->div; clkr++) {
548 if ((clkr->flags & cpu_mask) && (clkr->val == field_val))
553 printk(KERN_ERR "clock: Could not find fieldval %d for "
554 "clock %s parent %s\n", field_val, clk->name,
563 * omap2_divisor_to_clksel() - turn clksel integer divisor into a field value
564 * @clk: OMAP struct clk to use
565 * @div: integer divisor to search for
567 * Given a struct clk of a rate-selectable clksel clock, and a clock divisor,
568 * find the corresponding register field value. The return register value is
569 * the value before left-shifting. Returns 0xffffffff on error
571 u32 omap2_divisor_to_clksel(struct clk *clk, u32 div)
573 const struct clksel *clks;
574 const struct clksel_rate *clkr;
576 /* should never happen */
579 clks = omap2_get_clksel_by_parent(clk, clk->parent);
583 for (clkr = clks->rates; clkr->div; clkr++) {
584 if ((clkr->flags & cpu_mask) && (clkr->div == div))
589 printk(KERN_ERR "clock: Could not find divisor %d for "
590 "clock %s parent %s\n", div, clk->name,
599 * omap2_get_clksel - find clksel register addr & field mask for a clk
600 * @clk: struct clk to use
601 * @field_mask: ptr to u32 to store the register field mask
603 * Returns the address of the clksel register upon success or NULL on error.
605 void __iomem *omap2_get_clksel(struct clk *clk, u32 *field_mask)
607 if (unlikely((clk->clksel_reg == NULL) || (clk->clksel_mask == NULL)))
610 *field_mask = clk->clksel_mask;
612 return clk->clksel_reg;
616 * omap2_clksel_get_divisor - get current divider applied to parent clock.
617 * @clk: OMAP struct clk to use.
619 * Returns the integer divisor upon success or 0 on error.
621 u32 omap2_clksel_get_divisor(struct clk *clk)
623 u32 field_mask, field_val;
624 void __iomem *div_addr;
626 div_addr = omap2_get_clksel(clk, &field_mask);
627 if (div_addr == NULL)
630 field_val = __raw_readl(div_addr) & field_mask;
631 field_val >>= __ffs(field_mask);
633 return omap2_clksel_to_divisor(clk, field_val);
636 int omap2_clksel_set_rate(struct clk *clk, unsigned long rate)
638 u32 field_mask, field_val, reg_val, validrate, new_div = 0;
639 void __iomem *div_addr;
641 validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
642 if (validrate != rate)
645 div_addr = omap2_get_clksel(clk, &field_mask);
646 if (div_addr == NULL)
649 field_val = omap2_divisor_to_clksel(clk, new_div);
653 reg_val = __raw_readl(div_addr);
654 reg_val &= ~field_mask;
655 reg_val |= (field_val << __ffs(field_mask));
656 __raw_writel(reg_val, div_addr);
659 clk->rate = clk->parent->rate / new_div;
661 if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) {
662 prm_write_mod_reg(OMAP24XX_VALID_CONFIG,
663 OMAP24XX_GR_MOD, OMAP24XX_PRCM_CLKCFG_CTRL_OFFSET);
671 /* Set the clock rate for a clock source */
672 int omap2_clk_set_rate(struct clk *clk, unsigned long rate)
676 pr_debug("clock: set_rate for clock %s to rate %ld\n", clk->name, rate);
678 /* CONFIG_PARTICIPANT clocks are changed only in sets via the
679 rate table mechanism, driven by mpu_speed */
680 if (clk->flags & CONFIG_PARTICIPANT)
683 /* dpll_ck, core_ck, virt_prcm_set; plus all clksel clocks */
684 if (clk->set_rate != NULL)
685 ret = clk->set_rate(clk, rate);
687 if (unlikely(ret == 0 && (clk->flags & RATE_PROPAGATES)))
694 * Converts encoded control register address into a full address
695 * On error, *src_addr will be returned as 0.
697 static u32 omap2_clksel_get_src_field(void __iomem **src_addr,
698 struct clk *src_clk, u32 *field_mask,
699 struct clk *clk, u32 *parent_div)
701 const struct clksel *clks;
702 const struct clksel_rate *clkr;
707 clks = omap2_get_clksel_by_parent(clk, src_clk);
711 for (clkr = clks->rates; clkr->div; clkr++) {
712 if (clkr->flags & (cpu_mask | DEFAULT_RATE))
713 break; /* Found the default rate for this platform */
717 printk(KERN_ERR "clock: Could not find default rate for "
718 "clock %s parent %s\n", clk->name,
719 src_clk->parent->name);
723 /* Should never happen. Add a clksel mask to the struct clk. */
724 WARN_ON(clk->clksel_mask == 0);
726 *field_mask = clk->clksel_mask;
727 *src_addr = clk->clksel_reg;
728 *parent_div = clkr->div;
733 int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent)
735 void __iomem *src_addr;
736 u32 field_val, field_mask, reg_val, parent_div;
738 if (unlikely(clk->flags & CONFIG_PARTICIPANT))
744 field_val = omap2_clksel_get_src_field(&src_addr, new_parent,
745 &field_mask, clk, &parent_div);
746 if (src_addr == NULL)
749 if (clk->usecount > 0)
750 _omap2_clk_disable(clk);
752 /* Set new source value (previous dividers if any in effect) */
753 reg_val = __raw_readl(src_addr) & ~field_mask;
754 reg_val |= (field_val << __ffs(field_mask));
755 __raw_writel(reg_val, src_addr);
758 if (clk->flags & DELAYED_APP && cpu_is_omap24xx()) {
759 __raw_writel(OMAP24XX_VALID_CONFIG, OMAP24XX_PRCM_CLKCFG_CTRL);
763 if (clk->usecount > 0)
764 _omap2_clk_enable(clk);
766 clk->parent = new_parent;
768 /* CLKSEL clocks follow their parents' rates, divided by a divisor */
769 clk->rate = new_parent->rate;
772 clk->rate /= parent_div;
774 pr_debug("clock: set parent of %s to %s (new rate %ld)\n",
775 clk->name, clk->parent->name, clk->rate);
777 if (unlikely(clk->flags & RATE_PROPAGATES))
783 /* DPLL rate rounding code */
786 * omap2_dpll_set_rate_tolerance: set the error tolerance during rate rounding
787 * @clk: struct clk * of the DPLL
788 * @tolerance: maximum rate error tolerance
790 * Set the maximum DPLL rate error tolerance for the rate rounding
791 * algorithm. The rate tolerance is an attempt to balance DPLL power
792 * saving (the least divider value "n") vs. rate fidelity (the least
793 * difference between the desired DPLL target rate and the rounded
794 * rate out of the algorithm). So, increasing the tolerance is likely
795 * to decrease DPLL power consumption and increase DPLL rate error.
796 * Returns -EINVAL if provided a null clock ptr or a clk that is not a
797 * DPLL; or 0 upon success.
799 int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance)
801 if (!clk || !clk->dpll_data)
804 clk->dpll_data->rate_tolerance = tolerance;
809 static unsigned long _dpll_compute_new_rate(unsigned long parent_rate, unsigned int m, unsigned int n)
811 unsigned long long num;
813 num = (unsigned long long)parent_rate * m;
819 * _dpll_test_mult - test a DPLL multiplier value
820 * @m: pointer to the DPLL m (multiplier) value under test
821 * @n: current DPLL n (divider) value under test
822 * @new_rate: pointer to storage for the resulting rounded rate
823 * @target_rate: the desired DPLL rate
824 * @parent_rate: the DPLL's parent clock rate
826 * This code tests a DPLL multiplier value, ensuring that the
827 * resulting rate will not be higher than the target_rate, and that
828 * the multiplier value itself is valid for the DPLL. Initially, the
829 * integer pointed to by the m argument should be prescaled by
830 * multiplying by DPLL_SCALE_FACTOR. The code will replace this with
831 * a non-scaled m upon return. This non-scaled m will result in a
832 * new_rate as close as possible to target_rate (but not greater than
833 * target_rate) given the current (parent_rate, n, prescaled m)
834 * triple. Returns DPLL_MULT_UNDERFLOW in the event that the
835 * non-scaled m attempted to underflow, which can allow the calling
836 * function to bail out early; or 0 upon success.
838 static int _dpll_test_mult(int *m, int n, unsigned long *new_rate,
839 unsigned long target_rate,
840 unsigned long parent_rate)
842 int flags = 0, carry = 0;
844 /* Unscale m and round if necessary */
845 if (*m % DPLL_SCALE_FACTOR >= DPLL_ROUNDING_VAL)
847 *m = (*m / DPLL_SCALE_FACTOR) + carry;
850 * The new rate must be <= the target rate to avoid programming
851 * a rate that is impossible for the hardware to handle
853 *new_rate = _dpll_compute_new_rate(parent_rate, *m, n);
854 if (*new_rate > target_rate) {
859 /* Guard against m underflow */
860 if (*m < DPLL_MIN_MULTIPLIER) {
861 *m = DPLL_MIN_MULTIPLIER;
863 flags = DPLL_MULT_UNDERFLOW;
867 *new_rate = _dpll_compute_new_rate(parent_rate, *m, n);
873 * omap2_dpll_round_rate - round a target rate for an OMAP DPLL
874 * @clk: struct clk * for a DPLL
875 * @target_rate: desired DPLL clock rate
877 * Given a DPLL, a desired target rate, and a rate tolerance, round
878 * the target rate to a possible, programmable rate for this DPLL.
879 * Rate tolerance is assumed to be set by the caller before this
880 * function is called. Attempts to select the minimum possible n
881 * within the tolerance to reduce power consumption. Stores the
882 * computed (m, n) in the DPLL's dpll_data structure so set_rate()
883 * will not need to call this (expensive) function again. Returns ~0
884 * if the target rate cannot be rounded, either because the rate is
885 * too low or because the rate tolerance is set too tightly; or the
886 * rounded rate upon success.
888 long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
890 int m, n, r, e, scaled_max_m;
891 unsigned long scaled_rt_rp, new_rate;
892 int min_e = -1, min_e_m = -1, min_e_n = -1;
894 if (!clk || !clk->dpll_data)
897 pr_debug("clock: starting DPLL round_rate for clock %s, target rate "
898 "%ld\n", clk->name, target_rate);
900 scaled_rt_rp = target_rate / (clk->parent->rate / DPLL_SCALE_FACTOR);
901 scaled_max_m = clk->dpll_data->max_multiplier * DPLL_SCALE_FACTOR;
903 clk->dpll_data->last_rounded_rate = 0;
905 for (n = clk->dpll_data->max_divider; n >= DPLL_MIN_DIVIDER; n--) {
907 /* Compute the scaled DPLL multiplier, based on the divider */
908 m = scaled_rt_rp * n;
911 * Since we're counting n down, a m overflow means we can
912 * can immediately skip to the next n
914 if (m > scaled_max_m)
917 r = _dpll_test_mult(&m, n, &new_rate, target_rate,
920 e = target_rate - new_rate;
921 pr_debug("clock: n = %d: m = %d: rate error is %d "
922 "(new_rate = %ld)\n", n, m, e, new_rate);
925 min_e >= (int)(abs(e) - clk->dpll_data->rate_tolerance)) {
930 pr_debug("clock: found new least error %d\n", min_e);
934 * Since we're counting n down, a m underflow means we
935 * can bail out completely (since as n decreases in
936 * the next iteration, there's no way that m can
937 * increase beyond the current m)
939 if (r & DPLL_MULT_UNDERFLOW)
944 pr_debug("clock: error: target rate or tolerance too low\n");
948 clk->dpll_data->last_rounded_m = min_e_m;
949 clk->dpll_data->last_rounded_n = min_e_n;
950 clk->dpll_data->last_rounded_rate =
951 _dpll_compute_new_rate(clk->parent->rate, min_e_m, min_e_n);
953 pr_debug("clock: final least error: e = %d, m = %d, n = %d\n",
954 min_e, min_e_m, min_e_n);
955 pr_debug("clock: final rate: %ld (target rate: %ld)\n",
956 clk->dpll_data->last_rounded_rate, target_rate);
958 return clk->dpll_data->last_rounded_rate;
961 /*-------------------------------------------------------------------------
962 * Omap2 clock reset and init functions
963 *-------------------------------------------------------------------------*/
965 #ifdef CONFIG_OMAP_RESET_CLOCKS
966 void omap2_clk_disable_unused(struct clk *clk)
970 v = (clk->flags & INVERT_ENABLE) ? (1 << clk->enable_bit) : 0;
972 regval32 = __raw_readl(clk->enable_reg);
973 if ((regval32 & (1 << clk->enable_bit)) == v)
976 printk(KERN_INFO "Disabling unused clock \"%s\"\n", clk->name);
977 _omap2_clk_disable(clk);